2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "drm-uapi/drm_fourcc.h"
30 #include "state_tracker/drm_driver.h"
31 #include "util/format/u_format.h"
32 #include "util/os_time.h"
33 #include "util/u_log.h"
34 #include "util/u_memory.h"
35 #include "util/u_pack_color.h"
36 #include "util/u_resource.h"
37 #include "util/u_surface.h"
38 #include "util/u_transfer.h"
43 #include "amd/addrlib/inc/addrinterface.h"
45 static enum radeon_surf_mode
si_choose_tiling(struct si_screen
*sscreen
,
46 const struct pipe_resource
*templ
,
47 bool tc_compatible_htile
);
49 bool si_prepare_for_dma_blit(struct si_context
*sctx
, struct si_texture
*dst
, unsigned dst_level
,
50 unsigned dstx
, unsigned dsty
, unsigned dstz
, struct si_texture
*src
,
51 unsigned src_level
, const struct pipe_box
*src_box
)
56 if (dst
->surface
.bpe
!= src
->surface
.bpe
)
59 /* MSAA: Blits don't exist in the real world. */
60 if (src
->buffer
.b
.b
.nr_samples
> 1 || dst
->buffer
.b
.b
.nr_samples
> 1)
63 /* Depth-stencil surfaces:
64 * When dst is linear, the DB->CB copy preserves HTILE.
65 * When dst is tiled, the 3D path must be used to update HTILE.
67 if (src
->is_depth
|| dst
->is_depth
)
71 * src: Use the 3D path. DCC decompression is expensive.
72 * dst: Use the 3D path to compress the pixels with DCC.
74 if (vi_dcc_enabled(src
, src_level
) || vi_dcc_enabled(dst
, dst_level
))
78 * src: Both texture and SDMA paths need decompression. Use SDMA.
79 * dst: If overwriting the whole texture, discard CMASK and use
80 * SDMA. Otherwise, use the 3D path.
82 if (dst
->cmask_buffer
&& dst
->dirty_level_mask
& (1 << dst_level
)) {
83 /* The CMASK clear is only enabled for the first level. */
84 assert(dst_level
== 0);
85 if (!util_texrange_covers_whole_level(&dst
->buffer
.b
.b
, dst_level
, dstx
, dsty
, dstz
,
86 src_box
->width
, src_box
->height
, src_box
->depth
))
89 si_texture_discard_cmask(sctx
->screen
, dst
);
92 /* All requirements are met. Prepare textures for SDMA. */
93 if (src
->cmask_buffer
&& src
->dirty_level_mask
& (1 << src_level
))
94 sctx
->b
.flush_resource(&sctx
->b
, &src
->buffer
.b
.b
);
96 assert(!(src
->dirty_level_mask
& (1 << src_level
)));
97 assert(!(dst
->dirty_level_mask
& (1 << dst_level
)));
102 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
103 static void si_copy_region_with_blit(struct pipe_context
*pipe
, struct pipe_resource
*dst
,
104 unsigned dst_level
, unsigned dstx
, unsigned dsty
,
105 unsigned dstz
, struct pipe_resource
*src
, unsigned src_level
,
106 const struct pipe_box
*src_box
)
108 struct pipe_blit_info blit
;
110 memset(&blit
, 0, sizeof(blit
));
111 blit
.src
.resource
= src
;
112 blit
.src
.format
= src
->format
;
113 blit
.src
.level
= src_level
;
114 blit
.src
.box
= *src_box
;
115 blit
.dst
.resource
= dst
;
116 blit
.dst
.format
= dst
->format
;
117 blit
.dst
.level
= dst_level
;
118 blit
.dst
.box
.x
= dstx
;
119 blit
.dst
.box
.y
= dsty
;
120 blit
.dst
.box
.z
= dstz
;
121 blit
.dst
.box
.width
= src_box
->width
;
122 blit
.dst
.box
.height
= src_box
->height
;
123 blit
.dst
.box
.depth
= src_box
->depth
;
124 blit
.mask
= util_format_get_mask(dst
->format
);
125 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
128 pipe
->blit(pipe
, &blit
);
132 /* Copy from a full GPU texture to a transfer's staging one. */
133 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
135 struct si_context
*sctx
= (struct si_context
*)ctx
;
136 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
137 struct pipe_resource
*dst
= &stransfer
->staging
->b
.b
;
138 struct pipe_resource
*src
= transfer
->resource
;
140 if (src
->nr_samples
> 1 || ((struct si_texture
*)src
)->is_depth
) {
141 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
, &transfer
->box
);
145 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
, &transfer
->box
);
148 /* Copy from a transfer's staging texture to a full GPU one. */
149 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
151 struct si_context
*sctx
= (struct si_context
*)ctx
;
152 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
153 struct pipe_resource
*dst
= transfer
->resource
;
154 struct pipe_resource
*src
= &stransfer
->staging
->b
.b
;
155 struct pipe_box sbox
;
157 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
159 if (dst
->nr_samples
> 1 || ((struct si_texture
*)dst
)->is_depth
) {
160 si_copy_region_with_blit(ctx
, dst
, transfer
->level
, transfer
->box
.x
, transfer
->box
.y
,
161 transfer
->box
.z
, src
, 0, &sbox
);
165 if (util_format_is_compressed(dst
->format
)) {
166 sbox
.width
= util_format_get_nblocksx(dst
->format
, sbox
.width
);
167 sbox
.height
= util_format_get_nblocksx(dst
->format
, sbox
.height
);
170 sctx
->dma_copy(ctx
, dst
, transfer
->level
, transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
, src
,
174 static unsigned si_texture_get_offset(struct si_screen
*sscreen
, struct si_texture
*tex
,
175 unsigned level
, const struct pipe_box
*box
, unsigned *stride
,
176 unsigned *layer_stride
)
178 if (sscreen
->info
.chip_class
>= GFX9
) {
179 *stride
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
180 *layer_stride
= tex
->surface
.u
.gfx9
.surf_slice_size
;
185 /* Each texture is an array of slices. Each slice is an array
186 * of mipmap levels. */
187 return tex
->surface
.u
.gfx9
.surf_offset
+ box
->z
* tex
->surface
.u
.gfx9
.surf_slice_size
+
188 tex
->surface
.u
.gfx9
.offset
[level
] +
189 (box
->y
/ tex
->surface
.blk_h
* tex
->surface
.u
.gfx9
.surf_pitch
+
190 box
->x
/ tex
->surface
.blk_w
) *
193 *stride
= tex
->surface
.u
.legacy
.level
[level
].nblk_x
* tex
->surface
.bpe
;
194 assert((uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
195 *layer_stride
= (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
198 return tex
->surface
.u
.legacy
.level
[level
].offset
;
200 /* Each texture is an array of mipmap levels. Each level is
201 * an array of slices. */
202 return tex
->surface
.u
.legacy
.level
[level
].offset
+
203 box
->z
* (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
204 (box
->y
/ tex
->surface
.blk_h
* tex
->surface
.u
.legacy
.level
[level
].nblk_x
+
205 box
->x
/ tex
->surface
.blk_w
) *
210 static int si_init_surface(struct si_screen
*sscreen
, struct radeon_surf
*surface
,
211 const struct pipe_resource
*ptex
, enum radeon_surf_mode array_mode
,
212 bool is_imported
, bool is_scanout
, bool is_flushed_depth
,
213 bool tc_compatible_htile
)
215 const struct util_format_description
*desc
= util_format_description(ptex
->format
);
216 bool is_depth
, is_stencil
;
218 unsigned bpe
, flags
= 0;
220 is_depth
= util_format_has_depth(desc
);
221 is_stencil
= util_format_has_stencil(desc
);
223 if (!is_flushed_depth
&& ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
224 bpe
= 4; /* stencil is allocated separately */
226 bpe
= util_format_get_blocksize(ptex
->format
);
227 assert(util_is_power_of_two_or_zero(bpe
));
230 if (!is_flushed_depth
&& is_depth
) {
231 flags
|= RADEON_SURF_ZBUFFER
;
233 if (sscreen
->debug_flags
& DBG(NO_HYPERZ
)) {
234 flags
|= RADEON_SURF_NO_HTILE
;
235 } else if (tc_compatible_htile
&&
236 (sscreen
->info
.chip_class
>= GFX9
|| array_mode
== RADEON_SURF_MODE_2D
)) {
237 /* TC-compatible HTILE only supports Z32_FLOAT.
238 * GFX9 also supports Z16_UNORM.
239 * On GFX8, promote Z16 to Z32. DB->CB copies will convert
240 * the format for transfers.
242 if (sscreen
->info
.chip_class
== GFX8
)
245 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
249 flags
|= RADEON_SURF_SBUFFER
;
252 if (sscreen
->info
.chip_class
>= GFX8
&&
253 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
|| ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
254 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
255 flags
|= RADEON_SURF_DISABLE_DCC
;
257 /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */
258 if (sscreen
->info
.family
== CHIP_STONEY
&& bpe
== 16 && ptex
->nr_samples
>= 2)
259 flags
|= RADEON_SURF_DISABLE_DCC
;
261 /* GFX8: DCC clear for 4x and 8x MSAA array textures unimplemented. */
262 if (sscreen
->info
.chip_class
== GFX8
&& ptex
->nr_storage_samples
>= 4 && ptex
->array_size
> 1)
263 flags
|= RADEON_SURF_DISABLE_DCC
;
265 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
266 if (sscreen
->info
.chip_class
== GFX9
&&
267 (ptex
->nr_storage_samples
>= 4 ||
268 (sscreen
->info
.family
== CHIP_RAVEN
&& ptex
->nr_storage_samples
>= 2 && bpe
< 4)))
269 flags
|= RADEON_SURF_DISABLE_DCC
;
271 /* TODO: GFX10: DCC causes corruption with MSAA. */
272 if (sscreen
->info
.chip_class
>= GFX10
&& ptex
->nr_storage_samples
>= 2)
273 flags
|= RADEON_SURF_DISABLE_DCC
;
275 /* Shared textures must always set up DCC.
276 * If it's not present, it will be disabled by
277 * si_get_opaque_metadata later.
279 if (!is_imported
&& (sscreen
->debug_flags
& DBG(NO_DCC
)))
280 flags
|= RADEON_SURF_DISABLE_DCC
;
283 /* This should catch bugs in gallium users setting incorrect flags. */
284 assert(ptex
->nr_samples
<= 1 && ptex
->array_size
== 1 && ptex
->depth0
== 1 &&
285 ptex
->last_level
== 0 && !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
287 flags
|= RADEON_SURF_SCANOUT
;
290 if (ptex
->bind
& PIPE_BIND_SHARED
)
291 flags
|= RADEON_SURF_SHAREABLE
;
293 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
294 if (sscreen
->debug_flags
& DBG(NO_FMASK
))
295 flags
|= RADEON_SURF_NO_FMASK
;
297 if (sscreen
->info
.chip_class
== GFX9
&& (ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE
)) {
298 flags
|= RADEON_SURF_FORCE_MICRO_TILE_MODE
;
299 surface
->micro_tile_mode
= SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(ptex
->flags
);
302 if (ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
) {
303 flags
|= RADEON_SURF_FORCE_SWIZZLE_MODE
;
305 if (sscreen
->info
.chip_class
>= GFX10
)
306 surface
->u
.gfx9
.surf
.swizzle_mode
= ADDR_SW_64KB_R_X
;
309 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
, array_mode
, surface
);
317 void si_eliminate_fast_color_clear(struct si_context
*sctx
, struct si_texture
*tex
,
320 struct si_screen
*sscreen
= sctx
->screen
;
321 struct pipe_context
*ctx
= &sctx
->b
;
323 if (ctx
== sscreen
->aux_context
)
324 simple_mtx_lock(&sscreen
->aux_context_lock
);
326 unsigned n
= sctx
->num_decompress_calls
;
327 ctx
->flush_resource(ctx
, &tex
->buffer
.b
.b
);
329 /* Flush only if any fast clear elimination took place. */
330 bool flushed
= false;
331 if (n
!= sctx
->num_decompress_calls
)
333 ctx
->flush(ctx
, NULL
, 0);
337 *ctx_flushed
= flushed
;
339 if (ctx
== sscreen
->aux_context
)
340 simple_mtx_unlock(&sscreen
->aux_context_lock
);
343 void si_texture_discard_cmask(struct si_screen
*sscreen
, struct si_texture
*tex
)
345 if (!tex
->cmask_buffer
)
348 assert(tex
->buffer
.b
.b
.nr_samples
<= 1);
351 tex
->cmask_base_address_reg
= tex
->buffer
.gpu_address
>> 8;
352 tex
->dirty_level_mask
= 0;
354 tex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
356 if (tex
->cmask_buffer
!= &tex
->buffer
)
357 si_resource_reference(&tex
->cmask_buffer
, NULL
);
359 tex
->cmask_buffer
= NULL
;
361 /* Notify all contexts about the change. */
362 p_atomic_inc(&sscreen
->dirty_tex_counter
);
363 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
366 static bool si_can_disable_dcc(struct si_texture
*tex
)
368 /* We can't disable DCC if it can be written by another process. */
369 return tex
->surface
.dcc_offset
&&
370 (!tex
->buffer
.b
.is_shared
||
371 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
));
374 static bool si_texture_discard_dcc(struct si_screen
*sscreen
, struct si_texture
*tex
)
376 if (!si_can_disable_dcc(tex
))
379 assert(tex
->dcc_separate_buffer
== NULL
);
382 ac_surface_zero_dcc_fields(&tex
->surface
);
384 /* Notify all contexts about the change. */
385 p_atomic_inc(&sscreen
->dirty_tex_counter
);
390 * Disable DCC for the texture. (first decompress, then discard metadata).
392 * There is unresolved multi-context synchronization issue between
393 * screen::aux_context and the current context. If applications do this with
394 * multiple contexts, it's already undefined behavior for them and we don't
395 * have to worry about that. The scenario is:
397 * If context 1 disables DCC and context 2 has queued commands that write
398 * to the texture via CB with DCC enabled, and the order of operations is
400 * context 2 queues draw calls rendering to the texture, but doesn't flush
401 * context 1 disables DCC and flushes
402 * context 1 & 2 reset descriptors and FB state
403 * context 2 flushes (new compressed tiles written by the draw calls)
404 * context 1 & 2 read garbage, because DCC is disabled, yet there are
407 * \param sctx the current context if you have one, or sscreen->aux_context
410 bool si_texture_disable_dcc(struct si_context
*sctx
, struct si_texture
*tex
)
412 struct si_screen
*sscreen
= sctx
->screen
;
414 if (!sctx
->has_graphics
)
415 return si_texture_discard_dcc(sscreen
, tex
);
417 if (!si_can_disable_dcc(tex
))
420 if (&sctx
->b
== sscreen
->aux_context
)
421 simple_mtx_lock(&sscreen
->aux_context_lock
);
423 /* Decompress DCC. */
424 si_decompress_dcc(sctx
, tex
);
425 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
427 if (&sctx
->b
== sscreen
->aux_context
)
428 simple_mtx_unlock(&sscreen
->aux_context_lock
);
430 return si_texture_discard_dcc(sscreen
, tex
);
433 static void si_reallocate_texture_inplace(struct si_context
*sctx
, struct si_texture
*tex
,
434 unsigned new_bind_flag
, bool invalidate_storage
)
436 struct pipe_screen
*screen
= sctx
->b
.screen
;
437 struct si_texture
*new_tex
;
438 struct pipe_resource templ
= tex
->buffer
.b
.b
;
441 templ
.bind
|= new_bind_flag
;
443 if (tex
->buffer
.b
.is_shared
|| tex
->num_planes
> 1)
446 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
447 if (tex
->surface
.is_linear
)
450 /* This fails with MSAA, depth, and compressed textures. */
451 if (si_choose_tiling(sctx
->screen
, &templ
, false) != RADEON_SURF_MODE_LINEAR_ALIGNED
)
455 new_tex
= (struct si_texture
*)screen
->resource_create(screen
, &templ
);
459 /* Copy the pixels to the new texture. */
460 if (!invalidate_storage
) {
461 for (i
= 0; i
<= templ
.last_level
; i
++) {
464 u_box_3d(0, 0, 0, u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
465 util_num_layers(&templ
, i
), &box
);
467 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0, &tex
->buffer
.b
.b
, i
, &box
);
471 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
472 si_texture_discard_cmask(sctx
->screen
, tex
);
473 si_texture_discard_dcc(sctx
->screen
, tex
);
476 /* Replace the structure fields of tex. */
477 tex
->buffer
.b
.b
.bind
= templ
.bind
;
478 pb_reference(&tex
->buffer
.buf
, new_tex
->buffer
.buf
);
479 tex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
480 tex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
481 tex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
482 tex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
483 tex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
484 tex
->buffer
.domains
= new_tex
->buffer
.domains
;
485 tex
->buffer
.flags
= new_tex
->buffer
.flags
;
487 tex
->surface
= new_tex
->surface
;
488 si_texture_reference(&tex
->flushed_depth_texture
, new_tex
->flushed_depth_texture
);
490 tex
->surface
.fmask_offset
= new_tex
->surface
.fmask_offset
;
491 tex
->surface
.cmask_offset
= new_tex
->surface
.cmask_offset
;
492 tex
->cmask_base_address_reg
= new_tex
->cmask_base_address_reg
;
494 if (tex
->cmask_buffer
== &tex
->buffer
)
495 tex
->cmask_buffer
= NULL
;
497 si_resource_reference(&tex
->cmask_buffer
, NULL
);
499 if (new_tex
->cmask_buffer
== &new_tex
->buffer
)
500 tex
->cmask_buffer
= &tex
->buffer
;
502 si_resource_reference(&tex
->cmask_buffer
, new_tex
->cmask_buffer
);
504 tex
->surface
.dcc_offset
= new_tex
->surface
.dcc_offset
;
505 tex
->cb_color_info
= new_tex
->cb_color_info
;
506 memcpy(tex
->color_clear_value
, new_tex
->color_clear_value
, sizeof(tex
->color_clear_value
));
507 tex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
509 tex
->surface
.htile_offset
= new_tex
->surface
.htile_offset
;
510 tex
->depth_clear_value
= new_tex
->depth_clear_value
;
511 tex
->dirty_level_mask
= new_tex
->dirty_level_mask
;
512 tex
->stencil_dirty_level_mask
= new_tex
->stencil_dirty_level_mask
;
513 tex
->db_render_format
= new_tex
->db_render_format
;
514 tex
->stencil_clear_value
= new_tex
->stencil_clear_value
;
515 tex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
516 tex
->depth_cleared
= new_tex
->depth_cleared
;
517 tex
->stencil_cleared
= new_tex
->stencil_cleared
;
518 tex
->upgraded_depth
= new_tex
->upgraded_depth
;
519 tex
->db_compatible
= new_tex
->db_compatible
;
520 tex
->can_sample_z
= new_tex
->can_sample_z
;
521 tex
->can_sample_s
= new_tex
->can_sample_s
;
523 tex
->separate_dcc_dirty
= new_tex
->separate_dcc_dirty
;
524 tex
->displayable_dcc_dirty
= new_tex
->displayable_dcc_dirty
;
525 tex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
526 si_resource_reference(&tex
->dcc_separate_buffer
, new_tex
->dcc_separate_buffer
);
527 si_resource_reference(&tex
->last_dcc_separate_buffer
, new_tex
->last_dcc_separate_buffer
);
529 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
530 assert(!tex
->surface
.htile_offset
);
531 assert(!tex
->cmask_buffer
);
532 assert(!tex
->surface
.fmask_size
);
533 assert(!tex
->surface
.dcc_offset
);
534 assert(!tex
->is_depth
);
537 si_texture_reference(&new_tex
, NULL
);
539 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
542 static void si_set_tex_bo_metadata(struct si_screen
*sscreen
, struct si_texture
*tex
)
544 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
545 struct radeon_bo_metadata md
;
547 memset(&md
, 0, sizeof(md
));
549 assert(tex
->dcc_separate_buffer
== NULL
);
550 assert(tex
->surface
.fmask_size
== 0);
552 static const unsigned char swizzle
[] = {PIPE_SWIZZLE_X
, PIPE_SWIZZLE_Y
, PIPE_SWIZZLE_Z
,
554 bool is_array
= util_texture_is_array(res
->target
);
557 sscreen
->make_texture_descriptor(sscreen
, tex
, true, res
->target
, res
->format
, swizzle
, 0,
558 res
->last_level
, 0, is_array
? res
->array_size
- 1 : 0,
559 res
->width0
, res
->height0
, res
->depth0
, desc
, NULL
);
560 si_set_mutable_tex_desc_fields(sscreen
, tex
, &tex
->surface
.u
.legacy
.level
[0], 0, 0,
561 tex
->surface
.blk_w
, false, false, desc
);
563 ac_surface_get_umd_metadata(&sscreen
->info
, &tex
->surface
,
564 tex
->buffer
.b
.b
.last_level
+ 1,
565 desc
, &md
.size_metadata
, md
.metadata
);
566 sscreen
->ws
->buffer_set_metadata(tex
->buffer
.buf
, &md
, &tex
->surface
);
569 static bool si_has_displayable_dcc(struct si_texture
*tex
)
571 struct si_screen
*sscreen
= (struct si_screen
*)tex
->buffer
.b
.b
.screen
;
573 if (sscreen
->info
.chip_class
<= GFX8
)
576 return tex
->surface
.is_displayable
&& tex
->surface
.dcc_offset
;
579 static bool si_resource_get_param(struct pipe_screen
*screen
, struct pipe_context
*context
,
580 struct pipe_resource
*resource
, unsigned plane
, unsigned layer
,
581 enum pipe_resource_param param
, unsigned handle_usage
,
584 for (unsigned i
= 0; i
< plane
; i
++)
585 resource
= resource
->next
;
587 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
588 struct si_texture
*tex
= (struct si_texture
*)resource
;
589 struct winsys_handle whandle
;
592 case PIPE_RESOURCE_PARAM_NPLANES
:
593 *value
= resource
->target
== PIPE_BUFFER
? 1 : tex
->num_planes
;
596 case PIPE_RESOURCE_PARAM_STRIDE
:
597 if (resource
->target
== PIPE_BUFFER
)
599 else if (sscreen
->info
.chip_class
>= GFX9
)
600 *value
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
602 *value
= tex
->surface
.u
.legacy
.level
[0].nblk_x
* tex
->surface
.bpe
;
605 case PIPE_RESOURCE_PARAM_OFFSET
:
606 if (resource
->target
== PIPE_BUFFER
)
608 else if (sscreen
->info
.chip_class
>= GFX9
)
609 *value
= tex
->surface
.u
.gfx9
.surf_offset
+ layer
* tex
->surface
.u
.gfx9
.surf_slice_size
;
611 *value
= tex
->surface
.u
.legacy
.level
[0].offset
+
612 layer
* (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
615 case PIPE_RESOURCE_PARAM_MODIFIER
:
616 *value
= DRM_FORMAT_MOD_INVALID
;
619 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
620 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
:
621 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
622 memset(&whandle
, 0, sizeof(whandle
));
624 if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
)
625 whandle
.type
= WINSYS_HANDLE_TYPE_SHARED
;
626 else if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
)
627 whandle
.type
= WINSYS_HANDLE_TYPE_KMS
;
628 else if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
)
629 whandle
.type
= WINSYS_HANDLE_TYPE_FD
;
631 if (!screen
->resource_get_handle(screen
, context
, resource
, &whandle
, handle_usage
))
634 *value
= whandle
.handle
;
640 static void si_texture_get_info(struct pipe_screen
*screen
, struct pipe_resource
*resource
,
641 unsigned *pstride
, unsigned *poffset
)
646 si_resource_get_param(screen
, NULL
, resource
, 0, 0, PIPE_RESOURCE_PARAM_STRIDE
, 0, &value
);
651 si_resource_get_param(screen
, NULL
, resource
, 0, 0, PIPE_RESOURCE_PARAM_OFFSET
, 0, &value
);
656 static bool si_texture_get_handle(struct pipe_screen
*screen
, struct pipe_context
*ctx
,
657 struct pipe_resource
*resource
, struct winsys_handle
*whandle
,
660 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
661 struct si_context
*sctx
;
662 struct si_resource
*res
= si_resource(resource
);
663 struct si_texture
*tex
= (struct si_texture
*)resource
;
664 bool update_metadata
= false;
665 unsigned stride
, offset
, slice_size
;
668 ctx
= threaded_context_unwrap_sync(ctx
);
669 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
671 if (resource
->target
!= PIPE_BUFFER
) {
672 /* Individual planes are chained pipe_resource instances. */
673 for (unsigned i
= 0; i
< whandle
->plane
; i
++) {
674 resource
= resource
->next
;
675 res
= si_resource(resource
);
676 tex
= (struct si_texture
*)resource
;
679 /* This is not supported now, but it might be required for OpenCL
680 * interop in the future.
682 if (resource
->nr_samples
> 1 || tex
->is_depth
)
685 /* Move a suballocated texture into a non-suballocated allocation. */
686 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) || tex
->surface
.tile_swizzle
||
687 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
688 sscreen
->info
.has_local_buffers
)) {
689 assert(!res
->b
.is_shared
);
690 si_reallocate_texture_inplace(sctx
, tex
, PIPE_BIND_SHARED
, false);
692 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
693 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
694 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
695 assert(tex
->surface
.tile_swizzle
== 0);
698 /* Since shader image stores don't support DCC on GFX8,
699 * disable it for external clients that want write
702 if ((usage
& PIPE_HANDLE_USAGE_SHADER_WRITE
&& tex
->surface
.dcc_offset
) ||
703 /* Displayable DCC requires an explicit flush. */
704 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && si_has_displayable_dcc(tex
))) {
705 if (si_texture_disable_dcc(sctx
, tex
)) {
706 update_metadata
= true;
707 /* si_texture_disable_dcc flushes the context */
712 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
713 (tex
->cmask_buffer
|| tex
->surface
.dcc_offset
)) {
714 /* Eliminate fast clear (both CMASK and DCC) */
716 si_eliminate_fast_color_clear(sctx
, tex
, &flushed
);
717 /* eliminate_fast_color_clear sometimes flushes the context */
721 /* Disable CMASK if flush_resource isn't going
724 if (tex
->cmask_buffer
)
725 si_texture_discard_cmask(sscreen
, tex
);
729 if ((!res
->b
.is_shared
|| update_metadata
) && whandle
->offset
== 0)
730 si_set_tex_bo_metadata(sscreen
, tex
);
732 if (sscreen
->info
.chip_class
>= GFX9
) {
733 slice_size
= tex
->surface
.u
.gfx9
.surf_slice_size
;
735 slice_size
= (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
738 /* Buffer exports are for the OpenCL interop. */
739 /* Move a suballocated buffer into a non-suballocated allocation. */
740 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
741 /* A DMABUF export always fails if the BO is local. */
742 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
743 sscreen
->info
.has_local_buffers
)) {
744 assert(!res
->b
.is_shared
);
746 /* Allocate a new buffer with PIPE_BIND_SHARED. */
747 struct pipe_resource templ
= res
->b
.b
;
748 templ
.bind
|= PIPE_BIND_SHARED
;
750 struct pipe_resource
*newb
= screen
->resource_create(screen
, &templ
);
754 /* Copy the old buffer contents to the new one. */
756 u_box_1d(0, newb
->width0
, &box
);
757 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0, &res
->b
.b
, 0, &box
);
759 /* Move the new buffer storage to the old pipe_resource. */
760 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
761 pipe_resource_reference(&newb
, NULL
);
763 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
764 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
771 si_texture_get_info(screen
, resource
, &stride
, &offset
);
774 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
776 if (res
->b
.is_shared
) {
777 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
780 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
781 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
782 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
784 res
->b
.is_shared
= true;
785 res
->external_usage
= usage
;
788 whandle
->stride
= stride
;
789 whandle
->offset
= offset
+ slice_size
* whandle
->layer
;
791 return sscreen
->ws
->buffer_get_handle(sscreen
->ws
, res
->buf
, whandle
);
794 static void si_texture_destroy(struct pipe_screen
*screen
, struct pipe_resource
*ptex
)
796 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
797 struct si_texture
*tex
= (struct si_texture
*)ptex
;
798 struct si_resource
*resource
= &tex
->buffer
;
800 if (sscreen
->info
.chip_class
>= GFX9
)
801 free(tex
->surface
.u
.gfx9
.dcc_retile_map
);
803 si_texture_reference(&tex
->flushed_depth_texture
, NULL
);
805 if (tex
->cmask_buffer
!= &tex
->buffer
) {
806 si_resource_reference(&tex
->cmask_buffer
, NULL
);
808 pb_reference(&resource
->buf
, NULL
);
809 si_resource_reference(&tex
->dcc_separate_buffer
, NULL
);
810 si_resource_reference(&tex
->last_dcc_separate_buffer
, NULL
);
814 static const struct u_resource_vtbl si_texture_vtbl
;
816 void si_print_texture_info(struct si_screen
*sscreen
, struct si_texture
*tex
,
817 struct u_log_context
*log
)
821 /* Common parameters. */
823 " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
824 "blk_h=%u, array_size=%u, last_level=%u, "
825 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
826 tex
->buffer
.b
.b
.width0
, tex
->buffer
.b
.b
.height0
, tex
->buffer
.b
.b
.depth0
,
827 tex
->surface
.blk_w
, tex
->surface
.blk_h
, tex
->buffer
.b
.b
.array_size
,
828 tex
->buffer
.b
.b
.last_level
, tex
->surface
.bpe
, tex
->buffer
.b
.b
.nr_samples
,
829 tex
->surface
.flags
, util_format_short_name(tex
->buffer
.b
.b
.format
));
831 if (sscreen
->info
.chip_class
>= GFX9
) {
833 " Surf: size=%" PRIu64
", slice_size=%" PRIu64
", "
834 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
835 tex
->surface
.surf_size
, tex
->surface
.u
.gfx9
.surf_slice_size
,
836 tex
->surface
.surf_alignment
, tex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
837 tex
->surface
.u
.gfx9
.surf
.epitch
, tex
->surface
.u
.gfx9
.surf_pitch
);
839 if (tex
->surface
.fmask_offset
) {
841 " FMASK: offset=%" PRIu64
", size=%" PRIu64
", "
842 "alignment=%u, swmode=%u, epitch=%u\n",
843 tex
->surface
.fmask_offset
, tex
->surface
.fmask_size
,
844 tex
->surface
.fmask_alignment
, tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
845 tex
->surface
.u
.gfx9
.fmask
.epitch
);
848 if (tex
->cmask_buffer
) {
850 " CMask: offset=%" PRIu64
", size=%u, "
852 tex
->surface
.cmask_offset
, tex
->surface
.cmask_size
,
853 tex
->surface
.cmask_alignment
);
856 if (tex
->surface
.htile_offset
) {
858 " HTile: offset=%" PRIu64
", size=%u, alignment=%u\n",
859 tex
->surface
.htile_offset
, tex
->surface
.htile_size
,
860 tex
->surface
.htile_alignment
);
863 if (tex
->surface
.dcc_offset
) {
865 " DCC: offset=%" PRIu64
", size=%u, "
866 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
867 tex
->surface
.dcc_offset
, tex
->surface
.dcc_size
, tex
->surface
.dcc_alignment
,
868 tex
->surface
.u
.gfx9
.display_dcc_pitch_max
, tex
->surface
.num_dcc_levels
);
871 if (tex
->surface
.u
.gfx9
.stencil_offset
) {
872 u_log_printf(log
, " Stencil: offset=%" PRIu64
", swmode=%u, epitch=%u\n",
873 tex
->surface
.u
.gfx9
.stencil_offset
, tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
874 tex
->surface
.u
.gfx9
.stencil
.epitch
);
880 " Layout: size=%" PRIu64
", alignment=%u, bankw=%u, "
881 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
882 tex
->surface
.surf_size
, tex
->surface
.surf_alignment
, tex
->surface
.u
.legacy
.bankw
,
883 tex
->surface
.u
.legacy
.bankh
, tex
->surface
.u
.legacy
.num_banks
,
884 tex
->surface
.u
.legacy
.mtilea
, tex
->surface
.u
.legacy
.tile_split
,
885 tex
->surface
.u
.legacy
.pipe_config
, (tex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
887 if (tex
->surface
.fmask_offset
)
890 " FMask: offset=%" PRIu64
", size=%" PRIu64
", alignment=%u, pitch_in_pixels=%u, "
891 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
892 tex
->surface
.fmask_offset
, tex
->surface
.fmask_size
, tex
->surface
.fmask_alignment
,
893 tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
, tex
->surface
.u
.legacy
.fmask
.bankh
,
894 tex
->surface
.u
.legacy
.fmask
.slice_tile_max
, tex
->surface
.u
.legacy
.fmask
.tiling_index
);
896 if (tex
->cmask_buffer
)
898 " CMask: offset=%" PRIu64
", size=%u, alignment=%u, "
899 "slice_tile_max=%u\n",
900 tex
->surface
.cmask_offset
, tex
->surface
.cmask_size
, tex
->surface
.cmask_alignment
,
901 tex
->surface
.u
.legacy
.cmask_slice_tile_max
);
903 if (tex
->surface
.htile_offset
)
905 " HTile: offset=%" PRIu64
", size=%u, "
906 "alignment=%u, TC_compatible = %u\n",
907 tex
->surface
.htile_offset
, tex
->surface
.htile_size
, tex
->surface
.htile_alignment
,
908 tex
->tc_compatible_htile
);
910 if (tex
->surface
.dcc_offset
) {
911 u_log_printf(log
, " DCC: offset=%" PRIu64
", size=%u, alignment=%u\n",
912 tex
->surface
.dcc_offset
, tex
->surface
.dcc_size
, tex
->surface
.dcc_alignment
);
913 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
915 " DCCLevel[%i]: enabled=%u, offset=%u, "
916 "fast_clear_size=%u\n",
917 i
, i
< tex
->surface
.num_dcc_levels
, tex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
918 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
921 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
923 " Level[%i]: offset=%" PRIu64
", slice_size=%" PRIu64
", "
924 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
925 "mode=%u, tiling_index = %u\n",
926 i
, tex
->surface
.u
.legacy
.level
[i
].offset
,
927 (uint64_t)tex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
928 u_minify(tex
->buffer
.b
.b
.width0
, i
), u_minify(tex
->buffer
.b
.b
.height0
, i
),
929 u_minify(tex
->buffer
.b
.b
.depth0
, i
), tex
->surface
.u
.legacy
.level
[i
].nblk_x
,
930 tex
->surface
.u
.legacy
.level
[i
].nblk_y
, tex
->surface
.u
.legacy
.level
[i
].mode
,
931 tex
->surface
.u
.legacy
.tiling_index
[i
]);
933 if (tex
->surface
.has_stencil
) {
934 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
935 tex
->surface
.u
.legacy
.stencil_tile_split
);
936 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++) {
938 " StencilLevel[%i]: offset=%" PRIu64
", "
939 "slice_size=%" PRIu64
", npix_x=%u, "
940 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
941 "mode=%u, tiling_index = %u\n",
942 i
, tex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
943 (uint64_t)tex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
944 u_minify(tex
->buffer
.b
.b
.width0
, i
), u_minify(tex
->buffer
.b
.b
.height0
, i
),
945 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
946 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
947 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
948 tex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
949 tex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
955 * Common function for si_texture_create and si_texture_from_handle.
957 * \param screen screen
958 * \param base resource template
959 * \param surface radeon_surf
960 * \param plane0 if a non-zero plane is being created, this is the first plane
961 * \param imported_buf from si_texture_from_handle
962 * \param offset offset for non-zero planes or imported buffers
963 * \param alloc_size the size to allocate if plane0 != NULL
964 * \param alignment alignment for the allocation
966 static struct si_texture
*si_texture_create_object(struct pipe_screen
*screen
,
967 const struct pipe_resource
*base
,
968 const struct radeon_surf
*surface
,
969 const struct si_texture
*plane0
,
970 struct pb_buffer
*imported_buf
,
971 uint64_t offset
, unsigned pitch_in_bytes
,
972 uint64_t alloc_size
, unsigned alignment
)
974 struct si_texture
*tex
;
975 struct si_resource
*resource
;
976 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
978 tex
= CALLOC_STRUCT(si_texture
);
982 resource
= &tex
->buffer
;
983 resource
->b
.b
= *base
;
984 resource
->b
.vtbl
= &si_texture_vtbl
;
985 pipe_reference_init(&resource
->b
.b
.reference
, 1);
986 resource
->b
.b
.screen
= screen
;
988 /* don't include stencil-only formats which we don't support for rendering */
989 tex
->is_depth
= util_format_has_depth(util_format_description(tex
->buffer
.b
.b
.format
));
990 tex
->surface
= *surface
;
991 tex
->tc_compatible_htile
= false; /* This will be enabled on demand. */
993 /* TC-compatible HTILE:
994 * - GFX8 only supports Z32_FLOAT.
995 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
996 if (tex
->surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
) {
997 if (sscreen
->info
.chip_class
>= GFX9
&& base
->format
== PIPE_FORMAT_Z16_UNORM
)
998 tex
->db_render_format
= base
->format
;
1000 tex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1001 tex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1002 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1005 tex
->db_render_format
= base
->format
;
1008 /* Applies to GCN. */
1009 tex
->last_msaa_resolve_target_micro_mode
= tex
->surface
.micro_tile_mode
;
1011 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1012 * between frames, so the only thing that can enable separate DCC
1013 * with DRI2 is multiple slow clears within a frame.
1015 tex
->ps_draw_ratio
= 0;
1017 ac_surface_override_offset_stride(&sscreen
->info
, &tex
->surface
,
1018 tex
->buffer
.b
.b
.last_level
+ 1,
1019 offset
, pitch_in_bytes
/ tex
->surface
.bpe
);
1021 if (tex
->is_depth
) {
1022 if (sscreen
->info
.chip_class
>= GFX9
) {
1023 tex
->can_sample_z
= true;
1024 tex
->can_sample_s
= true;
1026 /* Stencil texturing with HTILE doesn't work
1027 * with mipmapping on Navi10-14. */
1028 if (sscreen
->info
.chip_class
== GFX10
&& base
->last_level
> 0)
1029 tex
->htile_stencil_disabled
= true;
1031 tex
->can_sample_z
= !tex
->surface
.u
.legacy
.depth_adjusted
;
1032 tex
->can_sample_s
= !tex
->surface
.u
.legacy
.stencil_adjusted
;
1035 tex
->db_compatible
= surface
->flags
& RADEON_SURF_ZBUFFER
;
1037 if (tex
->surface
.cmask_offset
) {
1038 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
1039 tex
->cmask_buffer
= &tex
->buffer
;
1044 /* The buffer is shared with the first plane. */
1045 resource
->bo_size
= plane0
->buffer
.bo_size
;
1046 resource
->bo_alignment
= plane0
->buffer
.bo_alignment
;
1047 resource
->flags
= plane0
->buffer
.flags
;
1048 resource
->domains
= plane0
->buffer
.domains
;
1049 resource
->vram_usage
= plane0
->buffer
.vram_usage
;
1050 resource
->gart_usage
= plane0
->buffer
.gart_usage
;
1052 pb_reference(&resource
->buf
, plane0
->buffer
.buf
);
1053 resource
->gpu_address
= plane0
->buffer
.gpu_address
;
1054 } else if (!(surface
->flags
& RADEON_SURF_IMPORTED
)) {
1055 /* Create the backing buffer. */
1056 si_init_resource_fields(sscreen
, resource
, alloc_size
, alignment
);
1058 if (!si_alloc_resource(sscreen
, resource
))
1061 resource
->buf
= imported_buf
;
1062 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1063 resource
->bo_size
= imported_buf
->size
;
1064 resource
->bo_alignment
= imported_buf
->alignment
;
1065 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1066 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1067 resource
->vram_usage
= resource
->bo_size
;
1068 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1069 resource
->gart_usage
= resource
->bo_size
;
1070 if (sscreen
->ws
->buffer_get_flags
)
1071 resource
->flags
= sscreen
->ws
->buffer_get_flags(resource
->buf
);
1074 if (tex
->cmask_buffer
) {
1075 /* Initialize the cmask to 0xCC (= compressed state). */
1076 si_screen_clear_buffer(sscreen
, &tex
->cmask_buffer
->b
.b
, tex
->surface
.cmask_offset
,
1077 tex
->surface
.cmask_size
, 0xCCCCCCCC);
1079 if (tex
->surface
.htile_offset
) {
1080 uint32_t clear_value
= 0;
1082 if (sscreen
->info
.chip_class
>= GFX9
|| tex
->tc_compatible_htile
)
1083 clear_value
= 0x0000030F;
1085 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.htile_offset
,
1086 tex
->surface
.htile_size
, clear_value
);
1089 /* Initialize DCC only if the texture is not being imported. */
1090 if (!(surface
->flags
& RADEON_SURF_IMPORTED
) && tex
->surface
.dcc_offset
) {
1091 /* Clear DCC to black for all tiles with DCC enabled.
1093 * This fixes corruption in 3DMark Slingshot Extreme, which
1094 * uses uninitialized textures, causing corruption.
1096 if (tex
->surface
.num_dcc_levels
== tex
->buffer
.b
.b
.last_level
+ 1 &&
1097 tex
->buffer
.b
.b
.nr_samples
<= 2) {
1098 /* Simple case - all tiles have DCC enabled. */
1099 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
,
1100 tex
->surface
.dcc_size
, DCC_CLEAR_COLOR_0000
);
1101 } else if (sscreen
->info
.chip_class
>= GFX9
) {
1102 /* Clear to uncompressed. Clearing this to black is complicated. */
1103 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
,
1104 tex
->surface
.dcc_size
, DCC_UNCOMPRESSED
);
1106 /* GFX8: Initialize mipmap levels and multisamples separately. */
1107 if (tex
->buffer
.b
.b
.nr_samples
>= 2) {
1108 /* Clearing this to black is complicated. */
1109 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
,
1110 tex
->surface
.dcc_size
, DCC_UNCOMPRESSED
);
1112 /* Clear the enabled mipmap levels to black. */
1115 for (unsigned i
= 0; i
< tex
->surface
.num_dcc_levels
; i
++) {
1116 if (!tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
)
1119 size
= tex
->surface
.u
.legacy
.level
[i
].dcc_offset
+
1120 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
;
1123 /* Mipmap levels with DCC. */
1125 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
, size
,
1126 DCC_CLEAR_COLOR_0000
);
1128 /* Mipmap levels without DCC. */
1129 if (size
!= tex
->surface
.dcc_size
) {
1130 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
+ size
,
1131 tex
->surface
.dcc_size
- size
, DCC_UNCOMPRESSED
);
1136 /* Initialize displayable DCC that requires the retile blit. */
1137 if (tex
->surface
.dcc_retile_map_offset
) {
1138 /* Uninitialized DCC can hang the display hw.
1139 * Clear to white to indicate that. */
1140 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.display_dcc_offset
,
1141 tex
->surface
.u
.gfx9
.display_dcc_size
, DCC_CLEAR_COLOR_1111
);
1143 /* Upload the DCC retile map.
1144 * Use a staging buffer for the upload, because
1145 * the buffer backing the texture is unmappable.
1147 bool use_uint16
= tex
->surface
.u
.gfx9
.dcc_retile_use_uint16
;
1148 unsigned num_elements
= tex
->surface
.u
.gfx9
.dcc_retile_num_elements
;
1149 struct si_resource
*buf
= si_aligned_buffer_create(screen
, 0, PIPE_USAGE_STREAM
,
1150 num_elements
* (use_uint16
? 2 : 4),
1151 sscreen
->info
.tcc_cache_line_size
);
1152 uint32_t *ui
= (uint32_t *)sscreen
->ws
->buffer_map(buf
->buf
, NULL
, PIPE_TRANSFER_WRITE
);
1153 uint16_t *us
= (uint16_t *)ui
;
1155 /* Upload the retile map into a staging buffer. */
1157 for (unsigned i
= 0; i
< num_elements
; i
++)
1158 us
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1160 for (unsigned i
= 0; i
< num_elements
; i
++)
1161 ui
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1164 /* Copy the staging buffer to the buffer backing the texture. */
1165 struct si_context
*sctx
= (struct si_context
*)sscreen
->aux_context
;
1167 assert(tex
->surface
.dcc_retile_map_offset
<= UINT_MAX
);
1168 simple_mtx_lock(&sscreen
->aux_context_lock
);
1169 si_sdma_copy_buffer(sctx
, &tex
->buffer
.b
.b
, &buf
->b
.b
, tex
->surface
.dcc_retile_map_offset
,
1170 0, buf
->b
.b
.width0
);
1171 sscreen
->aux_context
->flush(sscreen
->aux_context
, NULL
, 0);
1172 simple_mtx_unlock(&sscreen
->aux_context_lock
);
1174 si_resource_reference(&buf
, NULL
);
1178 /* Initialize the CMASK base register value. */
1179 tex
->cmask_base_address_reg
= (tex
->buffer
.gpu_address
+ tex
->surface
.cmask_offset
) >> 8;
1181 if (sscreen
->debug_flags
& DBG(VM
)) {
1183 "VM start=0x%" PRIX64
" end=0x%" PRIX64
1184 " | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1185 tex
->buffer
.gpu_address
, tex
->buffer
.gpu_address
+ tex
->buffer
.buf
->size
,
1186 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+ 1,
1187 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1190 if (sscreen
->debug_flags
& DBG(TEX
)) {
1192 struct u_log_context log
;
1193 u_log_context_init(&log
);
1194 si_print_texture_info(sscreen
, tex
, &log
);
1195 u_log_new_page_print(&log
, stdout
);
1197 u_log_context_destroy(&log
);
1204 if (sscreen
->info
.chip_class
>= GFX9
)
1205 free(surface
->u
.gfx9
.dcc_retile_map
);
1209 static enum radeon_surf_mode
si_choose_tiling(struct si_screen
*sscreen
,
1210 const struct pipe_resource
*templ
,
1211 bool tc_compatible_htile
)
1213 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1214 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
;
1215 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1216 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1218 /* MSAA resources must be 2D tiled. */
1219 if (templ
->nr_samples
> 1)
1220 return RADEON_SURF_MODE_2D
;
1222 /* Transfer resources should be linear. */
1223 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1224 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1226 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on GFX8,
1227 * which requires 2D tiling.
1229 if (sscreen
->info
.chip_class
== GFX8
&& tc_compatible_htile
)
1230 return RADEON_SURF_MODE_2D
;
1232 /* Handle common candidates for the linear mode.
1233 * Compressed textures and DB surfaces must always be tiled.
1235 if (!force_tiling
&& !is_depth_stencil
&& !util_format_is_compressed(templ
->format
)) {
1236 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1237 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1239 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1240 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1241 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1243 /* Cursors are linear on AMD GCN.
1244 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1245 if (templ
->bind
& PIPE_BIND_CURSOR
)
1246 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1248 if (templ
->bind
& PIPE_BIND_LINEAR
)
1249 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1251 /* Textures with a very small height are recommended to be linear. */
1252 if (templ
->target
== PIPE_TEXTURE_1D
|| templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1253 /* Only very thin and long 2D textures should benefit from
1254 * linear_aligned. */
1255 (templ
->width0
> 8 && templ
->height0
<= 2))
1256 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1258 /* Textures likely to be mapped often. */
1259 if (templ
->usage
== PIPE_USAGE_STAGING
|| templ
->usage
== PIPE_USAGE_STREAM
)
1260 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1263 /* Make small textures 1D tiled. */
1264 if (templ
->width0
<= 16 || templ
->height0
<= 16 || (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1265 return RADEON_SURF_MODE_1D
;
1267 /* The allocator will switch to 1D if needed. */
1268 return RADEON_SURF_MODE_2D
;
1271 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1272 const struct pipe_resource
*templ
)
1274 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1275 bool is_zs
= util_format_is_depth_or_stencil(templ
->format
);
1277 if (templ
->nr_samples
>= 2) {
1278 /* This is hackish (overwriting the const pipe_resource template),
1279 * but should be harmless and state trackers can also see
1280 * the overriden number of samples in the created pipe_resource.
1282 if (is_zs
&& sscreen
->eqaa_force_z_samples
) {
1283 ((struct pipe_resource
*)templ
)->nr_samples
=
1284 ((struct pipe_resource
*)templ
)->nr_storage_samples
= sscreen
->eqaa_force_z_samples
;
1285 } else if (!is_zs
&& sscreen
->eqaa_force_color_samples
) {
1286 ((struct pipe_resource
*)templ
)->nr_samples
= sscreen
->eqaa_force_coverage_samples
;
1287 ((struct pipe_resource
*)templ
)->nr_storage_samples
= sscreen
->eqaa_force_color_samples
;
1291 bool is_flushed_depth
=
1292 templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
|| templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
;
1293 bool tc_compatible_htile
=
1294 sscreen
->info
.chip_class
>= GFX8
&&
1295 /* There are issues with TC-compatible HTILE on Tonga (and
1296 * Iceland is the same design), and documented bug workarounds
1297 * don't help. For example, this fails:
1298 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1300 sscreen
->info
.family
!= CHIP_TONGA
&& sscreen
->info
.family
!= CHIP_ICELAND
&&
1301 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1302 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) && !is_flushed_depth
&&
1303 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1305 enum radeon_surf_mode tile_mode
= si_choose_tiling(sscreen
, templ
, tc_compatible_htile
);
1307 /* This allocates textures with multiple planes like NV12 in 1 buffer. */
1310 SI_TEXTURE_MAX_PLANES
= 3
1312 struct radeon_surf surface
[SI_TEXTURE_MAX_PLANES
] = {};
1313 struct pipe_resource plane_templ
[SI_TEXTURE_MAX_PLANES
];
1314 uint64_t plane_offset
[SI_TEXTURE_MAX_PLANES
] = {};
1315 uint64_t total_size
= 0;
1316 unsigned max_alignment
= 0;
1317 unsigned num_planes
= util_format_get_num_planes(templ
->format
);
1318 assert(num_planes
<= SI_TEXTURE_MAX_PLANES
);
1320 /* Compute texture or plane layouts and offsets. */
1321 for (unsigned i
= 0; i
< num_planes
; i
++) {
1322 plane_templ
[i
] = *templ
;
1323 plane_templ
[i
].format
= util_format_get_plane_format(templ
->format
, i
);
1324 plane_templ
[i
].width0
= util_format_get_plane_width(templ
->format
, i
, templ
->width0
);
1325 plane_templ
[i
].height0
= util_format_get_plane_height(templ
->format
, i
, templ
->height0
);
1327 /* Multi-plane allocations need PIPE_BIND_SHARED, because we can't
1328 * reallocate the storage to add PIPE_BIND_SHARED, because it's
1329 * shared by 3 pipe_resources.
1332 plane_templ
[i
].bind
|= PIPE_BIND_SHARED
;
1334 if (si_init_surface(sscreen
, &surface
[i
], &plane_templ
[i
], tile_mode
, false,
1335 plane_templ
[i
].bind
& PIPE_BIND_SCANOUT
, is_flushed_depth
,
1336 tc_compatible_htile
))
1339 plane_offset
[i
] = align64(total_size
, surface
[i
].surf_alignment
);
1340 total_size
= plane_offset
[i
] + surface
[i
].total_size
;
1341 max_alignment
= MAX2(max_alignment
, surface
[i
].surf_alignment
);
1344 struct si_texture
*plane0
= NULL
, *last_plane
= NULL
;
1346 for (unsigned i
= 0; i
< num_planes
; i
++) {
1347 struct si_texture
*tex
=
1348 si_texture_create_object(screen
, &plane_templ
[i
], &surface
[i
], plane0
, NULL
,
1349 plane_offset
[i
], 0, total_size
, max_alignment
);
1351 si_texture_reference(&plane0
, NULL
);
1355 tex
->plane_index
= i
;
1356 tex
->num_planes
= num_planes
;
1359 plane0
= last_plane
= tex
;
1361 last_plane
->buffer
.b
.b
.next
= &tex
->buffer
.b
.b
;
1366 return (struct pipe_resource
*)plane0
;
1369 static struct pipe_resource
*si_texture_from_winsys_buffer(struct si_screen
*sscreen
,
1370 const struct pipe_resource
*templ
,
1371 struct pb_buffer
*buf
, unsigned stride
,
1372 uint64_t offset
, unsigned usage
,
1375 struct radeon_surf surface
= {};
1376 struct radeon_bo_metadata metadata
= {};
1377 struct si_texture
*tex
;
1380 /* Ignore metadata for non-zero planes. */
1385 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
, &surface
);
1388 * The bo metadata is unset for un-dedicated images. So we fall
1389 * back to linear. See answer to question 5 of the
1390 * VK_KHX_external_memory spec for some details.
1392 * It is possible that this case isn't going to work if the
1393 * surface pitch isn't correctly aligned by default.
1395 * In order to support it correctly we require multi-image
1396 * metadata to be syncrhonized between radv and radeonsi. The
1397 * semantics of associating multiple image metadata to a memory
1398 * object on the vulkan export side are not concretely defined
1401 * All the use cases we are aware of at the moment for memory
1402 * objects use dedicated allocations. So lets keep the initial
1403 * implementation simple.
1405 * A possible alternative is to attempt to reconstruct the
1406 * tiling information when the TexParameter TEXTURE_TILING_EXT
1409 metadata
.mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1412 r
= si_init_surface(sscreen
, &surface
, templ
, metadata
.mode
, true,
1413 surface
.flags
& RADEON_SURF_SCANOUT
, false, false);
1417 tex
= si_texture_create_object(&sscreen
->b
, templ
, &surface
, NULL
, buf
,
1418 offset
, stride
, 0, 0);
1422 tex
->buffer
.b
.is_shared
= true;
1423 tex
->buffer
.external_usage
= usage
;
1424 tex
->num_planes
= 1;
1426 /* Account for multiple planes with lowered yuv import. */
1427 struct pipe_resource
*next_plane
= tex
->buffer
.b
.b
.next
;
1429 struct si_texture
*next_tex
= (struct si_texture
*)next_plane
;
1430 ++next_tex
->num_planes
;
1432 next_plane
= next_plane
->next
;
1435 if (!ac_surface_set_umd_metadata(&sscreen
->info
, &tex
->surface
,
1436 tex
->buffer
.b
.b
.nr_storage_samples
,
1437 tex
->buffer
.b
.b
.last_level
+ 1,
1438 metadata
.size_metadata
,
1439 metadata
.metadata
)) {
1440 si_texture_reference(&tex
, NULL
);
1444 /* Displayable DCC requires an explicit flush. */
1445 if (dedicated
&& offset
== 0 && !(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
1446 si_has_displayable_dcc(tex
)) {
1447 /* TODO: do we need to decompress DCC? */
1448 if (si_texture_discard_dcc(sscreen
, tex
)) {
1449 /* Update BO metadata after disabling DCC. */
1450 si_set_tex_bo_metadata(sscreen
, tex
);
1454 assert(tex
->surface
.tile_swizzle
== 0);
1455 return &tex
->buffer
.b
.b
;
1458 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1459 const struct pipe_resource
*templ
,
1460 struct winsys_handle
*whandle
, unsigned usage
)
1462 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1463 struct pb_buffer
*buf
= NULL
;
1465 /* Support only 2D textures without mipmaps */
1466 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
&&
1467 templ
->target
!= PIPE_TEXTURE_2D_ARRAY
) ||
1468 templ
->last_level
!= 0)
1471 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, sscreen
->info
.max_alignment
);
1475 return si_texture_from_winsys_buffer(sscreen
, templ
, buf
, whandle
->stride
, whandle
->offset
,
1479 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
, struct pipe_resource
*texture
)
1481 struct si_texture
*tex
= (struct si_texture
*)texture
;
1482 struct pipe_resource resource
;
1483 enum pipe_format pipe_format
= texture
->format
;
1485 assert(!tex
->flushed_depth_texture
);
1487 if (!tex
->can_sample_z
&& tex
->can_sample_s
) {
1488 switch (pipe_format
) {
1489 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1490 /* Save memory by not allocating the S plane. */
1491 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1493 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1494 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1495 /* Save memory bandwidth by not copying the
1496 * stencil part during flush.
1498 * This potentially increases memory bandwidth
1499 * if an application uses both Z and S texturing
1500 * simultaneously (a flushed Z24S8 texture
1501 * would be stored compactly), but how often
1502 * does that really happen?
1504 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1508 } else if (!tex
->can_sample_s
&& tex
->can_sample_z
) {
1509 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1511 /* DB->CB copies to an 8bpp surface don't work. */
1512 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1515 memset(&resource
, 0, sizeof(resource
));
1516 resource
.target
= texture
->target
;
1517 resource
.format
= pipe_format
;
1518 resource
.width0
= texture
->width0
;
1519 resource
.height0
= texture
->height0
;
1520 resource
.depth0
= texture
->depth0
;
1521 resource
.array_size
= texture
->array_size
;
1522 resource
.last_level
= texture
->last_level
;
1523 resource
.nr_samples
= texture
->nr_samples
;
1524 resource
.usage
= PIPE_USAGE_DEFAULT
;
1525 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1526 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1528 tex
->flushed_depth_texture
=
1529 (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1530 if (!tex
->flushed_depth_texture
) {
1531 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1538 * Initialize the pipe_resource descriptor to be of the same size as the box,
1539 * which is supposed to hold a subregion of the texture "orig" at the given
1542 static void si_init_temp_resource_from_box(struct pipe_resource
*res
, struct pipe_resource
*orig
,
1543 const struct pipe_box
*box
, unsigned level
,
1546 memset(res
, 0, sizeof(*res
));
1547 res
->format
= orig
->format
;
1548 res
->width0
= box
->width
;
1549 res
->height0
= box
->height
;
1551 res
->array_size
= 1;
1552 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1555 if (flags
& SI_RESOURCE_FLAG_TRANSFER
&& util_format_is_compressed(orig
->format
)) {
1556 /* Transfer resources are allocated with linear tiling, which is
1557 * not supported for compressed formats.
1559 unsigned blocksize
= util_format_get_blocksize(orig
->format
);
1561 if (blocksize
== 8) {
1562 res
->format
= PIPE_FORMAT_R16G16B16A16_UINT
;
1564 assert(blocksize
== 16);
1565 res
->format
= PIPE_FORMAT_R32G32B32A32_UINT
;
1568 res
->width0
= util_format_get_nblocksx(orig
->format
, box
->width
);
1569 res
->height0
= util_format_get_nblocksy(orig
->format
, box
->height
);
1572 /* We must set the correct texture target and dimensions for a 3D box. */
1573 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1574 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1575 res
->array_size
= box
->depth
;
1577 res
->target
= PIPE_TEXTURE_2D
;
1581 static bool si_can_invalidate_texture(struct si_screen
*sscreen
, struct si_texture
*tex
,
1582 unsigned transfer_usage
, const struct pipe_box
*box
)
1584 return !tex
->buffer
.b
.is_shared
&& !(tex
->surface
.flags
& RADEON_SURF_IMPORTED
) &&
1585 !(transfer_usage
& PIPE_TRANSFER_READ
) && tex
->buffer
.b
.b
.last_level
== 0 &&
1586 util_texrange_covers_whole_level(&tex
->buffer
.b
.b
, 0, box
->x
, box
->y
, box
->z
, box
->width
,
1587 box
->height
, box
->depth
);
1590 static void si_texture_invalidate_storage(struct si_context
*sctx
, struct si_texture
*tex
)
1592 struct si_screen
*sscreen
= sctx
->screen
;
1594 /* There is no point in discarding depth and tiled buffers. */
1595 assert(!tex
->is_depth
);
1596 assert(tex
->surface
.is_linear
);
1598 /* Reallocate the buffer in the same pipe_resource. */
1599 si_alloc_resource(sscreen
, &tex
->buffer
);
1601 /* Initialize the CMASK base address (needed even without CMASK). */
1602 tex
->cmask_base_address_reg
= (tex
->buffer
.gpu_address
+ tex
->surface
.cmask_offset
) >> 8;
1604 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1606 sctx
->num_alloc_tex_transfer_bytes
+= tex
->surface
.total_size
;
1609 static void *si_texture_transfer_map(struct pipe_context
*ctx
, struct pipe_resource
*texture
,
1610 unsigned level
, unsigned usage
, const struct pipe_box
*box
,
1611 struct pipe_transfer
**ptransfer
)
1613 struct si_context
*sctx
= (struct si_context
*)ctx
;
1614 struct si_texture
*tex
= (struct si_texture
*)texture
;
1615 struct si_transfer
*trans
;
1616 struct si_resource
*buf
;
1617 unsigned offset
= 0;
1619 bool use_staging_texture
= false;
1621 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
1622 assert(box
->width
&& box
->height
&& box
->depth
);
1624 /* If we are uploading into FP16 or R11G11B10_FLOAT via a blit, CB clobbers NaNs,
1625 * so in order to preserve them exactly, we have to use the compute blit.
1626 * The compute blit is used only when the destination doesn't have DCC, so
1627 * disable it here, which is kinda a hack.
1629 * This makes KHR-GL45.texture_view.view_classes pass on gfx9.
1630 * gfx10 has the same issue, but the test doesn't use a large enough texture
1631 * to enable DCC and fail, so it always passes.
1633 const struct util_format_description
*desc
= util_format_description(texture
->format
);
1634 if (vi_dcc_enabled(tex
, level
) &&
1635 desc
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
&&
1636 desc
->channel
[0].size
< 32)
1637 si_texture_disable_dcc(sctx
, tex
);
1639 if (tex
->is_depth
) {
1640 /* Depth textures use staging unconditionally. */
1641 use_staging_texture
= true;
1643 /* Degrade the tile mode if we get too many transfers on APUs.
1644 * On dGPUs, the staging texture is always faster.
1645 * Only count uploads that are at least 4x4 pixels large.
1647 if (!sctx
->screen
->info
.has_dedicated_vram
&& level
== 0 && box
->width
>= 4 &&
1648 box
->height
>= 4 && p_atomic_inc_return(&tex
->num_level0_transfers
) == 10) {
1649 bool can_invalidate
= si_can_invalidate_texture(sctx
->screen
, tex
, usage
, box
);
1651 si_reallocate_texture_inplace(sctx
, tex
, PIPE_BIND_LINEAR
, can_invalidate
);
1654 /* Tiled textures need to be converted into a linear texture for CPU
1655 * access. The staging texture is always linear and is placed in GART.
1657 * Reading from VRAM or GTT WC is slow, always use the staging
1658 * texture in this case.
1660 * Use the staging texture for uploads if the underlying BO
1663 if (!tex
->surface
.is_linear
)
1664 use_staging_texture
= true;
1665 else if (usage
& PIPE_TRANSFER_READ
)
1666 use_staging_texture
=
1667 tex
->buffer
.domains
& RADEON_DOMAIN_VRAM
|| tex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
1668 /* Write & linear only: */
1669 else if (si_rings_is_buffer_referenced(sctx
, tex
->buffer
.buf
, RADEON_USAGE_READWRITE
) ||
1670 !sctx
->ws
->buffer_wait(tex
->buffer
.buf
, 0, RADEON_USAGE_READWRITE
)) {
1672 if (si_can_invalidate_texture(sctx
->screen
, tex
, usage
, box
))
1673 si_texture_invalidate_storage(sctx
, tex
);
1675 use_staging_texture
= true;
1679 trans
= CALLOC_STRUCT(si_transfer
);
1682 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1683 trans
->b
.b
.level
= level
;
1684 trans
->b
.b
.usage
= usage
;
1685 trans
->b
.b
.box
= *box
;
1687 if (use_staging_texture
) {
1688 struct pipe_resource resource
;
1689 struct si_texture
*staging
;
1691 si_init_temp_resource_from_box(&resource
, texture
, box
, level
, SI_RESOURCE_FLAG_TRANSFER
);
1692 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ? PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1694 /* Since depth-stencil textures don't support linear tiling,
1695 * blit from ZS to color and vice versa. u_blitter will do
1696 * the packing for these formats.
1699 resource
.format
= util_blitter_get_color_format_for_zs(resource
.format
);
1701 /* Create the temporary texture. */
1702 staging
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1704 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1707 trans
->staging
= &staging
->buffer
;
1709 /* Just get the strides. */
1710 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
, &trans
->b
.b
.stride
,
1711 &trans
->b
.b
.layer_stride
);
1713 if (usage
& PIPE_TRANSFER_READ
)
1714 si_copy_to_staging_texture(ctx
, trans
);
1716 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1718 buf
= trans
->staging
;
1720 /* the resource is mapped directly */
1721 offset
= si_texture_get_offset(sctx
->screen
, tex
, level
, box
, &trans
->b
.b
.stride
,
1722 &trans
->b
.b
.layer_stride
);
1726 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1727 * we don't run out of the CPU address space.
1729 if (sizeof(void *) == 4)
1730 usage
|= RADEON_TRANSFER_TEMPORARY
;
1732 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
1735 *ptransfer
= &trans
->b
.b
;
1736 return map
+ offset
;
1739 si_resource_reference(&trans
->staging
, NULL
);
1740 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
1745 static void si_texture_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*transfer
)
1747 struct si_context
*sctx
= (struct si_context
*)ctx
;
1748 struct si_transfer
*stransfer
= (struct si_transfer
*)transfer
;
1749 struct pipe_resource
*texture
= transfer
->resource
;
1750 struct si_texture
*tex
= (struct si_texture
*)texture
;
1752 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1753 * we don't run out of the CPU address space.
1755 if (sizeof(void *) == 4) {
1756 struct si_resource
*buf
= stransfer
->staging
? stransfer
->staging
: &tex
->buffer
;
1758 sctx
->ws
->buffer_unmap(buf
->buf
);
1761 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && stransfer
->staging
)
1762 si_copy_from_staging_texture(ctx
, stransfer
);
1764 if (stransfer
->staging
) {
1765 sctx
->num_alloc_tex_transfer_bytes
+= stransfer
->staging
->buf
->size
;
1766 si_resource_reference(&stransfer
->staging
, NULL
);
1769 /* Heuristic for {upload, draw, upload, draw, ..}:
1771 * Flush the gfx IB if we've allocated too much texture storage.
1773 * The idea is that we don't want to build IBs that use too much
1774 * memory and put pressure on the kernel memory manager and we also
1775 * want to make temporary and invalidated buffers go idle ASAP to
1776 * decrease the total memory usage or make them reusable. The memory
1777 * usage will be slightly higher than given here because of the buffer
1778 * cache in the winsys.
1780 * The result is that the kernel memory manager is never a bottleneck.
1782 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
1783 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1784 sctx
->num_alloc_tex_transfer_bytes
= 0;
1787 pipe_resource_reference(&transfer
->resource
, NULL
);
1791 static const struct u_resource_vtbl si_texture_vtbl
= {
1792 NULL
, /* get_handle */
1793 si_texture_destroy
, /* resource_destroy */
1794 si_texture_transfer_map
, /* transfer_map */
1795 u_default_transfer_flush_region
, /* transfer_flush_region */
1796 si_texture_transfer_unmap
, /* transfer_unmap */
1799 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
1801 bool vi_dcc_formats_compatible(struct si_screen
*sscreen
, enum pipe_format format1
,
1802 enum pipe_format format2
)
1804 const struct util_format_description
*desc1
, *desc2
;
1806 /* No format change - exit early. */
1807 if (format1
== format2
)
1810 format1
= si_simplify_cb_format(format1
);
1811 format2
= si_simplify_cb_format(format2
);
1813 /* Check again after format adjustments. */
1814 if (format1
== format2
)
1817 desc1
= util_format_description(format1
);
1818 desc2
= util_format_description(format2
);
1820 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
|| desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1823 /* Float and non-float are totally incompatible. */
1824 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
1825 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
1828 /* Channel sizes must match across DCC formats.
1829 * Comparing just the first 2 channels should be enough.
1831 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
1832 (desc1
->nr_channels
>= 2 && desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
1835 /* Everything below is not needed if the driver never uses the DCC
1836 * clear code with the value of 1.
1839 /* If the clear values are all 1 or all 0, this constraint can be
1841 if (vi_alpha_is_on_msb(sscreen
, format1
) != vi_alpha_is_on_msb(sscreen
, format2
))
1844 /* Channel types must match if the clear value of 1 is used.
1845 * The type categories are only float, signed, unsigned.
1846 * NORM and INT are always compatible.
1848 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
1849 (desc1
->nr_channels
>= 2 && desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
1855 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
, unsigned level
,
1856 enum pipe_format view_format
)
1858 struct si_texture
*stex
= (struct si_texture
*)tex
;
1860 return vi_dcc_enabled(stex
, level
) &&
1861 !vi_dcc_formats_compatible((struct si_screen
*)tex
->screen
, tex
->format
, view_format
);
1864 /* This can't be merged with the above function, because
1865 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1866 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
, struct pipe_resource
*tex
,
1867 unsigned level
, enum pipe_format view_format
)
1869 struct si_texture
*stex
= (struct si_texture
*)tex
;
1871 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
1872 if (!si_texture_disable_dcc(sctx
, stex
))
1873 si_decompress_dcc(sctx
, stex
);
1876 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1877 struct pipe_resource
*texture
,
1878 const struct pipe_surface
*templ
, unsigned width0
,
1879 unsigned height0
, unsigned width
, unsigned height
)
1881 struct si_surface
*surface
= CALLOC_STRUCT(si_surface
);
1886 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1887 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1889 pipe_reference_init(&surface
->base
.reference
, 1);
1890 pipe_resource_reference(&surface
->base
.texture
, texture
);
1891 surface
->base
.context
= pipe
;
1892 surface
->base
.format
= templ
->format
;
1893 surface
->base
.width
= width
;
1894 surface
->base
.height
= height
;
1895 surface
->base
.u
= templ
->u
;
1897 surface
->width0
= width0
;
1898 surface
->height0
= height0
;
1900 surface
->dcc_incompatible
=
1901 texture
->target
!= PIPE_BUFFER
&&
1902 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
, templ
->format
);
1903 return &surface
->base
;
1906 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
, struct pipe_resource
*tex
,
1907 const struct pipe_surface
*templ
)
1909 unsigned level
= templ
->u
.tex
.level
;
1910 unsigned width
= u_minify(tex
->width0
, level
);
1911 unsigned height
= u_minify(tex
->height0
, level
);
1912 unsigned width0
= tex
->width0
;
1913 unsigned height0
= tex
->height0
;
1915 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1916 const struct util_format_description
*tex_desc
= util_format_description(tex
->format
);
1917 const struct util_format_description
*templ_desc
= util_format_description(templ
->format
);
1919 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1921 /* Adjust size of surface if and only if the block width or
1922 * height is changed. */
1923 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1924 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1925 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1926 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1928 width
= nblks_x
* templ_desc
->block
.width
;
1929 height
= nblks_y
* templ_desc
->block
.height
;
1931 width0
= util_format_get_nblocksx(tex
->format
, width0
);
1932 height0
= util_format_get_nblocksy(tex
->format
, height0
);
1936 return si_create_surface_custom(pipe
, tex
, templ
, width0
, height0
, width
, height
);
1939 static void si_surface_destroy(struct pipe_context
*pipe
, struct pipe_surface
*surface
)
1941 pipe_resource_reference(&surface
->texture
, NULL
);
1945 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1947 const struct util_format_description
*desc
= util_format_description(format
);
1949 #define HAS_SWIZZLE(chan, swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1951 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1952 return V_028C70_SWAP_STD
;
1954 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1957 switch (desc
->nr_channels
) {
1959 if (HAS_SWIZZLE(0, X
))
1960 return V_028C70_SWAP_STD
; /* X___ */
1961 else if (HAS_SWIZZLE(3, X
))
1962 return V_028C70_SWAP_ALT_REV
; /* ___X */
1965 if ((HAS_SWIZZLE(0, X
) && HAS_SWIZZLE(1, Y
)) || (HAS_SWIZZLE(0, X
) && HAS_SWIZZLE(1, NONE
)) ||
1966 (HAS_SWIZZLE(0, NONE
) && HAS_SWIZZLE(1, Y
)))
1967 return V_028C70_SWAP_STD
; /* XY__ */
1968 else if ((HAS_SWIZZLE(0, Y
) && HAS_SWIZZLE(1, X
)) ||
1969 (HAS_SWIZZLE(0, Y
) && HAS_SWIZZLE(1, NONE
)) ||
1970 (HAS_SWIZZLE(0, NONE
) && HAS_SWIZZLE(1, X
)))
1972 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
1973 else if (HAS_SWIZZLE(0, X
) && HAS_SWIZZLE(3, Y
))
1974 return V_028C70_SWAP_ALT
; /* X__Y */
1975 else if (HAS_SWIZZLE(0, Y
) && HAS_SWIZZLE(3, X
))
1976 return V_028C70_SWAP_ALT_REV
; /* Y__X */
1979 if (HAS_SWIZZLE(0, X
))
1980 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
1981 else if (HAS_SWIZZLE(0, Z
))
1982 return V_028C70_SWAP_STD_REV
; /* ZYX */
1985 /* check the middle channels, the 1st and 4th channel can be NONE */
1986 if (HAS_SWIZZLE(1, Y
) && HAS_SWIZZLE(2, Z
)) {
1987 return V_028C70_SWAP_STD
; /* XYZW */
1988 } else if (HAS_SWIZZLE(1, Z
) && HAS_SWIZZLE(2, Y
)) {
1989 return V_028C70_SWAP_STD_REV
; /* WZYX */
1990 } else if (HAS_SWIZZLE(1, Y
) && HAS_SWIZZLE(2, X
)) {
1991 return V_028C70_SWAP_ALT
; /* ZYXW */
1992 } else if (HAS_SWIZZLE(1, Z
) && HAS_SWIZZLE(2, W
)) {
1995 return V_028C70_SWAP_ALT_REV
;
1997 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2004 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2006 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
, int slot
)
2010 if (sctx
->dcc_stats
[slot
].query_active
)
2011 vi_separate_dcc_stop_query(sctx
, sctx
->dcc_stats
[slot
].tex
);
2013 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2014 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2015 sctx
->b
.destroy_query(&sctx
->b
, sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2016 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2019 si_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2023 * Return the per-context slot where DCC statistics queries for the texture live.
2025 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
, struct si_texture
*tex
)
2027 int i
, empty_slot
= -1;
2029 /* Remove zombie textures (textures kept alive by this array only). */
2030 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2031 if (sctx
->dcc_stats
[i
].tex
&& sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2032 vi_dcc_clean_up_context_slot(sctx
, i
);
2034 /* Find the texture. */
2035 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2036 /* Return if found. */
2037 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2038 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2042 /* Record the first seen empty slot. */
2043 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2047 /* Not found. Remove the oldest member to make space in the array. */
2048 if (empty_slot
== -1) {
2049 int oldest_slot
= 0;
2051 /* Find the oldest slot. */
2052 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2053 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2054 sctx
->dcc_stats
[i
].last_use_timestamp
)
2057 /* Clean up the oldest slot. */
2058 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2059 empty_slot
= oldest_slot
;
2062 /* Add the texture to the new slot. */
2063 si_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2064 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2068 static struct pipe_query
*vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2070 struct si_query_hw
*query
=
2071 (struct si_query_hw
*)sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2073 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2074 return (struct pipe_query
*)query
;
2078 * Called when binding a color buffer.
2080 void vi_separate_dcc_start_query(struct si_context
*sctx
, struct si_texture
*tex
)
2082 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2084 assert(!sctx
->dcc_stats
[i
].query_active
);
2086 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2087 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2089 /* begin or resume the query */
2090 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2091 sctx
->dcc_stats
[i
].query_active
= true;
2095 * Called when unbinding a color buffer.
2097 void vi_separate_dcc_stop_query(struct si_context
*sctx
, struct si_texture
*tex
)
2099 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2101 assert(sctx
->dcc_stats
[i
].query_active
);
2102 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2104 /* pause or end the query */
2105 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2106 sctx
->dcc_stats
[i
].query_active
= false;
2109 static bool vi_should_enable_separate_dcc(struct si_texture
*tex
)
2111 /* The minimum number of fullscreen draws per frame that is required
2113 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2116 /* Called by fast clear. */
2117 void vi_separate_dcc_try_enable(struct si_context
*sctx
, struct si_texture
*tex
)
2119 /* The intent is to use this with shared displayable back buffers,
2120 * but it's not strictly limited only to them.
2122 if (!tex
->buffer
.b
.is_shared
||
2123 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2124 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
|| tex
->buffer
.b
.b
.last_level
> 0 ||
2125 !tex
->surface
.dcc_size
|| sctx
->screen
->debug_flags
& DBG(NO_DCC
) ||
2126 sctx
->screen
->debug_flags
& DBG(NO_DCC_FB
))
2129 assert(sctx
->chip_class
>= GFX8
);
2131 if (tex
->surface
.dcc_offset
)
2132 return; /* already enabled */
2134 /* Enable the DCC stat gathering. */
2135 if (!tex
->dcc_gather_statistics
) {
2136 tex
->dcc_gather_statistics
= true;
2137 vi_separate_dcc_start_query(sctx
, tex
);
2140 if (!vi_should_enable_separate_dcc(tex
))
2141 return; /* stats show that DCC decompression is too expensive */
2143 assert(tex
->surface
.num_dcc_levels
);
2144 assert(!tex
->dcc_separate_buffer
);
2146 si_texture_discard_cmask(sctx
->screen
, tex
);
2148 /* Get a DCC buffer. */
2149 if (tex
->last_dcc_separate_buffer
) {
2150 assert(tex
->dcc_gather_statistics
);
2151 assert(!tex
->dcc_separate_buffer
);
2152 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2153 tex
->last_dcc_separate_buffer
= NULL
;
2155 tex
->dcc_separate_buffer
=
2156 si_aligned_buffer_create(sctx
->b
.screen
, SI_RESOURCE_FLAG_UNMAPPABLE
, PIPE_USAGE_DEFAULT
,
2157 tex
->surface
.dcc_size
, tex
->surface
.dcc_alignment
);
2158 if (!tex
->dcc_separate_buffer
)
2162 /* dcc_offset is the absolute GPUVM address. */
2163 tex
->surface
.dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2165 /* no need to flag anything since this is called by fast clear that
2166 * flags framebuffer state
2171 * Called by pipe_context::flush_resource, the place where DCC decompression
2174 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
, struct si_texture
*tex
)
2176 struct si_context
*sctx
= (struct si_context
*)ctx
;
2177 struct pipe_query
*tmp
;
2178 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2179 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2180 bool disable
= false;
2182 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2183 union pipe_query_result result
;
2185 /* Read the results. */
2186 struct pipe_query
*query
= sctx
->dcc_stats
[i
].ps_stats
[2];
2187 ctx
->get_query_result(ctx
, query
, true, &result
);
2188 si_query_buffer_reset(sctx
, &((struct si_query_hw
*)query
)->buffer
);
2190 /* Compute the approximate number of fullscreen draws. */
2191 tex
->ps_draw_ratio
= result
.pipeline_statistics
.ps_invocations
/
2192 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2193 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2195 disable
= tex
->dcc_separate_buffer
&& !vi_should_enable_separate_dcc(tex
);
2198 tex
->num_slow_clears
= 0;
2200 /* stop the statistics query for ps_stats[0] */
2202 vi_separate_dcc_stop_query(sctx
, tex
);
2204 /* Move the queries in the queue by one. */
2205 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2206 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2207 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2208 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2210 /* create and start a new query as ps_stats[0] */
2212 vi_separate_dcc_start_query(sctx
, tex
);
2215 assert(!tex
->last_dcc_separate_buffer
);
2216 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2217 tex
->dcc_separate_buffer
= NULL
;
2218 tex
->surface
.dcc_offset
= 0;
2219 /* no need to flag anything since this is called after
2220 * decompression that re-sets framebuffer state
2225 static struct pipe_memory_object
*
2226 si_memobj_from_handle(struct pipe_screen
*screen
, struct winsys_handle
*whandle
, bool dedicated
)
2228 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2229 struct si_memory_object
*memobj
= CALLOC_STRUCT(si_memory_object
);
2230 struct pb_buffer
*buf
= NULL
;
2235 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, sscreen
->info
.max_alignment
);
2241 memobj
->b
.dedicated
= dedicated
;
2243 memobj
->stride
= whandle
->stride
;
2245 return (struct pipe_memory_object
*)memobj
;
2248 static void si_memobj_destroy(struct pipe_screen
*screen
, struct pipe_memory_object
*_memobj
)
2250 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2252 pb_reference(&memobj
->buf
, NULL
);
2256 static struct pipe_resource
*si_texture_from_memobj(struct pipe_screen
*screen
,
2257 const struct pipe_resource
*templ
,
2258 struct pipe_memory_object
*_memobj
,
2261 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2262 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2263 struct pipe_resource
*tex
= si_texture_from_winsys_buffer(
2264 sscreen
, templ
, memobj
->buf
, memobj
->stride
, offset
,
2265 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
| PIPE_HANDLE_USAGE_SHADER_WRITE
, memobj
->b
.dedicated
);
2269 /* si_texture_from_winsys_buffer doesn't increment refcount of
2270 * memobj->buf, so increment it here.
2272 struct pb_buffer
*buf
= NULL
;
2273 pb_reference(&buf
, memobj
->buf
);
2277 static bool si_check_resource_capability(struct pipe_screen
*screen
, struct pipe_resource
*resource
,
2280 struct si_texture
*tex
= (struct si_texture
*)resource
;
2282 /* Buffers only support the linear flag. */
2283 if (resource
->target
== PIPE_BUFFER
)
2284 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2286 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2289 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2292 /* TODO: PIPE_BIND_CURSOR - do we care? */
2296 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2298 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2299 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2300 sscreen
->b
.resource_get_param
= si_resource_get_param
;
2301 sscreen
->b
.resource_get_info
= si_texture_get_info
;
2302 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2303 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2304 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2305 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2308 void si_init_context_texture_functions(struct si_context
*sctx
)
2310 sctx
->b
.create_surface
= si_create_surface
;
2311 sctx
->b
.surface_destroy
= si_surface_destroy
;