2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeonsi/si_pipe.h"
27 #include "radeonsi/si_query.h"
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_resource.h"
33 #include "util/u_surface.h"
34 #include "util/u_transfer.h"
35 #include "util/os_time.h"
38 #include "state_tracker/drm_driver.h"
39 #include "amd/common/sid.h"
41 static enum radeon_surf_mode
42 si_choose_tiling(struct si_screen
*sscreen
,
43 const struct pipe_resource
*templ
, bool tc_compatible_htile
);
46 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
47 struct si_texture
*dst
,
48 unsigned dst_level
, unsigned dstx
,
49 unsigned dsty
, unsigned dstz
,
50 struct si_texture
*src
,
52 const struct pipe_box
*src_box
)
57 if (dst
->surface
.bpe
!= src
->surface
.bpe
)
60 /* MSAA: Blits don't exist in the real world. */
61 if (src
->buffer
.b
.b
.nr_samples
> 1 ||
62 dst
->buffer
.b
.b
.nr_samples
> 1)
65 /* Depth-stencil surfaces:
66 * When dst is linear, the DB->CB copy preserves HTILE.
67 * When dst is tiled, the 3D path must be used to update HTILE.
69 if (src
->is_depth
|| dst
->is_depth
)
73 * src: Use the 3D path. DCC decompression is expensive.
74 * dst: Use the 3D path to compress the pixels with DCC.
76 if (vi_dcc_enabled(src
, src_level
) ||
77 vi_dcc_enabled(dst
, dst_level
))
81 * src: Both texture and SDMA paths need decompression. Use SDMA.
82 * dst: If overwriting the whole texture, discard CMASK and use
83 * SDMA. Otherwise, use the 3D path.
85 if (dst
->cmask_buffer
&& dst
->dirty_level_mask
& (1 << dst_level
)) {
86 /* The CMASK clear is only enabled for the first level. */
87 assert(dst_level
== 0);
88 if (!util_texrange_covers_whole_level(&dst
->buffer
.b
.b
, dst_level
,
89 dstx
, dsty
, dstz
, src_box
->width
,
90 src_box
->height
, src_box
->depth
))
93 si_texture_discard_cmask(sctx
->screen
, dst
);
96 /* All requirements are met. Prepare textures for SDMA. */
97 if (src
->cmask_buffer
&& src
->dirty_level_mask
& (1 << src_level
))
98 sctx
->b
.flush_resource(&sctx
->b
, &src
->buffer
.b
.b
);
100 assert(!(src
->dirty_level_mask
& (1 << src_level
)));
101 assert(!(dst
->dirty_level_mask
& (1 << dst_level
)));
106 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
107 static void si_copy_region_with_blit(struct pipe_context
*pipe
,
108 struct pipe_resource
*dst
,
110 unsigned dstx
, unsigned dsty
, unsigned dstz
,
111 struct pipe_resource
*src
,
113 const struct pipe_box
*src_box
)
115 struct pipe_blit_info blit
;
117 memset(&blit
, 0, sizeof(blit
));
118 blit
.src
.resource
= src
;
119 blit
.src
.format
= src
->format
;
120 blit
.src
.level
= src_level
;
121 blit
.src
.box
= *src_box
;
122 blit
.dst
.resource
= dst
;
123 blit
.dst
.format
= dst
->format
;
124 blit
.dst
.level
= dst_level
;
125 blit
.dst
.box
.x
= dstx
;
126 blit
.dst
.box
.y
= dsty
;
127 blit
.dst
.box
.z
= dstz
;
128 blit
.dst
.box
.width
= src_box
->width
;
129 blit
.dst
.box
.height
= src_box
->height
;
130 blit
.dst
.box
.depth
= src_box
->depth
;
131 blit
.mask
= util_format_get_mask(src
->format
) &
132 util_format_get_mask(dst
->format
);
133 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
136 pipe
->blit(pipe
, &blit
);
140 /* Copy from a full GPU texture to a transfer's staging one. */
141 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
143 struct si_context
*sctx
= (struct si_context
*)ctx
;
144 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
145 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
146 struct pipe_resource
*src
= transfer
->resource
;
148 if (src
->nr_samples
> 1) {
149 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
150 src
, transfer
->level
, &transfer
->box
);
154 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
158 /* Copy from a transfer's staging texture to a full GPU one. */
159 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
161 struct si_context
*sctx
= (struct si_context
*)ctx
;
162 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
163 struct pipe_resource
*dst
= transfer
->resource
;
164 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
165 struct pipe_box sbox
;
167 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
169 if (dst
->nr_samples
> 1) {
170 si_copy_region_with_blit(ctx
, dst
, transfer
->level
,
171 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
176 sctx
->dma_copy(ctx
, dst
, transfer
->level
,
177 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
181 static unsigned si_texture_get_offset(struct si_screen
*sscreen
,
182 struct si_texture
*tex
, unsigned level
,
183 const struct pipe_box
*box
,
185 unsigned *layer_stride
)
187 if (sscreen
->info
.chip_class
>= GFX9
) {
188 *stride
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
189 *layer_stride
= tex
->surface
.u
.gfx9
.surf_slice_size
;
194 /* Each texture is an array of slices. Each slice is an array
195 * of mipmap levels. */
196 return box
->z
* tex
->surface
.u
.gfx9
.surf_slice_size
+
197 tex
->surface
.u
.gfx9
.offset
[level
] +
198 (box
->y
/ tex
->surface
.blk_h
*
199 tex
->surface
.u
.gfx9
.surf_pitch
+
200 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
202 *stride
= tex
->surface
.u
.legacy
.level
[level
].nblk_x
*
204 assert((uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
205 *layer_stride
= (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
208 return tex
->surface
.u
.legacy
.level
[level
].offset
;
210 /* Each texture is an array of mipmap levels. Each level is
211 * an array of slices. */
212 return tex
->surface
.u
.legacy
.level
[level
].offset
+
213 box
->z
* (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
214 (box
->y
/ tex
->surface
.blk_h
*
215 tex
->surface
.u
.legacy
.level
[level
].nblk_x
+
216 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
220 static int si_init_surface(struct si_screen
*sscreen
,
221 struct radeon_surf
*surface
,
222 const struct pipe_resource
*ptex
,
223 unsigned num_color_samples
,
224 enum radeon_surf_mode array_mode
,
225 unsigned pitch_in_bytes_override
,
229 bool is_flushed_depth
,
230 bool tc_compatible_htile
)
232 const struct util_format_description
*desc
=
233 util_format_description(ptex
->format
);
234 bool is_depth
, is_stencil
;
236 unsigned i
, bpe
, flags
= 0;
238 is_depth
= util_format_has_depth(desc
);
239 is_stencil
= util_format_has_stencil(desc
);
241 if (!is_flushed_depth
&&
242 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
243 bpe
= 4; /* stencil is allocated separately on evergreen */
245 bpe
= util_format_get_blocksize(ptex
->format
);
246 assert(util_is_power_of_two_or_zero(bpe
));
249 if (!is_flushed_depth
&& is_depth
) {
250 flags
|= RADEON_SURF_ZBUFFER
;
252 if (tc_compatible_htile
&&
253 (sscreen
->info
.chip_class
>= GFX9
||
254 array_mode
== RADEON_SURF_MODE_2D
)) {
255 /* TC-compatible HTILE only supports Z32_FLOAT.
256 * GFX9 also supports Z16_UNORM.
257 * On VI, promote Z16 to Z32. DB->CB copies will convert
258 * the format for transfers.
260 if (sscreen
->info
.chip_class
== VI
)
263 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
267 flags
|= RADEON_SURF_SBUFFER
;
270 if (sscreen
->info
.chip_class
>= VI
&&
271 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
||
272 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
273 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
274 flags
|= RADEON_SURF_DISABLE_DCC
;
276 /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */
277 if (sscreen
->info
.family
== CHIP_STONEY
&&
278 bpe
== 16 && ptex
->nr_samples
>= 2)
279 flags
|= RADEON_SURF_DISABLE_DCC
;
281 /* VI: DCC clear for 4x and 8x MSAA array textures unimplemented. */
282 if (sscreen
->info
.chip_class
== VI
&&
283 num_color_samples
>= 4 &&
284 ptex
->array_size
> 1)
285 flags
|= RADEON_SURF_DISABLE_DCC
;
287 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
288 if (sscreen
->info
.chip_class
>= GFX9
&&
289 num_color_samples
>= 4)
290 flags
|= RADEON_SURF_DISABLE_DCC
;
292 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
293 /* This should catch bugs in gallium users setting incorrect flags. */
294 assert(ptex
->nr_samples
<= 1 &&
295 ptex
->array_size
== 1 &&
297 ptex
->last_level
== 0 &&
298 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
300 flags
|= RADEON_SURF_SCANOUT
;
303 if (ptex
->bind
& PIPE_BIND_SHARED
)
304 flags
|= RADEON_SURF_SHAREABLE
;
306 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
307 if (!(ptex
->flags
& SI_RESOURCE_FLAG_FORCE_TILING
))
308 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
310 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, num_color_samples
,
311 flags
, bpe
, array_mode
, surface
);
316 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
318 if (sscreen
->info
.chip_class
>= GFX9
) {
320 surface
->u
.gfx9
.surf_pitch
= pitch
;
321 surface
->u
.gfx9
.surf_slice_size
=
322 (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
324 surface
->u
.gfx9
.surf_offset
= offset
;
327 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
328 surface
->u
.legacy
.level
[0].slice_size_dw
=
329 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
332 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
333 surface
->u
.legacy
.level
[i
].offset
+= offset
;
339 static void si_texture_init_metadata(struct si_screen
*sscreen
,
340 struct si_texture
*tex
,
341 struct radeon_bo_metadata
*metadata
)
343 struct radeon_surf
*surface
= &tex
->surface
;
345 memset(metadata
, 0, sizeof(*metadata
));
347 if (sscreen
->info
.chip_class
>= GFX9
) {
348 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
350 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
351 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
352 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
353 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
354 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
355 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
356 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
357 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
358 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
359 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
360 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
361 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
365 static void si_surface_import_metadata(struct si_screen
*sscreen
,
366 struct radeon_surf
*surf
,
367 struct radeon_bo_metadata
*metadata
,
368 enum radeon_surf_mode
*array_mode
,
371 if (sscreen
->info
.chip_class
>= GFX9
) {
372 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
373 *array_mode
= RADEON_SURF_MODE_2D
;
375 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
377 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
378 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
380 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
382 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
383 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
384 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
385 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
386 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
387 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
389 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
390 *array_mode
= RADEON_SURF_MODE_2D
;
391 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
392 *array_mode
= RADEON_SURF_MODE_1D
;
394 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
396 *is_scanout
= metadata
->u
.legacy
.scanout
;
400 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
401 struct si_texture
*tex
)
403 struct si_screen
*sscreen
= sctx
->screen
;
404 struct pipe_context
*ctx
= &sctx
->b
;
406 if (ctx
== sscreen
->aux_context
)
407 mtx_lock(&sscreen
->aux_context_lock
);
409 unsigned n
= sctx
->num_decompress_calls
;
410 ctx
->flush_resource(ctx
, &tex
->buffer
.b
.b
);
412 /* Flush only if any fast clear elimination took place. */
413 if (n
!= sctx
->num_decompress_calls
)
414 ctx
->flush(ctx
, NULL
, 0);
416 if (ctx
== sscreen
->aux_context
)
417 mtx_unlock(&sscreen
->aux_context_lock
);
420 void si_texture_discard_cmask(struct si_screen
*sscreen
,
421 struct si_texture
*tex
)
423 if (!tex
->cmask_buffer
)
426 assert(tex
->buffer
.b
.b
.nr_samples
<= 1);
429 tex
->cmask_base_address_reg
= tex
->buffer
.gpu_address
>> 8;
430 tex
->dirty_level_mask
= 0;
432 tex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
434 if (tex
->cmask_buffer
!= &tex
->buffer
)
435 r600_resource_reference(&tex
->cmask_buffer
, NULL
);
437 tex
->cmask_buffer
= NULL
;
439 /* Notify all contexts about the change. */
440 p_atomic_inc(&sscreen
->dirty_tex_counter
);
441 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
444 static bool si_can_disable_dcc(struct si_texture
*tex
)
446 /* We can't disable DCC if it can be written by another process. */
447 return tex
->dcc_offset
&&
448 (!tex
->buffer
.b
.is_shared
||
449 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
452 static bool si_texture_discard_dcc(struct si_screen
*sscreen
,
453 struct si_texture
*tex
)
455 if (!si_can_disable_dcc(tex
))
458 assert(tex
->dcc_separate_buffer
== NULL
);
463 /* Notify all contexts about the change. */
464 p_atomic_inc(&sscreen
->dirty_tex_counter
);
469 * Disable DCC for the texture. (first decompress, then discard metadata).
471 * There is unresolved multi-context synchronization issue between
472 * screen::aux_context and the current context. If applications do this with
473 * multiple contexts, it's already undefined behavior for them and we don't
474 * have to worry about that. The scenario is:
476 * If context 1 disables DCC and context 2 has queued commands that write
477 * to the texture via CB with DCC enabled, and the order of operations is
479 * context 2 queues draw calls rendering to the texture, but doesn't flush
480 * context 1 disables DCC and flushes
481 * context 1 & 2 reset descriptors and FB state
482 * context 2 flushes (new compressed tiles written by the draw calls)
483 * context 1 & 2 read garbage, because DCC is disabled, yet there are
486 * \param sctx the current context if you have one, or rscreen->aux_context
489 bool si_texture_disable_dcc(struct si_context
*sctx
,
490 struct si_texture
*tex
)
492 struct si_screen
*sscreen
= sctx
->screen
;
494 if (!si_can_disable_dcc(tex
))
497 if (&sctx
->b
== sscreen
->aux_context
)
498 mtx_lock(&sscreen
->aux_context_lock
);
500 /* Decompress DCC. */
501 si_decompress_dcc(sctx
, tex
);
502 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
504 if (&sctx
->b
== sscreen
->aux_context
)
505 mtx_unlock(&sscreen
->aux_context_lock
);
507 return si_texture_discard_dcc(sscreen
, tex
);
510 static void si_reallocate_texture_inplace(struct si_context
*sctx
,
511 struct si_texture
*tex
,
512 unsigned new_bind_flag
,
513 bool invalidate_storage
)
515 struct pipe_screen
*screen
= sctx
->b
.screen
;
516 struct si_texture
*new_tex
;
517 struct pipe_resource templ
= tex
->buffer
.b
.b
;
520 templ
.bind
|= new_bind_flag
;
522 if (tex
->buffer
.b
.is_shared
)
525 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
526 if (tex
->surface
.is_linear
)
529 /* This fails with MSAA, depth, and compressed textures. */
530 if (si_choose_tiling(sctx
->screen
, &templ
, false) !=
531 RADEON_SURF_MODE_LINEAR_ALIGNED
)
535 new_tex
= (struct si_texture
*)screen
->resource_create(screen
, &templ
);
539 /* Copy the pixels to the new texture. */
540 if (!invalidate_storage
) {
541 for (i
= 0; i
<= templ
.last_level
; i
++) {
545 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
546 util_num_layers(&templ
, i
), &box
);
548 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0,
549 &tex
->buffer
.b
.b
, i
, &box
);
553 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
554 si_texture_discard_cmask(sctx
->screen
, tex
);
555 si_texture_discard_dcc(sctx
->screen
, tex
);
558 /* Replace the structure fields of tex. */
559 tex
->buffer
.b
.b
.bind
= templ
.bind
;
560 pb_reference(&tex
->buffer
.buf
, new_tex
->buffer
.buf
);
561 tex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
562 tex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
563 tex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
564 tex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
565 tex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
566 tex
->buffer
.domains
= new_tex
->buffer
.domains
;
567 tex
->buffer
.flags
= new_tex
->buffer
.flags
;
569 tex
->surface
= new_tex
->surface
;
570 tex
->size
= new_tex
->size
;
571 si_texture_reference(&tex
->flushed_depth_texture
,
572 new_tex
->flushed_depth_texture
);
574 tex
->fmask_offset
= new_tex
->fmask_offset
;
575 tex
->cmask_offset
= new_tex
->cmask_offset
;
576 tex
->cmask_base_address_reg
= new_tex
->cmask_base_address_reg
;
578 if (tex
->cmask_buffer
== &tex
->buffer
)
579 tex
->cmask_buffer
= NULL
;
581 r600_resource_reference(&tex
->cmask_buffer
, NULL
);
583 if (new_tex
->cmask_buffer
== &new_tex
->buffer
)
584 tex
->cmask_buffer
= &tex
->buffer
;
586 r600_resource_reference(&tex
->cmask_buffer
, new_tex
->cmask_buffer
);
588 tex
->dcc_offset
= new_tex
->dcc_offset
;
589 tex
->cb_color_info
= new_tex
->cb_color_info
;
590 memcpy(tex
->color_clear_value
, new_tex
->color_clear_value
,
591 sizeof(tex
->color_clear_value
));
592 tex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
594 tex
->htile_offset
= new_tex
->htile_offset
;
595 tex
->depth_clear_value
= new_tex
->depth_clear_value
;
596 tex
->dirty_level_mask
= new_tex
->dirty_level_mask
;
597 tex
->stencil_dirty_level_mask
= new_tex
->stencil_dirty_level_mask
;
598 tex
->db_render_format
= new_tex
->db_render_format
;
599 tex
->stencil_clear_value
= new_tex
->stencil_clear_value
;
600 tex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
601 tex
->depth_cleared
= new_tex
->depth_cleared
;
602 tex
->stencil_cleared
= new_tex
->stencil_cleared
;
603 tex
->upgraded_depth
= new_tex
->upgraded_depth
;
604 tex
->db_compatible
= new_tex
->db_compatible
;
605 tex
->can_sample_z
= new_tex
->can_sample_z
;
606 tex
->can_sample_s
= new_tex
->can_sample_s
;
608 tex
->separate_dcc_dirty
= new_tex
->separate_dcc_dirty
;
609 tex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
610 r600_resource_reference(&tex
->dcc_separate_buffer
,
611 new_tex
->dcc_separate_buffer
);
612 r600_resource_reference(&tex
->last_dcc_separate_buffer
,
613 new_tex
->last_dcc_separate_buffer
);
615 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
616 assert(!tex
->htile_offset
);
617 assert(!tex
->cmask_buffer
);
618 assert(!tex
->surface
.fmask_size
);
619 assert(!tex
->dcc_offset
);
620 assert(!tex
->is_depth
);
623 si_texture_reference(&new_tex
, NULL
);
625 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
628 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
630 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
633 static void si_query_opaque_metadata(struct si_screen
*sscreen
,
634 struct si_texture
*tex
,
635 struct radeon_bo_metadata
*md
)
637 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
638 static const unsigned char swizzle
[] = {
645 bool is_array
= util_texture_is_array(res
->target
);
647 if (!sscreen
->info
.has_bo_metadata
)
650 assert(tex
->dcc_separate_buffer
== NULL
);
651 assert(tex
->surface
.fmask_size
== 0);
653 /* Metadata image format format version 1:
654 * [0] = 1 (metadata format identifier)
655 * [1] = (VENDOR_ID << 16) | PCI_ID
656 * [2:9] = image descriptor for the whole resource
657 * [2] is always 0, because the base address is cleared
658 * [9] is the DCC offset bits [39:8] from the beginning of
660 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
663 md
->metadata
[0] = 1; /* metadata image format version 1 */
665 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
666 md
->metadata
[1] = si_get_bo_metadata_word1(sscreen
);
668 si_make_texture_descriptor(sscreen
, tex
, true,
669 res
->target
, res
->format
,
670 swizzle
, 0, res
->last_level
, 0,
671 is_array
? res
->array_size
- 1 : 0,
672 res
->width0
, res
->height0
, res
->depth0
,
675 si_set_mutable_tex_desc_fields(sscreen
, tex
, &tex
->surface
.u
.legacy
.level
[0],
676 0, 0, tex
->surface
.blk_w
, false, desc
);
678 /* Clear the base address and set the relative DCC offset. */
680 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
681 desc
[7] = tex
->dcc_offset
>> 8;
683 /* Dwords [2:9] contain the image descriptor. */
684 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
685 md
->size_metadata
= 10 * 4;
687 /* Dwords [10:..] contain the mipmap level offsets. */
688 if (sscreen
->info
.chip_class
<= VI
) {
689 for (i
= 0; i
<= res
->last_level
; i
++)
690 md
->metadata
[10+i
] = tex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
692 md
->size_metadata
+= (1 + res
->last_level
) * 4;
696 static void si_apply_opaque_metadata(struct si_screen
*sscreen
,
697 struct si_texture
*tex
,
698 struct radeon_bo_metadata
*md
)
700 uint32_t *desc
= &md
->metadata
[2];
702 if (sscreen
->info
.chip_class
< VI
)
705 /* Return if DCC is enabled. The texture should be set up with it
708 if (md
->size_metadata
>= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
709 md
->metadata
[0] != 0 &&
710 md
->metadata
[1] == si_get_bo_metadata_word1(sscreen
) &&
711 G_008F28_COMPRESSION_EN(desc
[6])) {
712 tex
->dcc_offset
= (uint64_t)desc
[7] << 8;
716 /* Disable DCC. These are always set by texture_from_handle and must
722 static boolean
si_texture_get_handle(struct pipe_screen
* screen
,
723 struct pipe_context
*ctx
,
724 struct pipe_resource
*resource
,
725 struct winsys_handle
*whandle
,
728 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
729 struct si_context
*sctx
;
730 struct r600_resource
*res
= r600_resource(resource
);
731 struct si_texture
*tex
= (struct si_texture
*)resource
;
732 struct radeon_bo_metadata metadata
;
733 bool update_metadata
= false;
734 unsigned stride
, offset
, slice_size
;
737 ctx
= threaded_context_unwrap_sync(ctx
);
738 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
740 if (resource
->target
!= PIPE_BUFFER
) {
741 /* This is not supported now, but it might be required for OpenCL
742 * interop in the future.
744 if (resource
->nr_samples
> 1 || tex
->is_depth
)
747 /* Move a suballocated texture into a non-suballocated allocation. */
748 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
749 tex
->surface
.tile_swizzle
||
750 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
751 sscreen
->info
.has_local_buffers
&&
752 whandle
->type
!= WINSYS_HANDLE_TYPE_KMS
)) {
753 assert(!res
->b
.is_shared
);
754 si_reallocate_texture_inplace(sctx
, tex
,
755 PIPE_BIND_SHARED
, false);
757 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
758 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
759 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
760 assert(tex
->surface
.tile_swizzle
== 0);
763 /* Since shader image stores don't support DCC on VI,
764 * disable it for external clients that want write
767 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& tex
->dcc_offset
) {
768 if (si_texture_disable_dcc(sctx
, tex
)) {
769 update_metadata
= true;
770 /* si_texture_disable_dcc flushes the context */
775 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
776 (tex
->cmask_buffer
|| tex
->dcc_offset
)) {
777 /* Eliminate fast clear (both CMASK and DCC) */
778 si_eliminate_fast_color_clear(sctx
, tex
);
779 /* eliminate_fast_color_clear flushes the context */
782 /* Disable CMASK if flush_resource isn't going
785 if (tex
->cmask_buffer
)
786 si_texture_discard_cmask(sscreen
, tex
);
790 if (!res
->b
.is_shared
|| update_metadata
) {
791 si_texture_init_metadata(sscreen
, tex
, &metadata
);
792 si_query_opaque_metadata(sscreen
, tex
, &metadata
);
794 sscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
797 if (sscreen
->info
.chip_class
>= GFX9
) {
798 offset
= tex
->surface
.u
.gfx9
.surf_offset
;
799 stride
= tex
->surface
.u
.gfx9
.surf_pitch
*
801 slice_size
= tex
->surface
.u
.gfx9
.surf_slice_size
;
803 offset
= tex
->surface
.u
.legacy
.level
[0].offset
;
804 stride
= tex
->surface
.u
.legacy
.level
[0].nblk_x
*
806 slice_size
= (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
809 /* Buffer exports are for the OpenCL interop. */
810 /* Move a suballocated buffer into a non-suballocated allocation. */
811 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
812 /* A DMABUF export always fails if the BO is local. */
813 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
814 sscreen
->info
.has_local_buffers
)) {
815 assert(!res
->b
.is_shared
);
817 /* Allocate a new buffer with PIPE_BIND_SHARED. */
818 struct pipe_resource templ
= res
->b
.b
;
819 templ
.bind
|= PIPE_BIND_SHARED
;
821 struct pipe_resource
*newb
=
822 screen
->resource_create(screen
, &templ
);
826 /* Copy the old buffer contents to the new one. */
828 u_box_1d(0, newb
->width0
, &box
);
829 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0,
832 /* Move the new buffer storage to the old pipe_resource. */
833 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
834 pipe_resource_reference(&newb
, NULL
);
836 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
837 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
847 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
849 if (res
->b
.is_shared
) {
850 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
853 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
854 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
855 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
857 res
->b
.is_shared
= true;
858 res
->external_usage
= usage
;
861 return sscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
862 slice_size
, whandle
);
865 static void si_texture_destroy(struct pipe_screen
*screen
,
866 struct pipe_resource
*ptex
)
868 struct si_texture
*tex
= (struct si_texture
*)ptex
;
869 struct r600_resource
*resource
= &tex
->buffer
;
871 si_texture_reference(&tex
->flushed_depth_texture
, NULL
);
873 if (tex
->cmask_buffer
!= &tex
->buffer
) {
874 r600_resource_reference(&tex
->cmask_buffer
, NULL
);
876 pb_reference(&resource
->buf
, NULL
);
877 r600_resource_reference(&tex
->dcc_separate_buffer
, NULL
);
878 r600_resource_reference(&tex
->last_dcc_separate_buffer
, NULL
);
882 static const struct u_resource_vtbl si_texture_vtbl
;
884 static void si_texture_get_htile_size(struct si_screen
*sscreen
,
885 struct si_texture
*tex
)
887 unsigned cl_width
, cl_height
, width
, height
;
888 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
889 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
891 assert(sscreen
->info
.chip_class
<= VI
);
893 tex
->surface
.htile_size
= 0;
895 if (tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
896 !sscreen
->info
.htile_cmask_support_1d_tiling
)
899 /* Overalign HTILE on P2 configs to work around GPU hangs in
900 * piglit/depthstencil-render-miplevels 585.
902 * This has been confirmed to help Kabini & Stoney, where the hangs
903 * are always reproducible. I think I have seen the test hang
904 * on Carrizo too, though it was very rare there.
906 if (sscreen
->info
.chip_class
>= CIK
&& num_pipes
< 4)
935 width
= align(tex
->buffer
.b
.b
.width0
, cl_width
* 8);
936 height
= align(tex
->buffer
.b
.b
.height0
, cl_height
* 8);
938 slice_elements
= (width
* height
) / (8 * 8);
939 slice_bytes
= slice_elements
* 4;
941 pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
942 base_align
= num_pipes
* pipe_interleave_bytes
;
944 tex
->surface
.htile_alignment
= base_align
;
945 tex
->surface
.htile_size
=
946 util_num_layers(&tex
->buffer
.b
.b
, 0) *
947 align(slice_bytes
, base_align
);
950 static void si_texture_allocate_htile(struct si_screen
*sscreen
,
951 struct si_texture
*tex
)
953 if (sscreen
->info
.chip_class
<= VI
&& !tex
->tc_compatible_htile
)
954 si_texture_get_htile_size(sscreen
, tex
);
956 if (!tex
->surface
.htile_size
)
959 tex
->htile_offset
= align(tex
->size
, tex
->surface
.htile_alignment
);
960 tex
->size
= tex
->htile_offset
+ tex
->surface
.htile_size
;
963 void si_print_texture_info(struct si_screen
*sscreen
,
964 struct si_texture
*tex
, struct u_log_context
*log
)
968 /* Common parameters. */
969 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
970 "blk_h=%u, array_size=%u, last_level=%u, "
971 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
972 tex
->buffer
.b
.b
.width0
, tex
->buffer
.b
.b
.height0
,
973 tex
->buffer
.b
.b
.depth0
, tex
->surface
.blk_w
,
975 tex
->buffer
.b
.b
.array_size
, tex
->buffer
.b
.b
.last_level
,
976 tex
->surface
.bpe
, tex
->buffer
.b
.b
.nr_samples
,
977 tex
->surface
.flags
, util_format_short_name(tex
->buffer
.b
.b
.format
));
979 if (sscreen
->info
.chip_class
>= GFX9
) {
980 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
981 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
982 tex
->surface
.surf_size
,
983 tex
->surface
.u
.gfx9
.surf_slice_size
,
984 tex
->surface
.surf_alignment
,
985 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
986 tex
->surface
.u
.gfx9
.surf
.epitch
,
987 tex
->surface
.u
.gfx9
.surf_pitch
);
989 if (tex
->surface
.fmask_size
) {
990 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
991 "alignment=%u, swmode=%u, epitch=%u\n",
993 tex
->surface
.fmask_size
,
994 tex
->surface
.fmask_alignment
,
995 tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
996 tex
->surface
.u
.gfx9
.fmask
.epitch
);
999 if (tex
->cmask_buffer
) {
1000 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, "
1001 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1003 tex
->surface
.cmask_size
,
1004 tex
->surface
.cmask_alignment
,
1005 tex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1006 tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1009 if (tex
->htile_offset
) {
1010 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1011 "rb_aligned=%u, pipe_aligned=%u\n",
1013 tex
->surface
.htile_size
,
1014 tex
->surface
.htile_alignment
,
1015 tex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1016 tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1019 if (tex
->dcc_offset
) {
1020 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1021 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1022 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1023 tex
->surface
.dcc_alignment
,
1024 tex
->surface
.u
.gfx9
.dcc_pitch_max
,
1025 tex
->surface
.num_dcc_levels
);
1028 if (tex
->surface
.u
.gfx9
.stencil_offset
) {
1029 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1030 tex
->surface
.u
.gfx9
.stencil_offset
,
1031 tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1032 tex
->surface
.u
.gfx9
.stencil
.epitch
);
1037 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1038 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1039 tex
->surface
.surf_size
, tex
->surface
.surf_alignment
, tex
->surface
.u
.legacy
.bankw
,
1040 tex
->surface
.u
.legacy
.bankh
, tex
->surface
.u
.legacy
.num_banks
, tex
->surface
.u
.legacy
.mtilea
,
1041 tex
->surface
.u
.legacy
.tile_split
, tex
->surface
.u
.legacy
.pipe_config
,
1042 (tex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1044 if (tex
->surface
.fmask_size
)
1045 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1046 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1047 tex
->fmask_offset
, tex
->surface
.fmask_size
, tex
->surface
.fmask_alignment
,
1048 tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
,
1049 tex
->surface
.u
.legacy
.fmask
.bankh
,
1050 tex
->surface
.u
.legacy
.fmask
.slice_tile_max
,
1051 tex
->surface
.u
.legacy
.fmask
.tiling_index
);
1053 if (tex
->cmask_buffer
)
1054 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, alignment=%u, "
1055 "slice_tile_max=%u\n",
1056 tex
->cmask_offset
, tex
->surface
.cmask_size
, tex
->surface
.cmask_alignment
,
1057 tex
->surface
.u
.legacy
.cmask_slice_tile_max
);
1059 if (tex
->htile_offset
)
1060 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1061 "alignment=%u, TC_compatible = %u\n",
1062 tex
->htile_offset
, tex
->surface
.htile_size
,
1063 tex
->surface
.htile_alignment
,
1064 tex
->tc_compatible_htile
);
1066 if (tex
->dcc_offset
) {
1067 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1068 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1069 tex
->surface
.dcc_alignment
);
1070 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1071 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1072 "fast_clear_size=%u\n",
1073 i
, i
< tex
->surface
.num_dcc_levels
,
1074 tex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1075 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1078 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1079 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1080 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1081 "mode=%u, tiling_index = %u\n",
1082 i
, tex
->surface
.u
.legacy
.level
[i
].offset
,
1083 (uint64_t)tex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1084 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1085 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1086 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1087 tex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1088 tex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1089 tex
->surface
.u
.legacy
.level
[i
].mode
,
1090 tex
->surface
.u
.legacy
.tiling_index
[i
]);
1092 if (tex
->surface
.has_stencil
) {
1093 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1094 tex
->surface
.u
.legacy
.stencil_tile_split
);
1095 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++) {
1096 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1097 "slice_size=%"PRIu64
", npix_x=%u, "
1098 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1099 "mode=%u, tiling_index = %u\n",
1100 i
, tex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1101 (uint64_t)tex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1102 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1103 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1104 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1105 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1106 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1107 tex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1108 tex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1113 /* Common processing for si_texture_create and si_texture_from_handle */
1114 static struct si_texture
*
1115 si_texture_create_object(struct pipe_screen
*screen
,
1116 const struct pipe_resource
*base
,
1117 unsigned num_color_samples
,
1118 struct pb_buffer
*buf
,
1119 struct radeon_surf
*surface
)
1121 struct si_texture
*tex
;
1122 struct r600_resource
*resource
;
1123 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1125 tex
= CALLOC_STRUCT(si_texture
);
1129 resource
= &tex
->buffer
;
1130 resource
->b
.b
= *base
;
1131 resource
->b
.b
.next
= NULL
;
1132 resource
->b
.vtbl
= &si_texture_vtbl
;
1133 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1134 resource
->b
.b
.screen
= screen
;
1136 /* don't include stencil-only formats which we don't support for rendering */
1137 tex
->is_depth
= util_format_has_depth(util_format_description(tex
->buffer
.b
.b
.format
));
1139 tex
->surface
= *surface
;
1140 tex
->size
= tex
->surface
.surf_size
;
1141 tex
->num_color_samples
= num_color_samples
;
1143 tex
->tc_compatible_htile
= tex
->surface
.htile_size
!= 0 &&
1144 (tex
->surface
.flags
&
1145 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1147 /* TC-compatible HTILE:
1148 * - VI only supports Z32_FLOAT.
1149 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1150 if (tex
->tc_compatible_htile
) {
1151 if (sscreen
->info
.chip_class
>= GFX9
&&
1152 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1153 tex
->db_render_format
= base
->format
;
1155 tex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1156 tex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1157 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1160 tex
->db_render_format
= base
->format
;
1163 /* Applies to GCN. */
1164 tex
->last_msaa_resolve_target_micro_mode
= tex
->surface
.micro_tile_mode
;
1166 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1167 * between frames, so the only thing that can enable separate DCC
1168 * with DRI2 is multiple slow clears within a frame.
1170 tex
->ps_draw_ratio
= 0;
1172 if (tex
->is_depth
) {
1173 if (sscreen
->info
.chip_class
>= GFX9
) {
1174 tex
->can_sample_z
= true;
1175 tex
->can_sample_s
= true;
1177 tex
->can_sample_z
= !tex
->surface
.u
.legacy
.depth_adjusted
;
1178 tex
->can_sample_s
= !tex
->surface
.u
.legacy
.stencil_adjusted
;
1181 if (!(base
->flags
& (SI_RESOURCE_FLAG_TRANSFER
|
1182 SI_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1183 tex
->db_compatible
= true;
1185 if (!(sscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1186 si_texture_allocate_htile(sscreen
, tex
);
1189 if (base
->nr_samples
> 1 &&
1191 !(sscreen
->debug_flags
& DBG(NO_FMASK
))) {
1192 /* Allocate FMASK. */
1193 tex
->fmask_offset
= align64(tex
->size
,
1194 tex
->surface
.fmask_alignment
);
1195 tex
->size
= tex
->fmask_offset
+ tex
->surface
.fmask_size
;
1197 /* Allocate CMASK. */
1198 tex
->cmask_offset
= align64(tex
->size
, tex
->surface
.cmask_alignment
);
1199 tex
->size
= tex
->cmask_offset
+ tex
->surface
.cmask_size
;
1200 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
1201 tex
->cmask_buffer
= &tex
->buffer
;
1203 if (!tex
->surface
.fmask_size
|| !tex
->surface
.cmask_size
) {
1209 /* Shared textures must always set up DCC here.
1210 * If it's not present, it will be disabled by
1211 * apply_opaque_metadata later.
1213 if (tex
->surface
.dcc_size
&&
1214 (buf
|| !(sscreen
->debug_flags
& DBG(NO_DCC
))) &&
1215 !(tex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1216 /* Reserve space for the DCC buffer. */
1217 tex
->dcc_offset
= align64(tex
->size
, tex
->surface
.dcc_alignment
);
1218 tex
->size
= tex
->dcc_offset
+ tex
->surface
.dcc_size
;
1222 /* Now create the backing buffer. */
1224 si_init_resource_fields(sscreen
, resource
, tex
->size
,
1225 tex
->surface
.surf_alignment
);
1227 if (!si_alloc_resource(sscreen
, resource
)) {
1232 resource
->buf
= buf
;
1233 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1234 resource
->bo_size
= buf
->size
;
1235 resource
->bo_alignment
= buf
->alignment
;
1236 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1237 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1238 resource
->vram_usage
= buf
->size
;
1239 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1240 resource
->gart_usage
= buf
->size
;
1243 if (tex
->cmask_buffer
) {
1244 /* Initialize the cmask to 0xCC (= compressed state). */
1245 si_screen_clear_buffer(sscreen
, &tex
->cmask_buffer
->b
.b
,
1246 tex
->cmask_offset
, tex
->surface
.cmask_size
,
1249 if (tex
->htile_offset
) {
1250 uint32_t clear_value
= 0;
1252 if (sscreen
->info
.chip_class
>= GFX9
|| tex
->tc_compatible_htile
)
1253 clear_value
= 0x0000030F;
1255 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1257 tex
->surface
.htile_size
,
1261 /* Initialize DCC only if the texture is not being imported. */
1262 if (!buf
&& tex
->dcc_offset
) {
1263 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1265 tex
->surface
.dcc_size
,
1269 /* Initialize the CMASK base register value. */
1270 tex
->cmask_base_address_reg
=
1271 (tex
->buffer
.gpu_address
+ tex
->cmask_offset
) >> 8;
1273 if (sscreen
->debug_flags
& DBG(VM
)) {
1274 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1275 tex
->buffer
.gpu_address
,
1276 tex
->buffer
.gpu_address
+ tex
->buffer
.buf
->size
,
1277 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1278 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1281 if (sscreen
->debug_flags
& DBG(TEX
)) {
1283 struct u_log_context log
;
1284 u_log_context_init(&log
);
1285 si_print_texture_info(sscreen
, tex
, &log
);
1286 u_log_new_page_print(&log
, stdout
);
1288 u_log_context_destroy(&log
);
1294 static enum radeon_surf_mode
1295 si_choose_tiling(struct si_screen
*sscreen
,
1296 const struct pipe_resource
*templ
, bool tc_compatible_htile
)
1298 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1299 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_TILING
;
1300 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1301 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1303 /* MSAA resources must be 2D tiled. */
1304 if (templ
->nr_samples
> 1)
1305 return RADEON_SURF_MODE_2D
;
1307 /* Transfer resources should be linear. */
1308 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1309 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1311 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1312 * which requires 2D tiling.
1314 if (sscreen
->info
.chip_class
== VI
&& tc_compatible_htile
)
1315 return RADEON_SURF_MODE_2D
;
1317 /* Handle common candidates for the linear mode.
1318 * Compressed textures and DB surfaces must always be tiled.
1320 if (!force_tiling
&&
1321 !is_depth_stencil
&&
1322 !util_format_is_compressed(templ
->format
)) {
1323 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1324 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1326 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1327 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1328 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1330 /* Cursors are linear on SI.
1331 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1332 if (templ
->bind
& PIPE_BIND_CURSOR
)
1333 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1335 if (templ
->bind
& PIPE_BIND_LINEAR
)
1336 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1338 /* Textures with a very small height are recommended to be linear. */
1339 if (templ
->target
== PIPE_TEXTURE_1D
||
1340 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1341 /* Only very thin and long 2D textures should benefit from
1342 * linear_aligned. */
1343 (templ
->width0
> 8 && templ
->height0
<= 2))
1344 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1346 /* Textures likely to be mapped often. */
1347 if (templ
->usage
== PIPE_USAGE_STAGING
||
1348 templ
->usage
== PIPE_USAGE_STREAM
)
1349 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1352 /* Make small textures 1D tiled. */
1353 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1354 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1355 return RADEON_SURF_MODE_1D
;
1357 /* The allocator will switch to 1D if needed. */
1358 return RADEON_SURF_MODE_2D
;
1361 static unsigned si_get_num_color_samples(struct si_screen
*sscreen
,
1362 const struct pipe_resource
*templ
,
1365 if (!imported
&& templ
->nr_samples
>= 2 &&
1366 sscreen
->eqaa_force_color_samples
)
1367 return sscreen
->eqaa_force_color_samples
;
1369 return CLAMP(templ
->nr_samples
, 1, 8);
1372 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1373 const struct pipe_resource
*templ
)
1375 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1376 bool is_zs
= util_format_is_depth_or_stencil(templ
->format
);
1378 if (templ
->nr_samples
>= 2) {
1379 /* This is hackish (overwriting the const pipe_resource template),
1380 * but should be harmless and state trackers can also see
1381 * the overriden number of samples in the created pipe_resource.
1383 if (is_zs
&& sscreen
->eqaa_force_z_samples
) {
1384 ((struct pipe_resource
*)templ
)->nr_samples
=
1385 sscreen
->eqaa_force_z_samples
;
1386 } else if (!is_zs
&& sscreen
->eqaa_force_color_samples
) {
1387 ((struct pipe_resource
*)templ
)->nr_samples
=
1388 sscreen
->eqaa_force_coverage_samples
;
1392 struct radeon_surf surface
= {0};
1393 bool is_flushed_depth
= templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1394 bool tc_compatible_htile
=
1395 sscreen
->info
.chip_class
>= VI
&&
1396 /* There are issues with TC-compatible HTILE on Tonga (and
1397 * Iceland is the same design), and documented bug workarounds
1398 * don't help. For example, this fails:
1399 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1401 sscreen
->info
.family
!= CHIP_TONGA
&&
1402 sscreen
->info
.family
!= CHIP_ICELAND
&&
1403 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1404 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1405 !is_flushed_depth
&&
1406 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1408 unsigned num_color_samples
= si_get_num_color_samples(sscreen
, templ
, false);
1411 r
= si_init_surface(sscreen
, &surface
, templ
, num_color_samples
,
1412 si_choose_tiling(sscreen
, templ
, tc_compatible_htile
),
1413 0, 0, false, false, is_flushed_depth
,
1414 tc_compatible_htile
);
1419 return (struct pipe_resource
*)
1420 si_texture_create_object(screen
, templ
, num_color_samples
,
1424 static struct pipe_resource
*si_texture_from_winsys_buffer(struct si_screen
*sscreen
,
1425 const struct pipe_resource
*templ
,
1426 struct pb_buffer
*buf
,
1432 enum radeon_surf_mode array_mode
;
1433 struct radeon_surf surface
= {};
1434 struct radeon_bo_metadata metadata
= {};
1435 struct si_texture
*tex
;
1440 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1441 si_surface_import_metadata(sscreen
, &surface
, &metadata
,
1442 &array_mode
, &is_scanout
);
1445 * The bo metadata is unset for un-dedicated images. So we fall
1446 * back to linear. See answer to question 5 of the
1447 * VK_KHX_external_memory spec for some details.
1449 * It is possible that this case isn't going to work if the
1450 * surface pitch isn't correctly aligned by default.
1452 * In order to support it correctly we require multi-image
1453 * metadata to be syncrhonized between radv and radeonsi. The
1454 * semantics of associating multiple image metadata to a memory
1455 * object on the vulkan export side are not concretely defined
1458 * All the use cases we are aware of at the moment for memory
1459 * objects use dedicated allocations. So lets keep the initial
1460 * implementation simple.
1462 * A possible alternative is to attempt to reconstruct the
1463 * tiling information when the TexParameter TEXTURE_TILING_EXT
1466 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1470 unsigned num_color_samples
= si_get_num_color_samples(sscreen
, templ
, true);
1472 r
= si_init_surface(sscreen
, &surface
, templ
, num_color_samples
,
1473 array_mode
, stride
, offset
, true, is_scanout
,
1478 tex
= si_texture_create_object(&sscreen
->b
, templ
, num_color_samples
,
1483 tex
->buffer
.b
.is_shared
= true;
1484 tex
->buffer
.external_usage
= usage
;
1486 si_apply_opaque_metadata(sscreen
, tex
, &metadata
);
1488 assert(tex
->surface
.tile_swizzle
== 0);
1489 return &tex
->buffer
.b
.b
;
1492 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1493 const struct pipe_resource
*templ
,
1494 struct winsys_handle
*whandle
,
1497 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1498 struct pb_buffer
*buf
= NULL
;
1499 unsigned stride
= 0, offset
= 0;
1501 /* Support only 2D textures without mipmaps */
1502 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1503 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1506 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, &stride
, &offset
);
1510 return si_texture_from_winsys_buffer(sscreen
, templ
, buf
, stride
,
1511 offset
, usage
, true);
1514 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1515 struct pipe_resource
*texture
,
1516 struct si_texture
**staging
)
1518 struct si_texture
*tex
= (struct si_texture
*)texture
;
1519 struct pipe_resource resource
;
1520 struct si_texture
**flushed_depth_texture
= staging
?
1521 staging
: &tex
->flushed_depth_texture
;
1522 enum pipe_format pipe_format
= texture
->format
;
1525 if (tex
->flushed_depth_texture
)
1526 return true; /* it's ready */
1528 if (!tex
->can_sample_z
&& tex
->can_sample_s
) {
1529 switch (pipe_format
) {
1530 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1531 /* Save memory by not allocating the S plane. */
1532 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1534 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1535 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1536 /* Save memory bandwidth by not copying the
1537 * stencil part during flush.
1539 * This potentially increases memory bandwidth
1540 * if an application uses both Z and S texturing
1541 * simultaneously (a flushed Z24S8 texture
1542 * would be stored compactly), but how often
1543 * does that really happen?
1545 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1549 } else if (!tex
->can_sample_s
&& tex
->can_sample_z
) {
1550 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1552 /* DB->CB copies to an 8bpp surface don't work. */
1553 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1557 memset(&resource
, 0, sizeof(resource
));
1558 resource
.target
= texture
->target
;
1559 resource
.format
= pipe_format
;
1560 resource
.width0
= texture
->width0
;
1561 resource
.height0
= texture
->height0
;
1562 resource
.depth0
= texture
->depth0
;
1563 resource
.array_size
= texture
->array_size
;
1564 resource
.last_level
= texture
->last_level
;
1565 resource
.nr_samples
= texture
->nr_samples
;
1566 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1567 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1568 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1571 resource
.flags
|= SI_RESOURCE_FLAG_TRANSFER
;
1573 *flushed_depth_texture
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1574 if (*flushed_depth_texture
== NULL
) {
1575 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1582 * Initialize the pipe_resource descriptor to be of the same size as the box,
1583 * which is supposed to hold a subregion of the texture "orig" at the given
1586 static void si_init_temp_resource_from_box(struct pipe_resource
*res
,
1587 struct pipe_resource
*orig
,
1588 const struct pipe_box
*box
,
1589 unsigned level
, unsigned flags
)
1591 memset(res
, 0, sizeof(*res
));
1592 res
->format
= orig
->format
;
1593 res
->width0
= box
->width
;
1594 res
->height0
= box
->height
;
1596 res
->array_size
= 1;
1597 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1600 /* We must set the correct texture target and dimensions for a 3D box. */
1601 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1602 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1603 res
->array_size
= box
->depth
;
1605 res
->target
= PIPE_TEXTURE_2D
;
1609 static bool si_can_invalidate_texture(struct si_screen
*sscreen
,
1610 struct si_texture
*tex
,
1611 unsigned transfer_usage
,
1612 const struct pipe_box
*box
)
1614 return !tex
->buffer
.b
.is_shared
&&
1615 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1616 tex
->buffer
.b
.b
.last_level
== 0 &&
1617 util_texrange_covers_whole_level(&tex
->buffer
.b
.b
, 0,
1618 box
->x
, box
->y
, box
->z
,
1619 box
->width
, box
->height
,
1623 static void si_texture_invalidate_storage(struct si_context
*sctx
,
1624 struct si_texture
*tex
)
1626 struct si_screen
*sscreen
= sctx
->screen
;
1628 /* There is no point in discarding depth and tiled buffers. */
1629 assert(!tex
->is_depth
);
1630 assert(tex
->surface
.is_linear
);
1632 /* Reallocate the buffer in the same pipe_resource. */
1633 si_alloc_resource(sscreen
, &tex
->buffer
);
1635 /* Initialize the CMASK base address (needed even without CMASK). */
1636 tex
->cmask_base_address_reg
=
1637 (tex
->buffer
.gpu_address
+ tex
->cmask_offset
) >> 8;
1639 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1641 sctx
->num_alloc_tex_transfer_bytes
+= tex
->size
;
1644 static void *si_texture_transfer_map(struct pipe_context
*ctx
,
1645 struct pipe_resource
*texture
,
1648 const struct pipe_box
*box
,
1649 struct pipe_transfer
**ptransfer
)
1651 struct si_context
*sctx
= (struct si_context
*)ctx
;
1652 struct si_texture
*tex
= (struct si_texture
*)texture
;
1653 struct r600_transfer
*trans
;
1654 struct r600_resource
*buf
;
1655 unsigned offset
= 0;
1657 bool use_staging_texture
= false;
1659 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
1660 assert(box
->width
&& box
->height
&& box
->depth
);
1662 /* Depth textures use staging unconditionally. */
1663 if (!tex
->is_depth
) {
1664 /* Degrade the tile mode if we get too many transfers on APUs.
1665 * On dGPUs, the staging texture is always faster.
1666 * Only count uploads that are at least 4x4 pixels large.
1668 if (!sctx
->screen
->info
.has_dedicated_vram
&&
1670 box
->width
>= 4 && box
->height
>= 4 &&
1671 p_atomic_inc_return(&tex
->num_level0_transfers
) == 10) {
1672 bool can_invalidate
=
1673 si_can_invalidate_texture(sctx
->screen
, tex
,
1676 si_reallocate_texture_inplace(sctx
, tex
,
1681 /* Tiled textures need to be converted into a linear texture for CPU
1682 * access. The staging texture is always linear and is placed in GART.
1684 * Reading from VRAM or GTT WC is slow, always use the staging
1685 * texture in this case.
1687 * Use the staging texture for uploads if the underlying BO
1690 if (!tex
->surface
.is_linear
)
1691 use_staging_texture
= true;
1692 else if (usage
& PIPE_TRANSFER_READ
)
1693 use_staging_texture
=
1694 tex
->buffer
.domains
& RADEON_DOMAIN_VRAM
||
1695 tex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
1696 /* Write & linear only: */
1697 else if (si_rings_is_buffer_referenced(sctx
, tex
->buffer
.buf
,
1698 RADEON_USAGE_READWRITE
) ||
1699 !sctx
->ws
->buffer_wait(tex
->buffer
.buf
, 0,
1700 RADEON_USAGE_READWRITE
)) {
1702 if (si_can_invalidate_texture(sctx
->screen
, tex
,
1704 si_texture_invalidate_storage(sctx
, tex
);
1706 use_staging_texture
= true;
1710 trans
= CALLOC_STRUCT(r600_transfer
);
1713 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1714 trans
->b
.b
.level
= level
;
1715 trans
->b
.b
.usage
= usage
;
1716 trans
->b
.b
.box
= *box
;
1718 if (tex
->is_depth
) {
1719 struct si_texture
*staging_depth
;
1721 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
1722 /* MSAA depth buffers need to be converted to single sample buffers.
1724 * Mapping MSAA depth buffers can occur if ReadPixels is called
1725 * with a multisample GLX visual.
1727 * First downsample the depth buffer to a temporary texture,
1728 * then decompress the temporary one to staging.
1730 * Only the region being mapped is transfered.
1732 struct pipe_resource resource
;
1734 si_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1736 if (!si_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1737 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1741 if (usage
& PIPE_TRANSFER_READ
) {
1742 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1744 PRINT_ERR("failed to create a temporary depth texture\n");
1748 si_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1749 si_blit_decompress_depth(ctx
, (struct si_texture
*)temp
, staging_depth
,
1750 0, 0, 0, box
->depth
, 0, 0);
1751 pipe_resource_reference(&temp
, NULL
);
1754 /* Just get the strides. */
1755 si_texture_get_offset(sctx
->screen
, staging_depth
, level
, NULL
,
1757 &trans
->b
.b
.layer_stride
);
1759 /* XXX: only readback the rectangle which is being mapped? */
1760 /* XXX: when discard is true, no need to read back from depth texture */
1761 if (!si_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1762 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1766 si_blit_decompress_depth(ctx
, tex
, staging_depth
,
1768 box
->z
, box
->z
+ box
->depth
- 1,
1771 offset
= si_texture_get_offset(sctx
->screen
, staging_depth
,
1774 &trans
->b
.b
.layer_stride
);
1777 trans
->staging
= &staging_depth
->buffer
;
1778 buf
= trans
->staging
;
1779 } else if (use_staging_texture
) {
1780 struct pipe_resource resource
;
1781 struct si_texture
*staging
;
1783 si_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1784 SI_RESOURCE_FLAG_TRANSFER
);
1785 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1786 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1788 /* Create the temporary texture. */
1789 staging
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1791 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1794 trans
->staging
= &staging
->buffer
;
1796 /* Just get the strides. */
1797 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
,
1799 &trans
->b
.b
.layer_stride
);
1801 if (usage
& PIPE_TRANSFER_READ
)
1802 si_copy_to_staging_texture(ctx
, trans
);
1804 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1806 buf
= trans
->staging
;
1808 /* the resource is mapped directly */
1809 offset
= si_texture_get_offset(sctx
->screen
, tex
, level
, box
,
1811 &trans
->b
.b
.layer_stride
);
1815 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
1818 *ptransfer
= &trans
->b
.b
;
1819 return map
+ offset
;
1822 r600_resource_reference(&trans
->staging
, NULL
);
1823 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
1828 static void si_texture_transfer_unmap(struct pipe_context
*ctx
,
1829 struct pipe_transfer
* transfer
)
1831 struct si_context
*sctx
= (struct si_context
*)ctx
;
1832 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1833 struct pipe_resource
*texture
= transfer
->resource
;
1834 struct si_texture
*tex
= (struct si_texture
*)texture
;
1836 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1837 if (tex
->is_depth
&& tex
->buffer
.b
.b
.nr_samples
<= 1) {
1838 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1839 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1840 &rtransfer
->staging
->b
.b
, transfer
->level
,
1843 si_copy_from_staging_texture(ctx
, rtransfer
);
1847 if (rtransfer
->staging
) {
1848 sctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1849 r600_resource_reference(&rtransfer
->staging
, NULL
);
1852 /* Heuristic for {upload, draw, upload, draw, ..}:
1854 * Flush the gfx IB if we've allocated too much texture storage.
1856 * The idea is that we don't want to build IBs that use too much
1857 * memory and put pressure on the kernel memory manager and we also
1858 * want to make temporary and invalidated buffers go idle ASAP to
1859 * decrease the total memory usage or make them reusable. The memory
1860 * usage will be slightly higher than given here because of the buffer
1861 * cache in the winsys.
1863 * The result is that the kernel memory manager is never a bottleneck.
1865 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
1866 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1867 sctx
->num_alloc_tex_transfer_bytes
= 0;
1870 pipe_resource_reference(&transfer
->resource
, NULL
);
1874 static const struct u_resource_vtbl si_texture_vtbl
=
1876 NULL
, /* get_handle */
1877 si_texture_destroy
, /* resource_destroy */
1878 si_texture_transfer_map
, /* transfer_map */
1879 u_default_transfer_flush_region
, /* transfer_flush_region */
1880 si_texture_transfer_unmap
, /* transfer_unmap */
1883 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
1885 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1886 enum pipe_format format2
)
1888 const struct util_format_description
*desc1
, *desc2
;
1890 /* No format change - exit early. */
1891 if (format1
== format2
)
1894 format1
= si_simplify_cb_format(format1
);
1895 format2
= si_simplify_cb_format(format2
);
1897 /* Check again after format adjustments. */
1898 if (format1
== format2
)
1901 desc1
= util_format_description(format1
);
1902 desc2
= util_format_description(format2
);
1904 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
1905 desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1908 /* Float and non-float are totally incompatible. */
1909 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
1910 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
1913 /* Channel sizes must match across DCC formats.
1914 * Comparing just the first 2 channels should be enough.
1916 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
1917 (desc1
->nr_channels
>= 2 &&
1918 desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
1921 /* Everything below is not needed if the driver never uses the DCC
1922 * clear code with the value of 1.
1925 /* If the clear values are all 1 or all 0, this constraint can be
1927 if (vi_alpha_is_on_msb(format1
) != vi_alpha_is_on_msb(format2
))
1930 /* Channel types must match if the clear value of 1 is used.
1931 * The type categories are only float, signed, unsigned.
1932 * NORM and INT are always compatible.
1934 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
1935 (desc1
->nr_channels
>= 2 &&
1936 desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
1942 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1944 enum pipe_format view_format
)
1946 struct si_texture
*stex
= (struct si_texture
*)tex
;
1948 return vi_dcc_enabled(stex
, level
) &&
1949 !vi_dcc_formats_compatible(tex
->format
, view_format
);
1952 /* This can't be merged with the above function, because
1953 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1954 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
1955 struct pipe_resource
*tex
,
1957 enum pipe_format view_format
)
1959 struct si_texture
*stex
= (struct si_texture
*)tex
;
1961 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
1962 if (!si_texture_disable_dcc(sctx
, stex
))
1963 si_decompress_dcc(sctx
, stex
);
1966 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1967 struct pipe_resource
*texture
,
1968 const struct pipe_surface
*templ
,
1969 unsigned width0
, unsigned height0
,
1970 unsigned width
, unsigned height
)
1972 struct si_surface
*surface
= CALLOC_STRUCT(si_surface
);
1977 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1978 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1980 pipe_reference_init(&surface
->base
.reference
, 1);
1981 pipe_resource_reference(&surface
->base
.texture
, texture
);
1982 surface
->base
.context
= pipe
;
1983 surface
->base
.format
= templ
->format
;
1984 surface
->base
.width
= width
;
1985 surface
->base
.height
= height
;
1986 surface
->base
.u
= templ
->u
;
1988 surface
->width0
= width0
;
1989 surface
->height0
= height0
;
1991 surface
->dcc_incompatible
=
1992 texture
->target
!= PIPE_BUFFER
&&
1993 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
1995 return &surface
->base
;
1998 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
,
1999 struct pipe_resource
*tex
,
2000 const struct pipe_surface
*templ
)
2002 unsigned level
= templ
->u
.tex
.level
;
2003 unsigned width
= u_minify(tex
->width0
, level
);
2004 unsigned height
= u_minify(tex
->height0
, level
);
2005 unsigned width0
= tex
->width0
;
2006 unsigned height0
= tex
->height0
;
2008 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2009 const struct util_format_description
*tex_desc
2010 = util_format_description(tex
->format
);
2011 const struct util_format_description
*templ_desc
2012 = util_format_description(templ
->format
);
2014 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2016 /* Adjust size of surface if and only if the block width or
2017 * height is changed. */
2018 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2019 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2020 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2021 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2023 width
= nblks_x
* templ_desc
->block
.width
;
2024 height
= nblks_y
* templ_desc
->block
.height
;
2026 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2027 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2031 return si_create_surface_custom(pipe
, tex
, templ
,
2036 static void si_surface_destroy(struct pipe_context
*pipe
,
2037 struct pipe_surface
*surface
)
2039 pipe_resource_reference(&surface
->texture
, NULL
);
2043 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2045 const struct util_format_description
*desc
= util_format_description(format
);
2047 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2049 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2050 return V_028C70_SWAP_STD
;
2052 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2055 switch (desc
->nr_channels
) {
2057 if (HAS_SWIZZLE(0,X
))
2058 return V_028C70_SWAP_STD
; /* X___ */
2059 else if (HAS_SWIZZLE(3,X
))
2060 return V_028C70_SWAP_ALT_REV
; /* ___X */
2063 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2064 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2065 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2066 return V_028C70_SWAP_STD
; /* XY__ */
2067 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2068 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2069 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2071 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2072 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2073 return V_028C70_SWAP_ALT
; /* X__Y */
2074 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2075 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2078 if (HAS_SWIZZLE(0,X
))
2079 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2080 else if (HAS_SWIZZLE(0,Z
))
2081 return V_028C70_SWAP_STD_REV
; /* ZYX */
2084 /* check the middle channels, the 1st and 4th channel can be NONE */
2085 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2086 return V_028C70_SWAP_STD
; /* XYZW */
2087 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2088 return V_028C70_SWAP_STD_REV
; /* WZYX */
2089 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2090 return V_028C70_SWAP_ALT
; /* ZYXW */
2091 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2094 return V_028C70_SWAP_ALT_REV
;
2096 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2103 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2105 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
,
2110 if (sctx
->dcc_stats
[slot
].query_active
)
2111 vi_separate_dcc_stop_query(sctx
,
2112 sctx
->dcc_stats
[slot
].tex
);
2114 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2115 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2116 sctx
->b
.destroy_query(&sctx
->b
,
2117 sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2118 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2121 si_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2125 * Return the per-context slot where DCC statistics queries for the texture live.
2127 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
,
2128 struct si_texture
*tex
)
2130 int i
, empty_slot
= -1;
2132 /* Remove zombie textures (textures kept alive by this array only). */
2133 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2134 if (sctx
->dcc_stats
[i
].tex
&&
2135 sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2136 vi_dcc_clean_up_context_slot(sctx
, i
);
2138 /* Find the texture. */
2139 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2140 /* Return if found. */
2141 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2142 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2146 /* Record the first seen empty slot. */
2147 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2151 /* Not found. Remove the oldest member to make space in the array. */
2152 if (empty_slot
== -1) {
2153 int oldest_slot
= 0;
2155 /* Find the oldest slot. */
2156 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2157 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2158 sctx
->dcc_stats
[i
].last_use_timestamp
)
2161 /* Clean up the oldest slot. */
2162 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2163 empty_slot
= oldest_slot
;
2166 /* Add the texture to the new slot. */
2167 si_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2168 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2172 static struct pipe_query
*
2173 vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2175 struct si_query_hw
*query
= (struct si_query_hw
*)
2176 sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2178 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2179 return (struct pipe_query
*)query
;
2183 * Called when binding a color buffer.
2185 void vi_separate_dcc_start_query(struct si_context
*sctx
,
2186 struct si_texture
*tex
)
2188 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2190 assert(!sctx
->dcc_stats
[i
].query_active
);
2192 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2193 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2195 /* begin or resume the query */
2196 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2197 sctx
->dcc_stats
[i
].query_active
= true;
2201 * Called when unbinding a color buffer.
2203 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
2204 struct si_texture
*tex
)
2206 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2208 assert(sctx
->dcc_stats
[i
].query_active
);
2209 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2211 /* pause or end the query */
2212 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2213 sctx
->dcc_stats
[i
].query_active
= false;
2216 static bool vi_should_enable_separate_dcc(struct si_texture
*tex
)
2218 /* The minimum number of fullscreen draws per frame that is required
2220 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2223 /* Called by fast clear. */
2224 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
2225 struct si_texture
*tex
)
2227 /* The intent is to use this with shared displayable back buffers,
2228 * but it's not strictly limited only to them.
2230 if (!tex
->buffer
.b
.is_shared
||
2231 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2232 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2233 tex
->buffer
.b
.b
.last_level
> 0 ||
2234 !tex
->surface
.dcc_size
)
2237 if (tex
->dcc_offset
)
2238 return; /* already enabled */
2240 /* Enable the DCC stat gathering. */
2241 if (!tex
->dcc_gather_statistics
) {
2242 tex
->dcc_gather_statistics
= true;
2243 vi_separate_dcc_start_query(sctx
, tex
);
2246 if (!vi_should_enable_separate_dcc(tex
))
2247 return; /* stats show that DCC decompression is too expensive */
2249 assert(tex
->surface
.num_dcc_levels
);
2250 assert(!tex
->dcc_separate_buffer
);
2252 si_texture_discard_cmask(sctx
->screen
, tex
);
2254 /* Get a DCC buffer. */
2255 if (tex
->last_dcc_separate_buffer
) {
2256 assert(tex
->dcc_gather_statistics
);
2257 assert(!tex
->dcc_separate_buffer
);
2258 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2259 tex
->last_dcc_separate_buffer
= NULL
;
2261 tex
->dcc_separate_buffer
=
2262 si_aligned_buffer_create(sctx
->b
.screen
,
2263 SI_RESOURCE_FLAG_UNMAPPABLE
,
2265 tex
->surface
.dcc_size
,
2266 tex
->surface
.dcc_alignment
);
2267 if (!tex
->dcc_separate_buffer
)
2271 /* dcc_offset is the absolute GPUVM address. */
2272 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2274 /* no need to flag anything since this is called by fast clear that
2275 * flags framebuffer state
2280 * Called by pipe_context::flush_resource, the place where DCC decompression
2283 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2284 struct si_texture
*tex
)
2286 struct si_context
*sctx
= (struct si_context
*)ctx
;
2287 struct pipe_query
*tmp
;
2288 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2289 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2290 bool disable
= false;
2292 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2293 union pipe_query_result result
;
2295 /* Read the results. */
2296 ctx
->get_query_result(ctx
, sctx
->dcc_stats
[i
].ps_stats
[2],
2298 si_query_hw_reset_buffers(sctx
,
2299 (struct si_query_hw
*)
2300 sctx
->dcc_stats
[i
].ps_stats
[2]);
2302 /* Compute the approximate number of fullscreen draws. */
2303 tex
->ps_draw_ratio
=
2304 result
.pipeline_statistics
.ps_invocations
/
2305 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2306 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2308 disable
= tex
->dcc_separate_buffer
&&
2309 !vi_should_enable_separate_dcc(tex
);
2312 tex
->num_slow_clears
= 0;
2314 /* stop the statistics query for ps_stats[0] */
2316 vi_separate_dcc_stop_query(sctx
, tex
);
2318 /* Move the queries in the queue by one. */
2319 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2320 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2321 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2322 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2324 /* create and start a new query as ps_stats[0] */
2326 vi_separate_dcc_start_query(sctx
, tex
);
2329 assert(!tex
->last_dcc_separate_buffer
);
2330 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2331 tex
->dcc_separate_buffer
= NULL
;
2332 tex
->dcc_offset
= 0;
2333 /* no need to flag anything since this is called after
2334 * decompression that re-sets framebuffer state
2339 static struct pipe_memory_object
*
2340 si_memobj_from_handle(struct pipe_screen
*screen
,
2341 struct winsys_handle
*whandle
,
2344 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2345 struct si_memory_object
*memobj
= CALLOC_STRUCT(si_memory_object
);
2346 struct pb_buffer
*buf
= NULL
;
2347 uint32_t stride
, offset
;
2352 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2359 memobj
->b
.dedicated
= dedicated
;
2361 memobj
->stride
= stride
;
2363 return (struct pipe_memory_object
*)memobj
;
2368 si_memobj_destroy(struct pipe_screen
*screen
,
2369 struct pipe_memory_object
*_memobj
)
2371 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2373 pb_reference(&memobj
->buf
, NULL
);
2377 static struct pipe_resource
*
2378 si_texture_from_memobj(struct pipe_screen
*screen
,
2379 const struct pipe_resource
*templ
,
2380 struct pipe_memory_object
*_memobj
,
2383 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2384 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2385 struct pipe_resource
*tex
=
2386 si_texture_from_winsys_buffer(sscreen
, templ
, memobj
->buf
,
2387 memobj
->stride
, offset
,
2388 PIPE_HANDLE_USAGE_READ_WRITE
,
2389 memobj
->b
.dedicated
);
2393 /* si_texture_from_winsys_buffer doesn't increment refcount of
2394 * memobj->buf, so increment it here.
2396 struct pb_buffer
*buf
= NULL
;
2397 pb_reference(&buf
, memobj
->buf
);
2401 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2402 struct pipe_resource
*resource
,
2405 struct si_texture
*tex
= (struct si_texture
*)resource
;
2407 /* Buffers only support the linear flag. */
2408 if (resource
->target
== PIPE_BUFFER
)
2409 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2411 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2414 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2417 /* TODO: PIPE_BIND_CURSOR - do we care? */
2421 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2423 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2424 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2425 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2426 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2427 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2428 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2431 void si_init_context_texture_functions(struct si_context
*sctx
)
2433 sctx
->b
.create_surface
= si_create_surface
;
2434 sctx
->b
.surface_destroy
= si_surface_destroy
;