2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "util/format/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_resource.h"
33 #include "util/u_surface.h"
34 #include "util/u_transfer.h"
35 #include "util/os_time.h"
38 #include "state_tracker/drm_driver.h"
40 #include "amd/addrlib/inc/addrinterface.h"
41 #include "drm-uapi/drm_fourcc.h"
43 static enum radeon_surf_mode
44 si_choose_tiling(struct si_screen
*sscreen
,
45 const struct pipe_resource
*templ
, bool tc_compatible_htile
);
48 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
49 struct si_texture
*dst
,
50 unsigned dst_level
, unsigned dstx
,
51 unsigned dsty
, unsigned dstz
,
52 struct si_texture
*src
,
54 const struct pipe_box
*src_box
)
59 if (dst
->surface
.bpe
!= src
->surface
.bpe
)
62 /* MSAA: Blits don't exist in the real world. */
63 if (src
->buffer
.b
.b
.nr_samples
> 1 ||
64 dst
->buffer
.b
.b
.nr_samples
> 1)
67 /* Depth-stencil surfaces:
68 * When dst is linear, the DB->CB copy preserves HTILE.
69 * When dst is tiled, the 3D path must be used to update HTILE.
71 if (src
->is_depth
|| dst
->is_depth
)
75 * src: Use the 3D path. DCC decompression is expensive.
76 * dst: Use the 3D path to compress the pixels with DCC.
78 if (vi_dcc_enabled(src
, src_level
) ||
79 vi_dcc_enabled(dst
, dst_level
))
83 * src: Both texture and SDMA paths need decompression. Use SDMA.
84 * dst: If overwriting the whole texture, discard CMASK and use
85 * SDMA. Otherwise, use the 3D path.
87 if (dst
->cmask_buffer
&& dst
->dirty_level_mask
& (1 << dst_level
)) {
88 /* The CMASK clear is only enabled for the first level. */
89 assert(dst_level
== 0);
90 if (!util_texrange_covers_whole_level(&dst
->buffer
.b
.b
, dst_level
,
91 dstx
, dsty
, dstz
, src_box
->width
,
92 src_box
->height
, src_box
->depth
))
95 si_texture_discard_cmask(sctx
->screen
, dst
);
98 /* All requirements are met. Prepare textures for SDMA. */
99 if (src
->cmask_buffer
&& src
->dirty_level_mask
& (1 << src_level
))
100 sctx
->b
.flush_resource(&sctx
->b
, &src
->buffer
.b
.b
);
102 assert(!(src
->dirty_level_mask
& (1 << src_level
)));
103 assert(!(dst
->dirty_level_mask
& (1 << dst_level
)));
108 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
109 static void si_copy_region_with_blit(struct pipe_context
*pipe
,
110 struct pipe_resource
*dst
,
112 unsigned dstx
, unsigned dsty
, unsigned dstz
,
113 struct pipe_resource
*src
,
115 const struct pipe_box
*src_box
)
117 struct pipe_blit_info blit
;
119 memset(&blit
, 0, sizeof(blit
));
120 blit
.src
.resource
= src
;
121 blit
.src
.format
= src
->format
;
122 blit
.src
.level
= src_level
;
123 blit
.src
.box
= *src_box
;
124 blit
.dst
.resource
= dst
;
125 blit
.dst
.format
= dst
->format
;
126 blit
.dst
.level
= dst_level
;
127 blit
.dst
.box
.x
= dstx
;
128 blit
.dst
.box
.y
= dsty
;
129 blit
.dst
.box
.z
= dstz
;
130 blit
.dst
.box
.width
= src_box
->width
;
131 blit
.dst
.box
.height
= src_box
->height
;
132 blit
.dst
.box
.depth
= src_box
->depth
;
133 blit
.mask
= util_format_get_mask(dst
->format
);
134 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
137 pipe
->blit(pipe
, &blit
);
141 /* Copy from a full GPU texture to a transfer's staging one. */
142 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
144 struct si_context
*sctx
= (struct si_context
*)ctx
;
145 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
146 struct pipe_resource
*dst
= &stransfer
->staging
->b
.b
;
147 struct pipe_resource
*src
= transfer
->resource
;
149 if (src
->nr_samples
> 1 || ((struct si_texture
*)src
)->is_depth
) {
150 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
151 src
, transfer
->level
, &transfer
->box
);
155 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
159 /* Copy from a transfer's staging texture to a full GPU one. */
160 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
162 struct si_context
*sctx
= (struct si_context
*)ctx
;
163 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
164 struct pipe_resource
*dst
= transfer
->resource
;
165 struct pipe_resource
*src
= &stransfer
->staging
->b
.b
;
166 struct pipe_box sbox
;
168 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
170 if (dst
->nr_samples
> 1 || ((struct si_texture
*)dst
)->is_depth
) {
171 si_copy_region_with_blit(ctx
, dst
, transfer
->level
,
172 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
177 if (util_format_is_compressed(dst
->format
)) {
178 sbox
.width
= util_format_get_nblocksx(dst
->format
, sbox
.width
);
179 sbox
.height
= util_format_get_nblocksx(dst
->format
, sbox
.height
);
182 sctx
->dma_copy(ctx
, dst
, transfer
->level
,
183 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
187 static unsigned si_texture_get_offset(struct si_screen
*sscreen
,
188 struct si_texture
*tex
, unsigned level
,
189 const struct pipe_box
*box
,
191 unsigned *layer_stride
)
193 if (sscreen
->info
.chip_class
>= GFX9
) {
194 *stride
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
195 *layer_stride
= tex
->surface
.u
.gfx9
.surf_slice_size
;
200 /* Each texture is an array of slices. Each slice is an array
201 * of mipmap levels. */
202 return tex
->surface
.u
.gfx9
.surf_offset
+
203 box
->z
* tex
->surface
.u
.gfx9
.surf_slice_size
+
204 tex
->surface
.u
.gfx9
.offset
[level
] +
205 (box
->y
/ tex
->surface
.blk_h
*
206 tex
->surface
.u
.gfx9
.surf_pitch
+
207 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
209 *stride
= tex
->surface
.u
.legacy
.level
[level
].nblk_x
*
211 assert((uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
212 *layer_stride
= (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
215 return tex
->surface
.u
.legacy
.level
[level
].offset
;
217 /* Each texture is an array of mipmap levels. Each level is
218 * an array of slices. */
219 return tex
->surface
.u
.legacy
.level
[level
].offset
+
220 box
->z
* (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
221 (box
->y
/ tex
->surface
.blk_h
*
222 tex
->surface
.u
.legacy
.level
[level
].nblk_x
+
223 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
227 static int si_init_surface(struct si_screen
*sscreen
,
228 struct radeon_surf
*surface
,
229 const struct pipe_resource
*ptex
,
230 enum radeon_surf_mode array_mode
,
231 unsigned pitch_in_bytes_override
,
234 bool is_flushed_depth
,
235 bool tc_compatible_htile
)
237 const struct util_format_description
*desc
=
238 util_format_description(ptex
->format
);
239 bool is_depth
, is_stencil
;
241 unsigned bpe
, flags
= 0;
243 is_depth
= util_format_has_depth(desc
);
244 is_stencil
= util_format_has_stencil(desc
);
246 if (!is_flushed_depth
&&
247 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
248 bpe
= 4; /* stencil is allocated separately */
250 bpe
= util_format_get_blocksize(ptex
->format
);
251 assert(util_is_power_of_two_or_zero(bpe
));
254 if (!is_flushed_depth
&& is_depth
) {
255 flags
|= RADEON_SURF_ZBUFFER
;
257 if (sscreen
->debug_flags
& DBG(NO_HYPERZ
)) {
258 flags
|= RADEON_SURF_NO_HTILE
;
259 } else if (tc_compatible_htile
&&
260 (sscreen
->info
.chip_class
>= GFX9
||
261 array_mode
== RADEON_SURF_MODE_2D
)) {
262 /* TC-compatible HTILE only supports Z32_FLOAT.
263 * GFX9 also supports Z16_UNORM.
264 * On GFX8, promote Z16 to Z32. DB->CB copies will convert
265 * the format for transfers.
267 if (sscreen
->info
.chip_class
== GFX8
)
270 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
274 flags
|= RADEON_SURF_SBUFFER
;
277 if (sscreen
->info
.chip_class
>= GFX8
&&
278 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
||
279 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
280 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
281 flags
|= RADEON_SURF_DISABLE_DCC
;
283 /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */
284 if (sscreen
->info
.family
== CHIP_STONEY
&&
285 bpe
== 16 && ptex
->nr_samples
>= 2)
286 flags
|= RADEON_SURF_DISABLE_DCC
;
288 /* GFX8: DCC clear for 4x and 8x MSAA array textures unimplemented. */
289 if (sscreen
->info
.chip_class
== GFX8
&&
290 ptex
->nr_storage_samples
>= 4 &&
291 ptex
->array_size
> 1)
292 flags
|= RADEON_SURF_DISABLE_DCC
;
294 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
295 if (sscreen
->info
.chip_class
== GFX9
&&
296 (ptex
->nr_storage_samples
>= 4 ||
297 (sscreen
->info
.family
== CHIP_RAVEN
&&
298 ptex
->nr_storage_samples
>= 2 && bpe
< 4)))
299 flags
|= RADEON_SURF_DISABLE_DCC
;
301 /* TODO: GFX10: DCC causes corruption with MSAA. */
302 if (sscreen
->info
.chip_class
>= GFX10
&&
303 ptex
->nr_storage_samples
>= 2)
304 flags
|= RADEON_SURF_DISABLE_DCC
;
306 /* Shared textures must always set up DCC.
307 * If it's not present, it will be disabled by
308 * si_get_opaque_metadata later.
310 if (!is_imported
&& (sscreen
->debug_flags
& DBG(NO_DCC
)))
311 flags
|= RADEON_SURF_DISABLE_DCC
;
314 /* This should catch bugs in gallium users setting incorrect flags. */
315 assert(ptex
->nr_samples
<= 1 &&
316 ptex
->array_size
== 1 &&
318 ptex
->last_level
== 0 &&
319 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
321 flags
|= RADEON_SURF_SCANOUT
;
324 if (ptex
->bind
& PIPE_BIND_SHARED
)
325 flags
|= RADEON_SURF_SHAREABLE
;
327 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
328 if (!(ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
))
329 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
330 if (sscreen
->debug_flags
& DBG(NO_FMASK
))
331 flags
|= RADEON_SURF_NO_FMASK
;
333 if (sscreen
->info
.chip_class
== GFX9
&&
334 (ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE
)) {
335 flags
|= RADEON_SURF_FORCE_MICRO_TILE_MODE
;
336 surface
->micro_tile_mode
= SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(ptex
->flags
);
339 if (sscreen
->info
.chip_class
>= GFX10
&&
340 (ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
)) {
341 flags
|= RADEON_SURF_FORCE_SWIZZLE_MODE
;
342 surface
->u
.gfx9
.surf
.swizzle_mode
= ADDR_SW_64KB_R_X
;
345 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
,
346 array_mode
, surface
);
351 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
353 if (sscreen
->info
.chip_class
>= GFX9
) {
355 surface
->u
.gfx9
.surf_pitch
= pitch
;
356 if (ptex
->last_level
== 0)
357 surface
->u
.gfx9
.surf
.epitch
= pitch
- 1;
358 surface
->u
.gfx9
.surf_slice_size
=
359 (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
363 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
364 surface
->u
.legacy
.level
[0].slice_size_dw
=
365 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
371 static void si_get_display_metadata(struct si_screen
*sscreen
,
372 struct radeon_surf
*surf
,
373 struct radeon_bo_metadata
*metadata
,
374 enum radeon_surf_mode
*array_mode
,
377 if (sscreen
->info
.chip_class
>= GFX9
) {
378 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
379 *array_mode
= RADEON_SURF_MODE_2D
;
381 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
383 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
384 *is_scanout
= metadata
->u
.gfx9
.scanout
;
386 if (metadata
->u
.gfx9
.dcc_offset_256B
) {
387 surf
->u
.gfx9
.display_dcc_pitch_max
= metadata
->u
.gfx9
.dcc_pitch_max
;
388 assert(metadata
->u
.gfx9
.dcc_independent_64B
== 1);
391 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
392 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
393 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
394 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
395 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
396 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
398 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
399 *array_mode
= RADEON_SURF_MODE_2D
;
400 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
401 *array_mode
= RADEON_SURF_MODE_1D
;
403 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
405 *is_scanout
= metadata
->u
.legacy
.scanout
;
409 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
410 struct si_texture
*tex
)
412 struct si_screen
*sscreen
= sctx
->screen
;
413 struct pipe_context
*ctx
= &sctx
->b
;
415 if (ctx
== sscreen
->aux_context
)
416 simple_mtx_lock(&sscreen
->aux_context_lock
);
418 unsigned n
= sctx
->num_decompress_calls
;
419 ctx
->flush_resource(ctx
, &tex
->buffer
.b
.b
);
421 /* Flush only if any fast clear elimination took place. */
422 if (n
!= sctx
->num_decompress_calls
)
423 ctx
->flush(ctx
, NULL
, 0);
425 if (ctx
== sscreen
->aux_context
)
426 simple_mtx_unlock(&sscreen
->aux_context_lock
);
429 void si_texture_discard_cmask(struct si_screen
*sscreen
,
430 struct si_texture
*tex
)
432 if (!tex
->cmask_buffer
)
435 assert(tex
->buffer
.b
.b
.nr_samples
<= 1);
438 tex
->cmask_base_address_reg
= tex
->buffer
.gpu_address
>> 8;
439 tex
->dirty_level_mask
= 0;
441 tex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
443 if (tex
->cmask_buffer
!= &tex
->buffer
)
444 si_resource_reference(&tex
->cmask_buffer
, NULL
);
446 tex
->cmask_buffer
= NULL
;
448 /* Notify all contexts about the change. */
449 p_atomic_inc(&sscreen
->dirty_tex_counter
);
450 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
453 static bool si_can_disable_dcc(struct si_texture
*tex
)
455 /* We can't disable DCC if it can be written by another process. */
456 return tex
->surface
.dcc_offset
&&
457 (!tex
->buffer
.b
.is_shared
||
458 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
));
461 static void si_texture_zero_dcc_fields(struct si_texture
*tex
)
463 tex
->surface
.dcc_offset
= 0;
464 tex
->surface
.display_dcc_offset
= 0;
465 tex
->surface
.dcc_retile_map_offset
= 0;
468 static bool si_texture_discard_dcc(struct si_screen
*sscreen
,
469 struct si_texture
*tex
)
471 if (!si_can_disable_dcc(tex
))
474 assert(tex
->dcc_separate_buffer
== NULL
);
477 si_texture_zero_dcc_fields(tex
);
479 /* Notify all contexts about the change. */
480 p_atomic_inc(&sscreen
->dirty_tex_counter
);
485 * Disable DCC for the texture. (first decompress, then discard metadata).
487 * There is unresolved multi-context synchronization issue between
488 * screen::aux_context and the current context. If applications do this with
489 * multiple contexts, it's already undefined behavior for them and we don't
490 * have to worry about that. The scenario is:
492 * If context 1 disables DCC and context 2 has queued commands that write
493 * to the texture via CB with DCC enabled, and the order of operations is
495 * context 2 queues draw calls rendering to the texture, but doesn't flush
496 * context 1 disables DCC and flushes
497 * context 1 & 2 reset descriptors and FB state
498 * context 2 flushes (new compressed tiles written by the draw calls)
499 * context 1 & 2 read garbage, because DCC is disabled, yet there are
502 * \param sctx the current context if you have one, or sscreen->aux_context
505 bool si_texture_disable_dcc(struct si_context
*sctx
,
506 struct si_texture
*tex
)
508 struct si_screen
*sscreen
= sctx
->screen
;
510 if (!sctx
->has_graphics
)
511 return si_texture_discard_dcc(sscreen
, tex
);
513 if (!si_can_disable_dcc(tex
))
516 if (&sctx
->b
== sscreen
->aux_context
)
517 simple_mtx_lock(&sscreen
->aux_context_lock
);
519 /* Decompress DCC. */
520 si_decompress_dcc(sctx
, tex
);
521 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
523 if (&sctx
->b
== sscreen
->aux_context
)
524 simple_mtx_unlock(&sscreen
->aux_context_lock
);
526 return si_texture_discard_dcc(sscreen
, tex
);
529 static void si_reallocate_texture_inplace(struct si_context
*sctx
,
530 struct si_texture
*tex
,
531 unsigned new_bind_flag
,
532 bool invalidate_storage
)
534 struct pipe_screen
*screen
= sctx
->b
.screen
;
535 struct si_texture
*new_tex
;
536 struct pipe_resource templ
= tex
->buffer
.b
.b
;
539 templ
.bind
|= new_bind_flag
;
541 if (tex
->buffer
.b
.is_shared
|| tex
->num_planes
> 1)
544 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
545 if (tex
->surface
.is_linear
)
548 /* This fails with MSAA, depth, and compressed textures. */
549 if (si_choose_tiling(sctx
->screen
, &templ
, false) !=
550 RADEON_SURF_MODE_LINEAR_ALIGNED
)
554 new_tex
= (struct si_texture
*)screen
->resource_create(screen
, &templ
);
558 /* Copy the pixels to the new texture. */
559 if (!invalidate_storage
) {
560 for (i
= 0; i
<= templ
.last_level
; i
++) {
564 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
565 util_num_layers(&templ
, i
), &box
);
567 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0,
568 &tex
->buffer
.b
.b
, i
, &box
);
572 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
573 si_texture_discard_cmask(sctx
->screen
, tex
);
574 si_texture_discard_dcc(sctx
->screen
, tex
);
577 /* Replace the structure fields of tex. */
578 tex
->buffer
.b
.b
.bind
= templ
.bind
;
579 pb_reference(&tex
->buffer
.buf
, new_tex
->buffer
.buf
);
580 tex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
581 tex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
582 tex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
583 tex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
584 tex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
585 tex
->buffer
.domains
= new_tex
->buffer
.domains
;
586 tex
->buffer
.flags
= new_tex
->buffer
.flags
;
588 tex
->surface
= new_tex
->surface
;
589 si_texture_reference(&tex
->flushed_depth_texture
,
590 new_tex
->flushed_depth_texture
);
592 tex
->surface
.fmask_offset
= new_tex
->surface
.fmask_offset
;
593 tex
->surface
.cmask_offset
= new_tex
->surface
.cmask_offset
;
594 tex
->cmask_base_address_reg
= new_tex
->cmask_base_address_reg
;
596 if (tex
->cmask_buffer
== &tex
->buffer
)
597 tex
->cmask_buffer
= NULL
;
599 si_resource_reference(&tex
->cmask_buffer
, NULL
);
601 if (new_tex
->cmask_buffer
== &new_tex
->buffer
)
602 tex
->cmask_buffer
= &tex
->buffer
;
604 si_resource_reference(&tex
->cmask_buffer
, new_tex
->cmask_buffer
);
606 tex
->surface
.dcc_offset
= new_tex
->surface
.dcc_offset
;
607 tex
->cb_color_info
= new_tex
->cb_color_info
;
608 memcpy(tex
->color_clear_value
, new_tex
->color_clear_value
,
609 sizeof(tex
->color_clear_value
));
610 tex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
612 tex
->surface
.htile_offset
= new_tex
->surface
.htile_offset
;
613 tex
->depth_clear_value
= new_tex
->depth_clear_value
;
614 tex
->dirty_level_mask
= new_tex
->dirty_level_mask
;
615 tex
->stencil_dirty_level_mask
= new_tex
->stencil_dirty_level_mask
;
616 tex
->db_render_format
= new_tex
->db_render_format
;
617 tex
->stencil_clear_value
= new_tex
->stencil_clear_value
;
618 tex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
619 tex
->depth_cleared
= new_tex
->depth_cleared
;
620 tex
->stencil_cleared
= new_tex
->stencil_cleared
;
621 tex
->upgraded_depth
= new_tex
->upgraded_depth
;
622 tex
->db_compatible
= new_tex
->db_compatible
;
623 tex
->can_sample_z
= new_tex
->can_sample_z
;
624 tex
->can_sample_s
= new_tex
->can_sample_s
;
626 tex
->separate_dcc_dirty
= new_tex
->separate_dcc_dirty
;
627 tex
->displayable_dcc_dirty
= new_tex
->displayable_dcc_dirty
;
628 tex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
629 si_resource_reference(&tex
->dcc_separate_buffer
,
630 new_tex
->dcc_separate_buffer
);
631 si_resource_reference(&tex
->last_dcc_separate_buffer
,
632 new_tex
->last_dcc_separate_buffer
);
634 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
635 assert(!tex
->surface
.htile_offset
);
636 assert(!tex
->cmask_buffer
);
637 assert(!tex
->surface
.fmask_size
);
638 assert(!tex
->surface
.dcc_offset
);
639 assert(!tex
->is_depth
);
642 si_texture_reference(&new_tex
, NULL
);
644 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
647 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
649 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
652 static void si_set_tex_bo_metadata(struct si_screen
*sscreen
,
653 struct si_texture
*tex
)
655 struct radeon_surf
*surface
= &tex
->surface
;
656 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
657 struct radeon_bo_metadata md
;
659 memset(&md
, 0, sizeof(md
));
661 if (sscreen
->info
.chip_class
>= GFX9
) {
662 md
.u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
663 md
.u
.gfx9
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
665 if (tex
->surface
.dcc_offset
&& !tex
->dcc_separate_buffer
) {
666 uint64_t dcc_offset
=
667 tex
->surface
.display_dcc_offset
? tex
->surface
.display_dcc_offset
668 : tex
->surface
.dcc_offset
;
670 assert((dcc_offset
>> 8) != 0 && (dcc_offset
>> 8) < (1 << 24));
671 md
.u
.gfx9
.dcc_offset_256B
= dcc_offset
>> 8;
672 md
.u
.gfx9
.dcc_pitch_max
= tex
->surface
.u
.gfx9
.display_dcc_pitch_max
;
673 md
.u
.gfx9
.dcc_independent_64B
= 1;
676 md
.u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
677 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
678 md
.u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
679 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
680 md
.u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
681 md
.u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
682 md
.u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
683 md
.u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
684 md
.u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
685 md
.u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
686 md
.u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
687 md
.u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
690 assert(tex
->dcc_separate_buffer
== NULL
);
691 assert(tex
->surface
.fmask_size
== 0);
693 /* Metadata image format format version 1:
694 * [0] = 1 (metadata format identifier)
695 * [1] = (VENDOR_ID << 16) | PCI_ID
696 * [2:9] = image descriptor for the whole resource
697 * [2] is always 0, because the base address is cleared
698 * [9] is the DCC offset bits [39:8] from the beginning of
700 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
703 md
.metadata
[0] = 1; /* metadata image format version 1 */
705 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
706 md
.metadata
[1] = si_get_bo_metadata_word1(sscreen
);
708 static const unsigned char swizzle
[] = {
714 bool is_array
= util_texture_is_array(res
->target
);
717 sscreen
->make_texture_descriptor(sscreen
, tex
, true,
718 res
->target
, res
->format
,
719 swizzle
, 0, res
->last_level
, 0,
720 is_array
? res
->array_size
- 1 : 0,
721 res
->width0
, res
->height0
, res
->depth0
,
724 si_set_mutable_tex_desc_fields(sscreen
, tex
, &tex
->surface
.u
.legacy
.level
[0],
725 0, 0, tex
->surface
.blk_w
, false, desc
);
727 /* Clear the base address and set the relative DCC offset. */
729 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
731 switch (sscreen
->info
.chip_class
) {
736 desc
[7] = tex
->surface
.dcc_offset
>> 8;
739 desc
[7] = tex
->surface
.dcc_offset
>> 8;
740 desc
[5] &= C_008F24_META_DATA_ADDRESS
;
741 desc
[5] |= S_008F24_META_DATA_ADDRESS(tex
->surface
.dcc_offset
>> 40);
744 desc
[6] &= C_00A018_META_DATA_ADDRESS_LO
;
745 desc
[6] |= S_00A018_META_DATA_ADDRESS_LO(tex
->surface
.dcc_offset
>> 8);
746 desc
[7] = tex
->surface
.dcc_offset
>> 16;
753 /* Dwords [2:9] contain the image descriptor. */
754 memcpy(&md
.metadata
[2], desc
, sizeof(desc
));
755 md
.size_metadata
= 10 * 4;
757 /* Dwords [10:..] contain the mipmap level offsets. */
758 if (sscreen
->info
.chip_class
<= GFX8
) {
759 for (unsigned i
= 0; i
<= res
->last_level
; i
++)
760 md
.metadata
[10+i
] = tex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
762 md
.size_metadata
+= (1 + res
->last_level
) * 4;
765 sscreen
->ws
->buffer_set_metadata(tex
->buffer
.buf
, &md
);
768 static bool si_read_tex_bo_metadata(struct si_screen
*sscreen
,
769 struct si_texture
*tex
,
771 struct radeon_bo_metadata
*md
)
773 uint32_t *desc
= &md
->metadata
[2];
775 if (offset
|| /* Non-zero planes ignore metadata. */
776 md
->size_metadata
< 10 * 4 || /* at least 2(header) + 8(desc) dwords */
777 md
->metadata
[0] == 0 || /* invalid version number */
778 md
->metadata
[1] != si_get_bo_metadata_word1(sscreen
)) /* invalid PCI ID */ {
779 /* Disable DCC because it might not be enabled. */
780 si_texture_zero_dcc_fields(tex
);
782 /* Don't report an error if the texture comes from an incompatible driver,
783 * but this might not work.
788 /* Validate that sample counts and the number of mipmap levels match. */
789 unsigned last_level
= G_008F1C_LAST_LEVEL(desc
[3]);
790 unsigned type
= G_008F1C_TYPE(desc
[3]);
792 if (type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA
||
793 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
794 unsigned log_samples
=
795 util_logbase2(MAX2(1, tex
->buffer
.b
.b
.nr_storage_samples
));
797 if (last_level
!= log_samples
) {
798 fprintf(stderr
, "radeonsi: invalid MSAA texture import, "
799 "metadata has log2(samples) = %u, the caller set %u\n",
800 last_level
, log_samples
);
804 if (last_level
!= tex
->buffer
.b
.b
.last_level
) {
805 fprintf(stderr
, "radeonsi: invalid mipmapped texture import, "
806 "metadata has last_level = %u, the caller set %u\n",
807 last_level
, tex
->buffer
.b
.b
.last_level
);
812 if (sscreen
->info
.chip_class
>= GFX8
&&
813 G_008F28_COMPRESSION_EN(desc
[6])) {
814 /* Read DCC information. */
815 switch (sscreen
->info
.chip_class
) {
817 tex
->surface
.dcc_offset
= (uint64_t)desc
[7] << 8;
821 tex
->surface
.dcc_offset
=
822 ((uint64_t)desc
[7] << 8) |
823 ((uint64_t)G_008F24_META_DATA_ADDRESS(desc
[5]) << 40);
824 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
=
825 G_008F24_META_PIPE_ALIGNED(desc
[5]);
826 tex
->surface
.u
.gfx9
.dcc
.rb_aligned
=
827 G_008F24_META_RB_ALIGNED(desc
[5]);
829 /* If DCC is unaligned, this can only be a displayable image. */
830 if (!tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&&
831 !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
832 assert(tex
->surface
.is_displayable
);
836 tex
->surface
.dcc_offset
=
837 ((uint64_t)G_00A018_META_DATA_ADDRESS_LO(desc
[6]) << 8) |
838 ((uint64_t)desc
[7] << 16);
839 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
=
840 G_00A018_META_PIPE_ALIGNED(desc
[6]);
848 /* Disable DCC. dcc_offset is always set by texture_from_handle
849 * and must be cleared here.
851 si_texture_zero_dcc_fields(tex
);
857 static bool si_has_displayable_dcc(struct si_texture
*tex
)
859 struct si_screen
*sscreen
= (struct si_screen
*)tex
->buffer
.b
.b
.screen
;
861 if (sscreen
->info
.chip_class
<= GFX8
)
864 /* This needs a cache flush before scanout.
865 * (it can't be scanned out and rendered to simultaneously)
867 if (sscreen
->info
.use_display_dcc_unaligned
&&
868 tex
->surface
.dcc_offset
&&
869 !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&&
870 !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
873 /* This needs an explicit flush (flush_resource). */
874 if (sscreen
->info
.use_display_dcc_with_retile_blit
&&
875 tex
->surface
.display_dcc_offset
)
881 static bool si_resource_get_param(struct pipe_screen
*screen
,
882 struct pipe_context
*context
,
883 struct pipe_resource
*resource
,
886 enum pipe_resource_param param
,
887 unsigned handle_usage
,
890 for (unsigned i
= 0; i
< plane
; i
++)
891 resource
= resource
->next
;
893 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
894 struct si_texture
*tex
= (struct si_texture
*)resource
;
895 struct winsys_handle whandle
;
898 case PIPE_RESOURCE_PARAM_NPLANES
:
899 *value
= resource
->target
== PIPE_BUFFER
? 1 : tex
->num_planes
;
902 case PIPE_RESOURCE_PARAM_STRIDE
:
903 if (resource
->target
== PIPE_BUFFER
)
905 else if (sscreen
->info
.chip_class
>= GFX9
)
906 *value
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
908 *value
= tex
->surface
.u
.legacy
.level
[0].nblk_x
* tex
->surface
.bpe
;
911 case PIPE_RESOURCE_PARAM_OFFSET
:
912 if (resource
->target
== PIPE_BUFFER
)
914 else if (sscreen
->info
.chip_class
>= GFX9
)
915 *value
= tex
->surface
.u
.gfx9
.surf_offset
+
916 layer
* tex
->surface
.u
.gfx9
.surf_slice_size
;
918 *value
= tex
->surface
.u
.legacy
.level
[0].offset
+
919 layer
* (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
922 case PIPE_RESOURCE_PARAM_MODIFIER
:
923 *value
= DRM_FORMAT_MOD_INVALID
;
926 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
927 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
:
928 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
929 memset(&whandle
, 0, sizeof(whandle
));
931 if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
)
932 whandle
.type
= WINSYS_HANDLE_TYPE_SHARED
;
933 else if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
)
934 whandle
.type
= WINSYS_HANDLE_TYPE_KMS
;
935 else if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
)
936 whandle
.type
= WINSYS_HANDLE_TYPE_FD
;
938 if (!screen
->resource_get_handle(screen
, context
, resource
,
939 &whandle
, handle_usage
))
942 *value
= whandle
.handle
;
948 static void si_texture_get_info(struct pipe_screen
* screen
,
949 struct pipe_resource
*resource
,
956 si_resource_get_param(screen
, NULL
, resource
, 0, 0,
957 PIPE_RESOURCE_PARAM_STRIDE
, 0, &value
);
962 si_resource_get_param(screen
, NULL
, resource
, 0, 0,
963 PIPE_RESOURCE_PARAM_OFFSET
, 0, &value
);
968 static bool si_texture_get_handle(struct pipe_screen
* screen
,
969 struct pipe_context
*ctx
,
970 struct pipe_resource
*resource
,
971 struct winsys_handle
*whandle
,
974 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
975 struct si_context
*sctx
;
976 struct si_resource
*res
= si_resource(resource
);
977 struct si_texture
*tex
= (struct si_texture
*)resource
;
978 bool update_metadata
= false;
979 unsigned stride
, offset
, slice_size
;
982 ctx
= threaded_context_unwrap_sync(ctx
);
983 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
985 if (resource
->target
!= PIPE_BUFFER
) {
986 /* Individual planes are chained pipe_resource instances. */
987 for (unsigned i
= 0; i
< whandle
->plane
; i
++) {
988 resource
= resource
->next
;
989 res
= si_resource(resource
);
990 tex
= (struct si_texture
*)resource
;
993 /* This is not supported now, but it might be required for OpenCL
994 * interop in the future.
996 if (resource
->nr_samples
> 1 || tex
->is_depth
)
999 /* Move a suballocated texture into a non-suballocated allocation. */
1000 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
1001 tex
->surface
.tile_swizzle
||
1002 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
1003 sscreen
->info
.has_local_buffers
)) {
1004 assert(!res
->b
.is_shared
);
1005 si_reallocate_texture_inplace(sctx
, tex
,
1006 PIPE_BIND_SHARED
, false);
1008 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
1009 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
1010 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
1011 assert(tex
->surface
.tile_swizzle
== 0);
1014 /* Since shader image stores don't support DCC on GFX8,
1015 * disable it for external clients that want write
1018 if ((usage
& PIPE_HANDLE_USAGE_SHADER_WRITE
&& tex
->surface
.dcc_offset
) ||
1019 /* Displayable DCC requires an explicit flush. */
1020 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
1021 si_has_displayable_dcc(tex
))) {
1022 if (si_texture_disable_dcc(sctx
, tex
)) {
1023 update_metadata
= true;
1024 /* si_texture_disable_dcc flushes the context */
1029 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
1030 (tex
->cmask_buffer
|| tex
->surface
.dcc_offset
)) {
1031 /* Eliminate fast clear (both CMASK and DCC) */
1032 si_eliminate_fast_color_clear(sctx
, tex
);
1033 /* eliminate_fast_color_clear flushes the context */
1036 /* Disable CMASK if flush_resource isn't going
1039 if (tex
->cmask_buffer
)
1040 si_texture_discard_cmask(sscreen
, tex
);
1044 if ((!res
->b
.is_shared
|| update_metadata
) && whandle
->offset
== 0)
1045 si_set_tex_bo_metadata(sscreen
, tex
);
1047 if (sscreen
->info
.chip_class
>= GFX9
) {
1048 slice_size
= tex
->surface
.u
.gfx9
.surf_slice_size
;
1050 slice_size
= (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
1053 /* Buffer exports are for the OpenCL interop. */
1054 /* Move a suballocated buffer into a non-suballocated allocation. */
1055 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
1056 /* A DMABUF export always fails if the BO is local. */
1057 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
1058 sscreen
->info
.has_local_buffers
)) {
1059 assert(!res
->b
.is_shared
);
1061 /* Allocate a new buffer with PIPE_BIND_SHARED. */
1062 struct pipe_resource templ
= res
->b
.b
;
1063 templ
.bind
|= PIPE_BIND_SHARED
;
1065 struct pipe_resource
*newb
=
1066 screen
->resource_create(screen
, &templ
);
1070 /* Copy the old buffer contents to the new one. */
1071 struct pipe_box box
;
1072 u_box_1d(0, newb
->width0
, &box
);
1073 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0,
1074 &res
->b
.b
, 0, &box
);
1076 /* Move the new buffer storage to the old pipe_resource. */
1077 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
1078 pipe_resource_reference(&newb
, NULL
);
1080 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
1081 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
1088 si_texture_get_info(screen
, resource
, &stride
, &offset
);
1091 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
1093 if (res
->b
.is_shared
) {
1094 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
1097 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
1098 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
1099 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
1101 res
->b
.is_shared
= true;
1102 res
->external_usage
= usage
;
1105 whandle
->stride
= stride
;
1106 whandle
->offset
= offset
+ slice_size
* whandle
->layer
;
1108 return sscreen
->ws
->buffer_get_handle(sscreen
->ws
, res
->buf
, whandle
);
1111 static void si_texture_destroy(struct pipe_screen
*screen
,
1112 struct pipe_resource
*ptex
)
1114 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1115 struct si_texture
*tex
= (struct si_texture
*)ptex
;
1116 struct si_resource
*resource
= &tex
->buffer
;
1118 if (sscreen
->info
.chip_class
>= GFX9
)
1119 free(tex
->surface
.u
.gfx9
.dcc_retile_map
);
1121 si_texture_reference(&tex
->flushed_depth_texture
, NULL
);
1123 if (tex
->cmask_buffer
!= &tex
->buffer
) {
1124 si_resource_reference(&tex
->cmask_buffer
, NULL
);
1126 pb_reference(&resource
->buf
, NULL
);
1127 si_resource_reference(&tex
->dcc_separate_buffer
, NULL
);
1128 si_resource_reference(&tex
->last_dcc_separate_buffer
, NULL
);
1132 static const struct u_resource_vtbl si_texture_vtbl
;
1134 void si_print_texture_info(struct si_screen
*sscreen
,
1135 struct si_texture
*tex
, struct u_log_context
*log
)
1139 /* Common parameters. */
1140 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1141 "blk_h=%u, array_size=%u, last_level=%u, "
1142 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1143 tex
->buffer
.b
.b
.width0
, tex
->buffer
.b
.b
.height0
,
1144 tex
->buffer
.b
.b
.depth0
, tex
->surface
.blk_w
,
1146 tex
->buffer
.b
.b
.array_size
, tex
->buffer
.b
.b
.last_level
,
1147 tex
->surface
.bpe
, tex
->buffer
.b
.b
.nr_samples
,
1148 tex
->surface
.flags
, util_format_short_name(tex
->buffer
.b
.b
.format
));
1150 if (sscreen
->info
.chip_class
>= GFX9
) {
1151 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1152 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1153 tex
->surface
.surf_size
,
1154 tex
->surface
.u
.gfx9
.surf_slice_size
,
1155 tex
->surface
.surf_alignment
,
1156 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1157 tex
->surface
.u
.gfx9
.surf
.epitch
,
1158 tex
->surface
.u
.gfx9
.surf_pitch
);
1160 if (tex
->surface
.fmask_offset
) {
1161 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1162 "alignment=%u, swmode=%u, epitch=%u\n",
1163 tex
->surface
.fmask_offset
,
1164 tex
->surface
.fmask_size
,
1165 tex
->surface
.fmask_alignment
,
1166 tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1167 tex
->surface
.u
.gfx9
.fmask
.epitch
);
1170 if (tex
->cmask_buffer
) {
1171 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, "
1172 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1173 tex
->surface
.cmask_offset
,
1174 tex
->surface
.cmask_size
,
1175 tex
->surface
.cmask_alignment
,
1176 tex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1177 tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1180 if (tex
->surface
.htile_offset
) {
1181 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1182 "rb_aligned=%u, pipe_aligned=%u\n",
1183 tex
->surface
.htile_offset
,
1184 tex
->surface
.htile_size
,
1185 tex
->surface
.htile_alignment
,
1186 tex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1187 tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1190 if (tex
->surface
.dcc_offset
) {
1191 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1192 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1193 tex
->surface
.dcc_offset
, tex
->surface
.dcc_size
,
1194 tex
->surface
.dcc_alignment
,
1195 tex
->surface
.u
.gfx9
.display_dcc_pitch_max
,
1196 tex
->surface
.num_dcc_levels
);
1199 if (tex
->surface
.u
.gfx9
.stencil_offset
) {
1200 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1201 tex
->surface
.u
.gfx9
.stencil_offset
,
1202 tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1203 tex
->surface
.u
.gfx9
.stencil
.epitch
);
1208 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1209 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1210 tex
->surface
.surf_size
, tex
->surface
.surf_alignment
, tex
->surface
.u
.legacy
.bankw
,
1211 tex
->surface
.u
.legacy
.bankh
, tex
->surface
.u
.legacy
.num_banks
, tex
->surface
.u
.legacy
.mtilea
,
1212 tex
->surface
.u
.legacy
.tile_split
, tex
->surface
.u
.legacy
.pipe_config
,
1213 (tex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1215 if (tex
->surface
.fmask_offset
)
1216 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1217 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1218 tex
->surface
.fmask_offset
, tex
->surface
.fmask_size
, tex
->surface
.fmask_alignment
,
1219 tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
,
1220 tex
->surface
.u
.legacy
.fmask
.bankh
,
1221 tex
->surface
.u
.legacy
.fmask
.slice_tile_max
,
1222 tex
->surface
.u
.legacy
.fmask
.tiling_index
);
1224 if (tex
->cmask_buffer
)
1225 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, alignment=%u, "
1226 "slice_tile_max=%u\n",
1227 tex
->surface
.cmask_offset
, tex
->surface
.cmask_size
, tex
->surface
.cmask_alignment
,
1228 tex
->surface
.u
.legacy
.cmask_slice_tile_max
);
1230 if (tex
->surface
.htile_offset
)
1231 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1232 "alignment=%u, TC_compatible = %u\n",
1233 tex
->surface
.htile_offset
, tex
->surface
.htile_size
,
1234 tex
->surface
.htile_alignment
,
1235 tex
->tc_compatible_htile
);
1237 if (tex
->surface
.dcc_offset
) {
1238 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1239 tex
->surface
.dcc_offset
, tex
->surface
.dcc_size
,
1240 tex
->surface
.dcc_alignment
);
1241 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1242 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1243 "fast_clear_size=%u\n",
1244 i
, i
< tex
->surface
.num_dcc_levels
,
1245 tex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1246 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1249 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1250 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1251 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1252 "mode=%u, tiling_index = %u\n",
1253 i
, tex
->surface
.u
.legacy
.level
[i
].offset
,
1254 (uint64_t)tex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1255 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1256 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1257 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1258 tex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1259 tex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1260 tex
->surface
.u
.legacy
.level
[i
].mode
,
1261 tex
->surface
.u
.legacy
.tiling_index
[i
]);
1263 if (tex
->surface
.has_stencil
) {
1264 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1265 tex
->surface
.u
.legacy
.stencil_tile_split
);
1266 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++) {
1267 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1268 "slice_size=%"PRIu64
", npix_x=%u, "
1269 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1270 "mode=%u, tiling_index = %u\n",
1271 i
, tex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1272 (uint64_t)tex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1273 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1274 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1275 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1276 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1277 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1278 tex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1279 tex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1285 * Common function for si_texture_create and si_texture_from_handle.
1287 * \param screen screen
1288 * \param base resource template
1289 * \param surface radeon_surf
1290 * \param plane0 if a non-zero plane is being created, this is the first plane
1291 * \param imported_buf from si_texture_from_handle
1292 * \param offset offset for non-zero planes or imported buffers
1293 * \param alloc_size the size to allocate if plane0 != NULL
1294 * \param alignment alignment for the allocation
1296 static struct si_texture
*
1297 si_texture_create_object(struct pipe_screen
*screen
,
1298 const struct pipe_resource
*base
,
1299 const struct radeon_surf
*surface
,
1300 const struct si_texture
*plane0
,
1301 struct pb_buffer
*imported_buf
,
1303 uint64_t alloc_size
,
1306 struct si_texture
*tex
;
1307 struct si_resource
*resource
;
1308 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1310 tex
= CALLOC_STRUCT(si_texture
);
1314 resource
= &tex
->buffer
;
1315 resource
->b
.b
= *base
;
1316 resource
->b
.b
.next
= NULL
;
1317 resource
->b
.vtbl
= &si_texture_vtbl
;
1318 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1319 resource
->b
.b
.screen
= screen
;
1321 /* don't include stencil-only formats which we don't support for rendering */
1322 tex
->is_depth
= util_format_has_depth(util_format_description(tex
->buffer
.b
.b
.format
));
1323 tex
->surface
= *surface
;
1324 tex
->tc_compatible_htile
= tex
->surface
.htile_size
!= 0 &&
1325 (tex
->surface
.flags
&
1326 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1328 /* TC-compatible HTILE:
1329 * - GFX8 only supports Z32_FLOAT.
1330 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1331 if (tex
->tc_compatible_htile
) {
1332 if (sscreen
->info
.chip_class
>= GFX9
&&
1333 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1334 tex
->db_render_format
= base
->format
;
1336 tex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1337 tex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1338 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1341 tex
->db_render_format
= base
->format
;
1344 /* Applies to GCN. */
1345 tex
->last_msaa_resolve_target_micro_mode
= tex
->surface
.micro_tile_mode
;
1347 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1348 * between frames, so the only thing that can enable separate DCC
1349 * with DRI2 is multiple slow clears within a frame.
1351 tex
->ps_draw_ratio
= 0;
1353 if (sscreen
->info
.chip_class
>= GFX9
) {
1354 tex
->surface
.u
.gfx9
.surf_offset
= offset
;
1356 for (unsigned i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
1357 tex
->surface
.u
.legacy
.level
[i
].offset
+= offset
;
1360 if (tex
->is_depth
) {
1361 if (sscreen
->info
.chip_class
>= GFX9
) {
1362 tex
->can_sample_z
= true;
1363 tex
->can_sample_s
= true;
1365 /* Stencil texturing with HTILE doesn't work
1366 * with mipmapping on Navi10-14. */
1367 if ((sscreen
->info
.family
== CHIP_NAVI10
||
1368 sscreen
->info
.family
== CHIP_NAVI12
||
1369 sscreen
->info
.family
== CHIP_NAVI14
) &&
1370 base
->last_level
> 0)
1371 tex
->htile_stencil_disabled
= true;
1373 tex
->can_sample_z
= !tex
->surface
.u
.legacy
.depth_adjusted
;
1374 tex
->can_sample_s
= !tex
->surface
.u
.legacy
.stencil_adjusted
;
1377 tex
->db_compatible
= surface
->flags
& RADEON_SURF_ZBUFFER
;
1379 if (tex
->surface
.cmask_offset
) {
1380 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
1381 tex
->cmask_buffer
= &tex
->buffer
;
1386 /* The buffer is shared with the first plane. */
1387 resource
->bo_size
= plane0
->buffer
.bo_size
;
1388 resource
->bo_alignment
= plane0
->buffer
.bo_alignment
;
1389 resource
->flags
= plane0
->buffer
.flags
;
1390 resource
->domains
= plane0
->buffer
.domains
;
1391 resource
->vram_usage
= plane0
->buffer
.vram_usage
;
1392 resource
->gart_usage
= plane0
->buffer
.gart_usage
;
1394 pb_reference(&resource
->buf
, plane0
->buffer
.buf
);
1395 resource
->gpu_address
= plane0
->buffer
.gpu_address
;
1396 } else if (!(surface
->flags
& RADEON_SURF_IMPORTED
)) {
1397 /* Create the backing buffer. */
1398 si_init_resource_fields(sscreen
, resource
, alloc_size
, alignment
);
1400 if (!si_alloc_resource(sscreen
, resource
))
1403 resource
->buf
= imported_buf
;
1404 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1405 resource
->bo_size
= imported_buf
->size
;
1406 resource
->bo_alignment
= imported_buf
->alignment
;
1407 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1408 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1409 resource
->vram_usage
= resource
->bo_size
;
1410 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1411 resource
->gart_usage
= resource
->bo_size
;
1414 if (tex
->cmask_buffer
) {
1415 /* Initialize the cmask to 0xCC (= compressed state). */
1416 si_screen_clear_buffer(sscreen
, &tex
->cmask_buffer
->b
.b
,
1417 tex
->surface
.cmask_offset
, tex
->surface
.cmask_size
,
1420 if (tex
->surface
.htile_offset
) {
1421 uint32_t clear_value
= 0;
1423 if (sscreen
->info
.chip_class
>= GFX9
|| tex
->tc_compatible_htile
)
1424 clear_value
= 0x0000030F;
1426 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1427 tex
->surface
.htile_offset
,
1428 tex
->surface
.htile_size
,
1432 /* Initialize DCC only if the texture is not being imported. */
1433 if (!(surface
->flags
& RADEON_SURF_IMPORTED
) && tex
->surface
.dcc_offset
) {
1434 /* Clear DCC to black for all tiles with DCC enabled.
1436 * This fixes corruption in 3DMark Slingshot Extreme, which
1437 * uses uninitialized textures, causing corruption.
1439 if (tex
->surface
.num_dcc_levels
== tex
->buffer
.b
.b
.last_level
+ 1 &&
1440 tex
->buffer
.b
.b
.nr_samples
<= 2) {
1441 /* Simple case - all tiles have DCC enabled. */
1442 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1443 tex
->surface
.dcc_offset
,
1444 tex
->surface
.dcc_size
,
1445 DCC_CLEAR_COLOR_0000
);
1446 } else if (sscreen
->info
.chip_class
>= GFX9
) {
1447 /* Clear to uncompressed. Clearing this to black is complicated. */
1448 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1449 tex
->surface
.dcc_offset
,
1450 tex
->surface
.dcc_size
,
1453 /* GFX8: Initialize mipmap levels and multisamples separately. */
1454 if (tex
->buffer
.b
.b
.nr_samples
>= 2) {
1455 /* Clearing this to black is complicated. */
1456 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1457 tex
->surface
.dcc_offset
,
1458 tex
->surface
.dcc_size
,
1461 /* Clear the enabled mipmap levels to black. */
1464 for (unsigned i
= 0; i
< tex
->surface
.num_dcc_levels
; i
++) {
1465 if (!tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
)
1468 size
= tex
->surface
.u
.legacy
.level
[i
].dcc_offset
+
1469 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
;
1472 /* Mipmap levels with DCC. */
1474 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1475 tex
->surface
.dcc_offset
, size
,
1476 DCC_CLEAR_COLOR_0000
);
1478 /* Mipmap levels without DCC. */
1479 if (size
!= tex
->surface
.dcc_size
) {
1480 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1481 tex
->surface
.dcc_offset
+ size
,
1482 tex
->surface
.dcc_size
- size
,
1488 /* Initialize displayable DCC that requires the retile blit. */
1489 if (tex
->surface
.dcc_retile_map_offset
) {
1490 /* Uninitialized DCC can hang the display hw.
1491 * Clear to white to indicate that. */
1492 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1493 tex
->surface
.display_dcc_offset
,
1494 tex
->surface
.u
.gfx9
.display_dcc_size
,
1495 DCC_CLEAR_COLOR_1111
);
1497 /* Upload the DCC retile map.
1498 * Use a staging buffer for the upload, because
1499 * the buffer backing the texture is unmappable.
1501 bool use_uint16
= tex
->surface
.u
.gfx9
.dcc_retile_use_uint16
;
1502 unsigned num_elements
= tex
->surface
.u
.gfx9
.dcc_retile_num_elements
;
1503 struct si_resource
*buf
=
1504 si_aligned_buffer_create(screen
, 0, PIPE_USAGE_STREAM
,
1505 num_elements
* (use_uint16
? 2 : 4),
1506 sscreen
->info
.tcc_cache_line_size
);
1507 uint32_t *ui
= (uint32_t*)sscreen
->ws
->buffer_map(buf
->buf
, NULL
,
1508 PIPE_TRANSFER_WRITE
);
1509 uint16_t *us
= (uint16_t*)ui
;
1511 /* Upload the retile map into a staging buffer. */
1513 for (unsigned i
= 0; i
< num_elements
; i
++)
1514 us
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1516 for (unsigned i
= 0; i
< num_elements
; i
++)
1517 ui
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1520 /* Copy the staging buffer to the buffer backing the texture. */
1521 struct si_context
*sctx
= (struct si_context
*)sscreen
->aux_context
;
1523 assert(tex
->surface
.dcc_retile_map_offset
<= UINT_MAX
);
1524 simple_mtx_lock(&sscreen
->aux_context_lock
);
1525 si_sdma_copy_buffer(sctx
, &tex
->buffer
.b
.b
, &buf
->b
.b
,
1526 tex
->surface
.dcc_retile_map_offset
,
1527 0, buf
->b
.b
.width0
);
1528 sscreen
->aux_context
->flush(sscreen
->aux_context
, NULL
, 0);
1529 simple_mtx_unlock(&sscreen
->aux_context_lock
);
1531 si_resource_reference(&buf
, NULL
);
1535 /* Initialize the CMASK base register value. */
1536 tex
->cmask_base_address_reg
=
1537 (tex
->buffer
.gpu_address
+ tex
->surface
.cmask_offset
) >> 8;
1539 if (sscreen
->debug_flags
& DBG(VM
)) {
1540 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1541 tex
->buffer
.gpu_address
,
1542 tex
->buffer
.gpu_address
+ tex
->buffer
.buf
->size
,
1543 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1544 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1547 if (sscreen
->debug_flags
& DBG(TEX
)) {
1549 struct u_log_context log
;
1550 u_log_context_init(&log
);
1551 si_print_texture_info(sscreen
, tex
, &log
);
1552 u_log_new_page_print(&log
, stdout
);
1554 u_log_context_destroy(&log
);
1561 if (sscreen
->info
.chip_class
>= GFX9
)
1562 free(surface
->u
.gfx9
.dcc_retile_map
);
1566 static enum radeon_surf_mode
1567 si_choose_tiling(struct si_screen
*sscreen
,
1568 const struct pipe_resource
*templ
, bool tc_compatible_htile
)
1570 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1571 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
;
1572 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1573 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1575 /* MSAA resources must be 2D tiled. */
1576 if (templ
->nr_samples
> 1)
1577 return RADEON_SURF_MODE_2D
;
1579 /* Transfer resources should be linear. */
1580 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1581 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1583 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on GFX8,
1584 * which requires 2D tiling.
1586 if (sscreen
->info
.chip_class
== GFX8
&& tc_compatible_htile
)
1587 return RADEON_SURF_MODE_2D
;
1589 /* Handle common candidates for the linear mode.
1590 * Compressed textures and DB surfaces must always be tiled.
1592 if (!force_tiling
&&
1593 !is_depth_stencil
&&
1594 !util_format_is_compressed(templ
->format
)) {
1595 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1596 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1598 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1599 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1600 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1602 /* Cursors are linear on AMD GCN.
1603 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1604 if (templ
->bind
& PIPE_BIND_CURSOR
)
1605 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1607 if (templ
->bind
& PIPE_BIND_LINEAR
)
1608 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1610 /* Textures with a very small height are recommended to be linear. */
1611 if (templ
->target
== PIPE_TEXTURE_1D
||
1612 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1613 /* Only very thin and long 2D textures should benefit from
1614 * linear_aligned. */
1615 (templ
->width0
> 8 && templ
->height0
<= 2))
1616 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1618 /* Textures likely to be mapped often. */
1619 if (templ
->usage
== PIPE_USAGE_STAGING
||
1620 templ
->usage
== PIPE_USAGE_STREAM
)
1621 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1624 /* Make small textures 1D tiled. */
1625 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1626 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1627 return RADEON_SURF_MODE_1D
;
1629 /* The allocator will switch to 1D if needed. */
1630 return RADEON_SURF_MODE_2D
;
1633 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1634 const struct pipe_resource
*templ
)
1636 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1637 bool is_zs
= util_format_is_depth_or_stencil(templ
->format
);
1639 if (templ
->nr_samples
>= 2) {
1640 /* This is hackish (overwriting the const pipe_resource template),
1641 * but should be harmless and state trackers can also see
1642 * the overriden number of samples in the created pipe_resource.
1644 if (is_zs
&& sscreen
->eqaa_force_z_samples
) {
1645 ((struct pipe_resource
*)templ
)->nr_samples
=
1646 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1647 sscreen
->eqaa_force_z_samples
;
1648 } else if (!is_zs
&& sscreen
->eqaa_force_color_samples
) {
1649 ((struct pipe_resource
*)templ
)->nr_samples
=
1650 sscreen
->eqaa_force_coverage_samples
;
1651 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1652 sscreen
->eqaa_force_color_samples
;
1656 bool is_flushed_depth
= templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
||
1657 templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
;
1658 bool tc_compatible_htile
=
1659 sscreen
->info
.chip_class
>= GFX8
&&
1660 /* There are issues with TC-compatible HTILE on Tonga (and
1661 * Iceland is the same design), and documented bug workarounds
1662 * don't help. For example, this fails:
1663 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1665 sscreen
->info
.family
!= CHIP_TONGA
&&
1666 sscreen
->info
.family
!= CHIP_ICELAND
&&
1667 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1668 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1669 !is_flushed_depth
&&
1670 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1672 enum radeon_surf_mode tile_mode
= si_choose_tiling(sscreen
, templ
,
1673 tc_compatible_htile
);
1675 /* This allocates textures with multiple planes like NV12 in 1 buffer. */
1676 enum { SI_TEXTURE_MAX_PLANES
= 3 };
1677 struct radeon_surf surface
[SI_TEXTURE_MAX_PLANES
] = {};
1678 struct pipe_resource plane_templ
[SI_TEXTURE_MAX_PLANES
];
1679 uint64_t plane_offset
[SI_TEXTURE_MAX_PLANES
] = {};
1680 uint64_t total_size
= 0;
1681 unsigned max_alignment
= 0;
1682 unsigned num_planes
= util_format_get_num_planes(templ
->format
);
1683 assert(num_planes
<= SI_TEXTURE_MAX_PLANES
);
1685 /* Compute texture or plane layouts and offsets. */
1686 for (unsigned i
= 0; i
< num_planes
; i
++) {
1687 plane_templ
[i
] = *templ
;
1688 plane_templ
[i
].format
= util_format_get_plane_format(templ
->format
, i
);
1689 plane_templ
[i
].width0
= util_format_get_plane_width(templ
->format
, i
, templ
->width0
);
1690 plane_templ
[i
].height0
= util_format_get_plane_height(templ
->format
, i
, templ
->height0
);
1692 /* Multi-plane allocations need PIPE_BIND_SHARED, because we can't
1693 * reallocate the storage to add PIPE_BIND_SHARED, because it's
1694 * shared by 3 pipe_resources.
1697 plane_templ
[i
].bind
|= PIPE_BIND_SHARED
;
1699 if (si_init_surface(sscreen
, &surface
[i
], &plane_templ
[i
],
1700 tile_mode
, 0, false,
1701 plane_templ
[i
].bind
& PIPE_BIND_SCANOUT
,
1702 is_flushed_depth
, tc_compatible_htile
))
1705 plane_offset
[i
] = align64(total_size
, surface
[i
].surf_alignment
);
1706 total_size
= plane_offset
[i
] + surface
[i
].total_size
;
1707 max_alignment
= MAX2(max_alignment
, surface
[i
].surf_alignment
);
1710 struct si_texture
*plane0
= NULL
, *last_plane
= NULL
;
1712 for (unsigned i
= 0; i
< num_planes
; i
++) {
1713 struct si_texture
*tex
=
1714 si_texture_create_object(screen
, &plane_templ
[i
], &surface
[i
],
1715 plane0
, NULL
, plane_offset
[i
],
1716 total_size
, max_alignment
);
1718 si_texture_reference(&plane0
, NULL
);
1722 tex
->plane_index
= i
;
1723 tex
->num_planes
= num_planes
;
1726 plane0
= last_plane
= tex
;
1728 last_plane
->buffer
.b
.b
.next
= &tex
->buffer
.b
.b
;
1733 return (struct pipe_resource
*)plane0
;
1736 static struct pipe_resource
*si_texture_from_winsys_buffer(struct si_screen
*sscreen
,
1737 const struct pipe_resource
*templ
,
1738 struct pb_buffer
*buf
,
1744 enum radeon_surf_mode array_mode
;
1745 struct radeon_surf surface
= {};
1746 struct radeon_bo_metadata metadata
= {};
1747 struct si_texture
*tex
;
1751 /* Ignore metadata for non-zero planes. */
1756 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1757 si_get_display_metadata(sscreen
, &surface
, &metadata
,
1758 &array_mode
, &is_scanout
);
1761 * The bo metadata is unset for un-dedicated images. So we fall
1762 * back to linear. See answer to question 5 of the
1763 * VK_KHX_external_memory spec for some details.
1765 * It is possible that this case isn't going to work if the
1766 * surface pitch isn't correctly aligned by default.
1768 * In order to support it correctly we require multi-image
1769 * metadata to be syncrhonized between radv and radeonsi. The
1770 * semantics of associating multiple image metadata to a memory
1771 * object on the vulkan export side are not concretely defined
1774 * All the use cases we are aware of at the moment for memory
1775 * objects use dedicated allocations. So lets keep the initial
1776 * implementation simple.
1778 * A possible alternative is to attempt to reconstruct the
1779 * tiling information when the TexParameter TEXTURE_TILING_EXT
1782 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1786 r
= si_init_surface(sscreen
, &surface
, templ
,
1787 array_mode
, stride
, true, is_scanout
,
1792 tex
= si_texture_create_object(&sscreen
->b
, templ
, &surface
, NULL
, buf
,
1797 tex
->buffer
.b
.is_shared
= true;
1798 tex
->buffer
.external_usage
= usage
;
1799 tex
->num_planes
= 1;
1801 if (!si_read_tex_bo_metadata(sscreen
, tex
, offset
, &metadata
)) {
1802 si_texture_reference(&tex
, NULL
);
1806 /* Displayable DCC requires an explicit flush. */
1807 if (dedicated
&& offset
== 0 &&
1808 !(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
1809 si_has_displayable_dcc(tex
)) {
1810 /* TODO: do we need to decompress DCC? */
1811 if (si_texture_discard_dcc(sscreen
, tex
)) {
1812 /* Update BO metadata after disabling DCC. */
1813 si_set_tex_bo_metadata(sscreen
, tex
);
1817 assert(tex
->surface
.tile_swizzle
== 0);
1818 return &tex
->buffer
.b
.b
;
1821 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1822 const struct pipe_resource
*templ
,
1823 struct winsys_handle
*whandle
,
1826 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1827 struct pb_buffer
*buf
= NULL
;
1829 /* Support only 2D textures without mipmaps */
1830 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
&&
1831 templ
->target
!= PIPE_TEXTURE_2D_ARRAY
) ||
1832 templ
->last_level
!= 0)
1835 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
1836 sscreen
->info
.max_alignment
);
1840 return si_texture_from_winsys_buffer(sscreen
, templ
, buf
,
1841 whandle
->stride
, whandle
->offset
,
1845 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1846 struct pipe_resource
*texture
)
1848 struct si_texture
*tex
= (struct si_texture
*)texture
;
1849 struct pipe_resource resource
;
1850 enum pipe_format pipe_format
= texture
->format
;
1852 assert(!tex
->flushed_depth_texture
);
1854 if (!tex
->can_sample_z
&& tex
->can_sample_s
) {
1855 switch (pipe_format
) {
1856 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1857 /* Save memory by not allocating the S plane. */
1858 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1860 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1861 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1862 /* Save memory bandwidth by not copying the
1863 * stencil part during flush.
1865 * This potentially increases memory bandwidth
1866 * if an application uses both Z and S texturing
1867 * simultaneously (a flushed Z24S8 texture
1868 * would be stored compactly), but how often
1869 * does that really happen?
1871 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1875 } else if (!tex
->can_sample_s
&& tex
->can_sample_z
) {
1876 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1878 /* DB->CB copies to an 8bpp surface don't work. */
1879 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1882 memset(&resource
, 0, sizeof(resource
));
1883 resource
.target
= texture
->target
;
1884 resource
.format
= pipe_format
;
1885 resource
.width0
= texture
->width0
;
1886 resource
.height0
= texture
->height0
;
1887 resource
.depth0
= texture
->depth0
;
1888 resource
.array_size
= texture
->array_size
;
1889 resource
.last_level
= texture
->last_level
;
1890 resource
.nr_samples
= texture
->nr_samples
;
1891 resource
.usage
= PIPE_USAGE_DEFAULT
;
1892 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1893 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1895 tex
->flushed_depth_texture
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1896 if (!tex
->flushed_depth_texture
) {
1897 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1904 * Initialize the pipe_resource descriptor to be of the same size as the box,
1905 * which is supposed to hold a subregion of the texture "orig" at the given
1908 static void si_init_temp_resource_from_box(struct pipe_resource
*res
,
1909 struct pipe_resource
*orig
,
1910 const struct pipe_box
*box
,
1911 unsigned level
, unsigned flags
)
1913 memset(res
, 0, sizeof(*res
));
1914 res
->format
= orig
->format
;
1915 res
->width0
= box
->width
;
1916 res
->height0
= box
->height
;
1918 res
->array_size
= 1;
1919 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1922 if (flags
& SI_RESOURCE_FLAG_TRANSFER
&&
1923 util_format_is_compressed(orig
->format
)) {
1924 /* Transfer resources are allocated with linear tiling, which is
1925 * not supported for compressed formats.
1927 unsigned blocksize
=
1928 util_format_get_blocksize(orig
->format
);
1930 if (blocksize
== 8) {
1931 res
->format
= PIPE_FORMAT_R16G16B16A16_UINT
;
1933 assert(blocksize
== 16);
1934 res
->format
= PIPE_FORMAT_R32G32B32A32_UINT
;
1937 res
->width0
= util_format_get_nblocksx(orig
->format
, box
->width
);
1938 res
->height0
= util_format_get_nblocksy(orig
->format
, box
->height
);
1941 /* We must set the correct texture target and dimensions for a 3D box. */
1942 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1943 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1944 res
->array_size
= box
->depth
;
1946 res
->target
= PIPE_TEXTURE_2D
;
1950 static bool si_can_invalidate_texture(struct si_screen
*sscreen
,
1951 struct si_texture
*tex
,
1952 unsigned transfer_usage
,
1953 const struct pipe_box
*box
)
1955 return !tex
->buffer
.b
.is_shared
&&
1956 !(tex
->surface
.flags
& RADEON_SURF_IMPORTED
) &&
1957 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1958 tex
->buffer
.b
.b
.last_level
== 0 &&
1959 util_texrange_covers_whole_level(&tex
->buffer
.b
.b
, 0,
1960 box
->x
, box
->y
, box
->z
,
1961 box
->width
, box
->height
,
1965 static void si_texture_invalidate_storage(struct si_context
*sctx
,
1966 struct si_texture
*tex
)
1968 struct si_screen
*sscreen
= sctx
->screen
;
1970 /* There is no point in discarding depth and tiled buffers. */
1971 assert(!tex
->is_depth
);
1972 assert(tex
->surface
.is_linear
);
1974 /* Reallocate the buffer in the same pipe_resource. */
1975 si_alloc_resource(sscreen
, &tex
->buffer
);
1977 /* Initialize the CMASK base address (needed even without CMASK). */
1978 tex
->cmask_base_address_reg
=
1979 (tex
->buffer
.gpu_address
+ tex
->surface
.cmask_offset
) >> 8;
1981 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1983 sctx
->num_alloc_tex_transfer_bytes
+= tex
->surface
.total_size
;
1986 static void *si_texture_transfer_map(struct pipe_context
*ctx
,
1987 struct pipe_resource
*texture
,
1990 const struct pipe_box
*box
,
1991 struct pipe_transfer
**ptransfer
)
1993 struct si_context
*sctx
= (struct si_context
*)ctx
;
1994 struct si_texture
*tex
= (struct si_texture
*)texture
;
1995 struct si_transfer
*trans
;
1996 struct si_resource
*buf
;
1997 unsigned offset
= 0;
1999 bool use_staging_texture
= false;
2001 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
2002 assert(box
->width
&& box
->height
&& box
->depth
);
2004 if (tex
->is_depth
) {
2005 /* Depth textures use staging unconditionally. */
2006 use_staging_texture
= true;
2008 /* Degrade the tile mode if we get too many transfers on APUs.
2009 * On dGPUs, the staging texture is always faster.
2010 * Only count uploads that are at least 4x4 pixels large.
2012 if (!sctx
->screen
->info
.has_dedicated_vram
&&
2014 box
->width
>= 4 && box
->height
>= 4 &&
2015 p_atomic_inc_return(&tex
->num_level0_transfers
) == 10) {
2016 bool can_invalidate
=
2017 si_can_invalidate_texture(sctx
->screen
, tex
,
2020 si_reallocate_texture_inplace(sctx
, tex
,
2025 /* Tiled textures need to be converted into a linear texture for CPU
2026 * access. The staging texture is always linear and is placed in GART.
2028 * Reading from VRAM or GTT WC is slow, always use the staging
2029 * texture in this case.
2031 * Use the staging texture for uploads if the underlying BO
2034 if (!tex
->surface
.is_linear
)
2035 use_staging_texture
= true;
2036 else if (usage
& PIPE_TRANSFER_READ
)
2037 use_staging_texture
=
2038 tex
->buffer
.domains
& RADEON_DOMAIN_VRAM
||
2039 tex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
2040 /* Write & linear only: */
2041 else if (si_rings_is_buffer_referenced(sctx
, tex
->buffer
.buf
,
2042 RADEON_USAGE_READWRITE
) ||
2043 !sctx
->ws
->buffer_wait(tex
->buffer
.buf
, 0,
2044 RADEON_USAGE_READWRITE
)) {
2046 if (si_can_invalidate_texture(sctx
->screen
, tex
,
2048 si_texture_invalidate_storage(sctx
, tex
);
2050 use_staging_texture
= true;
2054 trans
= CALLOC_STRUCT(si_transfer
);
2057 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
2058 trans
->b
.b
.level
= level
;
2059 trans
->b
.b
.usage
= usage
;
2060 trans
->b
.b
.box
= *box
;
2062 if (use_staging_texture
) {
2063 struct pipe_resource resource
;
2064 struct si_texture
*staging
;
2066 si_init_temp_resource_from_box(&resource
, texture
, box
, level
,
2067 SI_RESOURCE_FLAG_TRANSFER
);
2068 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
2069 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
2071 /* Since depth-stencil textures don't support linear tiling,
2072 * blit from ZS to color and vice versa. u_blitter will do
2073 * the packing for these formats.
2076 resource
.format
= util_blitter_get_color_format_for_zs(resource
.format
);
2078 /* Create the temporary texture. */
2079 staging
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
2081 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
2084 trans
->staging
= &staging
->buffer
;
2086 /* Just get the strides. */
2087 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
,
2089 &trans
->b
.b
.layer_stride
);
2091 if (usage
& PIPE_TRANSFER_READ
)
2092 si_copy_to_staging_texture(ctx
, trans
);
2094 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
2096 buf
= trans
->staging
;
2098 /* the resource is mapped directly */
2099 offset
= si_texture_get_offset(sctx
->screen
, tex
, level
, box
,
2101 &trans
->b
.b
.layer_stride
);
2105 /* Always unmap texture CPU mappings on 32-bit architectures, so that
2106 * we don't run out of the CPU address space.
2108 if (sizeof(void*) == 4)
2109 usage
|= RADEON_TRANSFER_TEMPORARY
;
2111 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
2114 *ptransfer
= &trans
->b
.b
;
2115 return map
+ offset
;
2118 si_resource_reference(&trans
->staging
, NULL
);
2119 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
2124 static void si_texture_transfer_unmap(struct pipe_context
*ctx
,
2125 struct pipe_transfer
* transfer
)
2127 struct si_context
*sctx
= (struct si_context
*)ctx
;
2128 struct si_transfer
*stransfer
= (struct si_transfer
*)transfer
;
2129 struct pipe_resource
*texture
= transfer
->resource
;
2130 struct si_texture
*tex
= (struct si_texture
*)texture
;
2132 /* Always unmap texture CPU mappings on 32-bit architectures, so that
2133 * we don't run out of the CPU address space.
2135 if (sizeof(void*) == 4) {
2136 struct si_resource
*buf
=
2137 stransfer
->staging
? stransfer
->staging
: &tex
->buffer
;
2139 sctx
->ws
->buffer_unmap(buf
->buf
);
2142 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && stransfer
->staging
)
2143 si_copy_from_staging_texture(ctx
, stransfer
);
2145 if (stransfer
->staging
) {
2146 sctx
->num_alloc_tex_transfer_bytes
+= stransfer
->staging
->buf
->size
;
2147 si_resource_reference(&stransfer
->staging
, NULL
);
2150 /* Heuristic for {upload, draw, upload, draw, ..}:
2152 * Flush the gfx IB if we've allocated too much texture storage.
2154 * The idea is that we don't want to build IBs that use too much
2155 * memory and put pressure on the kernel memory manager and we also
2156 * want to make temporary and invalidated buffers go idle ASAP to
2157 * decrease the total memory usage or make them reusable. The memory
2158 * usage will be slightly higher than given here because of the buffer
2159 * cache in the winsys.
2161 * The result is that the kernel memory manager is never a bottleneck.
2163 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
2164 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
2165 sctx
->num_alloc_tex_transfer_bytes
= 0;
2168 pipe_resource_reference(&transfer
->resource
, NULL
);
2172 static const struct u_resource_vtbl si_texture_vtbl
=
2174 NULL
, /* get_handle */
2175 si_texture_destroy
, /* resource_destroy */
2176 si_texture_transfer_map
, /* transfer_map */
2177 u_default_transfer_flush_region
, /* transfer_flush_region */
2178 si_texture_transfer_unmap
, /* transfer_unmap */
2181 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
2183 bool vi_dcc_formats_compatible(struct si_screen
*sscreen
,
2184 enum pipe_format format1
,
2185 enum pipe_format format2
)
2187 const struct util_format_description
*desc1
, *desc2
;
2189 /* No format change - exit early. */
2190 if (format1
== format2
)
2193 format1
= si_simplify_cb_format(format1
);
2194 format2
= si_simplify_cb_format(format2
);
2196 /* Check again after format adjustments. */
2197 if (format1
== format2
)
2200 desc1
= util_format_description(format1
);
2201 desc2
= util_format_description(format2
);
2203 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2204 desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2207 /* Float and non-float are totally incompatible. */
2208 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
2209 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
2212 /* Channel sizes must match across DCC formats.
2213 * Comparing just the first 2 channels should be enough.
2215 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
2216 (desc1
->nr_channels
>= 2 &&
2217 desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
2220 /* Everything below is not needed if the driver never uses the DCC
2221 * clear code with the value of 1.
2224 /* If the clear values are all 1 or all 0, this constraint can be
2226 if (vi_alpha_is_on_msb(sscreen
, format1
) != vi_alpha_is_on_msb(sscreen
, format2
))
2229 /* Channel types must match if the clear value of 1 is used.
2230 * The type categories are only float, signed, unsigned.
2231 * NORM and INT are always compatible.
2233 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
2234 (desc1
->nr_channels
>= 2 &&
2235 desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
2241 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
2243 enum pipe_format view_format
)
2245 struct si_texture
*stex
= (struct si_texture
*)tex
;
2247 return vi_dcc_enabled(stex
, level
) &&
2248 !vi_dcc_formats_compatible((struct si_screen
*)tex
->screen
,
2249 tex
->format
, view_format
);
2252 /* This can't be merged with the above function, because
2253 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
2254 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
2255 struct pipe_resource
*tex
,
2257 enum pipe_format view_format
)
2259 struct si_texture
*stex
= (struct si_texture
*)tex
;
2261 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
2262 if (!si_texture_disable_dcc(sctx
, stex
))
2263 si_decompress_dcc(sctx
, stex
);
2266 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
2267 struct pipe_resource
*texture
,
2268 const struct pipe_surface
*templ
,
2269 unsigned width0
, unsigned height0
,
2270 unsigned width
, unsigned height
)
2272 struct si_surface
*surface
= CALLOC_STRUCT(si_surface
);
2277 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2278 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2280 pipe_reference_init(&surface
->base
.reference
, 1);
2281 pipe_resource_reference(&surface
->base
.texture
, texture
);
2282 surface
->base
.context
= pipe
;
2283 surface
->base
.format
= templ
->format
;
2284 surface
->base
.width
= width
;
2285 surface
->base
.height
= height
;
2286 surface
->base
.u
= templ
->u
;
2288 surface
->width0
= width0
;
2289 surface
->height0
= height0
;
2291 surface
->dcc_incompatible
=
2292 texture
->target
!= PIPE_BUFFER
&&
2293 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
2295 return &surface
->base
;
2298 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
,
2299 struct pipe_resource
*tex
,
2300 const struct pipe_surface
*templ
)
2302 unsigned level
= templ
->u
.tex
.level
;
2303 unsigned width
= u_minify(tex
->width0
, level
);
2304 unsigned height
= u_minify(tex
->height0
, level
);
2305 unsigned width0
= tex
->width0
;
2306 unsigned height0
= tex
->height0
;
2308 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2309 const struct util_format_description
*tex_desc
2310 = util_format_description(tex
->format
);
2311 const struct util_format_description
*templ_desc
2312 = util_format_description(templ
->format
);
2314 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2316 /* Adjust size of surface if and only if the block width or
2317 * height is changed. */
2318 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2319 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2320 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2321 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2323 width
= nblks_x
* templ_desc
->block
.width
;
2324 height
= nblks_y
* templ_desc
->block
.height
;
2326 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2327 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2331 return si_create_surface_custom(pipe
, tex
, templ
,
2336 static void si_surface_destroy(struct pipe_context
*pipe
,
2337 struct pipe_surface
*surface
)
2339 pipe_resource_reference(&surface
->texture
, NULL
);
2343 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2345 const struct util_format_description
*desc
= util_format_description(format
);
2347 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2349 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2350 return V_028C70_SWAP_STD
;
2352 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2355 switch (desc
->nr_channels
) {
2357 if (HAS_SWIZZLE(0,X
))
2358 return V_028C70_SWAP_STD
; /* X___ */
2359 else if (HAS_SWIZZLE(3,X
))
2360 return V_028C70_SWAP_ALT_REV
; /* ___X */
2363 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2364 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2365 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2366 return V_028C70_SWAP_STD
; /* XY__ */
2367 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2368 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2369 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2371 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2372 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2373 return V_028C70_SWAP_ALT
; /* X__Y */
2374 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2375 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2378 if (HAS_SWIZZLE(0,X
))
2379 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2380 else if (HAS_SWIZZLE(0,Z
))
2381 return V_028C70_SWAP_STD_REV
; /* ZYX */
2384 /* check the middle channels, the 1st and 4th channel can be NONE */
2385 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2386 return V_028C70_SWAP_STD
; /* XYZW */
2387 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2388 return V_028C70_SWAP_STD_REV
; /* WZYX */
2389 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2390 return V_028C70_SWAP_ALT
; /* ZYXW */
2391 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2394 return V_028C70_SWAP_ALT_REV
;
2396 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2403 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2405 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
,
2410 if (sctx
->dcc_stats
[slot
].query_active
)
2411 vi_separate_dcc_stop_query(sctx
,
2412 sctx
->dcc_stats
[slot
].tex
);
2414 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2415 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2416 sctx
->b
.destroy_query(&sctx
->b
,
2417 sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2418 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2421 si_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2425 * Return the per-context slot where DCC statistics queries for the texture live.
2427 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
,
2428 struct si_texture
*tex
)
2430 int i
, empty_slot
= -1;
2432 /* Remove zombie textures (textures kept alive by this array only). */
2433 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2434 if (sctx
->dcc_stats
[i
].tex
&&
2435 sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2436 vi_dcc_clean_up_context_slot(sctx
, i
);
2438 /* Find the texture. */
2439 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2440 /* Return if found. */
2441 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2442 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2446 /* Record the first seen empty slot. */
2447 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2451 /* Not found. Remove the oldest member to make space in the array. */
2452 if (empty_slot
== -1) {
2453 int oldest_slot
= 0;
2455 /* Find the oldest slot. */
2456 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2457 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2458 sctx
->dcc_stats
[i
].last_use_timestamp
)
2461 /* Clean up the oldest slot. */
2462 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2463 empty_slot
= oldest_slot
;
2466 /* Add the texture to the new slot. */
2467 si_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2468 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2472 static struct pipe_query
*
2473 vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2475 struct si_query_hw
*query
= (struct si_query_hw
*)
2476 sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2478 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2479 return (struct pipe_query
*)query
;
2483 * Called when binding a color buffer.
2485 void vi_separate_dcc_start_query(struct si_context
*sctx
,
2486 struct si_texture
*tex
)
2488 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2490 assert(!sctx
->dcc_stats
[i
].query_active
);
2492 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2493 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2495 /* begin or resume the query */
2496 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2497 sctx
->dcc_stats
[i
].query_active
= true;
2501 * Called when unbinding a color buffer.
2503 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
2504 struct si_texture
*tex
)
2506 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2508 assert(sctx
->dcc_stats
[i
].query_active
);
2509 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2511 /* pause or end the query */
2512 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2513 sctx
->dcc_stats
[i
].query_active
= false;
2516 static bool vi_should_enable_separate_dcc(struct si_texture
*tex
)
2518 /* The minimum number of fullscreen draws per frame that is required
2520 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2523 /* Called by fast clear. */
2524 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
2525 struct si_texture
*tex
)
2527 /* The intent is to use this with shared displayable back buffers,
2528 * but it's not strictly limited only to them.
2530 if (!tex
->buffer
.b
.is_shared
||
2531 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2532 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2533 tex
->buffer
.b
.b
.last_level
> 0 ||
2534 !tex
->surface
.dcc_size
||
2535 sctx
->screen
->debug_flags
& DBG(NO_DCC
) ||
2536 sctx
->screen
->debug_flags
& DBG(NO_DCC_FB
))
2539 assert(sctx
->chip_class
>= GFX8
);
2541 if (tex
->surface
.dcc_offset
)
2542 return; /* already enabled */
2544 /* Enable the DCC stat gathering. */
2545 if (!tex
->dcc_gather_statistics
) {
2546 tex
->dcc_gather_statistics
= true;
2547 vi_separate_dcc_start_query(sctx
, tex
);
2550 if (!vi_should_enable_separate_dcc(tex
))
2551 return; /* stats show that DCC decompression is too expensive */
2553 assert(tex
->surface
.num_dcc_levels
);
2554 assert(!tex
->dcc_separate_buffer
);
2556 si_texture_discard_cmask(sctx
->screen
, tex
);
2558 /* Get a DCC buffer. */
2559 if (tex
->last_dcc_separate_buffer
) {
2560 assert(tex
->dcc_gather_statistics
);
2561 assert(!tex
->dcc_separate_buffer
);
2562 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2563 tex
->last_dcc_separate_buffer
= NULL
;
2565 tex
->dcc_separate_buffer
=
2566 si_aligned_buffer_create(sctx
->b
.screen
,
2567 SI_RESOURCE_FLAG_UNMAPPABLE
,
2569 tex
->surface
.dcc_size
,
2570 tex
->surface
.dcc_alignment
);
2571 if (!tex
->dcc_separate_buffer
)
2575 /* dcc_offset is the absolute GPUVM address. */
2576 tex
->surface
.dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2578 /* no need to flag anything since this is called by fast clear that
2579 * flags framebuffer state
2584 * Called by pipe_context::flush_resource, the place where DCC decompression
2587 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2588 struct si_texture
*tex
)
2590 struct si_context
*sctx
= (struct si_context
*)ctx
;
2591 struct pipe_query
*tmp
;
2592 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2593 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2594 bool disable
= false;
2596 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2597 union pipe_query_result result
;
2599 /* Read the results. */
2600 struct pipe_query
*query
= sctx
->dcc_stats
[i
].ps_stats
[2];
2601 ctx
->get_query_result(ctx
, query
,
2603 si_query_buffer_reset(sctx
, &((struct si_query_hw
*)query
)->buffer
);
2605 /* Compute the approximate number of fullscreen draws. */
2606 tex
->ps_draw_ratio
=
2607 result
.pipeline_statistics
.ps_invocations
/
2608 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2609 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2611 disable
= tex
->dcc_separate_buffer
&&
2612 !vi_should_enable_separate_dcc(tex
);
2615 tex
->num_slow_clears
= 0;
2617 /* stop the statistics query for ps_stats[0] */
2619 vi_separate_dcc_stop_query(sctx
, tex
);
2621 /* Move the queries in the queue by one. */
2622 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2623 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2624 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2625 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2627 /* create and start a new query as ps_stats[0] */
2629 vi_separate_dcc_start_query(sctx
, tex
);
2632 assert(!tex
->last_dcc_separate_buffer
);
2633 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2634 tex
->dcc_separate_buffer
= NULL
;
2635 tex
->surface
.dcc_offset
= 0;
2636 /* no need to flag anything since this is called after
2637 * decompression that re-sets framebuffer state
2642 static struct pipe_memory_object
*
2643 si_memobj_from_handle(struct pipe_screen
*screen
,
2644 struct winsys_handle
*whandle
,
2647 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2648 struct si_memory_object
*memobj
= CALLOC_STRUCT(si_memory_object
);
2649 struct pb_buffer
*buf
= NULL
;
2654 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2655 sscreen
->info
.max_alignment
);
2661 memobj
->b
.dedicated
= dedicated
;
2663 memobj
->stride
= whandle
->stride
;
2665 return (struct pipe_memory_object
*)memobj
;
2670 si_memobj_destroy(struct pipe_screen
*screen
,
2671 struct pipe_memory_object
*_memobj
)
2673 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2675 pb_reference(&memobj
->buf
, NULL
);
2679 static struct pipe_resource
*
2680 si_texture_from_memobj(struct pipe_screen
*screen
,
2681 const struct pipe_resource
*templ
,
2682 struct pipe_memory_object
*_memobj
,
2685 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2686 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2687 struct pipe_resource
*tex
=
2688 si_texture_from_winsys_buffer(sscreen
, templ
, memobj
->buf
,
2689 memobj
->stride
, offset
,
2690 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
|
2691 PIPE_HANDLE_USAGE_SHADER_WRITE
,
2692 memobj
->b
.dedicated
);
2696 /* si_texture_from_winsys_buffer doesn't increment refcount of
2697 * memobj->buf, so increment it here.
2699 struct pb_buffer
*buf
= NULL
;
2700 pb_reference(&buf
, memobj
->buf
);
2704 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2705 struct pipe_resource
*resource
,
2708 struct si_texture
*tex
= (struct si_texture
*)resource
;
2710 /* Buffers only support the linear flag. */
2711 if (resource
->target
== PIPE_BUFFER
)
2712 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2714 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2717 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2720 /* TODO: PIPE_BIND_CURSOR - do we care? */
2724 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2726 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2727 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2728 sscreen
->b
.resource_get_param
= si_resource_get_param
;
2729 sscreen
->b
.resource_get_info
= si_texture_get_info
;
2730 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2731 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2732 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2733 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2736 void si_init_context_texture_functions(struct si_context
*sctx
)
2738 sctx
->b
.create_surface
= si_create_surface
;
2739 sctx
->b
.surface_destroy
= si_surface_destroy
;