2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_resource.h"
33 #include "util/u_surface.h"
34 #include "util/u_transfer.h"
35 #include "util/os_time.h"
38 #include "state_tracker/drm_driver.h"
40 #include "amd/addrlib/inc/addrinterface.h"
42 static enum radeon_surf_mode
43 si_choose_tiling(struct si_screen
*sscreen
,
44 const struct pipe_resource
*templ
, bool tc_compatible_htile
);
47 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
48 struct si_texture
*dst
,
49 unsigned dst_level
, unsigned dstx
,
50 unsigned dsty
, unsigned dstz
,
51 struct si_texture
*src
,
53 const struct pipe_box
*src_box
)
58 if (dst
->surface
.bpe
!= src
->surface
.bpe
)
61 /* MSAA: Blits don't exist in the real world. */
62 if (src
->buffer
.b
.b
.nr_samples
> 1 ||
63 dst
->buffer
.b
.b
.nr_samples
> 1)
66 /* Depth-stencil surfaces:
67 * When dst is linear, the DB->CB copy preserves HTILE.
68 * When dst is tiled, the 3D path must be used to update HTILE.
70 if (src
->is_depth
|| dst
->is_depth
)
74 * src: Use the 3D path. DCC decompression is expensive.
75 * dst: Use the 3D path to compress the pixels with DCC.
77 if (vi_dcc_enabled(src
, src_level
) ||
78 vi_dcc_enabled(dst
, dst_level
))
82 * src: Both texture and SDMA paths need decompression. Use SDMA.
83 * dst: If overwriting the whole texture, discard CMASK and use
84 * SDMA. Otherwise, use the 3D path.
86 if (dst
->cmask_buffer
&& dst
->dirty_level_mask
& (1 << dst_level
)) {
87 /* The CMASK clear is only enabled for the first level. */
88 assert(dst_level
== 0);
89 if (!util_texrange_covers_whole_level(&dst
->buffer
.b
.b
, dst_level
,
90 dstx
, dsty
, dstz
, src_box
->width
,
91 src_box
->height
, src_box
->depth
))
94 si_texture_discard_cmask(sctx
->screen
, dst
);
97 /* All requirements are met. Prepare textures for SDMA. */
98 if (src
->cmask_buffer
&& src
->dirty_level_mask
& (1 << src_level
))
99 sctx
->b
.flush_resource(&sctx
->b
, &src
->buffer
.b
.b
);
101 assert(!(src
->dirty_level_mask
& (1 << src_level
)));
102 assert(!(dst
->dirty_level_mask
& (1 << dst_level
)));
107 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
108 static void si_copy_region_with_blit(struct pipe_context
*pipe
,
109 struct pipe_resource
*dst
,
111 unsigned dstx
, unsigned dsty
, unsigned dstz
,
112 struct pipe_resource
*src
,
114 const struct pipe_box
*src_box
)
116 struct pipe_blit_info blit
;
118 memset(&blit
, 0, sizeof(blit
));
119 blit
.src
.resource
= src
;
120 blit
.src
.format
= src
->format
;
121 blit
.src
.level
= src_level
;
122 blit
.src
.box
= *src_box
;
123 blit
.dst
.resource
= dst
;
124 blit
.dst
.format
= dst
->format
;
125 blit
.dst
.level
= dst_level
;
126 blit
.dst
.box
.x
= dstx
;
127 blit
.dst
.box
.y
= dsty
;
128 blit
.dst
.box
.z
= dstz
;
129 blit
.dst
.box
.width
= src_box
->width
;
130 blit
.dst
.box
.height
= src_box
->height
;
131 blit
.dst
.box
.depth
= src_box
->depth
;
132 blit
.mask
= util_format_get_mask(dst
->format
);
133 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
136 pipe
->blit(pipe
, &blit
);
140 /* Copy from a full GPU texture to a transfer's staging one. */
141 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
143 struct si_context
*sctx
= (struct si_context
*)ctx
;
144 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
145 struct pipe_resource
*dst
= &stransfer
->staging
->b
.b
;
146 struct pipe_resource
*src
= transfer
->resource
;
148 if (src
->nr_samples
> 1 || ((struct si_texture
*)src
)->is_depth
) {
149 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
150 src
, transfer
->level
, &transfer
->box
);
154 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
158 /* Copy from a transfer's staging texture to a full GPU one. */
159 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
161 struct si_context
*sctx
= (struct si_context
*)ctx
;
162 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
163 struct pipe_resource
*dst
= transfer
->resource
;
164 struct pipe_resource
*src
= &stransfer
->staging
->b
.b
;
165 struct pipe_box sbox
;
167 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
169 if (dst
->nr_samples
> 1 || ((struct si_texture
*)dst
)->is_depth
) {
170 si_copy_region_with_blit(ctx
, dst
, transfer
->level
,
171 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
176 if (util_format_is_compressed(dst
->format
)) {
177 sbox
.width
= util_format_get_nblocksx(dst
->format
, sbox
.width
);
178 sbox
.height
= util_format_get_nblocksx(dst
->format
, sbox
.height
);
181 sctx
->dma_copy(ctx
, dst
, transfer
->level
,
182 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
186 static unsigned si_texture_get_offset(struct si_screen
*sscreen
,
187 struct si_texture
*tex
, unsigned level
,
188 const struct pipe_box
*box
,
190 unsigned *layer_stride
)
192 if (sscreen
->info
.chip_class
>= GFX9
) {
193 *stride
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
194 *layer_stride
= tex
->surface
.u
.gfx9
.surf_slice_size
;
199 /* Each texture is an array of slices. Each slice is an array
200 * of mipmap levels. */
201 return box
->z
* tex
->surface
.u
.gfx9
.surf_slice_size
+
202 tex
->surface
.u
.gfx9
.offset
[level
] +
203 (box
->y
/ tex
->surface
.blk_h
*
204 tex
->surface
.u
.gfx9
.surf_pitch
+
205 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
207 *stride
= tex
->surface
.u
.legacy
.level
[level
].nblk_x
*
209 assert((uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
210 *layer_stride
= (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
213 return tex
->surface
.u
.legacy
.level
[level
].offset
;
215 /* Each texture is an array of mipmap levels. Each level is
216 * an array of slices. */
217 return tex
->surface
.u
.legacy
.level
[level
].offset
+
218 box
->z
* (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
219 (box
->y
/ tex
->surface
.blk_h
*
220 tex
->surface
.u
.legacy
.level
[level
].nblk_x
+
221 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
225 static int si_init_surface(struct si_screen
*sscreen
,
226 struct radeon_surf
*surface
,
227 const struct pipe_resource
*ptex
,
228 enum radeon_surf_mode array_mode
,
229 unsigned pitch_in_bytes_override
,
233 bool is_flushed_depth
,
234 bool tc_compatible_htile
)
236 const struct util_format_description
*desc
=
237 util_format_description(ptex
->format
);
238 bool is_depth
, is_stencil
;
240 unsigned i
, bpe
, flags
= 0;
242 is_depth
= util_format_has_depth(desc
);
243 is_stencil
= util_format_has_stencil(desc
);
245 if (!is_flushed_depth
&&
246 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
247 bpe
= 4; /* stencil is allocated separately */
249 bpe
= util_format_get_blocksize(ptex
->format
);
250 assert(util_is_power_of_two_or_zero(bpe
));
253 if (!is_flushed_depth
&& is_depth
) {
254 flags
|= RADEON_SURF_ZBUFFER
;
256 if (tc_compatible_htile
&&
257 (sscreen
->info
.chip_class
>= GFX9
||
258 array_mode
== RADEON_SURF_MODE_2D
)) {
259 /* TC-compatible HTILE only supports Z32_FLOAT.
260 * GFX9 also supports Z16_UNORM.
261 * On GFX8, promote Z16 to Z32. DB->CB copies will convert
262 * the format for transfers.
264 if (sscreen
->info
.chip_class
== GFX8
)
267 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
271 flags
|= RADEON_SURF_SBUFFER
;
274 if (sscreen
->info
.chip_class
>= GFX8
&&
275 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
||
276 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
277 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
278 flags
|= RADEON_SURF_DISABLE_DCC
;
280 /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */
281 if (sscreen
->info
.family
== CHIP_STONEY
&&
282 bpe
== 16 && ptex
->nr_samples
>= 2)
283 flags
|= RADEON_SURF_DISABLE_DCC
;
285 /* GFX8: DCC clear for 4x and 8x MSAA array textures unimplemented. */
286 if (sscreen
->info
.chip_class
== GFX8
&&
287 ptex
->nr_storage_samples
>= 4 &&
288 ptex
->array_size
> 1)
289 flags
|= RADEON_SURF_DISABLE_DCC
;
291 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
292 if (sscreen
->info
.chip_class
== GFX9
&&
293 ptex
->nr_storage_samples
>= 4)
294 flags
|= RADEON_SURF_DISABLE_DCC
;
296 /* TODO: GFX10: DCC causes corruption with MSAA. */
297 if (sscreen
->info
.chip_class
>= GFX10
&&
298 ptex
->nr_storage_samples
>= 2)
299 flags
|= RADEON_SURF_DISABLE_DCC
;
301 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
302 /* This should catch bugs in gallium users setting incorrect flags. */
303 assert(ptex
->nr_samples
<= 1 &&
304 ptex
->array_size
== 1 &&
306 ptex
->last_level
== 0 &&
307 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
309 flags
|= RADEON_SURF_SCANOUT
;
312 if (ptex
->bind
& PIPE_BIND_SHARED
)
313 flags
|= RADEON_SURF_SHAREABLE
;
315 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
316 if (!(ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
))
317 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
319 if (sscreen
->info
.chip_class
>= GFX10
&&
320 (ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
)) {
321 flags
|= RADEON_SURF_FORCE_SWIZZLE_MODE
;
322 surface
->u
.gfx9
.surf
.swizzle_mode
= ADDR_SW_64KB_R_X
;
325 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
,
326 array_mode
, surface
);
331 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
333 if (sscreen
->info
.chip_class
>= GFX9
) {
335 surface
->u
.gfx9
.surf_pitch
= pitch
;
336 surface
->u
.gfx9
.surf_slice_size
=
337 (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
339 surface
->u
.gfx9
.surf_offset
= offset
;
342 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
343 surface
->u
.legacy
.level
[0].slice_size_dw
=
344 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
347 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
348 surface
->u
.legacy
.level
[i
].offset
+= offset
;
354 static void si_get_display_metadata(struct si_screen
*sscreen
,
355 struct radeon_surf
*surf
,
356 struct radeon_bo_metadata
*metadata
,
357 enum radeon_surf_mode
*array_mode
,
360 if (sscreen
->info
.chip_class
>= GFX9
) {
361 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
362 *array_mode
= RADEON_SURF_MODE_2D
;
364 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
366 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
367 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
369 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
371 if (metadata
->u
.gfx9
.dcc_offset_256B
) {
372 surf
->u
.gfx9
.display_dcc_pitch_max
= metadata
->u
.gfx9
.dcc_pitch_max
;
373 assert(metadata
->u
.gfx9
.dcc_independent_64B
== 1);
376 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
377 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
378 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
379 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
380 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
381 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
383 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
384 *array_mode
= RADEON_SURF_MODE_2D
;
385 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
386 *array_mode
= RADEON_SURF_MODE_1D
;
388 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
390 *is_scanout
= metadata
->u
.legacy
.scanout
;
394 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
395 struct si_texture
*tex
)
397 struct si_screen
*sscreen
= sctx
->screen
;
398 struct pipe_context
*ctx
= &sctx
->b
;
400 if (ctx
== sscreen
->aux_context
)
401 mtx_lock(&sscreen
->aux_context_lock
);
403 unsigned n
= sctx
->num_decompress_calls
;
404 ctx
->flush_resource(ctx
, &tex
->buffer
.b
.b
);
406 /* Flush only if any fast clear elimination took place. */
407 if (n
!= sctx
->num_decompress_calls
)
408 ctx
->flush(ctx
, NULL
, 0);
410 if (ctx
== sscreen
->aux_context
)
411 mtx_unlock(&sscreen
->aux_context_lock
);
414 void si_texture_discard_cmask(struct si_screen
*sscreen
,
415 struct si_texture
*tex
)
417 if (!tex
->cmask_buffer
)
420 assert(tex
->buffer
.b
.b
.nr_samples
<= 1);
423 tex
->cmask_base_address_reg
= tex
->buffer
.gpu_address
>> 8;
424 tex
->dirty_level_mask
= 0;
426 tex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
428 if (tex
->cmask_buffer
!= &tex
->buffer
)
429 si_resource_reference(&tex
->cmask_buffer
, NULL
);
431 tex
->cmask_buffer
= NULL
;
433 /* Notify all contexts about the change. */
434 p_atomic_inc(&sscreen
->dirty_tex_counter
);
435 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
438 static bool si_can_disable_dcc(struct si_texture
*tex
)
440 /* We can't disable DCC if it can be written by another process. */
441 return tex
->dcc_offset
&&
442 (!tex
->buffer
.b
.is_shared
||
443 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
));
446 static bool si_texture_discard_dcc(struct si_screen
*sscreen
,
447 struct si_texture
*tex
)
449 if (!si_can_disable_dcc(tex
)) {
450 assert(tex
->display_dcc_offset
== 0);
454 assert(tex
->dcc_separate_buffer
== NULL
);
458 tex
->display_dcc_offset
= 0;
459 tex
->dcc_retile_map_offset
= 0;
461 /* Notify all contexts about the change. */
462 p_atomic_inc(&sscreen
->dirty_tex_counter
);
467 * Disable DCC for the texture. (first decompress, then discard metadata).
469 * There is unresolved multi-context synchronization issue between
470 * screen::aux_context and the current context. If applications do this with
471 * multiple contexts, it's already undefined behavior for them and we don't
472 * have to worry about that. The scenario is:
474 * If context 1 disables DCC and context 2 has queued commands that write
475 * to the texture via CB with DCC enabled, and the order of operations is
477 * context 2 queues draw calls rendering to the texture, but doesn't flush
478 * context 1 disables DCC and flushes
479 * context 1 & 2 reset descriptors and FB state
480 * context 2 flushes (new compressed tiles written by the draw calls)
481 * context 1 & 2 read garbage, because DCC is disabled, yet there are
484 * \param sctx the current context if you have one, or sscreen->aux_context
487 bool si_texture_disable_dcc(struct si_context
*sctx
,
488 struct si_texture
*tex
)
490 struct si_screen
*sscreen
= sctx
->screen
;
492 if (!sctx
->has_graphics
)
493 return si_texture_discard_dcc(sscreen
, tex
);
495 if (!si_can_disable_dcc(tex
))
498 if (&sctx
->b
== sscreen
->aux_context
)
499 mtx_lock(&sscreen
->aux_context_lock
);
501 /* Decompress DCC. */
502 si_decompress_dcc(sctx
, tex
);
503 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
505 if (&sctx
->b
== sscreen
->aux_context
)
506 mtx_unlock(&sscreen
->aux_context_lock
);
508 return si_texture_discard_dcc(sscreen
, tex
);
511 static void si_reallocate_texture_inplace(struct si_context
*sctx
,
512 struct si_texture
*tex
,
513 unsigned new_bind_flag
,
514 bool invalidate_storage
)
516 struct pipe_screen
*screen
= sctx
->b
.screen
;
517 struct si_texture
*new_tex
;
518 struct pipe_resource templ
= tex
->buffer
.b
.b
;
521 templ
.bind
|= new_bind_flag
;
523 if (tex
->buffer
.b
.is_shared
)
526 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
527 if (tex
->surface
.is_linear
)
530 /* This fails with MSAA, depth, and compressed textures. */
531 if (si_choose_tiling(sctx
->screen
, &templ
, false) !=
532 RADEON_SURF_MODE_LINEAR_ALIGNED
)
536 new_tex
= (struct si_texture
*)screen
->resource_create(screen
, &templ
);
540 /* Copy the pixels to the new texture. */
541 if (!invalidate_storage
) {
542 for (i
= 0; i
<= templ
.last_level
; i
++) {
546 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
547 util_num_layers(&templ
, i
), &box
);
549 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0,
550 &tex
->buffer
.b
.b
, i
, &box
);
554 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
555 si_texture_discard_cmask(sctx
->screen
, tex
);
556 si_texture_discard_dcc(sctx
->screen
, tex
);
559 /* Replace the structure fields of tex. */
560 tex
->buffer
.b
.b
.bind
= templ
.bind
;
561 pb_reference(&tex
->buffer
.buf
, new_tex
->buffer
.buf
);
562 tex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
563 tex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
564 tex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
565 tex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
566 tex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
567 tex
->buffer
.domains
= new_tex
->buffer
.domains
;
568 tex
->buffer
.flags
= new_tex
->buffer
.flags
;
570 tex
->surface
= new_tex
->surface
;
571 tex
->size
= new_tex
->size
;
572 si_texture_reference(&tex
->flushed_depth_texture
,
573 new_tex
->flushed_depth_texture
);
575 tex
->fmask_offset
= new_tex
->fmask_offset
;
576 tex
->cmask_offset
= new_tex
->cmask_offset
;
577 tex
->cmask_base_address_reg
= new_tex
->cmask_base_address_reg
;
579 if (tex
->cmask_buffer
== &tex
->buffer
)
580 tex
->cmask_buffer
= NULL
;
582 si_resource_reference(&tex
->cmask_buffer
, NULL
);
584 if (new_tex
->cmask_buffer
== &new_tex
->buffer
)
585 tex
->cmask_buffer
= &tex
->buffer
;
587 si_resource_reference(&tex
->cmask_buffer
, new_tex
->cmask_buffer
);
589 tex
->dcc_offset
= new_tex
->dcc_offset
;
590 tex
->cb_color_info
= new_tex
->cb_color_info
;
591 memcpy(tex
->color_clear_value
, new_tex
->color_clear_value
,
592 sizeof(tex
->color_clear_value
));
593 tex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
595 tex
->htile_offset
= new_tex
->htile_offset
;
596 tex
->depth_clear_value
= new_tex
->depth_clear_value
;
597 tex
->dirty_level_mask
= new_tex
->dirty_level_mask
;
598 tex
->stencil_dirty_level_mask
= new_tex
->stencil_dirty_level_mask
;
599 tex
->db_render_format
= new_tex
->db_render_format
;
600 tex
->stencil_clear_value
= new_tex
->stencil_clear_value
;
601 tex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
602 tex
->depth_cleared
= new_tex
->depth_cleared
;
603 tex
->stencil_cleared
= new_tex
->stencil_cleared
;
604 tex
->upgraded_depth
= new_tex
->upgraded_depth
;
605 tex
->db_compatible
= new_tex
->db_compatible
;
606 tex
->can_sample_z
= new_tex
->can_sample_z
;
607 tex
->can_sample_s
= new_tex
->can_sample_s
;
609 tex
->separate_dcc_dirty
= new_tex
->separate_dcc_dirty
;
610 tex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
611 si_resource_reference(&tex
->dcc_separate_buffer
,
612 new_tex
->dcc_separate_buffer
);
613 si_resource_reference(&tex
->last_dcc_separate_buffer
,
614 new_tex
->last_dcc_separate_buffer
);
616 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
617 assert(!tex
->htile_offset
);
618 assert(!tex
->cmask_buffer
);
619 assert(!tex
->surface
.fmask_size
);
620 assert(!tex
->dcc_offset
);
621 assert(!tex
->is_depth
);
624 si_texture_reference(&new_tex
, NULL
);
626 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
629 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
631 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
634 static void si_set_tex_bo_metadata(struct si_screen
*sscreen
,
635 struct si_texture
*tex
)
637 struct radeon_surf
*surface
= &tex
->surface
;
638 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
639 struct radeon_bo_metadata md
;
641 memset(&md
, 0, sizeof(md
));
643 if (sscreen
->info
.chip_class
>= GFX9
) {
644 md
.u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
646 if (tex
->dcc_offset
&& !tex
->dcc_separate_buffer
) {
647 uint64_t dcc_offset
=
648 tex
->display_dcc_offset
? tex
->display_dcc_offset
651 assert((dcc_offset
>> 8) != 0 && (dcc_offset
>> 8) < (1 << 24));
652 md
.u
.gfx9
.dcc_offset_256B
= dcc_offset
>> 8;
653 md
.u
.gfx9
.dcc_pitch_max
= tex
->surface
.u
.gfx9
.display_dcc_pitch_max
;
654 md
.u
.gfx9
.dcc_independent_64B
= 1;
657 md
.u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
658 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
659 md
.u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
660 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
661 md
.u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
662 md
.u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
663 md
.u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
664 md
.u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
665 md
.u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
666 md
.u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
667 md
.u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
668 md
.u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
671 assert(tex
->dcc_separate_buffer
== NULL
);
672 assert(tex
->surface
.fmask_size
== 0);
674 /* Metadata image format format version 1:
675 * [0] = 1 (metadata format identifier)
676 * [1] = (VENDOR_ID << 16) | PCI_ID
677 * [2:9] = image descriptor for the whole resource
678 * [2] is always 0, because the base address is cleared
679 * [9] is the DCC offset bits [39:8] from the beginning of
681 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
684 md
.metadata
[0] = 1; /* metadata image format version 1 */
686 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
687 md
.metadata
[1] = si_get_bo_metadata_word1(sscreen
);
689 static const unsigned char swizzle
[] = {
695 bool is_array
= util_texture_is_array(res
->target
);
698 sscreen
->make_texture_descriptor(sscreen
, tex
, true,
699 res
->target
, res
->format
,
700 swizzle
, 0, res
->last_level
, 0,
701 is_array
? res
->array_size
- 1 : 0,
702 res
->width0
, res
->height0
, res
->depth0
,
705 si_set_mutable_tex_desc_fields(sscreen
, tex
, &tex
->surface
.u
.legacy
.level
[0],
706 0, 0, tex
->surface
.blk_w
, false, desc
);
708 /* Clear the base address and set the relative DCC offset. */
710 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
711 desc
[7] = tex
->dcc_offset
>> 8;
713 /* Dwords [2:9] contain the image descriptor. */
714 memcpy(&md
.metadata
[2], desc
, sizeof(desc
));
715 md
.size_metadata
= 10 * 4;
717 /* Dwords [10:..] contain the mipmap level offsets. */
718 if (sscreen
->info
.chip_class
<= GFX8
) {
719 for (unsigned i
= 0; i
<= res
->last_level
; i
++)
720 md
.metadata
[10+i
] = tex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
722 md
.size_metadata
+= (1 + res
->last_level
) * 4;
725 sscreen
->ws
->buffer_set_metadata(tex
->buffer
.buf
, &md
);
728 static void si_read_tex_bo_metadata(struct si_screen
*sscreen
,
729 struct si_texture
*tex
,
730 struct radeon_bo_metadata
*md
)
732 uint32_t *desc
= &md
->metadata
[2];
734 if (md
->size_metadata
< 10 * 4 || /* at least 2(header) + 8(desc) dwords */
735 md
->metadata
[0] == 0 || /* invalid version number */
736 md
->metadata
[1] != si_get_bo_metadata_word1(sscreen
)) /* invalid PCI ID */
739 if (sscreen
->info
.chip_class
>= GFX8
&&
740 G_008F28_COMPRESSION_EN(desc
[6])) {
741 /* Read DCC information.
743 * Some state trackers don't set the SCANOUT flag when
744 * importing displayable images, which affects PIPE_ALIGNED
745 * and RB_ALIGNED, so we need to recover them here.
747 switch (sscreen
->info
.chip_class
) {
749 tex
->dcc_offset
= (uint64_t)desc
[7] << 8;
754 ((uint64_t)desc
[7] << 8) |
755 ((uint64_t)G_008F24_META_DATA_ADDRESS(desc
[5]) << 40);
756 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
=
757 G_008F24_META_PIPE_ALIGNED(desc
[5]);
758 tex
->surface
.u
.gfx9
.dcc
.rb_aligned
=
759 G_008F24_META_RB_ALIGNED(desc
[5]);
761 /* If DCC is unaligned, this can only be a displayable image. */
762 if (!tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&&
763 !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
764 tex
->surface
.is_displayable
= true;
769 ((uint64_t)G_00A018_META_DATA_ADDRESS_LO(desc
[6]) << 8) |
770 ((uint64_t)desc
[7] << 16);
771 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
=
772 G_00A018_META_PIPE_ALIGNED(desc
[6]);
780 /* Disable DCC. dcc_offset is always set by texture_from_handle
781 * and must be cleared here.
787 static bool si_has_displayable_dcc(struct si_texture
*tex
)
789 struct si_screen
*sscreen
= (struct si_screen
*)tex
->buffer
.b
.b
.screen
;
791 if (sscreen
->info
.chip_class
<= GFX8
)
794 /* This needs a cache flush before scanout.
795 * (it can't be scanned out and rendered to simultaneously)
797 if (sscreen
->info
.use_display_dcc_unaligned
&&
799 !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&&
800 !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
803 /* This needs an explicit flush (flush_resource). */
804 if (sscreen
->info
.use_display_dcc_with_retile_blit
&&
805 tex
->display_dcc_offset
)
811 static void si_texture_get_info(struct pipe_screen
* screen
,
812 struct pipe_resource
*resource
,
816 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
817 struct si_texture
*tex
= (struct si_texture
*)resource
;
821 if (!sscreen
|| !tex
)
824 if (resource
->target
!= PIPE_BUFFER
) {
825 if (sscreen
->info
.chip_class
>= GFX9
) {
826 offset
= tex
->surface
.u
.gfx9
.surf_offset
;
827 stride
= tex
->surface
.u
.gfx9
.surf_pitch
*
830 offset
= tex
->surface
.u
.legacy
.level
[0].offset
;
831 stride
= tex
->surface
.u
.legacy
.level
[0].nblk_x
*
843 static bool si_texture_get_handle(struct pipe_screen
* screen
,
844 struct pipe_context
*ctx
,
845 struct pipe_resource
*resource
,
846 struct winsys_handle
*whandle
,
849 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
850 struct si_context
*sctx
;
851 struct si_resource
*res
= si_resource(resource
);
852 struct si_texture
*tex
= (struct si_texture
*)resource
;
853 bool update_metadata
= false;
854 unsigned stride
, offset
, slice_size
;
857 ctx
= threaded_context_unwrap_sync(ctx
);
858 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
860 if (resource
->target
!= PIPE_BUFFER
) {
861 /* This is not supported now, but it might be required for OpenCL
862 * interop in the future.
864 if (resource
->nr_samples
> 1 || tex
->is_depth
)
867 /* Move a suballocated texture into a non-suballocated allocation. */
868 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
869 tex
->surface
.tile_swizzle
||
870 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
871 sscreen
->info
.has_local_buffers
&&
872 whandle
->type
!= WINSYS_HANDLE_TYPE_KMS
)) {
873 assert(!res
->b
.is_shared
);
874 si_reallocate_texture_inplace(sctx
, tex
,
875 PIPE_BIND_SHARED
, false);
877 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
878 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
879 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
880 assert(tex
->surface
.tile_swizzle
== 0);
883 /* Since shader image stores don't support DCC on GFX8,
884 * disable it for external clients that want write
887 if ((usage
& PIPE_HANDLE_USAGE_SHADER_WRITE
&& tex
->dcc_offset
) ||
888 /* Displayable DCC requires an explicit flush. */
889 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
890 si_has_displayable_dcc(tex
))) {
891 if (si_texture_disable_dcc(sctx
, tex
)) {
892 update_metadata
= true;
893 /* si_texture_disable_dcc flushes the context */
898 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
899 (tex
->cmask_buffer
|| tex
->dcc_offset
)) {
900 /* Eliminate fast clear (both CMASK and DCC) */
901 si_eliminate_fast_color_clear(sctx
, tex
);
902 /* eliminate_fast_color_clear flushes the context */
905 /* Disable CMASK if flush_resource isn't going
908 if (tex
->cmask_buffer
)
909 si_texture_discard_cmask(sscreen
, tex
);
913 if (!res
->b
.is_shared
|| update_metadata
)
914 si_set_tex_bo_metadata(sscreen
, tex
);
916 if (sscreen
->info
.chip_class
>= GFX9
) {
917 slice_size
= tex
->surface
.u
.gfx9
.surf_slice_size
;
919 slice_size
= (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
922 /* Buffer exports are for the OpenCL interop. */
923 /* Move a suballocated buffer into a non-suballocated allocation. */
924 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
925 /* A DMABUF export always fails if the BO is local. */
926 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
927 sscreen
->info
.has_local_buffers
)) {
928 assert(!res
->b
.is_shared
);
930 /* Allocate a new buffer with PIPE_BIND_SHARED. */
931 struct pipe_resource templ
= res
->b
.b
;
932 templ
.bind
|= PIPE_BIND_SHARED
;
934 struct pipe_resource
*newb
=
935 screen
->resource_create(screen
, &templ
);
939 /* Copy the old buffer contents to the new one. */
941 u_box_1d(0, newb
->width0
, &box
);
942 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0,
945 /* Move the new buffer storage to the old pipe_resource. */
946 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
947 pipe_resource_reference(&newb
, NULL
);
949 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
950 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
957 si_texture_get_info(screen
, resource
, &stride
, &offset
);
960 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
962 if (res
->b
.is_shared
) {
963 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
966 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
967 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
968 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
970 res
->b
.is_shared
= true;
971 res
->external_usage
= usage
;
974 return sscreen
->ws
->buffer_get_handle(sscreen
->ws
, res
->buf
, stride
,
975 offset
, slice_size
, whandle
);
978 static void si_texture_destroy(struct pipe_screen
*screen
,
979 struct pipe_resource
*ptex
)
981 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
982 struct si_texture
*tex
= (struct si_texture
*)ptex
;
983 struct si_resource
*resource
= &tex
->buffer
;
985 if (sscreen
->info
.chip_class
>= GFX9
)
986 free(tex
->surface
.u
.gfx9
.dcc_retile_map
);
988 si_texture_reference(&tex
->flushed_depth_texture
, NULL
);
990 if (tex
->cmask_buffer
!= &tex
->buffer
) {
991 si_resource_reference(&tex
->cmask_buffer
, NULL
);
993 pb_reference(&resource
->buf
, NULL
);
994 si_resource_reference(&tex
->dcc_separate_buffer
, NULL
);
995 si_resource_reference(&tex
->last_dcc_separate_buffer
, NULL
);
999 static const struct u_resource_vtbl si_texture_vtbl
;
1001 static void si_texture_get_htile_size(struct si_screen
*sscreen
,
1002 struct si_texture
*tex
)
1004 unsigned cl_width
, cl_height
, width
, height
;
1005 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
1006 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
1008 assert(sscreen
->info
.chip_class
<= GFX8
);
1010 tex
->surface
.htile_size
= 0;
1012 if (tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
1013 !sscreen
->info
.htile_cmask_support_1d_tiling
)
1016 /* Overalign HTILE on P2 configs to work around GPU hangs in
1017 * piglit/depthstencil-render-miplevels 585.
1019 * This has been confirmed to help Kabini & Stoney, where the hangs
1020 * are always reproducible. I think I have seen the test hang
1021 * on Carrizo too, though it was very rare there.
1023 if (sscreen
->info
.chip_class
>= GFX7
&& num_pipes
< 4)
1026 switch (num_pipes
) {
1052 width
= align(tex
->surface
.u
.legacy
.level
[0].nblk_x
, cl_width
* 8);
1053 height
= align(tex
->surface
.u
.legacy
.level
[0].nblk_y
, cl_height
* 8);
1055 slice_elements
= (width
* height
) / (8 * 8);
1056 slice_bytes
= slice_elements
* 4;
1058 pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
1059 base_align
= num_pipes
* pipe_interleave_bytes
;
1061 tex
->surface
.htile_alignment
= base_align
;
1062 tex
->surface
.htile_size
=
1063 util_num_layers(&tex
->buffer
.b
.b
, 0) *
1064 align(slice_bytes
, base_align
);
1067 static void si_texture_allocate_htile(struct si_screen
*sscreen
,
1068 struct si_texture
*tex
)
1070 if (sscreen
->info
.chip_class
<= GFX8
&& !tex
->tc_compatible_htile
)
1071 si_texture_get_htile_size(sscreen
, tex
);
1073 if (!tex
->surface
.htile_size
)
1076 tex
->htile_offset
= align(tex
->size
, tex
->surface
.htile_alignment
);
1077 tex
->size
= tex
->htile_offset
+ tex
->surface
.htile_size
;
1080 void si_print_texture_info(struct si_screen
*sscreen
,
1081 struct si_texture
*tex
, struct u_log_context
*log
)
1085 /* Common parameters. */
1086 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1087 "blk_h=%u, array_size=%u, last_level=%u, "
1088 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1089 tex
->buffer
.b
.b
.width0
, tex
->buffer
.b
.b
.height0
,
1090 tex
->buffer
.b
.b
.depth0
, tex
->surface
.blk_w
,
1092 tex
->buffer
.b
.b
.array_size
, tex
->buffer
.b
.b
.last_level
,
1093 tex
->surface
.bpe
, tex
->buffer
.b
.b
.nr_samples
,
1094 tex
->surface
.flags
, util_format_short_name(tex
->buffer
.b
.b
.format
));
1096 if (sscreen
->info
.chip_class
>= GFX9
) {
1097 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1098 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1099 tex
->surface
.surf_size
,
1100 tex
->surface
.u
.gfx9
.surf_slice_size
,
1101 tex
->surface
.surf_alignment
,
1102 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1103 tex
->surface
.u
.gfx9
.surf
.epitch
,
1104 tex
->surface
.u
.gfx9
.surf_pitch
);
1106 if (tex
->fmask_offset
) {
1107 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1108 "alignment=%u, swmode=%u, epitch=%u\n",
1110 tex
->surface
.fmask_size
,
1111 tex
->surface
.fmask_alignment
,
1112 tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1113 tex
->surface
.u
.gfx9
.fmask
.epitch
);
1116 if (tex
->cmask_buffer
) {
1117 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, "
1118 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1120 tex
->surface
.cmask_size
,
1121 tex
->surface
.cmask_alignment
,
1122 tex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1123 tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1126 if (tex
->htile_offset
) {
1127 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1128 "rb_aligned=%u, pipe_aligned=%u\n",
1130 tex
->surface
.htile_size
,
1131 tex
->surface
.htile_alignment
,
1132 tex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1133 tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1136 if (tex
->dcc_offset
) {
1137 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1138 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1139 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1140 tex
->surface
.dcc_alignment
,
1141 tex
->surface
.u
.gfx9
.display_dcc_pitch_max
,
1142 tex
->surface
.num_dcc_levels
);
1145 if (tex
->surface
.u
.gfx9
.stencil_offset
) {
1146 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1147 tex
->surface
.u
.gfx9
.stencil_offset
,
1148 tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1149 tex
->surface
.u
.gfx9
.stencil
.epitch
);
1154 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1155 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1156 tex
->surface
.surf_size
, tex
->surface
.surf_alignment
, tex
->surface
.u
.legacy
.bankw
,
1157 tex
->surface
.u
.legacy
.bankh
, tex
->surface
.u
.legacy
.num_banks
, tex
->surface
.u
.legacy
.mtilea
,
1158 tex
->surface
.u
.legacy
.tile_split
, tex
->surface
.u
.legacy
.pipe_config
,
1159 (tex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1161 if (tex
->fmask_offset
)
1162 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1163 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1164 tex
->fmask_offset
, tex
->surface
.fmask_size
, tex
->surface
.fmask_alignment
,
1165 tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
,
1166 tex
->surface
.u
.legacy
.fmask
.bankh
,
1167 tex
->surface
.u
.legacy
.fmask
.slice_tile_max
,
1168 tex
->surface
.u
.legacy
.fmask
.tiling_index
);
1170 if (tex
->cmask_buffer
)
1171 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, alignment=%u, "
1172 "slice_tile_max=%u\n",
1173 tex
->cmask_offset
, tex
->surface
.cmask_size
, tex
->surface
.cmask_alignment
,
1174 tex
->surface
.u
.legacy
.cmask_slice_tile_max
);
1176 if (tex
->htile_offset
)
1177 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1178 "alignment=%u, TC_compatible = %u\n",
1179 tex
->htile_offset
, tex
->surface
.htile_size
,
1180 tex
->surface
.htile_alignment
,
1181 tex
->tc_compatible_htile
);
1183 if (tex
->dcc_offset
) {
1184 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1185 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1186 tex
->surface
.dcc_alignment
);
1187 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1188 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1189 "fast_clear_size=%u\n",
1190 i
, i
< tex
->surface
.num_dcc_levels
,
1191 tex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1192 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1195 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1196 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1197 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1198 "mode=%u, tiling_index = %u\n",
1199 i
, tex
->surface
.u
.legacy
.level
[i
].offset
,
1200 (uint64_t)tex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1201 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1202 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1203 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1204 tex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1205 tex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1206 tex
->surface
.u
.legacy
.level
[i
].mode
,
1207 tex
->surface
.u
.legacy
.tiling_index
[i
]);
1209 if (tex
->surface
.has_stencil
) {
1210 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1211 tex
->surface
.u
.legacy
.stencil_tile_split
);
1212 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++) {
1213 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1214 "slice_size=%"PRIu64
", npix_x=%u, "
1215 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1216 "mode=%u, tiling_index = %u\n",
1217 i
, tex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1218 (uint64_t)tex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1219 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1220 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1221 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1222 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1223 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1224 tex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1225 tex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1230 /* Common processing for si_texture_create and si_texture_from_handle */
1231 static struct si_texture
*
1232 si_texture_create_object(struct pipe_screen
*screen
,
1233 const struct pipe_resource
*base
,
1234 struct pb_buffer
*buf
,
1235 struct radeon_surf
*surface
)
1237 struct si_texture
*tex
;
1238 struct si_resource
*resource
;
1239 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1241 tex
= CALLOC_STRUCT(si_texture
);
1245 resource
= &tex
->buffer
;
1246 resource
->b
.b
= *base
;
1247 resource
->b
.b
.next
= NULL
;
1248 resource
->b
.vtbl
= &si_texture_vtbl
;
1249 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1250 resource
->b
.b
.screen
= screen
;
1252 /* don't include stencil-only formats which we don't support for rendering */
1253 tex
->is_depth
= util_format_has_depth(util_format_description(tex
->buffer
.b
.b
.format
));
1255 tex
->surface
= *surface
;
1256 tex
->size
= tex
->surface
.surf_size
;
1258 tex
->tc_compatible_htile
= tex
->surface
.htile_size
!= 0 &&
1259 (tex
->surface
.flags
&
1260 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1262 /* TC-compatible HTILE:
1263 * - GFX8 only supports Z32_FLOAT.
1264 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1265 if (tex
->tc_compatible_htile
) {
1266 if (sscreen
->info
.chip_class
>= GFX9
&&
1267 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1268 tex
->db_render_format
= base
->format
;
1270 tex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1271 tex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1272 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1275 tex
->db_render_format
= base
->format
;
1278 /* Applies to GCN. */
1279 tex
->last_msaa_resolve_target_micro_mode
= tex
->surface
.micro_tile_mode
;
1281 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1282 * between frames, so the only thing that can enable separate DCC
1283 * with DRI2 is multiple slow clears within a frame.
1285 tex
->ps_draw_ratio
= 0;
1287 if (tex
->is_depth
) {
1288 if (sscreen
->info
.chip_class
>= GFX9
) {
1289 tex
->can_sample_z
= true;
1290 tex
->can_sample_s
= true;
1292 /* Stencil texturing with HTILE doesn't work
1293 * with mipmapping on Navi10-14. */
1294 if ((sscreen
->info
.family
== CHIP_NAVI10
||
1295 sscreen
->info
.family
== CHIP_NAVI12
||
1296 sscreen
->info
.family
== CHIP_NAVI14
) &&
1297 base
->last_level
> 0)
1298 tex
->htile_stencil_disabled
= true;
1300 tex
->can_sample_z
= !tex
->surface
.u
.legacy
.depth_adjusted
;
1301 tex
->can_sample_s
= !tex
->surface
.u
.legacy
.stencil_adjusted
;
1304 if (!(base
->flags
& (SI_RESOURCE_FLAG_TRANSFER
|
1305 SI_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1306 tex
->db_compatible
= true;
1308 if (!(sscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1309 si_texture_allocate_htile(sscreen
, tex
);
1312 if (base
->nr_samples
> 1 &&
1314 !(sscreen
->debug_flags
& DBG(NO_FMASK
))) {
1315 /* Allocate FMASK. */
1316 tex
->fmask_offset
= align64(tex
->size
,
1317 tex
->surface
.fmask_alignment
);
1318 tex
->size
= tex
->fmask_offset
+ tex
->surface
.fmask_size
;
1320 /* Allocate CMASK. */
1321 tex
->cmask_offset
= align64(tex
->size
, tex
->surface
.cmask_alignment
);
1322 tex
->size
= tex
->cmask_offset
+ tex
->surface
.cmask_size
;
1323 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
1324 tex
->cmask_buffer
= &tex
->buffer
;
1326 if (!tex
->surface
.fmask_size
|| !tex
->surface
.cmask_size
)
1330 /* Shared textures must always set up DCC here.
1331 * If it's not present, it will be disabled by
1332 * si_get_opaque_metadata later.
1334 if (tex
->surface
.dcc_size
&&
1335 (buf
|| !(sscreen
->debug_flags
& DBG(NO_DCC
))) &&
1336 (sscreen
->info
.use_display_dcc_unaligned
||
1337 sscreen
->info
.use_display_dcc_with_retile_blit
||
1338 !(tex
->surface
.flags
& RADEON_SURF_SCANOUT
))) {
1339 /* Add space for the DCC buffer. */
1340 tex
->dcc_offset
= align64(tex
->size
, tex
->surface
.dcc_alignment
);
1341 tex
->size
= tex
->dcc_offset
+ tex
->surface
.dcc_size
;
1343 if (sscreen
->info
.chip_class
>= GFX9
&&
1344 tex
->surface
.u
.gfx9
.dcc_retile_num_elements
) {
1345 /* Add space for the displayable DCC buffer. */
1346 tex
->display_dcc_offset
=
1347 align64(tex
->size
, tex
->surface
.u
.gfx9
.display_dcc_alignment
);
1348 tex
->size
= tex
->display_dcc_offset
+
1349 tex
->surface
.u
.gfx9
.display_dcc_size
;
1351 /* Add space for the DCC retile buffer. (16-bit or 32-bit elements) */
1352 tex
->dcc_retile_map_offset
=
1353 align64(tex
->size
, sscreen
->info
.tcc_cache_line_size
);
1355 if (tex
->surface
.u
.gfx9
.dcc_retile_use_uint16
) {
1356 tex
->size
= tex
->dcc_retile_map_offset
+
1357 tex
->surface
.u
.gfx9
.dcc_retile_num_elements
* 2;
1359 tex
->size
= tex
->dcc_retile_map_offset
+
1360 tex
->surface
.u
.gfx9
.dcc_retile_num_elements
* 4;
1366 /* Now create the backing buffer. */
1368 si_init_resource_fields(sscreen
, resource
, tex
->size
,
1369 tex
->surface
.surf_alignment
);
1371 if (!si_alloc_resource(sscreen
, resource
))
1374 resource
->buf
= buf
;
1375 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1376 resource
->bo_size
= buf
->size
;
1377 resource
->bo_alignment
= buf
->alignment
;
1378 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1379 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1380 resource
->vram_usage
= buf
->size
;
1381 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1382 resource
->gart_usage
= buf
->size
;
1385 if (tex
->cmask_buffer
) {
1386 /* Initialize the cmask to 0xCC (= compressed state). */
1387 si_screen_clear_buffer(sscreen
, &tex
->cmask_buffer
->b
.b
,
1388 tex
->cmask_offset
, tex
->surface
.cmask_size
,
1391 if (tex
->htile_offset
) {
1392 uint32_t clear_value
= 0;
1394 if (sscreen
->info
.chip_class
>= GFX9
|| tex
->tc_compatible_htile
)
1395 clear_value
= 0x0000030F;
1397 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1399 tex
->surface
.htile_size
,
1403 /* Initialize DCC only if the texture is not being imported. */
1404 if (!buf
&& tex
->dcc_offset
) {
1405 /* Clear DCC to black for all tiles with DCC enabled.
1407 * This fixes corruption in 3DMark Slingshot Extreme, which
1408 * uses uninitialized textures, causing corruption.
1410 if (tex
->surface
.num_dcc_levels
== tex
->buffer
.b
.b
.last_level
+ 1 &&
1411 tex
->buffer
.b
.b
.nr_samples
<= 2) {
1412 /* Simple case - all tiles have DCC enabled. */
1413 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1415 tex
->surface
.dcc_size
,
1416 DCC_CLEAR_COLOR_0000
);
1417 } else if (sscreen
->info
.chip_class
>= GFX9
) {
1418 /* Clear to uncompressed. Clearing this to black is complicated. */
1419 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1421 tex
->surface
.dcc_size
,
1424 /* GFX8: Initialize mipmap levels and multisamples separately. */
1425 if (tex
->buffer
.b
.b
.nr_samples
>= 2) {
1426 /* Clearing this to black is complicated. */
1427 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1429 tex
->surface
.dcc_size
,
1432 /* Clear the enabled mipmap levels to black. */
1435 for (unsigned i
= 0; i
< tex
->surface
.num_dcc_levels
; i
++) {
1436 if (!tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
)
1439 size
= tex
->surface
.u
.legacy
.level
[i
].dcc_offset
+
1440 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
;
1443 /* Mipmap levels with DCC. */
1445 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1446 tex
->dcc_offset
, size
,
1447 DCC_CLEAR_COLOR_0000
);
1449 /* Mipmap levels without DCC. */
1450 if (size
!= tex
->surface
.dcc_size
) {
1451 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1452 tex
->dcc_offset
+ size
,
1453 tex
->surface
.dcc_size
- size
,
1459 /* Upload the DCC retile map. */
1460 if (tex
->dcc_retile_map_offset
) {
1461 /* Use a staging buffer for the upload, because
1462 * the buffer backing the texture is unmappable.
1464 bool use_uint16
= tex
->surface
.u
.gfx9
.dcc_retile_use_uint16
;
1465 unsigned num_elements
= tex
->surface
.u
.gfx9
.dcc_retile_num_elements
;
1466 struct si_resource
*buf
=
1467 si_aligned_buffer_create(screen
, 0, PIPE_USAGE_STREAM
,
1468 num_elements
* (use_uint16
? 2 : 4),
1469 sscreen
->info
.tcc_cache_line_size
);
1470 uint32_t *ui
= (uint32_t*)sscreen
->ws
->buffer_map(buf
->buf
, NULL
,
1471 PIPE_TRANSFER_WRITE
);
1472 uint16_t *us
= (uint16_t*)ui
;
1474 /* Upload the retile map into a staging buffer. */
1476 for (unsigned i
= 0; i
< num_elements
; i
++)
1477 us
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1479 for (unsigned i
= 0; i
< num_elements
; i
++)
1480 ui
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1483 /* Copy the staging buffer to the buffer backing the texture. */
1484 struct si_context
*sctx
= (struct si_context
*)sscreen
->aux_context
;
1485 struct pipe_box box
;
1486 u_box_1d(0, buf
->b
.b
.width0
, &box
);
1488 assert(tex
->dcc_retile_map_offset
<= UINT_MAX
);
1489 mtx_lock(&sscreen
->aux_context_lock
);
1490 sctx
->dma_copy(&sctx
->b
, &tex
->buffer
.b
.b
, 0,
1491 tex
->dcc_retile_map_offset
, 0, 0,
1492 &buf
->b
.b
, 0, &box
);
1493 sscreen
->aux_context
->flush(sscreen
->aux_context
, NULL
, 0);
1494 mtx_unlock(&sscreen
->aux_context_lock
);
1496 si_resource_reference(&buf
, NULL
);
1500 /* Initialize the CMASK base register value. */
1501 tex
->cmask_base_address_reg
=
1502 (tex
->buffer
.gpu_address
+ tex
->cmask_offset
) >> 8;
1504 if (sscreen
->debug_flags
& DBG(VM
)) {
1505 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1506 tex
->buffer
.gpu_address
,
1507 tex
->buffer
.gpu_address
+ tex
->buffer
.buf
->size
,
1508 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1509 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1512 if (sscreen
->debug_flags
& DBG(TEX
)) {
1514 struct u_log_context log
;
1515 u_log_context_init(&log
);
1516 si_print_texture_info(sscreen
, tex
, &log
);
1517 u_log_new_page_print(&log
, stdout
);
1519 u_log_context_destroy(&log
);
1526 if (sscreen
->info
.chip_class
>= GFX9
)
1527 free(surface
->u
.gfx9
.dcc_retile_map
);
1531 static enum radeon_surf_mode
1532 si_choose_tiling(struct si_screen
*sscreen
,
1533 const struct pipe_resource
*templ
, bool tc_compatible_htile
)
1535 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1536 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
;
1537 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1538 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1540 /* MSAA resources must be 2D tiled. */
1541 if (templ
->nr_samples
> 1)
1542 return RADEON_SURF_MODE_2D
;
1544 /* Transfer resources should be linear. */
1545 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1546 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1548 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on GFX8,
1549 * which requires 2D tiling.
1551 if (sscreen
->info
.chip_class
== GFX8
&& tc_compatible_htile
)
1552 return RADEON_SURF_MODE_2D
;
1554 /* Handle common candidates for the linear mode.
1555 * Compressed textures and DB surfaces must always be tiled.
1557 if (!force_tiling
&&
1558 !is_depth_stencil
&&
1559 !util_format_is_compressed(templ
->format
)) {
1560 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1561 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1563 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1564 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1565 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1567 /* Cursors are linear on AMD GCN.
1568 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1569 if (templ
->bind
& PIPE_BIND_CURSOR
)
1570 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1572 if (templ
->bind
& PIPE_BIND_LINEAR
)
1573 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1575 /* Textures with a very small height are recommended to be linear. */
1576 if (templ
->target
== PIPE_TEXTURE_1D
||
1577 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1578 /* Only very thin and long 2D textures should benefit from
1579 * linear_aligned. */
1580 (templ
->width0
> 8 && templ
->height0
<= 2))
1581 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1583 /* Textures likely to be mapped often. */
1584 if (templ
->usage
== PIPE_USAGE_STAGING
||
1585 templ
->usage
== PIPE_USAGE_STREAM
)
1586 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1589 /* Make small textures 1D tiled. */
1590 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1591 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1592 return RADEON_SURF_MODE_1D
;
1594 /* The allocator will switch to 1D if needed. */
1595 return RADEON_SURF_MODE_2D
;
1598 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1599 const struct pipe_resource
*templ
)
1601 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1602 bool is_zs
= util_format_is_depth_or_stencil(templ
->format
);
1604 if (templ
->nr_samples
>= 2) {
1605 /* This is hackish (overwriting the const pipe_resource template),
1606 * but should be harmless and state trackers can also see
1607 * the overriden number of samples in the created pipe_resource.
1609 if (is_zs
&& sscreen
->eqaa_force_z_samples
) {
1610 ((struct pipe_resource
*)templ
)->nr_samples
=
1611 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1612 sscreen
->eqaa_force_z_samples
;
1613 } else if (!is_zs
&& sscreen
->eqaa_force_color_samples
) {
1614 ((struct pipe_resource
*)templ
)->nr_samples
=
1615 sscreen
->eqaa_force_coverage_samples
;
1616 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1617 sscreen
->eqaa_force_color_samples
;
1621 struct radeon_surf surface
= {0};
1622 bool is_flushed_depth
= templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1623 bool tc_compatible_htile
=
1624 sscreen
->info
.chip_class
>= GFX8
&&
1625 /* There are issues with TC-compatible HTILE on Tonga (and
1626 * Iceland is the same design), and documented bug workarounds
1627 * don't help. For example, this fails:
1628 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1630 sscreen
->info
.family
!= CHIP_TONGA
&&
1631 sscreen
->info
.family
!= CHIP_ICELAND
&&
1632 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1633 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1634 !is_flushed_depth
&&
1635 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1639 r
= si_init_surface(sscreen
, &surface
, templ
,
1640 si_choose_tiling(sscreen
, templ
, tc_compatible_htile
),
1641 0, 0, false, false, is_flushed_depth
,
1642 tc_compatible_htile
);
1647 return (struct pipe_resource
*)
1648 si_texture_create_object(screen
, templ
, NULL
, &surface
);
1651 static struct pipe_resource
*si_texture_from_winsys_buffer(struct si_screen
*sscreen
,
1652 const struct pipe_resource
*templ
,
1653 struct pb_buffer
*buf
,
1659 enum radeon_surf_mode array_mode
;
1660 struct radeon_surf surface
= {};
1661 struct radeon_bo_metadata metadata
= {};
1662 struct si_texture
*tex
;
1667 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1668 si_get_display_metadata(sscreen
, &surface
, &metadata
,
1669 &array_mode
, &is_scanout
);
1672 * The bo metadata is unset for un-dedicated images. So we fall
1673 * back to linear. See answer to question 5 of the
1674 * VK_KHX_external_memory spec for some details.
1676 * It is possible that this case isn't going to work if the
1677 * surface pitch isn't correctly aligned by default.
1679 * In order to support it correctly we require multi-image
1680 * metadata to be syncrhonized between radv and radeonsi. The
1681 * semantics of associating multiple image metadata to a memory
1682 * object on the vulkan export side are not concretely defined
1685 * All the use cases we are aware of at the moment for memory
1686 * objects use dedicated allocations. So lets keep the initial
1687 * implementation simple.
1689 * A possible alternative is to attempt to reconstruct the
1690 * tiling information when the TexParameter TEXTURE_TILING_EXT
1693 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1697 r
= si_init_surface(sscreen
, &surface
, templ
,
1698 array_mode
, stride
, offset
, true, is_scanout
,
1703 tex
= si_texture_create_object(&sscreen
->b
, templ
, buf
, &surface
);
1707 tex
->buffer
.b
.is_shared
= true;
1708 tex
->buffer
.external_usage
= usage
;
1710 si_read_tex_bo_metadata(sscreen
, tex
, &metadata
);
1712 /* Displayable DCC requires an explicit flush. */
1714 !(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
1715 si_has_displayable_dcc(tex
)) {
1716 /* TODO: do we need to decompress DCC? */
1717 if (si_texture_discard_dcc(sscreen
, tex
)) {
1718 /* Update BO metadata after disabling DCC. */
1719 si_set_tex_bo_metadata(sscreen
, tex
);
1723 assert(tex
->surface
.tile_swizzle
== 0);
1724 return &tex
->buffer
.b
.b
;
1727 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1728 const struct pipe_resource
*templ
,
1729 struct winsys_handle
*whandle
,
1732 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1733 struct pb_buffer
*buf
= NULL
;
1734 unsigned stride
= 0, offset
= 0;
1736 /* Support only 2D textures without mipmaps */
1737 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
&&
1738 templ
->target
!= PIPE_TEXTURE_2D_ARRAY
) ||
1739 templ
->last_level
!= 0)
1742 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
1743 sscreen
->info
.max_alignment
,
1748 return si_texture_from_winsys_buffer(sscreen
, templ
, buf
, stride
,
1749 offset
, usage
, true);
1752 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1753 struct pipe_resource
*texture
)
1755 struct si_texture
*tex
= (struct si_texture
*)texture
;
1756 struct pipe_resource resource
;
1757 enum pipe_format pipe_format
= texture
->format
;
1759 assert(!tex
->flushed_depth_texture
);
1761 if (!tex
->can_sample_z
&& tex
->can_sample_s
) {
1762 switch (pipe_format
) {
1763 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1764 /* Save memory by not allocating the S plane. */
1765 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1767 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1768 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1769 /* Save memory bandwidth by not copying the
1770 * stencil part during flush.
1772 * This potentially increases memory bandwidth
1773 * if an application uses both Z and S texturing
1774 * simultaneously (a flushed Z24S8 texture
1775 * would be stored compactly), but how often
1776 * does that really happen?
1778 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1782 } else if (!tex
->can_sample_s
&& tex
->can_sample_z
) {
1783 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1785 /* DB->CB copies to an 8bpp surface don't work. */
1786 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1789 memset(&resource
, 0, sizeof(resource
));
1790 resource
.target
= texture
->target
;
1791 resource
.format
= pipe_format
;
1792 resource
.width0
= texture
->width0
;
1793 resource
.height0
= texture
->height0
;
1794 resource
.depth0
= texture
->depth0
;
1795 resource
.array_size
= texture
->array_size
;
1796 resource
.last_level
= texture
->last_level
;
1797 resource
.nr_samples
= texture
->nr_samples
;
1798 resource
.usage
= PIPE_USAGE_DEFAULT
;
1799 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1800 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1802 tex
->flushed_depth_texture
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1803 if (!tex
->flushed_depth_texture
) {
1804 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1811 * Initialize the pipe_resource descriptor to be of the same size as the box,
1812 * which is supposed to hold a subregion of the texture "orig" at the given
1815 static void si_init_temp_resource_from_box(struct pipe_resource
*res
,
1816 struct pipe_resource
*orig
,
1817 const struct pipe_box
*box
,
1818 unsigned level
, unsigned flags
)
1820 memset(res
, 0, sizeof(*res
));
1821 res
->format
= orig
->format
;
1822 res
->width0
= box
->width
;
1823 res
->height0
= box
->height
;
1825 res
->array_size
= 1;
1826 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1829 if (flags
& SI_RESOURCE_FLAG_TRANSFER
&&
1830 util_format_is_compressed(orig
->format
)) {
1831 /* Transfer resources are allocated with linear tiling, which is
1832 * not supported for compressed formats.
1834 unsigned blocksize
=
1835 util_format_get_blocksize(orig
->format
);
1837 if (blocksize
== 8) {
1838 res
->format
= PIPE_FORMAT_R16G16B16A16_UINT
;
1840 assert(blocksize
== 16);
1841 res
->format
= PIPE_FORMAT_R32G32B32A32_UINT
;
1844 res
->width0
= util_format_get_nblocksx(orig
->format
, box
->width
);
1845 res
->height0
= util_format_get_nblocksy(orig
->format
, box
->height
);
1848 /* We must set the correct texture target and dimensions for a 3D box. */
1849 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1850 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1851 res
->array_size
= box
->depth
;
1853 res
->target
= PIPE_TEXTURE_2D
;
1857 static bool si_can_invalidate_texture(struct si_screen
*sscreen
,
1858 struct si_texture
*tex
,
1859 unsigned transfer_usage
,
1860 const struct pipe_box
*box
)
1862 return !tex
->buffer
.b
.is_shared
&&
1863 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1864 tex
->buffer
.b
.b
.last_level
== 0 &&
1865 util_texrange_covers_whole_level(&tex
->buffer
.b
.b
, 0,
1866 box
->x
, box
->y
, box
->z
,
1867 box
->width
, box
->height
,
1871 static void si_texture_invalidate_storage(struct si_context
*sctx
,
1872 struct si_texture
*tex
)
1874 struct si_screen
*sscreen
= sctx
->screen
;
1876 /* There is no point in discarding depth and tiled buffers. */
1877 assert(!tex
->is_depth
);
1878 assert(tex
->surface
.is_linear
);
1880 /* Reallocate the buffer in the same pipe_resource. */
1881 si_alloc_resource(sscreen
, &tex
->buffer
);
1883 /* Initialize the CMASK base address (needed even without CMASK). */
1884 tex
->cmask_base_address_reg
=
1885 (tex
->buffer
.gpu_address
+ tex
->cmask_offset
) >> 8;
1887 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1889 sctx
->num_alloc_tex_transfer_bytes
+= tex
->size
;
1892 static void *si_texture_transfer_map(struct pipe_context
*ctx
,
1893 struct pipe_resource
*texture
,
1896 const struct pipe_box
*box
,
1897 struct pipe_transfer
**ptransfer
)
1899 struct si_context
*sctx
= (struct si_context
*)ctx
;
1900 struct si_texture
*tex
= (struct si_texture
*)texture
;
1901 struct si_transfer
*trans
;
1902 struct si_resource
*buf
;
1903 unsigned offset
= 0;
1905 bool use_staging_texture
= false;
1907 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
1908 assert(box
->width
&& box
->height
&& box
->depth
);
1910 if (tex
->is_depth
) {
1911 /* Depth textures use staging unconditionally. */
1912 use_staging_texture
= true;
1914 /* Degrade the tile mode if we get too many transfers on APUs.
1915 * On dGPUs, the staging texture is always faster.
1916 * Only count uploads that are at least 4x4 pixels large.
1918 if (!sctx
->screen
->info
.has_dedicated_vram
&&
1920 box
->width
>= 4 && box
->height
>= 4 &&
1921 p_atomic_inc_return(&tex
->num_level0_transfers
) == 10) {
1922 bool can_invalidate
=
1923 si_can_invalidate_texture(sctx
->screen
, tex
,
1926 si_reallocate_texture_inplace(sctx
, tex
,
1931 /* Tiled textures need to be converted into a linear texture for CPU
1932 * access. The staging texture is always linear and is placed in GART.
1934 * Reading from VRAM or GTT WC is slow, always use the staging
1935 * texture in this case.
1937 * Use the staging texture for uploads if the underlying BO
1940 if (!tex
->surface
.is_linear
)
1941 use_staging_texture
= true;
1942 else if (usage
& PIPE_TRANSFER_READ
)
1943 use_staging_texture
=
1944 tex
->buffer
.domains
& RADEON_DOMAIN_VRAM
||
1945 tex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
1946 /* Write & linear only: */
1947 else if (si_rings_is_buffer_referenced(sctx
, tex
->buffer
.buf
,
1948 RADEON_USAGE_READWRITE
) ||
1949 !sctx
->ws
->buffer_wait(tex
->buffer
.buf
, 0,
1950 RADEON_USAGE_READWRITE
)) {
1952 if (si_can_invalidate_texture(sctx
->screen
, tex
,
1954 si_texture_invalidate_storage(sctx
, tex
);
1956 use_staging_texture
= true;
1960 trans
= CALLOC_STRUCT(si_transfer
);
1963 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1964 trans
->b
.b
.level
= level
;
1965 trans
->b
.b
.usage
= usage
;
1966 trans
->b
.b
.box
= *box
;
1968 if (use_staging_texture
) {
1969 struct pipe_resource resource
;
1970 struct si_texture
*staging
;
1972 si_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1973 SI_RESOURCE_FLAG_TRANSFER
);
1974 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1975 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1977 /* Since depth-stencil textures don't support linear tiling,
1978 * blit from ZS to color and vice versa. u_blitter will do
1979 * the packing for these formats.
1982 resource
.format
= util_blitter_get_color_format_for_zs(resource
.format
);
1984 /* Create the temporary texture. */
1985 staging
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1987 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1990 trans
->staging
= &staging
->buffer
;
1992 /* Just get the strides. */
1993 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
,
1995 &trans
->b
.b
.layer_stride
);
1997 if (usage
& PIPE_TRANSFER_READ
)
1998 si_copy_to_staging_texture(ctx
, trans
);
2000 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
2002 buf
= trans
->staging
;
2004 /* the resource is mapped directly */
2005 offset
= si_texture_get_offset(sctx
->screen
, tex
, level
, box
,
2007 &trans
->b
.b
.layer_stride
);
2011 /* Always unmap texture CPU mappings on 32-bit architectures, so that
2012 * we don't run out of the CPU address space.
2014 if (sizeof(void*) == 4)
2015 usage
|= RADEON_TRANSFER_TEMPORARY
;
2017 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
2020 *ptransfer
= &trans
->b
.b
;
2021 return map
+ offset
;
2024 si_resource_reference(&trans
->staging
, NULL
);
2025 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
2030 static void si_texture_transfer_unmap(struct pipe_context
*ctx
,
2031 struct pipe_transfer
* transfer
)
2033 struct si_context
*sctx
= (struct si_context
*)ctx
;
2034 struct si_transfer
*stransfer
= (struct si_transfer
*)transfer
;
2035 struct pipe_resource
*texture
= transfer
->resource
;
2036 struct si_texture
*tex
= (struct si_texture
*)texture
;
2038 /* Always unmap texture CPU mappings on 32-bit architectures, so that
2039 * we don't run out of the CPU address space.
2041 if (sizeof(void*) == 4) {
2042 struct si_resource
*buf
=
2043 stransfer
->staging
? stransfer
->staging
: &tex
->buffer
;
2045 sctx
->ws
->buffer_unmap(buf
->buf
);
2048 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && stransfer
->staging
)
2049 si_copy_from_staging_texture(ctx
, stransfer
);
2051 if (stransfer
->staging
) {
2052 sctx
->num_alloc_tex_transfer_bytes
+= stransfer
->staging
->buf
->size
;
2053 si_resource_reference(&stransfer
->staging
, NULL
);
2056 /* Heuristic for {upload, draw, upload, draw, ..}:
2058 * Flush the gfx IB if we've allocated too much texture storage.
2060 * The idea is that we don't want to build IBs that use too much
2061 * memory and put pressure on the kernel memory manager and we also
2062 * want to make temporary and invalidated buffers go idle ASAP to
2063 * decrease the total memory usage or make them reusable. The memory
2064 * usage will be slightly higher than given here because of the buffer
2065 * cache in the winsys.
2067 * The result is that the kernel memory manager is never a bottleneck.
2069 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
2070 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
2071 sctx
->num_alloc_tex_transfer_bytes
= 0;
2074 pipe_resource_reference(&transfer
->resource
, NULL
);
2078 static const struct u_resource_vtbl si_texture_vtbl
=
2080 NULL
, /* get_handle */
2081 si_texture_destroy
, /* resource_destroy */
2082 si_texture_transfer_map
, /* transfer_map */
2083 u_default_transfer_flush_region
, /* transfer_flush_region */
2084 si_texture_transfer_unmap
, /* transfer_unmap */
2087 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
2089 bool vi_dcc_formats_compatible(struct si_screen
*sscreen
,
2090 enum pipe_format format1
,
2091 enum pipe_format format2
)
2093 const struct util_format_description
*desc1
, *desc2
;
2095 /* No format change - exit early. */
2096 if (format1
== format2
)
2099 format1
= si_simplify_cb_format(format1
);
2100 format2
= si_simplify_cb_format(format2
);
2102 /* Check again after format adjustments. */
2103 if (format1
== format2
)
2106 desc1
= util_format_description(format1
);
2107 desc2
= util_format_description(format2
);
2109 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2110 desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2113 /* Float and non-float are totally incompatible. */
2114 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
2115 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
2118 /* Channel sizes must match across DCC formats.
2119 * Comparing just the first 2 channels should be enough.
2121 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
2122 (desc1
->nr_channels
>= 2 &&
2123 desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
2126 /* Everything below is not needed if the driver never uses the DCC
2127 * clear code with the value of 1.
2130 /* If the clear values are all 1 or all 0, this constraint can be
2132 if (vi_alpha_is_on_msb(sscreen
, format1
) != vi_alpha_is_on_msb(sscreen
, format2
))
2135 /* Channel types must match if the clear value of 1 is used.
2136 * The type categories are only float, signed, unsigned.
2137 * NORM and INT are always compatible.
2139 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
2140 (desc1
->nr_channels
>= 2 &&
2141 desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
2147 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
2149 enum pipe_format view_format
)
2151 struct si_texture
*stex
= (struct si_texture
*)tex
;
2153 return vi_dcc_enabled(stex
, level
) &&
2154 !vi_dcc_formats_compatible((struct si_screen
*)tex
->screen
,
2155 tex
->format
, view_format
);
2158 /* This can't be merged with the above function, because
2159 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
2160 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
2161 struct pipe_resource
*tex
,
2163 enum pipe_format view_format
)
2165 struct si_texture
*stex
= (struct si_texture
*)tex
;
2167 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
2168 if (!si_texture_disable_dcc(sctx
, stex
))
2169 si_decompress_dcc(sctx
, stex
);
2172 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
2173 struct pipe_resource
*texture
,
2174 const struct pipe_surface
*templ
,
2175 unsigned width0
, unsigned height0
,
2176 unsigned width
, unsigned height
)
2178 struct si_surface
*surface
= CALLOC_STRUCT(si_surface
);
2183 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2184 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2186 pipe_reference_init(&surface
->base
.reference
, 1);
2187 pipe_resource_reference(&surface
->base
.texture
, texture
);
2188 surface
->base
.context
= pipe
;
2189 surface
->base
.format
= templ
->format
;
2190 surface
->base
.width
= width
;
2191 surface
->base
.height
= height
;
2192 surface
->base
.u
= templ
->u
;
2194 surface
->width0
= width0
;
2195 surface
->height0
= height0
;
2197 surface
->dcc_incompatible
=
2198 texture
->target
!= PIPE_BUFFER
&&
2199 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
2201 return &surface
->base
;
2204 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
,
2205 struct pipe_resource
*tex
,
2206 const struct pipe_surface
*templ
)
2208 unsigned level
= templ
->u
.tex
.level
;
2209 unsigned width
= u_minify(tex
->width0
, level
);
2210 unsigned height
= u_minify(tex
->height0
, level
);
2211 unsigned width0
= tex
->width0
;
2212 unsigned height0
= tex
->height0
;
2214 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2215 const struct util_format_description
*tex_desc
2216 = util_format_description(tex
->format
);
2217 const struct util_format_description
*templ_desc
2218 = util_format_description(templ
->format
);
2220 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2222 /* Adjust size of surface if and only if the block width or
2223 * height is changed. */
2224 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2225 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2226 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2227 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2229 width
= nblks_x
* templ_desc
->block
.width
;
2230 height
= nblks_y
* templ_desc
->block
.height
;
2232 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2233 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2237 return si_create_surface_custom(pipe
, tex
, templ
,
2242 static void si_surface_destroy(struct pipe_context
*pipe
,
2243 struct pipe_surface
*surface
)
2245 pipe_resource_reference(&surface
->texture
, NULL
);
2249 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2251 const struct util_format_description
*desc
= util_format_description(format
);
2253 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2255 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2256 return V_028C70_SWAP_STD
;
2258 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2261 switch (desc
->nr_channels
) {
2263 if (HAS_SWIZZLE(0,X
))
2264 return V_028C70_SWAP_STD
; /* X___ */
2265 else if (HAS_SWIZZLE(3,X
))
2266 return V_028C70_SWAP_ALT_REV
; /* ___X */
2269 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2270 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2271 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2272 return V_028C70_SWAP_STD
; /* XY__ */
2273 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2274 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2275 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2277 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2278 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2279 return V_028C70_SWAP_ALT
; /* X__Y */
2280 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2281 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2284 if (HAS_SWIZZLE(0,X
))
2285 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2286 else if (HAS_SWIZZLE(0,Z
))
2287 return V_028C70_SWAP_STD_REV
; /* ZYX */
2290 /* check the middle channels, the 1st and 4th channel can be NONE */
2291 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2292 return V_028C70_SWAP_STD
; /* XYZW */
2293 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2294 return V_028C70_SWAP_STD_REV
; /* WZYX */
2295 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2296 return V_028C70_SWAP_ALT
; /* ZYXW */
2297 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2300 return V_028C70_SWAP_ALT_REV
;
2302 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2309 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2311 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
,
2316 if (sctx
->dcc_stats
[slot
].query_active
)
2317 vi_separate_dcc_stop_query(sctx
,
2318 sctx
->dcc_stats
[slot
].tex
);
2320 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2321 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2322 sctx
->b
.destroy_query(&sctx
->b
,
2323 sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2324 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2327 si_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2331 * Return the per-context slot where DCC statistics queries for the texture live.
2333 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
,
2334 struct si_texture
*tex
)
2336 int i
, empty_slot
= -1;
2338 /* Remove zombie textures (textures kept alive by this array only). */
2339 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2340 if (sctx
->dcc_stats
[i
].tex
&&
2341 sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2342 vi_dcc_clean_up_context_slot(sctx
, i
);
2344 /* Find the texture. */
2345 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2346 /* Return if found. */
2347 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2348 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2352 /* Record the first seen empty slot. */
2353 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2357 /* Not found. Remove the oldest member to make space in the array. */
2358 if (empty_slot
== -1) {
2359 int oldest_slot
= 0;
2361 /* Find the oldest slot. */
2362 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2363 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2364 sctx
->dcc_stats
[i
].last_use_timestamp
)
2367 /* Clean up the oldest slot. */
2368 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2369 empty_slot
= oldest_slot
;
2372 /* Add the texture to the new slot. */
2373 si_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2374 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2378 static struct pipe_query
*
2379 vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2381 struct si_query_hw
*query
= (struct si_query_hw
*)
2382 sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2384 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2385 return (struct pipe_query
*)query
;
2389 * Called when binding a color buffer.
2391 void vi_separate_dcc_start_query(struct si_context
*sctx
,
2392 struct si_texture
*tex
)
2394 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2396 assert(!sctx
->dcc_stats
[i
].query_active
);
2398 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2399 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2401 /* begin or resume the query */
2402 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2403 sctx
->dcc_stats
[i
].query_active
= true;
2407 * Called when unbinding a color buffer.
2409 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
2410 struct si_texture
*tex
)
2412 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2414 assert(sctx
->dcc_stats
[i
].query_active
);
2415 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2417 /* pause or end the query */
2418 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2419 sctx
->dcc_stats
[i
].query_active
= false;
2422 static bool vi_should_enable_separate_dcc(struct si_texture
*tex
)
2424 /* The minimum number of fullscreen draws per frame that is required
2426 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2429 /* Called by fast clear. */
2430 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
2431 struct si_texture
*tex
)
2433 /* The intent is to use this with shared displayable back buffers,
2434 * but it's not strictly limited only to them.
2436 if (!tex
->buffer
.b
.is_shared
||
2437 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2438 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2439 tex
->buffer
.b
.b
.last_level
> 0 ||
2440 !tex
->surface
.dcc_size
||
2441 sctx
->screen
->debug_flags
& DBG(NO_DCC
) ||
2442 sctx
->screen
->debug_flags
& DBG(NO_DCC_FB
))
2445 assert(sctx
->chip_class
>= GFX8
);
2447 if (tex
->dcc_offset
)
2448 return; /* already enabled */
2450 /* Enable the DCC stat gathering. */
2451 if (!tex
->dcc_gather_statistics
) {
2452 tex
->dcc_gather_statistics
= true;
2453 vi_separate_dcc_start_query(sctx
, tex
);
2456 if (!vi_should_enable_separate_dcc(tex
))
2457 return; /* stats show that DCC decompression is too expensive */
2459 assert(tex
->surface
.num_dcc_levels
);
2460 assert(!tex
->dcc_separate_buffer
);
2462 si_texture_discard_cmask(sctx
->screen
, tex
);
2464 /* Get a DCC buffer. */
2465 if (tex
->last_dcc_separate_buffer
) {
2466 assert(tex
->dcc_gather_statistics
);
2467 assert(!tex
->dcc_separate_buffer
);
2468 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2469 tex
->last_dcc_separate_buffer
= NULL
;
2471 tex
->dcc_separate_buffer
=
2472 si_aligned_buffer_create(sctx
->b
.screen
,
2473 SI_RESOURCE_FLAG_UNMAPPABLE
,
2475 tex
->surface
.dcc_size
,
2476 tex
->surface
.dcc_alignment
);
2477 if (!tex
->dcc_separate_buffer
)
2481 /* dcc_offset is the absolute GPUVM address. */
2482 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2484 /* no need to flag anything since this is called by fast clear that
2485 * flags framebuffer state
2490 * Called by pipe_context::flush_resource, the place where DCC decompression
2493 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2494 struct si_texture
*tex
)
2496 struct si_context
*sctx
= (struct si_context
*)ctx
;
2497 struct pipe_query
*tmp
;
2498 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2499 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2500 bool disable
= false;
2502 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2503 union pipe_query_result result
;
2505 /* Read the results. */
2506 struct pipe_query
*query
= sctx
->dcc_stats
[i
].ps_stats
[2];
2507 ctx
->get_query_result(ctx
, query
,
2509 si_query_buffer_reset(sctx
, &((struct si_query_hw
*)query
)->buffer
);
2511 /* Compute the approximate number of fullscreen draws. */
2512 tex
->ps_draw_ratio
=
2513 result
.pipeline_statistics
.ps_invocations
/
2514 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2515 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2517 disable
= tex
->dcc_separate_buffer
&&
2518 !vi_should_enable_separate_dcc(tex
);
2521 tex
->num_slow_clears
= 0;
2523 /* stop the statistics query for ps_stats[0] */
2525 vi_separate_dcc_stop_query(sctx
, tex
);
2527 /* Move the queries in the queue by one. */
2528 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2529 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2530 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2531 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2533 /* create and start a new query as ps_stats[0] */
2535 vi_separate_dcc_start_query(sctx
, tex
);
2538 assert(!tex
->last_dcc_separate_buffer
);
2539 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2540 tex
->dcc_separate_buffer
= NULL
;
2541 tex
->dcc_offset
= 0;
2542 /* no need to flag anything since this is called after
2543 * decompression that re-sets framebuffer state
2548 static struct pipe_memory_object
*
2549 si_memobj_from_handle(struct pipe_screen
*screen
,
2550 struct winsys_handle
*whandle
,
2553 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2554 struct si_memory_object
*memobj
= CALLOC_STRUCT(si_memory_object
);
2555 struct pb_buffer
*buf
= NULL
;
2556 uint32_t stride
, offset
;
2561 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2562 sscreen
->info
.max_alignment
,
2569 memobj
->b
.dedicated
= dedicated
;
2571 memobj
->stride
= stride
;
2573 return (struct pipe_memory_object
*)memobj
;
2578 si_memobj_destroy(struct pipe_screen
*screen
,
2579 struct pipe_memory_object
*_memobj
)
2581 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2583 pb_reference(&memobj
->buf
, NULL
);
2587 static struct pipe_resource
*
2588 si_texture_from_memobj(struct pipe_screen
*screen
,
2589 const struct pipe_resource
*templ
,
2590 struct pipe_memory_object
*_memobj
,
2593 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2594 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2595 struct pipe_resource
*tex
=
2596 si_texture_from_winsys_buffer(sscreen
, templ
, memobj
->buf
,
2597 memobj
->stride
, offset
,
2598 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
|
2599 PIPE_HANDLE_USAGE_SHADER_WRITE
,
2600 memobj
->b
.dedicated
);
2604 /* si_texture_from_winsys_buffer doesn't increment refcount of
2605 * memobj->buf, so increment it here.
2607 struct pb_buffer
*buf
= NULL
;
2608 pb_reference(&buf
, memobj
->buf
);
2612 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2613 struct pipe_resource
*resource
,
2616 struct si_texture
*tex
= (struct si_texture
*)resource
;
2618 /* Buffers only support the linear flag. */
2619 if (resource
->target
== PIPE_BUFFER
)
2620 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2622 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2625 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2628 /* TODO: PIPE_BIND_CURSOR - do we care? */
2632 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2634 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2635 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2636 sscreen
->b
.resource_get_info
= si_texture_get_info
;
2637 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2638 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2639 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2640 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2643 void si_init_context_texture_functions(struct si_context
*sctx
)
2645 sctx
->b
.create_surface
= si_create_surface
;
2646 sctx
->b
.surface_destroy
= si_surface_destroy
;