2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_resource.h"
33 #include "util/u_surface.h"
34 #include "util/u_transfer.h"
35 #include "util/os_time.h"
38 #include "state_tracker/drm_driver.h"
40 #include "amd/addrlib/inc/addrinterface.h"
42 static enum radeon_surf_mode
43 si_choose_tiling(struct si_screen
*sscreen
,
44 const struct pipe_resource
*templ
, bool tc_compatible_htile
);
47 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
48 struct si_texture
*dst
,
49 unsigned dst_level
, unsigned dstx
,
50 unsigned dsty
, unsigned dstz
,
51 struct si_texture
*src
,
53 const struct pipe_box
*src_box
)
58 if (dst
->surface
.bpe
!= src
->surface
.bpe
)
61 /* MSAA: Blits don't exist in the real world. */
62 if (src
->buffer
.b
.b
.nr_samples
> 1 ||
63 dst
->buffer
.b
.b
.nr_samples
> 1)
66 /* Depth-stencil surfaces:
67 * When dst is linear, the DB->CB copy preserves HTILE.
68 * When dst is tiled, the 3D path must be used to update HTILE.
70 if (src
->is_depth
|| dst
->is_depth
)
74 * src: Use the 3D path. DCC decompression is expensive.
75 * dst: Use the 3D path to compress the pixels with DCC.
77 if (vi_dcc_enabled(src
, src_level
) ||
78 vi_dcc_enabled(dst
, dst_level
))
82 * src: Both texture and SDMA paths need decompression. Use SDMA.
83 * dst: If overwriting the whole texture, discard CMASK and use
84 * SDMA. Otherwise, use the 3D path.
86 if (dst
->cmask_buffer
&& dst
->dirty_level_mask
& (1 << dst_level
)) {
87 /* The CMASK clear is only enabled for the first level. */
88 assert(dst_level
== 0);
89 if (!util_texrange_covers_whole_level(&dst
->buffer
.b
.b
, dst_level
,
90 dstx
, dsty
, dstz
, src_box
->width
,
91 src_box
->height
, src_box
->depth
))
94 si_texture_discard_cmask(sctx
->screen
, dst
);
97 /* All requirements are met. Prepare textures for SDMA. */
98 if (src
->cmask_buffer
&& src
->dirty_level_mask
& (1 << src_level
))
99 sctx
->b
.flush_resource(&sctx
->b
, &src
->buffer
.b
.b
);
101 assert(!(src
->dirty_level_mask
& (1 << src_level
)));
102 assert(!(dst
->dirty_level_mask
& (1 << dst_level
)));
107 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
108 static void si_copy_region_with_blit(struct pipe_context
*pipe
,
109 struct pipe_resource
*dst
,
111 unsigned dstx
, unsigned dsty
, unsigned dstz
,
112 struct pipe_resource
*src
,
114 const struct pipe_box
*src_box
)
116 struct pipe_blit_info blit
;
118 memset(&blit
, 0, sizeof(blit
));
119 blit
.src
.resource
= src
;
120 blit
.src
.format
= src
->format
;
121 blit
.src
.level
= src_level
;
122 blit
.src
.box
= *src_box
;
123 blit
.dst
.resource
= dst
;
124 blit
.dst
.format
= dst
->format
;
125 blit
.dst
.level
= dst_level
;
126 blit
.dst
.box
.x
= dstx
;
127 blit
.dst
.box
.y
= dsty
;
128 blit
.dst
.box
.z
= dstz
;
129 blit
.dst
.box
.width
= src_box
->width
;
130 blit
.dst
.box
.height
= src_box
->height
;
131 blit
.dst
.box
.depth
= src_box
->depth
;
132 blit
.mask
= util_format_get_mask(dst
->format
);
133 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
136 pipe
->blit(pipe
, &blit
);
140 /* Copy from a full GPU texture to a transfer's staging one. */
141 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
143 struct si_context
*sctx
= (struct si_context
*)ctx
;
144 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
145 struct pipe_resource
*dst
= &stransfer
->staging
->b
.b
;
146 struct pipe_resource
*src
= transfer
->resource
;
148 if (src
->nr_samples
> 1 || ((struct si_texture
*)src
)->is_depth
) {
149 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
150 src
, transfer
->level
, &transfer
->box
);
154 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
158 /* Copy from a transfer's staging texture to a full GPU one. */
159 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
161 struct si_context
*sctx
= (struct si_context
*)ctx
;
162 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
163 struct pipe_resource
*dst
= transfer
->resource
;
164 struct pipe_resource
*src
= &stransfer
->staging
->b
.b
;
165 struct pipe_box sbox
;
167 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
169 if (dst
->nr_samples
> 1 || ((struct si_texture
*)dst
)->is_depth
) {
170 si_copy_region_with_blit(ctx
, dst
, transfer
->level
,
171 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
176 if (util_format_is_compressed(dst
->format
)) {
177 sbox
.width
= util_format_get_nblocksx(dst
->format
, sbox
.width
);
178 sbox
.height
= util_format_get_nblocksx(dst
->format
, sbox
.height
);
181 sctx
->dma_copy(ctx
, dst
, transfer
->level
,
182 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
186 static unsigned si_texture_get_offset(struct si_screen
*sscreen
,
187 struct si_texture
*tex
, unsigned level
,
188 const struct pipe_box
*box
,
190 unsigned *layer_stride
)
192 if (sscreen
->info
.chip_class
>= GFX9
) {
193 *stride
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
194 *layer_stride
= tex
->surface
.u
.gfx9
.surf_slice_size
;
199 /* Each texture is an array of slices. Each slice is an array
200 * of mipmap levels. */
201 return box
->z
* tex
->surface
.u
.gfx9
.surf_slice_size
+
202 tex
->surface
.u
.gfx9
.offset
[level
] +
203 (box
->y
/ tex
->surface
.blk_h
*
204 tex
->surface
.u
.gfx9
.surf_pitch
+
205 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
207 *stride
= tex
->surface
.u
.legacy
.level
[level
].nblk_x
*
209 assert((uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
210 *layer_stride
= (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
213 return tex
->surface
.u
.legacy
.level
[level
].offset
;
215 /* Each texture is an array of mipmap levels. Each level is
216 * an array of slices. */
217 return tex
->surface
.u
.legacy
.level
[level
].offset
+
218 box
->z
* (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
219 (box
->y
/ tex
->surface
.blk_h
*
220 tex
->surface
.u
.legacy
.level
[level
].nblk_x
+
221 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
225 static int si_init_surface(struct si_screen
*sscreen
,
226 struct radeon_surf
*surface
,
227 const struct pipe_resource
*ptex
,
228 enum radeon_surf_mode array_mode
,
229 unsigned pitch_in_bytes_override
,
233 bool is_flushed_depth
,
234 bool tc_compatible_htile
)
236 const struct util_format_description
*desc
=
237 util_format_description(ptex
->format
);
238 bool is_depth
, is_stencil
;
240 unsigned i
, bpe
, flags
= 0;
242 is_depth
= util_format_has_depth(desc
);
243 is_stencil
= util_format_has_stencil(desc
);
245 if (!is_flushed_depth
&&
246 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
247 bpe
= 4; /* stencil is allocated separately */
249 bpe
= util_format_get_blocksize(ptex
->format
);
250 assert(util_is_power_of_two_or_zero(bpe
));
253 if (!is_flushed_depth
&& is_depth
) {
254 flags
|= RADEON_SURF_ZBUFFER
;
256 if (sscreen
->debug_flags
& DBG(NO_HYPERZ
)) {
257 flags
|= RADEON_SURF_NO_HTILE
;
258 } else if (tc_compatible_htile
&&
259 (sscreen
->info
.chip_class
>= GFX9
||
260 array_mode
== RADEON_SURF_MODE_2D
)) {
261 /* TC-compatible HTILE only supports Z32_FLOAT.
262 * GFX9 also supports Z16_UNORM.
263 * On GFX8, promote Z16 to Z32. DB->CB copies will convert
264 * the format for transfers.
266 if (sscreen
->info
.chip_class
== GFX8
)
269 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
273 flags
|= RADEON_SURF_SBUFFER
;
276 if (sscreen
->info
.chip_class
>= GFX8
&&
277 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
||
278 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
279 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
280 flags
|= RADEON_SURF_DISABLE_DCC
;
282 /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */
283 if (sscreen
->info
.family
== CHIP_STONEY
&&
284 bpe
== 16 && ptex
->nr_samples
>= 2)
285 flags
|= RADEON_SURF_DISABLE_DCC
;
287 /* GFX8: DCC clear for 4x and 8x MSAA array textures unimplemented. */
288 if (sscreen
->info
.chip_class
== GFX8
&&
289 ptex
->nr_storage_samples
>= 4 &&
290 ptex
->array_size
> 1)
291 flags
|= RADEON_SURF_DISABLE_DCC
;
293 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
294 if (sscreen
->info
.chip_class
== GFX9
&&
295 ptex
->nr_storage_samples
>= 4)
296 flags
|= RADEON_SURF_DISABLE_DCC
;
298 /* TODO: GFX10: DCC causes corruption with MSAA. */
299 if (sscreen
->info
.chip_class
>= GFX10
&&
300 ptex
->nr_storage_samples
>= 2)
301 flags
|= RADEON_SURF_DISABLE_DCC
;
303 /* Shared textures must always set up DCC.
304 * If it's not present, it will be disabled by
305 * si_get_opaque_metadata later.
307 if (!is_imported
&& (sscreen
->debug_flags
& DBG(NO_DCC
)))
308 flags
|= RADEON_SURF_DISABLE_DCC
;
310 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
311 /* This should catch bugs in gallium users setting incorrect flags. */
312 assert(ptex
->nr_samples
<= 1 &&
313 ptex
->array_size
== 1 &&
315 ptex
->last_level
== 0 &&
316 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
318 flags
|= RADEON_SURF_SCANOUT
;
321 if (ptex
->bind
& PIPE_BIND_SHARED
)
322 flags
|= RADEON_SURF_SHAREABLE
;
324 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
325 if (!(ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
))
326 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
327 if (sscreen
->debug_flags
& DBG(NO_FMASK
))
328 flags
|= RADEON_SURF_NO_FMASK
;
330 if (sscreen
->info
.chip_class
>= GFX10
&&
331 (ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
)) {
332 flags
|= RADEON_SURF_FORCE_SWIZZLE_MODE
;
333 surface
->u
.gfx9
.surf
.swizzle_mode
= ADDR_SW_64KB_R_X
;
336 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
,
337 array_mode
, surface
);
342 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
344 if (sscreen
->info
.chip_class
>= GFX9
) {
346 surface
->u
.gfx9
.surf_pitch
= pitch
;
347 surface
->u
.gfx9
.surf_slice_size
=
348 (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
350 surface
->u
.gfx9
.surf_offset
= offset
;
353 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
354 surface
->u
.legacy
.level
[0].slice_size_dw
=
355 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
358 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
359 surface
->u
.legacy
.level
[i
].offset
+= offset
;
365 static void si_get_display_metadata(struct si_screen
*sscreen
,
366 struct radeon_surf
*surf
,
367 struct radeon_bo_metadata
*metadata
,
368 enum radeon_surf_mode
*array_mode
,
371 if (sscreen
->info
.chip_class
>= GFX9
) {
372 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
373 *array_mode
= RADEON_SURF_MODE_2D
;
375 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
377 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
378 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
380 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
382 if (metadata
->u
.gfx9
.dcc_offset_256B
) {
383 surf
->u
.gfx9
.display_dcc_pitch_max
= metadata
->u
.gfx9
.dcc_pitch_max
;
384 assert(metadata
->u
.gfx9
.dcc_independent_64B
== 1);
387 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
388 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
389 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
390 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
391 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
392 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
394 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
395 *array_mode
= RADEON_SURF_MODE_2D
;
396 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
397 *array_mode
= RADEON_SURF_MODE_1D
;
399 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
401 *is_scanout
= metadata
->u
.legacy
.scanout
;
405 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
406 struct si_texture
*tex
)
408 struct si_screen
*sscreen
= sctx
->screen
;
409 struct pipe_context
*ctx
= &sctx
->b
;
411 if (ctx
== sscreen
->aux_context
)
412 mtx_lock(&sscreen
->aux_context_lock
);
414 unsigned n
= sctx
->num_decompress_calls
;
415 ctx
->flush_resource(ctx
, &tex
->buffer
.b
.b
);
417 /* Flush only if any fast clear elimination took place. */
418 if (n
!= sctx
->num_decompress_calls
)
419 ctx
->flush(ctx
, NULL
, 0);
421 if (ctx
== sscreen
->aux_context
)
422 mtx_unlock(&sscreen
->aux_context_lock
);
425 void si_texture_discard_cmask(struct si_screen
*sscreen
,
426 struct si_texture
*tex
)
428 if (!tex
->cmask_buffer
)
431 assert(tex
->buffer
.b
.b
.nr_samples
<= 1);
434 tex
->cmask_base_address_reg
= tex
->buffer
.gpu_address
>> 8;
435 tex
->dirty_level_mask
= 0;
437 tex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
439 if (tex
->cmask_buffer
!= &tex
->buffer
)
440 si_resource_reference(&tex
->cmask_buffer
, NULL
);
442 tex
->cmask_buffer
= NULL
;
444 /* Notify all contexts about the change. */
445 p_atomic_inc(&sscreen
->dirty_tex_counter
);
446 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
449 static bool si_can_disable_dcc(struct si_texture
*tex
)
451 /* We can't disable DCC if it can be written by another process. */
452 return tex
->surface
.dcc_offset
&&
453 (!tex
->buffer
.b
.is_shared
||
454 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
));
457 static void si_texture_zero_dcc_fields(struct si_texture
*tex
)
459 tex
->surface
.dcc_offset
= 0;
460 tex
->surface
.display_dcc_offset
= 0;
461 tex
->surface
.dcc_retile_map_offset
= 0;
464 static bool si_texture_discard_dcc(struct si_screen
*sscreen
,
465 struct si_texture
*tex
)
467 if (!si_can_disable_dcc(tex
)) {
468 assert(tex
->surface
.display_dcc_offset
== 0);
472 assert(tex
->dcc_separate_buffer
== NULL
);
475 si_texture_zero_dcc_fields(tex
);
477 /* Notify all contexts about the change. */
478 p_atomic_inc(&sscreen
->dirty_tex_counter
);
483 * Disable DCC for the texture. (first decompress, then discard metadata).
485 * There is unresolved multi-context synchronization issue between
486 * screen::aux_context and the current context. If applications do this with
487 * multiple contexts, it's already undefined behavior for them and we don't
488 * have to worry about that. The scenario is:
490 * If context 1 disables DCC and context 2 has queued commands that write
491 * to the texture via CB with DCC enabled, and the order of operations is
493 * context 2 queues draw calls rendering to the texture, but doesn't flush
494 * context 1 disables DCC and flushes
495 * context 1 & 2 reset descriptors and FB state
496 * context 2 flushes (new compressed tiles written by the draw calls)
497 * context 1 & 2 read garbage, because DCC is disabled, yet there are
500 * \param sctx the current context if you have one, or sscreen->aux_context
503 bool si_texture_disable_dcc(struct si_context
*sctx
,
504 struct si_texture
*tex
)
506 struct si_screen
*sscreen
= sctx
->screen
;
508 if (!sctx
->has_graphics
)
509 return si_texture_discard_dcc(sscreen
, tex
);
511 if (!si_can_disable_dcc(tex
))
514 if (&sctx
->b
== sscreen
->aux_context
)
515 mtx_lock(&sscreen
->aux_context_lock
);
517 /* Decompress DCC. */
518 si_decompress_dcc(sctx
, tex
);
519 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
521 if (&sctx
->b
== sscreen
->aux_context
)
522 mtx_unlock(&sscreen
->aux_context_lock
);
524 return si_texture_discard_dcc(sscreen
, tex
);
527 static void si_reallocate_texture_inplace(struct si_context
*sctx
,
528 struct si_texture
*tex
,
529 unsigned new_bind_flag
,
530 bool invalidate_storage
)
532 struct pipe_screen
*screen
= sctx
->b
.screen
;
533 struct si_texture
*new_tex
;
534 struct pipe_resource templ
= tex
->buffer
.b
.b
;
537 templ
.bind
|= new_bind_flag
;
539 if (tex
->buffer
.b
.is_shared
)
542 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
543 if (tex
->surface
.is_linear
)
546 /* This fails with MSAA, depth, and compressed textures. */
547 if (si_choose_tiling(sctx
->screen
, &templ
, false) !=
548 RADEON_SURF_MODE_LINEAR_ALIGNED
)
552 new_tex
= (struct si_texture
*)screen
->resource_create(screen
, &templ
);
556 /* Copy the pixels to the new texture. */
557 if (!invalidate_storage
) {
558 for (i
= 0; i
<= templ
.last_level
; i
++) {
562 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
563 util_num_layers(&templ
, i
), &box
);
565 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0,
566 &tex
->buffer
.b
.b
, i
, &box
);
570 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
571 si_texture_discard_cmask(sctx
->screen
, tex
);
572 si_texture_discard_dcc(sctx
->screen
, tex
);
575 /* Replace the structure fields of tex. */
576 tex
->buffer
.b
.b
.bind
= templ
.bind
;
577 pb_reference(&tex
->buffer
.buf
, new_tex
->buffer
.buf
);
578 tex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
579 tex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
580 tex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
581 tex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
582 tex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
583 tex
->buffer
.domains
= new_tex
->buffer
.domains
;
584 tex
->buffer
.flags
= new_tex
->buffer
.flags
;
586 tex
->surface
= new_tex
->surface
;
587 si_texture_reference(&tex
->flushed_depth_texture
,
588 new_tex
->flushed_depth_texture
);
590 tex
->surface
.fmask_offset
= new_tex
->surface
.fmask_offset
;
591 tex
->surface
.cmask_offset
= new_tex
->surface
.cmask_offset
;
592 tex
->cmask_base_address_reg
= new_tex
->cmask_base_address_reg
;
594 if (tex
->cmask_buffer
== &tex
->buffer
)
595 tex
->cmask_buffer
= NULL
;
597 si_resource_reference(&tex
->cmask_buffer
, NULL
);
599 if (new_tex
->cmask_buffer
== &new_tex
->buffer
)
600 tex
->cmask_buffer
= &tex
->buffer
;
602 si_resource_reference(&tex
->cmask_buffer
, new_tex
->cmask_buffer
);
604 tex
->surface
.dcc_offset
= new_tex
->surface
.dcc_offset
;
605 tex
->cb_color_info
= new_tex
->cb_color_info
;
606 memcpy(tex
->color_clear_value
, new_tex
->color_clear_value
,
607 sizeof(tex
->color_clear_value
));
608 tex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
610 tex
->surface
.htile_offset
= new_tex
->surface
.htile_offset
;
611 tex
->depth_clear_value
= new_tex
->depth_clear_value
;
612 tex
->dirty_level_mask
= new_tex
->dirty_level_mask
;
613 tex
->stencil_dirty_level_mask
= new_tex
->stencil_dirty_level_mask
;
614 tex
->db_render_format
= new_tex
->db_render_format
;
615 tex
->stencil_clear_value
= new_tex
->stencil_clear_value
;
616 tex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
617 tex
->depth_cleared
= new_tex
->depth_cleared
;
618 tex
->stencil_cleared
= new_tex
->stencil_cleared
;
619 tex
->upgraded_depth
= new_tex
->upgraded_depth
;
620 tex
->db_compatible
= new_tex
->db_compatible
;
621 tex
->can_sample_z
= new_tex
->can_sample_z
;
622 tex
->can_sample_s
= new_tex
->can_sample_s
;
624 tex
->separate_dcc_dirty
= new_tex
->separate_dcc_dirty
;
625 tex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
626 si_resource_reference(&tex
->dcc_separate_buffer
,
627 new_tex
->dcc_separate_buffer
);
628 si_resource_reference(&tex
->last_dcc_separate_buffer
,
629 new_tex
->last_dcc_separate_buffer
);
631 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
632 assert(!tex
->surface
.htile_offset
);
633 assert(!tex
->cmask_buffer
);
634 assert(!tex
->surface
.fmask_size
);
635 assert(!tex
->surface
.dcc_offset
);
636 assert(!tex
->is_depth
);
639 si_texture_reference(&new_tex
, NULL
);
641 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
644 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
646 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
649 static void si_set_tex_bo_metadata(struct si_screen
*sscreen
,
650 struct si_texture
*tex
)
652 struct radeon_surf
*surface
= &tex
->surface
;
653 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
654 struct radeon_bo_metadata md
;
656 memset(&md
, 0, sizeof(md
));
658 if (sscreen
->info
.chip_class
>= GFX9
) {
659 md
.u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
661 if (tex
->surface
.dcc_offset
&& !tex
->dcc_separate_buffer
) {
662 uint64_t dcc_offset
=
663 tex
->surface
.display_dcc_offset
? tex
->surface
.display_dcc_offset
664 : tex
->surface
.dcc_offset
;
666 assert((dcc_offset
>> 8) != 0 && (dcc_offset
>> 8) < (1 << 24));
667 md
.u
.gfx9
.dcc_offset_256B
= dcc_offset
>> 8;
668 md
.u
.gfx9
.dcc_pitch_max
= tex
->surface
.u
.gfx9
.display_dcc_pitch_max
;
669 md
.u
.gfx9
.dcc_independent_64B
= 1;
672 md
.u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
673 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
674 md
.u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
675 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
676 md
.u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
677 md
.u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
678 md
.u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
679 md
.u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
680 md
.u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
681 md
.u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
682 md
.u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
683 md
.u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
686 assert(tex
->dcc_separate_buffer
== NULL
);
687 assert(tex
->surface
.fmask_size
== 0);
689 /* Metadata image format format version 1:
690 * [0] = 1 (metadata format identifier)
691 * [1] = (VENDOR_ID << 16) | PCI_ID
692 * [2:9] = image descriptor for the whole resource
693 * [2] is always 0, because the base address is cleared
694 * [9] is the DCC offset bits [39:8] from the beginning of
696 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
699 md
.metadata
[0] = 1; /* metadata image format version 1 */
701 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
702 md
.metadata
[1] = si_get_bo_metadata_word1(sscreen
);
704 static const unsigned char swizzle
[] = {
710 bool is_array
= util_texture_is_array(res
->target
);
713 sscreen
->make_texture_descriptor(sscreen
, tex
, true,
714 res
->target
, res
->format
,
715 swizzle
, 0, res
->last_level
, 0,
716 is_array
? res
->array_size
- 1 : 0,
717 res
->width0
, res
->height0
, res
->depth0
,
720 si_set_mutable_tex_desc_fields(sscreen
, tex
, &tex
->surface
.u
.legacy
.level
[0],
721 0, 0, tex
->surface
.blk_w
, false, desc
);
723 /* Clear the base address and set the relative DCC offset. */
725 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
727 switch (sscreen
->info
.chip_class
) {
732 desc
[7] = tex
->surface
.dcc_offset
>> 8;
735 desc
[7] = tex
->surface
.dcc_offset
>> 8;
736 desc
[5] &= C_008F24_META_DATA_ADDRESS
;
737 desc
[5] |= S_008F24_META_DATA_ADDRESS(tex
->surface
.dcc_offset
>> 40);
740 desc
[6] &= C_00A018_META_DATA_ADDRESS_LO
;
741 desc
[6] |= S_00A018_META_DATA_ADDRESS_LO(tex
->surface
.dcc_offset
>> 8);
742 desc
[7] = tex
->surface
.dcc_offset
>> 16;
749 /* Dwords [2:9] contain the image descriptor. */
750 memcpy(&md
.metadata
[2], desc
, sizeof(desc
));
751 md
.size_metadata
= 10 * 4;
753 /* Dwords [10:..] contain the mipmap level offsets. */
754 if (sscreen
->info
.chip_class
<= GFX8
) {
755 for (unsigned i
= 0; i
<= res
->last_level
; i
++)
756 md
.metadata
[10+i
] = tex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
758 md
.size_metadata
+= (1 + res
->last_level
) * 4;
761 sscreen
->ws
->buffer_set_metadata(tex
->buffer
.buf
, &md
);
764 static bool si_read_tex_bo_metadata(struct si_screen
*sscreen
,
765 struct si_texture
*tex
,
766 struct radeon_bo_metadata
*md
)
768 uint32_t *desc
= &md
->metadata
[2];
770 if (md
->size_metadata
< 10 * 4 || /* at least 2(header) + 8(desc) dwords */
771 md
->metadata
[0] == 0 || /* invalid version number */
772 md
->metadata
[1] != si_get_bo_metadata_word1(sscreen
)) /* invalid PCI ID */ {
773 /* Disable DCC because it might not be enabled. */
774 si_texture_zero_dcc_fields(tex
);
776 /* Don't report an error if the texture comes from an incompatible driver,
777 * but this might not work.
782 /* Validate that sample counts and the number of mipmap levels match. */
783 unsigned last_level
= G_008F1C_LAST_LEVEL(desc
[3]);
784 unsigned type
= G_008F1C_TYPE(desc
[3]);
786 if (type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA
||
787 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
788 unsigned log_samples
=
789 util_logbase2(MAX2(1, tex
->buffer
.b
.b
.nr_storage_samples
));
791 if (last_level
!= log_samples
) {
792 fprintf(stderr
, "radeonsi: invalid MSAA texture import, "
793 "metadata has log2(samples) = %u, the caller set %u\n",
794 last_level
, log_samples
);
798 if (last_level
!= tex
->buffer
.b
.b
.last_level
) {
799 fprintf(stderr
, "radeonsi: invalid mipmapped texture import, "
800 "metadata has last_level = %u, the caller set %u\n",
801 last_level
, tex
->buffer
.b
.b
.last_level
);
806 if (sscreen
->info
.chip_class
>= GFX8
&&
807 G_008F28_COMPRESSION_EN(desc
[6])) {
808 /* Read DCC information.
810 * Some state trackers don't set the SCANOUT flag when
811 * importing displayable images, which affects PIPE_ALIGNED
812 * and RB_ALIGNED, so we need to recover them here.
814 switch (sscreen
->info
.chip_class
) {
816 tex
->surface
.dcc_offset
= (uint64_t)desc
[7] << 8;
820 tex
->surface
.dcc_offset
=
821 ((uint64_t)desc
[7] << 8) |
822 ((uint64_t)G_008F24_META_DATA_ADDRESS(desc
[5]) << 40);
823 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
=
824 G_008F24_META_PIPE_ALIGNED(desc
[5]);
825 tex
->surface
.u
.gfx9
.dcc
.rb_aligned
=
826 G_008F24_META_RB_ALIGNED(desc
[5]);
828 /* If DCC is unaligned, this can only be a displayable image. */
829 if (!tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&&
830 !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
831 tex
->surface
.is_displayable
= true;
835 tex
->surface
.dcc_offset
=
836 ((uint64_t)G_00A018_META_DATA_ADDRESS_LO(desc
[6]) << 8) |
837 ((uint64_t)desc
[7] << 16);
838 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
=
839 G_00A018_META_PIPE_ALIGNED(desc
[6]);
847 /* Disable DCC. dcc_offset is always set by texture_from_handle
848 * and must be cleared here.
850 si_texture_zero_dcc_fields(tex
);
856 static bool si_has_displayable_dcc(struct si_texture
*tex
)
858 struct si_screen
*sscreen
= (struct si_screen
*)tex
->buffer
.b
.b
.screen
;
860 if (sscreen
->info
.chip_class
<= GFX8
)
863 /* This needs a cache flush before scanout.
864 * (it can't be scanned out and rendered to simultaneously)
866 if (sscreen
->info
.use_display_dcc_unaligned
&&
867 tex
->surface
.dcc_offset
&&
868 !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&&
869 !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
872 /* This needs an explicit flush (flush_resource). */
873 if (sscreen
->info
.use_display_dcc_with_retile_blit
&&
874 tex
->surface
.display_dcc_offset
)
880 static void si_texture_get_info(struct pipe_screen
* screen
,
881 struct pipe_resource
*resource
,
885 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
886 struct si_texture
*tex
= (struct si_texture
*)resource
;
890 if (!sscreen
|| !tex
)
893 if (resource
->target
!= PIPE_BUFFER
) {
894 if (sscreen
->info
.chip_class
>= GFX9
) {
895 offset
= tex
->surface
.u
.gfx9
.surf_offset
;
896 stride
= tex
->surface
.u
.gfx9
.surf_pitch
*
899 offset
= tex
->surface
.u
.legacy
.level
[0].offset
;
900 stride
= tex
->surface
.u
.legacy
.level
[0].nblk_x
*
912 static bool si_texture_get_handle(struct pipe_screen
* screen
,
913 struct pipe_context
*ctx
,
914 struct pipe_resource
*resource
,
915 struct winsys_handle
*whandle
,
918 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
919 struct si_context
*sctx
;
920 struct si_resource
*res
= si_resource(resource
);
921 struct si_texture
*tex
= (struct si_texture
*)resource
;
922 bool update_metadata
= false;
923 unsigned stride
, offset
, slice_size
;
926 ctx
= threaded_context_unwrap_sync(ctx
);
927 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
929 if (resource
->target
!= PIPE_BUFFER
) {
930 /* This is not supported now, but it might be required for OpenCL
931 * interop in the future.
933 if (resource
->nr_samples
> 1 || tex
->is_depth
)
936 /* Move a suballocated texture into a non-suballocated allocation. */
937 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
938 tex
->surface
.tile_swizzle
||
939 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
940 sscreen
->info
.has_local_buffers
)) {
941 assert(!res
->b
.is_shared
);
942 si_reallocate_texture_inplace(sctx
, tex
,
943 PIPE_BIND_SHARED
, false);
945 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
946 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
947 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
948 assert(tex
->surface
.tile_swizzle
== 0);
951 /* Since shader image stores don't support DCC on GFX8,
952 * disable it for external clients that want write
955 if ((usage
& PIPE_HANDLE_USAGE_SHADER_WRITE
&& tex
->surface
.dcc_offset
) ||
956 /* Displayable DCC requires an explicit flush. */
957 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
958 si_has_displayable_dcc(tex
))) {
959 if (si_texture_disable_dcc(sctx
, tex
)) {
960 update_metadata
= true;
961 /* si_texture_disable_dcc flushes the context */
966 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
967 (tex
->cmask_buffer
|| tex
->surface
.dcc_offset
)) {
968 /* Eliminate fast clear (both CMASK and DCC) */
969 si_eliminate_fast_color_clear(sctx
, tex
);
970 /* eliminate_fast_color_clear flushes the context */
973 /* Disable CMASK if flush_resource isn't going
976 if (tex
->cmask_buffer
)
977 si_texture_discard_cmask(sscreen
, tex
);
981 if (!res
->b
.is_shared
|| update_metadata
)
982 si_set_tex_bo_metadata(sscreen
, tex
);
984 if (sscreen
->info
.chip_class
>= GFX9
) {
985 slice_size
= tex
->surface
.u
.gfx9
.surf_slice_size
;
987 slice_size
= (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
990 /* Buffer exports are for the OpenCL interop. */
991 /* Move a suballocated buffer into a non-suballocated allocation. */
992 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
993 /* A DMABUF export always fails if the BO is local. */
994 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
995 sscreen
->info
.has_local_buffers
)) {
996 assert(!res
->b
.is_shared
);
998 /* Allocate a new buffer with PIPE_BIND_SHARED. */
999 struct pipe_resource templ
= res
->b
.b
;
1000 templ
.bind
|= PIPE_BIND_SHARED
;
1002 struct pipe_resource
*newb
=
1003 screen
->resource_create(screen
, &templ
);
1007 /* Copy the old buffer contents to the new one. */
1008 struct pipe_box box
;
1009 u_box_1d(0, newb
->width0
, &box
);
1010 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0,
1011 &res
->b
.b
, 0, &box
);
1013 /* Move the new buffer storage to the old pipe_resource. */
1014 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
1015 pipe_resource_reference(&newb
, NULL
);
1017 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
1018 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
1025 si_texture_get_info(screen
, resource
, &stride
, &offset
);
1028 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
1030 if (res
->b
.is_shared
) {
1031 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
1034 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
1035 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
1036 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
1038 res
->b
.is_shared
= true;
1039 res
->external_usage
= usage
;
1042 whandle
->stride
= stride
;
1043 whandle
->offset
= offset
+ slice_size
* whandle
->layer
;
1045 return sscreen
->ws
->buffer_get_handle(sscreen
->ws
, res
->buf
, whandle
);
1048 static void si_texture_destroy(struct pipe_screen
*screen
,
1049 struct pipe_resource
*ptex
)
1051 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1052 struct si_texture
*tex
= (struct si_texture
*)ptex
;
1053 struct si_resource
*resource
= &tex
->buffer
;
1055 if (sscreen
->info
.chip_class
>= GFX9
)
1056 free(tex
->surface
.u
.gfx9
.dcc_retile_map
);
1058 si_texture_reference(&tex
->flushed_depth_texture
, NULL
);
1060 if (tex
->cmask_buffer
!= &tex
->buffer
) {
1061 si_resource_reference(&tex
->cmask_buffer
, NULL
);
1063 pb_reference(&resource
->buf
, NULL
);
1064 si_resource_reference(&tex
->dcc_separate_buffer
, NULL
);
1065 si_resource_reference(&tex
->last_dcc_separate_buffer
, NULL
);
1069 static const struct u_resource_vtbl si_texture_vtbl
;
1071 void si_print_texture_info(struct si_screen
*sscreen
,
1072 struct si_texture
*tex
, struct u_log_context
*log
)
1076 /* Common parameters. */
1077 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1078 "blk_h=%u, array_size=%u, last_level=%u, "
1079 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1080 tex
->buffer
.b
.b
.width0
, tex
->buffer
.b
.b
.height0
,
1081 tex
->buffer
.b
.b
.depth0
, tex
->surface
.blk_w
,
1083 tex
->buffer
.b
.b
.array_size
, tex
->buffer
.b
.b
.last_level
,
1084 tex
->surface
.bpe
, tex
->buffer
.b
.b
.nr_samples
,
1085 tex
->surface
.flags
, util_format_short_name(tex
->buffer
.b
.b
.format
));
1087 if (sscreen
->info
.chip_class
>= GFX9
) {
1088 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1089 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1090 tex
->surface
.surf_size
,
1091 tex
->surface
.u
.gfx9
.surf_slice_size
,
1092 tex
->surface
.surf_alignment
,
1093 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1094 tex
->surface
.u
.gfx9
.surf
.epitch
,
1095 tex
->surface
.u
.gfx9
.surf_pitch
);
1097 if (tex
->surface
.fmask_offset
) {
1098 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1099 "alignment=%u, swmode=%u, epitch=%u\n",
1100 tex
->surface
.fmask_offset
,
1101 tex
->surface
.fmask_size
,
1102 tex
->surface
.fmask_alignment
,
1103 tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1104 tex
->surface
.u
.gfx9
.fmask
.epitch
);
1107 if (tex
->cmask_buffer
) {
1108 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, "
1109 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1110 tex
->surface
.cmask_offset
,
1111 tex
->surface
.cmask_size
,
1112 tex
->surface
.cmask_alignment
,
1113 tex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1114 tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1117 if (tex
->surface
.htile_offset
) {
1118 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1119 "rb_aligned=%u, pipe_aligned=%u\n",
1120 tex
->surface
.htile_offset
,
1121 tex
->surface
.htile_size
,
1122 tex
->surface
.htile_alignment
,
1123 tex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1124 tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1127 if (tex
->surface
.dcc_offset
) {
1128 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1129 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1130 tex
->surface
.dcc_offset
, tex
->surface
.dcc_size
,
1131 tex
->surface
.dcc_alignment
,
1132 tex
->surface
.u
.gfx9
.display_dcc_pitch_max
,
1133 tex
->surface
.num_dcc_levels
);
1136 if (tex
->surface
.u
.gfx9
.stencil_offset
) {
1137 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1138 tex
->surface
.u
.gfx9
.stencil_offset
,
1139 tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1140 tex
->surface
.u
.gfx9
.stencil
.epitch
);
1145 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1146 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1147 tex
->surface
.surf_size
, tex
->surface
.surf_alignment
, tex
->surface
.u
.legacy
.bankw
,
1148 tex
->surface
.u
.legacy
.bankh
, tex
->surface
.u
.legacy
.num_banks
, tex
->surface
.u
.legacy
.mtilea
,
1149 tex
->surface
.u
.legacy
.tile_split
, tex
->surface
.u
.legacy
.pipe_config
,
1150 (tex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1152 if (tex
->surface
.fmask_offset
)
1153 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1154 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1155 tex
->surface
.fmask_offset
, tex
->surface
.fmask_size
, tex
->surface
.fmask_alignment
,
1156 tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
,
1157 tex
->surface
.u
.legacy
.fmask
.bankh
,
1158 tex
->surface
.u
.legacy
.fmask
.slice_tile_max
,
1159 tex
->surface
.u
.legacy
.fmask
.tiling_index
);
1161 if (tex
->cmask_buffer
)
1162 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, alignment=%u, "
1163 "slice_tile_max=%u\n",
1164 tex
->surface
.cmask_offset
, tex
->surface
.cmask_size
, tex
->surface
.cmask_alignment
,
1165 tex
->surface
.u
.legacy
.cmask_slice_tile_max
);
1167 if (tex
->surface
.htile_offset
)
1168 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1169 "alignment=%u, TC_compatible = %u\n",
1170 tex
->surface
.htile_offset
, tex
->surface
.htile_size
,
1171 tex
->surface
.htile_alignment
,
1172 tex
->tc_compatible_htile
);
1174 if (tex
->surface
.dcc_offset
) {
1175 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1176 tex
->surface
.dcc_offset
, tex
->surface
.dcc_size
,
1177 tex
->surface
.dcc_alignment
);
1178 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1179 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1180 "fast_clear_size=%u\n",
1181 i
, i
< tex
->surface
.num_dcc_levels
,
1182 tex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1183 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1186 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1187 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1188 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1189 "mode=%u, tiling_index = %u\n",
1190 i
, tex
->surface
.u
.legacy
.level
[i
].offset
,
1191 (uint64_t)tex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1192 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1193 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1194 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1195 tex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1196 tex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1197 tex
->surface
.u
.legacy
.level
[i
].mode
,
1198 tex
->surface
.u
.legacy
.tiling_index
[i
]);
1200 if (tex
->surface
.has_stencil
) {
1201 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1202 tex
->surface
.u
.legacy
.stencil_tile_split
);
1203 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++) {
1204 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1205 "slice_size=%"PRIu64
", npix_x=%u, "
1206 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1207 "mode=%u, tiling_index = %u\n",
1208 i
, tex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1209 (uint64_t)tex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1210 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1211 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1212 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1213 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1214 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1215 tex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1216 tex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1221 /* Common processing for si_texture_create and si_texture_from_handle */
1222 static struct si_texture
*
1223 si_texture_create_object(struct pipe_screen
*screen
,
1224 const struct pipe_resource
*base
,
1225 struct pb_buffer
*buf
,
1226 struct radeon_surf
*surface
)
1228 struct si_texture
*tex
;
1229 struct si_resource
*resource
;
1230 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1232 tex
= CALLOC_STRUCT(si_texture
);
1236 resource
= &tex
->buffer
;
1237 resource
->b
.b
= *base
;
1238 resource
->b
.b
.next
= NULL
;
1239 resource
->b
.vtbl
= &si_texture_vtbl
;
1240 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1241 resource
->b
.b
.screen
= screen
;
1243 /* don't include stencil-only formats which we don't support for rendering */
1244 tex
->is_depth
= util_format_has_depth(util_format_description(tex
->buffer
.b
.b
.format
));
1245 tex
->surface
= *surface
;
1246 tex
->tc_compatible_htile
= tex
->surface
.htile_size
!= 0 &&
1247 (tex
->surface
.flags
&
1248 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1250 /* TC-compatible HTILE:
1251 * - GFX8 only supports Z32_FLOAT.
1252 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1253 if (tex
->tc_compatible_htile
) {
1254 if (sscreen
->info
.chip_class
>= GFX9
&&
1255 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1256 tex
->db_render_format
= base
->format
;
1258 tex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1259 tex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1260 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1263 tex
->db_render_format
= base
->format
;
1266 /* Applies to GCN. */
1267 tex
->last_msaa_resolve_target_micro_mode
= tex
->surface
.micro_tile_mode
;
1269 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1270 * between frames, so the only thing that can enable separate DCC
1271 * with DRI2 is multiple slow clears within a frame.
1273 tex
->ps_draw_ratio
= 0;
1275 if (tex
->is_depth
) {
1276 if (sscreen
->info
.chip_class
>= GFX9
) {
1277 tex
->can_sample_z
= true;
1278 tex
->can_sample_s
= true;
1280 /* Stencil texturing with HTILE doesn't work
1281 * with mipmapping on Navi10-14. */
1282 if ((sscreen
->info
.family
== CHIP_NAVI10
||
1283 sscreen
->info
.family
== CHIP_NAVI12
||
1284 sscreen
->info
.family
== CHIP_NAVI14
) &&
1285 base
->last_level
> 0)
1286 tex
->htile_stencil_disabled
= true;
1288 tex
->can_sample_z
= !tex
->surface
.u
.legacy
.depth_adjusted
;
1289 tex
->can_sample_s
= !tex
->surface
.u
.legacy
.stencil_adjusted
;
1292 tex
->db_compatible
= surface
->flags
& RADEON_SURF_ZBUFFER
;
1294 if (tex
->surface
.cmask_offset
) {
1295 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
1296 tex
->cmask_buffer
= &tex
->buffer
;
1300 /* Now create the backing buffer. */
1302 si_init_resource_fields(sscreen
, resource
, tex
->surface
.total_size
,
1303 tex
->surface
.surf_alignment
);
1305 if (!si_alloc_resource(sscreen
, resource
))
1308 resource
->buf
= buf
;
1309 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1310 resource
->bo_size
= buf
->size
;
1311 resource
->bo_alignment
= buf
->alignment
;
1312 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1313 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1314 resource
->vram_usage
= buf
->size
;
1315 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1316 resource
->gart_usage
= buf
->size
;
1319 if (tex
->cmask_buffer
) {
1320 /* Initialize the cmask to 0xCC (= compressed state). */
1321 si_screen_clear_buffer(sscreen
, &tex
->cmask_buffer
->b
.b
,
1322 tex
->surface
.cmask_offset
, tex
->surface
.cmask_size
,
1325 if (tex
->surface
.htile_offset
) {
1326 uint32_t clear_value
= 0;
1328 if (sscreen
->info
.chip_class
>= GFX9
|| tex
->tc_compatible_htile
)
1329 clear_value
= 0x0000030F;
1331 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1332 tex
->surface
.htile_offset
,
1333 tex
->surface
.htile_size
,
1337 /* Initialize DCC only if the texture is not being imported. */
1338 if (!buf
&& tex
->surface
.dcc_offset
) {
1339 /* Clear DCC to black for all tiles with DCC enabled.
1341 * This fixes corruption in 3DMark Slingshot Extreme, which
1342 * uses uninitialized textures, causing corruption.
1344 if (tex
->surface
.num_dcc_levels
== tex
->buffer
.b
.b
.last_level
+ 1 &&
1345 tex
->buffer
.b
.b
.nr_samples
<= 2) {
1346 /* Simple case - all tiles have DCC enabled. */
1347 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1348 tex
->surface
.dcc_offset
,
1349 tex
->surface
.dcc_size
,
1350 DCC_CLEAR_COLOR_0000
);
1351 } else if (sscreen
->info
.chip_class
>= GFX9
) {
1352 /* Clear to uncompressed. Clearing this to black is complicated. */
1353 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1354 tex
->surface
.dcc_offset
,
1355 tex
->surface
.dcc_size
,
1358 /* GFX8: Initialize mipmap levels and multisamples separately. */
1359 if (tex
->buffer
.b
.b
.nr_samples
>= 2) {
1360 /* Clearing this to black is complicated. */
1361 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1362 tex
->surface
.dcc_offset
,
1363 tex
->surface
.dcc_size
,
1366 /* Clear the enabled mipmap levels to black. */
1369 for (unsigned i
= 0; i
< tex
->surface
.num_dcc_levels
; i
++) {
1370 if (!tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
)
1373 size
= tex
->surface
.u
.legacy
.level
[i
].dcc_offset
+
1374 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
;
1377 /* Mipmap levels with DCC. */
1379 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1380 tex
->surface
.dcc_offset
, size
,
1381 DCC_CLEAR_COLOR_0000
);
1383 /* Mipmap levels without DCC. */
1384 if (size
!= tex
->surface
.dcc_size
) {
1385 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1386 tex
->surface
.dcc_offset
+ size
,
1387 tex
->surface
.dcc_size
- size
,
1393 /* Upload the DCC retile map. */
1394 if (tex
->surface
.dcc_retile_map_offset
) {
1395 /* Use a staging buffer for the upload, because
1396 * the buffer backing the texture is unmappable.
1398 bool use_uint16
= tex
->surface
.u
.gfx9
.dcc_retile_use_uint16
;
1399 unsigned num_elements
= tex
->surface
.u
.gfx9
.dcc_retile_num_elements
;
1400 struct si_resource
*buf
=
1401 si_aligned_buffer_create(screen
, 0, PIPE_USAGE_STREAM
,
1402 num_elements
* (use_uint16
? 2 : 4),
1403 sscreen
->info
.tcc_cache_line_size
);
1404 uint32_t *ui
= (uint32_t*)sscreen
->ws
->buffer_map(buf
->buf
, NULL
,
1405 PIPE_TRANSFER_WRITE
);
1406 uint16_t *us
= (uint16_t*)ui
;
1408 /* Upload the retile map into a staging buffer. */
1410 for (unsigned i
= 0; i
< num_elements
; i
++)
1411 us
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1413 for (unsigned i
= 0; i
< num_elements
; i
++)
1414 ui
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1417 /* Copy the staging buffer to the buffer backing the texture. */
1418 struct si_context
*sctx
= (struct si_context
*)sscreen
->aux_context
;
1419 struct pipe_box box
;
1420 u_box_1d(0, buf
->b
.b
.width0
, &box
);
1422 assert(tex
->surface
.dcc_retile_map_offset
<= UINT_MAX
);
1423 mtx_lock(&sscreen
->aux_context_lock
);
1424 sctx
->dma_copy(&sctx
->b
, &tex
->buffer
.b
.b
, 0,
1425 tex
->surface
.dcc_retile_map_offset
, 0, 0,
1426 &buf
->b
.b
, 0, &box
);
1427 sscreen
->aux_context
->flush(sscreen
->aux_context
, NULL
, 0);
1428 mtx_unlock(&sscreen
->aux_context_lock
);
1430 si_resource_reference(&buf
, NULL
);
1434 /* Initialize the CMASK base register value. */
1435 tex
->cmask_base_address_reg
=
1436 (tex
->buffer
.gpu_address
+ tex
->surface
.cmask_offset
) >> 8;
1438 if (sscreen
->debug_flags
& DBG(VM
)) {
1439 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1440 tex
->buffer
.gpu_address
,
1441 tex
->buffer
.gpu_address
+ tex
->buffer
.buf
->size
,
1442 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1443 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1446 if (sscreen
->debug_flags
& DBG(TEX
)) {
1448 struct u_log_context log
;
1449 u_log_context_init(&log
);
1450 si_print_texture_info(sscreen
, tex
, &log
);
1451 u_log_new_page_print(&log
, stdout
);
1453 u_log_context_destroy(&log
);
1460 if (sscreen
->info
.chip_class
>= GFX9
)
1461 free(surface
->u
.gfx9
.dcc_retile_map
);
1465 static enum radeon_surf_mode
1466 si_choose_tiling(struct si_screen
*sscreen
,
1467 const struct pipe_resource
*templ
, bool tc_compatible_htile
)
1469 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1470 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
;
1471 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1472 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1474 /* MSAA resources must be 2D tiled. */
1475 if (templ
->nr_samples
> 1)
1476 return RADEON_SURF_MODE_2D
;
1478 /* Transfer resources should be linear. */
1479 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1480 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1482 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on GFX8,
1483 * which requires 2D tiling.
1485 if (sscreen
->info
.chip_class
== GFX8
&& tc_compatible_htile
)
1486 return RADEON_SURF_MODE_2D
;
1488 /* Handle common candidates for the linear mode.
1489 * Compressed textures and DB surfaces must always be tiled.
1491 if (!force_tiling
&&
1492 !is_depth_stencil
&&
1493 !util_format_is_compressed(templ
->format
)) {
1494 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1495 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1497 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1498 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1499 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1501 /* Cursors are linear on AMD GCN.
1502 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1503 if (templ
->bind
& PIPE_BIND_CURSOR
)
1504 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1506 if (templ
->bind
& PIPE_BIND_LINEAR
)
1507 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1509 /* Textures with a very small height are recommended to be linear. */
1510 if (templ
->target
== PIPE_TEXTURE_1D
||
1511 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1512 /* Only very thin and long 2D textures should benefit from
1513 * linear_aligned. */
1514 (templ
->width0
> 8 && templ
->height0
<= 2))
1515 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1517 /* Textures likely to be mapped often. */
1518 if (templ
->usage
== PIPE_USAGE_STAGING
||
1519 templ
->usage
== PIPE_USAGE_STREAM
)
1520 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1523 /* Make small textures 1D tiled. */
1524 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1525 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1526 return RADEON_SURF_MODE_1D
;
1528 /* The allocator will switch to 1D if needed. */
1529 return RADEON_SURF_MODE_2D
;
1532 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1533 const struct pipe_resource
*templ
)
1535 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1536 bool is_zs
= util_format_is_depth_or_stencil(templ
->format
);
1538 if (templ
->nr_samples
>= 2) {
1539 /* This is hackish (overwriting the const pipe_resource template),
1540 * but should be harmless and state trackers can also see
1541 * the overriden number of samples in the created pipe_resource.
1543 if (is_zs
&& sscreen
->eqaa_force_z_samples
) {
1544 ((struct pipe_resource
*)templ
)->nr_samples
=
1545 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1546 sscreen
->eqaa_force_z_samples
;
1547 } else if (!is_zs
&& sscreen
->eqaa_force_color_samples
) {
1548 ((struct pipe_resource
*)templ
)->nr_samples
=
1549 sscreen
->eqaa_force_coverage_samples
;
1550 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1551 sscreen
->eqaa_force_color_samples
;
1555 struct radeon_surf surface
= {0};
1556 bool is_flushed_depth
= templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
||
1557 templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
;
1558 bool tc_compatible_htile
=
1559 sscreen
->info
.chip_class
>= GFX8
&&
1560 /* There are issues with TC-compatible HTILE on Tonga (and
1561 * Iceland is the same design), and documented bug workarounds
1562 * don't help. For example, this fails:
1563 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1565 sscreen
->info
.family
!= CHIP_TONGA
&&
1566 sscreen
->info
.family
!= CHIP_ICELAND
&&
1567 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1568 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1569 !is_flushed_depth
&&
1570 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1574 r
= si_init_surface(sscreen
, &surface
, templ
,
1575 si_choose_tiling(sscreen
, templ
, tc_compatible_htile
),
1576 0, 0, false, false, is_flushed_depth
,
1577 tc_compatible_htile
);
1582 return (struct pipe_resource
*)
1583 si_texture_create_object(screen
, templ
, NULL
, &surface
);
1586 static struct pipe_resource
*si_texture_from_winsys_buffer(struct si_screen
*sscreen
,
1587 const struct pipe_resource
*templ
,
1588 struct pb_buffer
*buf
,
1594 enum radeon_surf_mode array_mode
;
1595 struct radeon_surf surface
= {};
1596 struct radeon_bo_metadata metadata
= {};
1597 struct si_texture
*tex
;
1602 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1603 si_get_display_metadata(sscreen
, &surface
, &metadata
,
1604 &array_mode
, &is_scanout
);
1607 * The bo metadata is unset for un-dedicated images. So we fall
1608 * back to linear. See answer to question 5 of the
1609 * VK_KHX_external_memory spec for some details.
1611 * It is possible that this case isn't going to work if the
1612 * surface pitch isn't correctly aligned by default.
1614 * In order to support it correctly we require multi-image
1615 * metadata to be syncrhonized between radv and radeonsi. The
1616 * semantics of associating multiple image metadata to a memory
1617 * object on the vulkan export side are not concretely defined
1620 * All the use cases we are aware of at the moment for memory
1621 * objects use dedicated allocations. So lets keep the initial
1622 * implementation simple.
1624 * A possible alternative is to attempt to reconstruct the
1625 * tiling information when the TexParameter TEXTURE_TILING_EXT
1628 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1632 r
= si_init_surface(sscreen
, &surface
, templ
,
1633 array_mode
, stride
, offset
, true, is_scanout
,
1638 tex
= si_texture_create_object(&sscreen
->b
, templ
, buf
, &surface
);
1642 tex
->buffer
.b
.is_shared
= true;
1643 tex
->buffer
.external_usage
= usage
;
1645 if (!si_read_tex_bo_metadata(sscreen
, tex
, &metadata
)) {
1646 si_texture_reference(&tex
, NULL
);
1650 /* Displayable DCC requires an explicit flush. */
1652 !(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
1653 si_has_displayable_dcc(tex
)) {
1654 /* TODO: do we need to decompress DCC? */
1655 if (si_texture_discard_dcc(sscreen
, tex
)) {
1656 /* Update BO metadata after disabling DCC. */
1657 si_set_tex_bo_metadata(sscreen
, tex
);
1661 assert(tex
->surface
.tile_swizzle
== 0);
1662 return &tex
->buffer
.b
.b
;
1665 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1666 const struct pipe_resource
*templ
,
1667 struct winsys_handle
*whandle
,
1670 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1671 struct pb_buffer
*buf
= NULL
;
1673 /* Support only 2D textures without mipmaps */
1674 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
&&
1675 templ
->target
!= PIPE_TEXTURE_2D_ARRAY
) ||
1676 templ
->last_level
!= 0)
1679 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
1680 sscreen
->info
.max_alignment
);
1684 return si_texture_from_winsys_buffer(sscreen
, templ
, buf
,
1685 whandle
->stride
, whandle
->offset
,
1689 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1690 struct pipe_resource
*texture
)
1692 struct si_texture
*tex
= (struct si_texture
*)texture
;
1693 struct pipe_resource resource
;
1694 enum pipe_format pipe_format
= texture
->format
;
1696 assert(!tex
->flushed_depth_texture
);
1698 if (!tex
->can_sample_z
&& tex
->can_sample_s
) {
1699 switch (pipe_format
) {
1700 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1701 /* Save memory by not allocating the S plane. */
1702 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1704 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1705 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1706 /* Save memory bandwidth by not copying the
1707 * stencil part during flush.
1709 * This potentially increases memory bandwidth
1710 * if an application uses both Z and S texturing
1711 * simultaneously (a flushed Z24S8 texture
1712 * would be stored compactly), but how often
1713 * does that really happen?
1715 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1719 } else if (!tex
->can_sample_s
&& tex
->can_sample_z
) {
1720 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1722 /* DB->CB copies to an 8bpp surface don't work. */
1723 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1726 memset(&resource
, 0, sizeof(resource
));
1727 resource
.target
= texture
->target
;
1728 resource
.format
= pipe_format
;
1729 resource
.width0
= texture
->width0
;
1730 resource
.height0
= texture
->height0
;
1731 resource
.depth0
= texture
->depth0
;
1732 resource
.array_size
= texture
->array_size
;
1733 resource
.last_level
= texture
->last_level
;
1734 resource
.nr_samples
= texture
->nr_samples
;
1735 resource
.usage
= PIPE_USAGE_DEFAULT
;
1736 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1737 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1739 tex
->flushed_depth_texture
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1740 if (!tex
->flushed_depth_texture
) {
1741 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1748 * Initialize the pipe_resource descriptor to be of the same size as the box,
1749 * which is supposed to hold a subregion of the texture "orig" at the given
1752 static void si_init_temp_resource_from_box(struct pipe_resource
*res
,
1753 struct pipe_resource
*orig
,
1754 const struct pipe_box
*box
,
1755 unsigned level
, unsigned flags
)
1757 memset(res
, 0, sizeof(*res
));
1758 res
->format
= orig
->format
;
1759 res
->width0
= box
->width
;
1760 res
->height0
= box
->height
;
1762 res
->array_size
= 1;
1763 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1766 if (flags
& SI_RESOURCE_FLAG_TRANSFER
&&
1767 util_format_is_compressed(orig
->format
)) {
1768 /* Transfer resources are allocated with linear tiling, which is
1769 * not supported for compressed formats.
1771 unsigned blocksize
=
1772 util_format_get_blocksize(orig
->format
);
1774 if (blocksize
== 8) {
1775 res
->format
= PIPE_FORMAT_R16G16B16A16_UINT
;
1777 assert(blocksize
== 16);
1778 res
->format
= PIPE_FORMAT_R32G32B32A32_UINT
;
1781 res
->width0
= util_format_get_nblocksx(orig
->format
, box
->width
);
1782 res
->height0
= util_format_get_nblocksy(orig
->format
, box
->height
);
1785 /* We must set the correct texture target and dimensions for a 3D box. */
1786 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1787 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1788 res
->array_size
= box
->depth
;
1790 res
->target
= PIPE_TEXTURE_2D
;
1794 static bool si_can_invalidate_texture(struct si_screen
*sscreen
,
1795 struct si_texture
*tex
,
1796 unsigned transfer_usage
,
1797 const struct pipe_box
*box
)
1799 return !tex
->buffer
.b
.is_shared
&&
1800 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1801 tex
->buffer
.b
.b
.last_level
== 0 &&
1802 util_texrange_covers_whole_level(&tex
->buffer
.b
.b
, 0,
1803 box
->x
, box
->y
, box
->z
,
1804 box
->width
, box
->height
,
1808 static void si_texture_invalidate_storage(struct si_context
*sctx
,
1809 struct si_texture
*tex
)
1811 struct si_screen
*sscreen
= sctx
->screen
;
1813 /* There is no point in discarding depth and tiled buffers. */
1814 assert(!tex
->is_depth
);
1815 assert(tex
->surface
.is_linear
);
1817 /* Reallocate the buffer in the same pipe_resource. */
1818 si_alloc_resource(sscreen
, &tex
->buffer
);
1820 /* Initialize the CMASK base address (needed even without CMASK). */
1821 tex
->cmask_base_address_reg
=
1822 (tex
->buffer
.gpu_address
+ tex
->surface
.cmask_offset
) >> 8;
1824 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1826 sctx
->num_alloc_tex_transfer_bytes
+= tex
->surface
.total_size
;
1829 static void *si_texture_transfer_map(struct pipe_context
*ctx
,
1830 struct pipe_resource
*texture
,
1833 const struct pipe_box
*box
,
1834 struct pipe_transfer
**ptransfer
)
1836 struct si_context
*sctx
= (struct si_context
*)ctx
;
1837 struct si_texture
*tex
= (struct si_texture
*)texture
;
1838 struct si_transfer
*trans
;
1839 struct si_resource
*buf
;
1840 unsigned offset
= 0;
1842 bool use_staging_texture
= false;
1844 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
1845 assert(box
->width
&& box
->height
&& box
->depth
);
1847 if (tex
->is_depth
) {
1848 /* Depth textures use staging unconditionally. */
1849 use_staging_texture
= true;
1851 /* Degrade the tile mode if we get too many transfers on APUs.
1852 * On dGPUs, the staging texture is always faster.
1853 * Only count uploads that are at least 4x4 pixels large.
1855 if (!sctx
->screen
->info
.has_dedicated_vram
&&
1857 box
->width
>= 4 && box
->height
>= 4 &&
1858 p_atomic_inc_return(&tex
->num_level0_transfers
) == 10) {
1859 bool can_invalidate
=
1860 si_can_invalidate_texture(sctx
->screen
, tex
,
1863 si_reallocate_texture_inplace(sctx
, tex
,
1868 /* Tiled textures need to be converted into a linear texture for CPU
1869 * access. The staging texture is always linear and is placed in GART.
1871 * Reading from VRAM or GTT WC is slow, always use the staging
1872 * texture in this case.
1874 * Use the staging texture for uploads if the underlying BO
1877 if (!tex
->surface
.is_linear
)
1878 use_staging_texture
= true;
1879 else if (usage
& PIPE_TRANSFER_READ
)
1880 use_staging_texture
=
1881 tex
->buffer
.domains
& RADEON_DOMAIN_VRAM
||
1882 tex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
1883 /* Write & linear only: */
1884 else if (si_rings_is_buffer_referenced(sctx
, tex
->buffer
.buf
,
1885 RADEON_USAGE_READWRITE
) ||
1886 !sctx
->ws
->buffer_wait(tex
->buffer
.buf
, 0,
1887 RADEON_USAGE_READWRITE
)) {
1889 if (si_can_invalidate_texture(sctx
->screen
, tex
,
1891 si_texture_invalidate_storage(sctx
, tex
);
1893 use_staging_texture
= true;
1897 trans
= CALLOC_STRUCT(si_transfer
);
1900 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1901 trans
->b
.b
.level
= level
;
1902 trans
->b
.b
.usage
= usage
;
1903 trans
->b
.b
.box
= *box
;
1905 if (use_staging_texture
) {
1906 struct pipe_resource resource
;
1907 struct si_texture
*staging
;
1909 si_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1910 SI_RESOURCE_FLAG_TRANSFER
);
1911 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1912 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1914 /* Since depth-stencil textures don't support linear tiling,
1915 * blit from ZS to color and vice versa. u_blitter will do
1916 * the packing for these formats.
1919 resource
.format
= util_blitter_get_color_format_for_zs(resource
.format
);
1921 /* Create the temporary texture. */
1922 staging
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1924 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1927 trans
->staging
= &staging
->buffer
;
1929 /* Just get the strides. */
1930 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
,
1932 &trans
->b
.b
.layer_stride
);
1934 if (usage
& PIPE_TRANSFER_READ
)
1935 si_copy_to_staging_texture(ctx
, trans
);
1937 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1939 buf
= trans
->staging
;
1941 /* the resource is mapped directly */
1942 offset
= si_texture_get_offset(sctx
->screen
, tex
, level
, box
,
1944 &trans
->b
.b
.layer_stride
);
1948 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1949 * we don't run out of the CPU address space.
1951 if (sizeof(void*) == 4)
1952 usage
|= RADEON_TRANSFER_TEMPORARY
;
1954 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
1957 *ptransfer
= &trans
->b
.b
;
1958 return map
+ offset
;
1961 si_resource_reference(&trans
->staging
, NULL
);
1962 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
1967 static void si_texture_transfer_unmap(struct pipe_context
*ctx
,
1968 struct pipe_transfer
* transfer
)
1970 struct si_context
*sctx
= (struct si_context
*)ctx
;
1971 struct si_transfer
*stransfer
= (struct si_transfer
*)transfer
;
1972 struct pipe_resource
*texture
= transfer
->resource
;
1973 struct si_texture
*tex
= (struct si_texture
*)texture
;
1975 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1976 * we don't run out of the CPU address space.
1978 if (sizeof(void*) == 4) {
1979 struct si_resource
*buf
=
1980 stransfer
->staging
? stransfer
->staging
: &tex
->buffer
;
1982 sctx
->ws
->buffer_unmap(buf
->buf
);
1985 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && stransfer
->staging
)
1986 si_copy_from_staging_texture(ctx
, stransfer
);
1988 if (stransfer
->staging
) {
1989 sctx
->num_alloc_tex_transfer_bytes
+= stransfer
->staging
->buf
->size
;
1990 si_resource_reference(&stransfer
->staging
, NULL
);
1993 /* Heuristic for {upload, draw, upload, draw, ..}:
1995 * Flush the gfx IB if we've allocated too much texture storage.
1997 * The idea is that we don't want to build IBs that use too much
1998 * memory and put pressure on the kernel memory manager and we also
1999 * want to make temporary and invalidated buffers go idle ASAP to
2000 * decrease the total memory usage or make them reusable. The memory
2001 * usage will be slightly higher than given here because of the buffer
2002 * cache in the winsys.
2004 * The result is that the kernel memory manager is never a bottleneck.
2006 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
2007 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
2008 sctx
->num_alloc_tex_transfer_bytes
= 0;
2011 pipe_resource_reference(&transfer
->resource
, NULL
);
2015 static const struct u_resource_vtbl si_texture_vtbl
=
2017 NULL
, /* get_handle */
2018 si_texture_destroy
, /* resource_destroy */
2019 si_texture_transfer_map
, /* transfer_map */
2020 u_default_transfer_flush_region
, /* transfer_flush_region */
2021 si_texture_transfer_unmap
, /* transfer_unmap */
2024 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
2026 bool vi_dcc_formats_compatible(struct si_screen
*sscreen
,
2027 enum pipe_format format1
,
2028 enum pipe_format format2
)
2030 const struct util_format_description
*desc1
, *desc2
;
2032 /* No format change - exit early. */
2033 if (format1
== format2
)
2036 format1
= si_simplify_cb_format(format1
);
2037 format2
= si_simplify_cb_format(format2
);
2039 /* Check again after format adjustments. */
2040 if (format1
== format2
)
2043 desc1
= util_format_description(format1
);
2044 desc2
= util_format_description(format2
);
2046 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2047 desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2050 /* Float and non-float are totally incompatible. */
2051 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
2052 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
2055 /* Channel sizes must match across DCC formats.
2056 * Comparing just the first 2 channels should be enough.
2058 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
2059 (desc1
->nr_channels
>= 2 &&
2060 desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
2063 /* Everything below is not needed if the driver never uses the DCC
2064 * clear code with the value of 1.
2067 /* If the clear values are all 1 or all 0, this constraint can be
2069 if (vi_alpha_is_on_msb(sscreen
, format1
) != vi_alpha_is_on_msb(sscreen
, format2
))
2072 /* Channel types must match if the clear value of 1 is used.
2073 * The type categories are only float, signed, unsigned.
2074 * NORM and INT are always compatible.
2076 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
2077 (desc1
->nr_channels
>= 2 &&
2078 desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
2084 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
2086 enum pipe_format view_format
)
2088 struct si_texture
*stex
= (struct si_texture
*)tex
;
2090 return vi_dcc_enabled(stex
, level
) &&
2091 !vi_dcc_formats_compatible((struct si_screen
*)tex
->screen
,
2092 tex
->format
, view_format
);
2095 /* This can't be merged with the above function, because
2096 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
2097 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
2098 struct pipe_resource
*tex
,
2100 enum pipe_format view_format
)
2102 struct si_texture
*stex
= (struct si_texture
*)tex
;
2104 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
2105 if (!si_texture_disable_dcc(sctx
, stex
))
2106 si_decompress_dcc(sctx
, stex
);
2109 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
2110 struct pipe_resource
*texture
,
2111 const struct pipe_surface
*templ
,
2112 unsigned width0
, unsigned height0
,
2113 unsigned width
, unsigned height
)
2115 struct si_surface
*surface
= CALLOC_STRUCT(si_surface
);
2120 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2121 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2123 pipe_reference_init(&surface
->base
.reference
, 1);
2124 pipe_resource_reference(&surface
->base
.texture
, texture
);
2125 surface
->base
.context
= pipe
;
2126 surface
->base
.format
= templ
->format
;
2127 surface
->base
.width
= width
;
2128 surface
->base
.height
= height
;
2129 surface
->base
.u
= templ
->u
;
2131 surface
->width0
= width0
;
2132 surface
->height0
= height0
;
2134 surface
->dcc_incompatible
=
2135 texture
->target
!= PIPE_BUFFER
&&
2136 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
2138 return &surface
->base
;
2141 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
,
2142 struct pipe_resource
*tex
,
2143 const struct pipe_surface
*templ
)
2145 unsigned level
= templ
->u
.tex
.level
;
2146 unsigned width
= u_minify(tex
->width0
, level
);
2147 unsigned height
= u_minify(tex
->height0
, level
);
2148 unsigned width0
= tex
->width0
;
2149 unsigned height0
= tex
->height0
;
2151 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2152 const struct util_format_description
*tex_desc
2153 = util_format_description(tex
->format
);
2154 const struct util_format_description
*templ_desc
2155 = util_format_description(templ
->format
);
2157 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2159 /* Adjust size of surface if and only if the block width or
2160 * height is changed. */
2161 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2162 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2163 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2164 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2166 width
= nblks_x
* templ_desc
->block
.width
;
2167 height
= nblks_y
* templ_desc
->block
.height
;
2169 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2170 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2174 return si_create_surface_custom(pipe
, tex
, templ
,
2179 static void si_surface_destroy(struct pipe_context
*pipe
,
2180 struct pipe_surface
*surface
)
2182 pipe_resource_reference(&surface
->texture
, NULL
);
2186 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2188 const struct util_format_description
*desc
= util_format_description(format
);
2190 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2192 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2193 return V_028C70_SWAP_STD
;
2195 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2198 switch (desc
->nr_channels
) {
2200 if (HAS_SWIZZLE(0,X
))
2201 return V_028C70_SWAP_STD
; /* X___ */
2202 else if (HAS_SWIZZLE(3,X
))
2203 return V_028C70_SWAP_ALT_REV
; /* ___X */
2206 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2207 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2208 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2209 return V_028C70_SWAP_STD
; /* XY__ */
2210 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2211 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2212 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2214 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2215 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2216 return V_028C70_SWAP_ALT
; /* X__Y */
2217 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2218 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2221 if (HAS_SWIZZLE(0,X
))
2222 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2223 else if (HAS_SWIZZLE(0,Z
))
2224 return V_028C70_SWAP_STD_REV
; /* ZYX */
2227 /* check the middle channels, the 1st and 4th channel can be NONE */
2228 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2229 return V_028C70_SWAP_STD
; /* XYZW */
2230 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2231 return V_028C70_SWAP_STD_REV
; /* WZYX */
2232 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2233 return V_028C70_SWAP_ALT
; /* ZYXW */
2234 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2237 return V_028C70_SWAP_ALT_REV
;
2239 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2246 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2248 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
,
2253 if (sctx
->dcc_stats
[slot
].query_active
)
2254 vi_separate_dcc_stop_query(sctx
,
2255 sctx
->dcc_stats
[slot
].tex
);
2257 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2258 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2259 sctx
->b
.destroy_query(&sctx
->b
,
2260 sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2261 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2264 si_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2268 * Return the per-context slot where DCC statistics queries for the texture live.
2270 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
,
2271 struct si_texture
*tex
)
2273 int i
, empty_slot
= -1;
2275 /* Remove zombie textures (textures kept alive by this array only). */
2276 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2277 if (sctx
->dcc_stats
[i
].tex
&&
2278 sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2279 vi_dcc_clean_up_context_slot(sctx
, i
);
2281 /* Find the texture. */
2282 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2283 /* Return if found. */
2284 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2285 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2289 /* Record the first seen empty slot. */
2290 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2294 /* Not found. Remove the oldest member to make space in the array. */
2295 if (empty_slot
== -1) {
2296 int oldest_slot
= 0;
2298 /* Find the oldest slot. */
2299 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2300 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2301 sctx
->dcc_stats
[i
].last_use_timestamp
)
2304 /* Clean up the oldest slot. */
2305 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2306 empty_slot
= oldest_slot
;
2309 /* Add the texture to the new slot. */
2310 si_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2311 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2315 static struct pipe_query
*
2316 vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2318 struct si_query_hw
*query
= (struct si_query_hw
*)
2319 sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2321 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2322 return (struct pipe_query
*)query
;
2326 * Called when binding a color buffer.
2328 void vi_separate_dcc_start_query(struct si_context
*sctx
,
2329 struct si_texture
*tex
)
2331 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2333 assert(!sctx
->dcc_stats
[i
].query_active
);
2335 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2336 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2338 /* begin or resume the query */
2339 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2340 sctx
->dcc_stats
[i
].query_active
= true;
2344 * Called when unbinding a color buffer.
2346 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
2347 struct si_texture
*tex
)
2349 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2351 assert(sctx
->dcc_stats
[i
].query_active
);
2352 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2354 /* pause or end the query */
2355 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2356 sctx
->dcc_stats
[i
].query_active
= false;
2359 static bool vi_should_enable_separate_dcc(struct si_texture
*tex
)
2361 /* The minimum number of fullscreen draws per frame that is required
2363 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2366 /* Called by fast clear. */
2367 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
2368 struct si_texture
*tex
)
2370 /* The intent is to use this with shared displayable back buffers,
2371 * but it's not strictly limited only to them.
2373 if (!tex
->buffer
.b
.is_shared
||
2374 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2375 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2376 tex
->buffer
.b
.b
.last_level
> 0 ||
2377 !tex
->surface
.dcc_size
||
2378 sctx
->screen
->debug_flags
& DBG(NO_DCC
) ||
2379 sctx
->screen
->debug_flags
& DBG(NO_DCC_FB
))
2382 assert(sctx
->chip_class
>= GFX8
);
2384 if (tex
->surface
.dcc_offset
)
2385 return; /* already enabled */
2387 /* Enable the DCC stat gathering. */
2388 if (!tex
->dcc_gather_statistics
) {
2389 tex
->dcc_gather_statistics
= true;
2390 vi_separate_dcc_start_query(sctx
, tex
);
2393 if (!vi_should_enable_separate_dcc(tex
))
2394 return; /* stats show that DCC decompression is too expensive */
2396 assert(tex
->surface
.num_dcc_levels
);
2397 assert(!tex
->dcc_separate_buffer
);
2399 si_texture_discard_cmask(sctx
->screen
, tex
);
2401 /* Get a DCC buffer. */
2402 if (tex
->last_dcc_separate_buffer
) {
2403 assert(tex
->dcc_gather_statistics
);
2404 assert(!tex
->dcc_separate_buffer
);
2405 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2406 tex
->last_dcc_separate_buffer
= NULL
;
2408 tex
->dcc_separate_buffer
=
2409 si_aligned_buffer_create(sctx
->b
.screen
,
2410 SI_RESOURCE_FLAG_UNMAPPABLE
,
2412 tex
->surface
.dcc_size
,
2413 tex
->surface
.dcc_alignment
);
2414 if (!tex
->dcc_separate_buffer
)
2418 /* dcc_offset is the absolute GPUVM address. */
2419 tex
->surface
.dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2421 /* no need to flag anything since this is called by fast clear that
2422 * flags framebuffer state
2427 * Called by pipe_context::flush_resource, the place where DCC decompression
2430 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2431 struct si_texture
*tex
)
2433 struct si_context
*sctx
= (struct si_context
*)ctx
;
2434 struct pipe_query
*tmp
;
2435 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2436 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2437 bool disable
= false;
2439 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2440 union pipe_query_result result
;
2442 /* Read the results. */
2443 struct pipe_query
*query
= sctx
->dcc_stats
[i
].ps_stats
[2];
2444 ctx
->get_query_result(ctx
, query
,
2446 si_query_buffer_reset(sctx
, &((struct si_query_hw
*)query
)->buffer
);
2448 /* Compute the approximate number of fullscreen draws. */
2449 tex
->ps_draw_ratio
=
2450 result
.pipeline_statistics
.ps_invocations
/
2451 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2452 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2454 disable
= tex
->dcc_separate_buffer
&&
2455 !vi_should_enable_separate_dcc(tex
);
2458 tex
->num_slow_clears
= 0;
2460 /* stop the statistics query for ps_stats[0] */
2462 vi_separate_dcc_stop_query(sctx
, tex
);
2464 /* Move the queries in the queue by one. */
2465 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2466 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2467 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2468 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2470 /* create and start a new query as ps_stats[0] */
2472 vi_separate_dcc_start_query(sctx
, tex
);
2475 assert(!tex
->last_dcc_separate_buffer
);
2476 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2477 tex
->dcc_separate_buffer
= NULL
;
2478 tex
->surface
.dcc_offset
= 0;
2479 /* no need to flag anything since this is called after
2480 * decompression that re-sets framebuffer state
2485 static struct pipe_memory_object
*
2486 si_memobj_from_handle(struct pipe_screen
*screen
,
2487 struct winsys_handle
*whandle
,
2490 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2491 struct si_memory_object
*memobj
= CALLOC_STRUCT(si_memory_object
);
2492 struct pb_buffer
*buf
= NULL
;
2497 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2498 sscreen
->info
.max_alignment
);
2504 memobj
->b
.dedicated
= dedicated
;
2506 memobj
->stride
= whandle
->stride
;
2508 return (struct pipe_memory_object
*)memobj
;
2513 si_memobj_destroy(struct pipe_screen
*screen
,
2514 struct pipe_memory_object
*_memobj
)
2516 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2518 pb_reference(&memobj
->buf
, NULL
);
2522 static struct pipe_resource
*
2523 si_texture_from_memobj(struct pipe_screen
*screen
,
2524 const struct pipe_resource
*templ
,
2525 struct pipe_memory_object
*_memobj
,
2528 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2529 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2530 struct pipe_resource
*tex
=
2531 si_texture_from_winsys_buffer(sscreen
, templ
, memobj
->buf
,
2532 memobj
->stride
, offset
,
2533 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
|
2534 PIPE_HANDLE_USAGE_SHADER_WRITE
,
2535 memobj
->b
.dedicated
);
2539 /* si_texture_from_winsys_buffer doesn't increment refcount of
2540 * memobj->buf, so increment it here.
2542 struct pb_buffer
*buf
= NULL
;
2543 pb_reference(&buf
, memobj
->buf
);
2547 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2548 struct pipe_resource
*resource
,
2551 struct si_texture
*tex
= (struct si_texture
*)resource
;
2553 /* Buffers only support the linear flag. */
2554 if (resource
->target
== PIPE_BUFFER
)
2555 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2557 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2560 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2563 /* TODO: PIPE_BIND_CURSOR - do we care? */
2567 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2569 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2570 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2571 sscreen
->b
.resource_get_info
= si_texture_get_info
;
2572 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2573 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2574 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2575 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2578 void si_init_context_texture_functions(struct si_context
*sctx
)
2580 sctx
->b
.create_surface
= si_create_surface
;
2581 sctx
->b
.surface_destroy
= si_surface_destroy
;