2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "drm-uapi/drm_fourcc.h"
30 #include "state_tracker/drm_driver.h"
31 #include "util/format/u_format.h"
32 #include "util/os_time.h"
33 #include "util/u_log.h"
34 #include "util/u_memory.h"
35 #include "util/u_pack_color.h"
36 #include "util/u_resource.h"
37 #include "util/u_surface.h"
38 #include "util/u_transfer.h"
43 #include "amd/addrlib/inc/addrinterface.h"
45 static enum radeon_surf_mode
si_choose_tiling(struct si_screen
*sscreen
,
46 const struct pipe_resource
*templ
,
47 bool tc_compatible_htile
);
49 bool si_prepare_for_dma_blit(struct si_context
*sctx
, struct si_texture
*dst
, unsigned dst_level
,
50 unsigned dstx
, unsigned dsty
, unsigned dstz
, struct si_texture
*src
,
51 unsigned src_level
, const struct pipe_box
*src_box
)
56 if (dst
->surface
.bpe
!= src
->surface
.bpe
)
59 /* MSAA: Blits don't exist in the real world. */
60 if (src
->buffer
.b
.b
.nr_samples
> 1 || dst
->buffer
.b
.b
.nr_samples
> 1)
63 /* Depth-stencil surfaces:
64 * When dst is linear, the DB->CB copy preserves HTILE.
65 * When dst is tiled, the 3D path must be used to update HTILE.
67 if (src
->is_depth
|| dst
->is_depth
)
71 * src: Use the 3D path. DCC decompression is expensive.
72 * dst: Use the 3D path to compress the pixels with DCC.
74 if (vi_dcc_enabled(src
, src_level
) || vi_dcc_enabled(dst
, dst_level
))
78 * src: Both texture and SDMA paths need decompression. Use SDMA.
79 * dst: If overwriting the whole texture, discard CMASK and use
80 * SDMA. Otherwise, use the 3D path.
82 if (dst
->cmask_buffer
&& dst
->dirty_level_mask
& (1 << dst_level
)) {
83 /* The CMASK clear is only enabled for the first level. */
84 assert(dst_level
== 0);
85 if (!util_texrange_covers_whole_level(&dst
->buffer
.b
.b
, dst_level
, dstx
, dsty
, dstz
,
86 src_box
->width
, src_box
->height
, src_box
->depth
))
89 si_texture_discard_cmask(sctx
->screen
, dst
);
92 /* All requirements are met. Prepare textures for SDMA. */
93 if (src
->cmask_buffer
&& src
->dirty_level_mask
& (1 << src_level
))
94 sctx
->b
.flush_resource(&sctx
->b
, &src
->buffer
.b
.b
);
96 assert(!(src
->dirty_level_mask
& (1 << src_level
)));
97 assert(!(dst
->dirty_level_mask
& (1 << dst_level
)));
102 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
103 static void si_copy_region_with_blit(struct pipe_context
*pipe
, struct pipe_resource
*dst
,
104 unsigned dst_level
, unsigned dstx
, unsigned dsty
,
105 unsigned dstz
, struct pipe_resource
*src
, unsigned src_level
,
106 const struct pipe_box
*src_box
)
108 struct pipe_blit_info blit
;
110 memset(&blit
, 0, sizeof(blit
));
111 blit
.src
.resource
= src
;
112 blit
.src
.format
= src
->format
;
113 blit
.src
.level
= src_level
;
114 blit
.src
.box
= *src_box
;
115 blit
.dst
.resource
= dst
;
116 blit
.dst
.format
= dst
->format
;
117 blit
.dst
.level
= dst_level
;
118 blit
.dst
.box
.x
= dstx
;
119 blit
.dst
.box
.y
= dsty
;
120 blit
.dst
.box
.z
= dstz
;
121 blit
.dst
.box
.width
= src_box
->width
;
122 blit
.dst
.box
.height
= src_box
->height
;
123 blit
.dst
.box
.depth
= src_box
->depth
;
124 blit
.mask
= util_format_get_mask(dst
->format
);
125 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
128 pipe
->blit(pipe
, &blit
);
132 /* Copy from a full GPU texture to a transfer's staging one. */
133 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
135 struct si_context
*sctx
= (struct si_context
*)ctx
;
136 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
137 struct pipe_resource
*dst
= &stransfer
->staging
->b
.b
;
138 struct pipe_resource
*src
= transfer
->resource
;
140 if (src
->nr_samples
> 1 || ((struct si_texture
*)src
)->is_depth
) {
141 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
, &transfer
->box
);
145 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
, &transfer
->box
);
148 /* Copy from a transfer's staging texture to a full GPU one. */
149 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
151 struct si_context
*sctx
= (struct si_context
*)ctx
;
152 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
153 struct pipe_resource
*dst
= transfer
->resource
;
154 struct pipe_resource
*src
= &stransfer
->staging
->b
.b
;
155 struct pipe_box sbox
;
157 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
159 if (dst
->nr_samples
> 1 || ((struct si_texture
*)dst
)->is_depth
) {
160 si_copy_region_with_blit(ctx
, dst
, transfer
->level
, transfer
->box
.x
, transfer
->box
.y
,
161 transfer
->box
.z
, src
, 0, &sbox
);
165 if (util_format_is_compressed(dst
->format
)) {
166 sbox
.width
= util_format_get_nblocksx(dst
->format
, sbox
.width
);
167 sbox
.height
= util_format_get_nblocksx(dst
->format
, sbox
.height
);
170 sctx
->dma_copy(ctx
, dst
, transfer
->level
, transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
, src
,
174 static unsigned si_texture_get_offset(struct si_screen
*sscreen
, struct si_texture
*tex
,
175 unsigned level
, const struct pipe_box
*box
, unsigned *stride
,
176 unsigned *layer_stride
)
178 if (sscreen
->info
.chip_class
>= GFX9
) {
179 *stride
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
180 *layer_stride
= tex
->surface
.u
.gfx9
.surf_slice_size
;
185 /* Each texture is an array of slices. Each slice is an array
186 * of mipmap levels. */
187 return tex
->surface
.u
.gfx9
.surf_offset
+ box
->z
* tex
->surface
.u
.gfx9
.surf_slice_size
+
188 tex
->surface
.u
.gfx9
.offset
[level
] +
189 (box
->y
/ tex
->surface
.blk_h
* tex
->surface
.u
.gfx9
.surf_pitch
+
190 box
->x
/ tex
->surface
.blk_w
) *
193 *stride
= tex
->surface
.u
.legacy
.level
[level
].nblk_x
* tex
->surface
.bpe
;
194 assert((uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
195 *layer_stride
= (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
198 return tex
->surface
.u
.legacy
.level
[level
].offset
;
200 /* Each texture is an array of mipmap levels. Each level is
201 * an array of slices. */
202 return tex
->surface
.u
.legacy
.level
[level
].offset
+
203 box
->z
* (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
204 (box
->y
/ tex
->surface
.blk_h
* tex
->surface
.u
.legacy
.level
[level
].nblk_x
+
205 box
->x
/ tex
->surface
.blk_w
) *
210 static int si_init_surface(struct si_screen
*sscreen
, struct radeon_surf
*surface
,
211 const struct pipe_resource
*ptex
, enum radeon_surf_mode array_mode
,
212 unsigned pitch_in_bytes_override
, bool is_imported
, bool is_scanout
,
213 bool is_flushed_depth
, bool tc_compatible_htile
)
215 const struct util_format_description
*desc
= util_format_description(ptex
->format
);
216 bool is_depth
, is_stencil
;
218 unsigned bpe
, flags
= 0;
220 is_depth
= util_format_has_depth(desc
);
221 is_stencil
= util_format_has_stencil(desc
);
223 if (!is_flushed_depth
&& ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
224 bpe
= 4; /* stencil is allocated separately */
226 bpe
= util_format_get_blocksize(ptex
->format
);
227 assert(util_is_power_of_two_or_zero(bpe
));
230 if (!is_flushed_depth
&& is_depth
) {
231 flags
|= RADEON_SURF_ZBUFFER
;
233 if (sscreen
->debug_flags
& DBG(NO_HYPERZ
)) {
234 flags
|= RADEON_SURF_NO_HTILE
;
235 } else if (tc_compatible_htile
&&
236 (sscreen
->info
.chip_class
>= GFX9
|| array_mode
== RADEON_SURF_MODE_2D
)) {
237 /* TC-compatible HTILE only supports Z32_FLOAT.
238 * GFX9 also supports Z16_UNORM.
239 * On GFX8, promote Z16 to Z32. DB->CB copies will convert
240 * the format for transfers.
242 if (sscreen
->info
.chip_class
== GFX8
)
245 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
249 flags
|= RADEON_SURF_SBUFFER
;
252 if (sscreen
->info
.chip_class
>= GFX8
&&
253 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
|| ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
254 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
255 flags
|= RADEON_SURF_DISABLE_DCC
;
257 /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */
258 if (sscreen
->info
.family
== CHIP_STONEY
&& bpe
== 16 && ptex
->nr_samples
>= 2)
259 flags
|= RADEON_SURF_DISABLE_DCC
;
261 /* GFX8: DCC clear for 4x and 8x MSAA array textures unimplemented. */
262 if (sscreen
->info
.chip_class
== GFX8
&& ptex
->nr_storage_samples
>= 4 && ptex
->array_size
> 1)
263 flags
|= RADEON_SURF_DISABLE_DCC
;
265 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
266 if (sscreen
->info
.chip_class
== GFX9
&&
267 (ptex
->nr_storage_samples
>= 4 ||
268 (sscreen
->info
.family
== CHIP_RAVEN
&& ptex
->nr_storage_samples
>= 2 && bpe
< 4)))
269 flags
|= RADEON_SURF_DISABLE_DCC
;
271 /* TODO: GFX10: DCC causes corruption with MSAA. */
272 if (sscreen
->info
.chip_class
>= GFX10
&& ptex
->nr_storage_samples
>= 2)
273 flags
|= RADEON_SURF_DISABLE_DCC
;
275 /* Shared textures must always set up DCC.
276 * If it's not present, it will be disabled by
277 * si_get_opaque_metadata later.
279 if (!is_imported
&& (sscreen
->debug_flags
& DBG(NO_DCC
)))
280 flags
|= RADEON_SURF_DISABLE_DCC
;
283 /* This should catch bugs in gallium users setting incorrect flags. */
284 assert(ptex
->nr_samples
<= 1 && ptex
->array_size
== 1 && ptex
->depth0
== 1 &&
285 ptex
->last_level
== 0 && !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
287 flags
|= RADEON_SURF_SCANOUT
;
290 if (ptex
->bind
& PIPE_BIND_SHARED
)
291 flags
|= RADEON_SURF_SHAREABLE
;
293 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
294 if (!(ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
))
295 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
296 if (sscreen
->debug_flags
& DBG(NO_FMASK
))
297 flags
|= RADEON_SURF_NO_FMASK
;
299 if (sscreen
->info
.chip_class
== GFX9
&& (ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE
)) {
300 flags
|= RADEON_SURF_FORCE_MICRO_TILE_MODE
;
301 surface
->micro_tile_mode
= SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(ptex
->flags
);
304 if (sscreen
->info
.chip_class
>= GFX10
&& (ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
)) {
305 flags
|= RADEON_SURF_FORCE_SWIZZLE_MODE
;
306 surface
->u
.gfx9
.surf
.swizzle_mode
= ADDR_SW_64KB_R_X
;
309 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
, array_mode
, surface
);
314 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
316 if (sscreen
->info
.chip_class
>= GFX9
) {
318 surface
->u
.gfx9
.surf_pitch
= pitch
;
319 if (ptex
->last_level
== 0)
320 surface
->u
.gfx9
.surf
.epitch
= pitch
- 1;
321 surface
->u
.gfx9
.surf_slice_size
= (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
325 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
326 surface
->u
.legacy
.level
[0].slice_size_dw
=
327 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
333 static void si_get_display_metadata(struct si_screen
*sscreen
, struct radeon_surf
*surf
,
334 struct radeon_bo_metadata
*metadata
,
335 enum radeon_surf_mode
*array_mode
, bool *is_scanout
)
337 if (sscreen
->info
.chip_class
>= GFX9
) {
338 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
339 *array_mode
= RADEON_SURF_MODE_2D
;
341 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
343 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
344 *is_scanout
= metadata
->u
.gfx9
.scanout
;
346 if (metadata
->u
.gfx9
.dcc_offset_256B
) {
347 surf
->u
.gfx9
.display_dcc_pitch_max
= metadata
->u
.gfx9
.dcc_pitch_max
;
348 assert(metadata
->u
.gfx9
.dcc_independent_64B
== 1);
351 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
352 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
353 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
354 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
355 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
356 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
358 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
359 *array_mode
= RADEON_SURF_MODE_2D
;
360 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
361 *array_mode
= RADEON_SURF_MODE_1D
;
363 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
365 *is_scanout
= metadata
->u
.legacy
.scanout
;
369 void si_eliminate_fast_color_clear(struct si_context
*sctx
, struct si_texture
*tex
)
371 struct si_screen
*sscreen
= sctx
->screen
;
372 struct pipe_context
*ctx
= &sctx
->b
;
374 if (ctx
== sscreen
->aux_context
)
375 simple_mtx_lock(&sscreen
->aux_context_lock
);
377 unsigned n
= sctx
->num_decompress_calls
;
378 ctx
->flush_resource(ctx
, &tex
->buffer
.b
.b
);
380 /* Flush only if any fast clear elimination took place. */
381 if (n
!= sctx
->num_decompress_calls
)
382 ctx
->flush(ctx
, NULL
, 0);
384 if (ctx
== sscreen
->aux_context
)
385 simple_mtx_unlock(&sscreen
->aux_context_lock
);
388 void si_texture_discard_cmask(struct si_screen
*sscreen
, struct si_texture
*tex
)
390 if (!tex
->cmask_buffer
)
393 assert(tex
->buffer
.b
.b
.nr_samples
<= 1);
396 tex
->cmask_base_address_reg
= tex
->buffer
.gpu_address
>> 8;
397 tex
->dirty_level_mask
= 0;
399 tex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
401 if (tex
->cmask_buffer
!= &tex
->buffer
)
402 si_resource_reference(&tex
->cmask_buffer
, NULL
);
404 tex
->cmask_buffer
= NULL
;
406 /* Notify all contexts about the change. */
407 p_atomic_inc(&sscreen
->dirty_tex_counter
);
408 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
411 static bool si_can_disable_dcc(struct si_texture
*tex
)
413 /* We can't disable DCC if it can be written by another process. */
414 return tex
->surface
.dcc_offset
&&
415 (!tex
->buffer
.b
.is_shared
||
416 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
));
419 static void si_texture_zero_dcc_fields(struct si_texture
*tex
)
421 tex
->surface
.dcc_offset
= 0;
422 tex
->surface
.display_dcc_offset
= 0;
423 tex
->surface
.dcc_retile_map_offset
= 0;
426 static bool si_texture_discard_dcc(struct si_screen
*sscreen
, struct si_texture
*tex
)
428 if (!si_can_disable_dcc(tex
))
431 assert(tex
->dcc_separate_buffer
== NULL
);
434 si_texture_zero_dcc_fields(tex
);
436 /* Notify all contexts about the change. */
437 p_atomic_inc(&sscreen
->dirty_tex_counter
);
442 * Disable DCC for the texture. (first decompress, then discard metadata).
444 * There is unresolved multi-context synchronization issue between
445 * screen::aux_context and the current context. If applications do this with
446 * multiple contexts, it's already undefined behavior for them and we don't
447 * have to worry about that. The scenario is:
449 * If context 1 disables DCC and context 2 has queued commands that write
450 * to the texture via CB with DCC enabled, and the order of operations is
452 * context 2 queues draw calls rendering to the texture, but doesn't flush
453 * context 1 disables DCC and flushes
454 * context 1 & 2 reset descriptors and FB state
455 * context 2 flushes (new compressed tiles written by the draw calls)
456 * context 1 & 2 read garbage, because DCC is disabled, yet there are
459 * \param sctx the current context if you have one, or sscreen->aux_context
462 bool si_texture_disable_dcc(struct si_context
*sctx
, struct si_texture
*tex
)
464 struct si_screen
*sscreen
= sctx
->screen
;
466 if (!sctx
->has_graphics
)
467 return si_texture_discard_dcc(sscreen
, tex
);
469 if (!si_can_disable_dcc(tex
))
472 if (&sctx
->b
== sscreen
->aux_context
)
473 simple_mtx_lock(&sscreen
->aux_context_lock
);
475 /* Decompress DCC. */
476 si_decompress_dcc(sctx
, tex
);
477 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
479 if (&sctx
->b
== sscreen
->aux_context
)
480 simple_mtx_unlock(&sscreen
->aux_context_lock
);
482 return si_texture_discard_dcc(sscreen
, tex
);
485 static void si_reallocate_texture_inplace(struct si_context
*sctx
, struct si_texture
*tex
,
486 unsigned new_bind_flag
, bool invalidate_storage
)
488 struct pipe_screen
*screen
= sctx
->b
.screen
;
489 struct si_texture
*new_tex
;
490 struct pipe_resource templ
= tex
->buffer
.b
.b
;
493 templ
.bind
|= new_bind_flag
;
495 if (tex
->buffer
.b
.is_shared
|| tex
->num_planes
> 1)
498 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
499 if (tex
->surface
.is_linear
)
502 /* This fails with MSAA, depth, and compressed textures. */
503 if (si_choose_tiling(sctx
->screen
, &templ
, false) != RADEON_SURF_MODE_LINEAR_ALIGNED
)
507 new_tex
= (struct si_texture
*)screen
->resource_create(screen
, &templ
);
511 /* Copy the pixels to the new texture. */
512 if (!invalidate_storage
) {
513 for (i
= 0; i
<= templ
.last_level
; i
++) {
516 u_box_3d(0, 0, 0, u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
517 util_num_layers(&templ
, i
), &box
);
519 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0, &tex
->buffer
.b
.b
, i
, &box
);
523 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
524 si_texture_discard_cmask(sctx
->screen
, tex
);
525 si_texture_discard_dcc(sctx
->screen
, tex
);
528 /* Replace the structure fields of tex. */
529 tex
->buffer
.b
.b
.bind
= templ
.bind
;
530 pb_reference(&tex
->buffer
.buf
, new_tex
->buffer
.buf
);
531 tex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
532 tex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
533 tex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
534 tex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
535 tex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
536 tex
->buffer
.domains
= new_tex
->buffer
.domains
;
537 tex
->buffer
.flags
= new_tex
->buffer
.flags
;
539 tex
->surface
= new_tex
->surface
;
540 si_texture_reference(&tex
->flushed_depth_texture
, new_tex
->flushed_depth_texture
);
542 tex
->surface
.fmask_offset
= new_tex
->surface
.fmask_offset
;
543 tex
->surface
.cmask_offset
= new_tex
->surface
.cmask_offset
;
544 tex
->cmask_base_address_reg
= new_tex
->cmask_base_address_reg
;
546 if (tex
->cmask_buffer
== &tex
->buffer
)
547 tex
->cmask_buffer
= NULL
;
549 si_resource_reference(&tex
->cmask_buffer
, NULL
);
551 if (new_tex
->cmask_buffer
== &new_tex
->buffer
)
552 tex
->cmask_buffer
= &tex
->buffer
;
554 si_resource_reference(&tex
->cmask_buffer
, new_tex
->cmask_buffer
);
556 tex
->surface
.dcc_offset
= new_tex
->surface
.dcc_offset
;
557 tex
->cb_color_info
= new_tex
->cb_color_info
;
558 memcpy(tex
->color_clear_value
, new_tex
->color_clear_value
, sizeof(tex
->color_clear_value
));
559 tex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
561 tex
->surface
.htile_offset
= new_tex
->surface
.htile_offset
;
562 tex
->depth_clear_value
= new_tex
->depth_clear_value
;
563 tex
->dirty_level_mask
= new_tex
->dirty_level_mask
;
564 tex
->stencil_dirty_level_mask
= new_tex
->stencil_dirty_level_mask
;
565 tex
->db_render_format
= new_tex
->db_render_format
;
566 tex
->stencil_clear_value
= new_tex
->stencil_clear_value
;
567 tex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
568 tex
->depth_cleared
= new_tex
->depth_cleared
;
569 tex
->stencil_cleared
= new_tex
->stencil_cleared
;
570 tex
->upgraded_depth
= new_tex
->upgraded_depth
;
571 tex
->db_compatible
= new_tex
->db_compatible
;
572 tex
->can_sample_z
= new_tex
->can_sample_z
;
573 tex
->can_sample_s
= new_tex
->can_sample_s
;
575 tex
->separate_dcc_dirty
= new_tex
->separate_dcc_dirty
;
576 tex
->displayable_dcc_dirty
= new_tex
->displayable_dcc_dirty
;
577 tex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
578 si_resource_reference(&tex
->dcc_separate_buffer
, new_tex
->dcc_separate_buffer
);
579 si_resource_reference(&tex
->last_dcc_separate_buffer
, new_tex
->last_dcc_separate_buffer
);
581 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
582 assert(!tex
->surface
.htile_offset
);
583 assert(!tex
->cmask_buffer
);
584 assert(!tex
->surface
.fmask_size
);
585 assert(!tex
->surface
.dcc_offset
);
586 assert(!tex
->is_depth
);
589 si_texture_reference(&new_tex
, NULL
);
591 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
594 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
596 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
599 static void si_set_tex_bo_metadata(struct si_screen
*sscreen
, struct si_texture
*tex
)
601 struct radeon_surf
*surface
= &tex
->surface
;
602 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
603 struct radeon_bo_metadata md
;
605 memset(&md
, 0, sizeof(md
));
607 if (sscreen
->info
.chip_class
>= GFX9
) {
608 md
.u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
609 md
.u
.gfx9
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
611 if (tex
->surface
.dcc_offset
&& !tex
->dcc_separate_buffer
) {
612 uint64_t dcc_offset
= tex
->surface
.display_dcc_offset
? tex
->surface
.display_dcc_offset
613 : tex
->surface
.dcc_offset
;
615 assert((dcc_offset
>> 8) != 0 && (dcc_offset
>> 8) < (1 << 24));
616 md
.u
.gfx9
.dcc_offset_256B
= dcc_offset
>> 8;
617 md
.u
.gfx9
.dcc_pitch_max
= tex
->surface
.u
.gfx9
.display_dcc_pitch_max
;
618 md
.u
.gfx9
.dcc_independent_64B
= 1;
621 md
.u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
622 ? RADEON_LAYOUT_TILED
623 : RADEON_LAYOUT_LINEAR
;
624 md
.u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
625 ? RADEON_LAYOUT_TILED
626 : RADEON_LAYOUT_LINEAR
;
627 md
.u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
628 md
.u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
629 md
.u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
630 md
.u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
631 md
.u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
632 md
.u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
633 md
.u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
634 md
.u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
637 assert(tex
->dcc_separate_buffer
== NULL
);
638 assert(tex
->surface
.fmask_size
== 0);
640 /* Metadata image format format version 1:
641 * [0] = 1 (metadata format identifier)
642 * [1] = (VENDOR_ID << 16) | PCI_ID
643 * [2:9] = image descriptor for the whole resource
644 * [2] is always 0, because the base address is cleared
645 * [9] is the DCC offset bits [39:8] from the beginning of
647 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
650 md
.metadata
[0] = 1; /* metadata image format version 1 */
652 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
653 md
.metadata
[1] = si_get_bo_metadata_word1(sscreen
);
655 static const unsigned char swizzle
[] = {PIPE_SWIZZLE_X
, PIPE_SWIZZLE_Y
, PIPE_SWIZZLE_Z
,
657 bool is_array
= util_texture_is_array(res
->target
);
660 sscreen
->make_texture_descriptor(sscreen
, tex
, true, res
->target
, res
->format
, swizzle
, 0,
661 res
->last_level
, 0, is_array
? res
->array_size
- 1 : 0,
662 res
->width0
, res
->height0
, res
->depth0
, desc
, NULL
);
664 si_set_mutable_tex_desc_fields(sscreen
, tex
, &tex
->surface
.u
.legacy
.level
[0], 0, 0,
665 tex
->surface
.blk_w
, false, desc
);
667 /* Clear the base address and set the relative DCC offset. */
669 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
671 switch (sscreen
->info
.chip_class
) {
676 desc
[7] = tex
->surface
.dcc_offset
>> 8;
679 desc
[7] = tex
->surface
.dcc_offset
>> 8;
680 desc
[5] &= C_008F24_META_DATA_ADDRESS
;
681 desc
[5] |= S_008F24_META_DATA_ADDRESS(tex
->surface
.dcc_offset
>> 40);
684 desc
[6] &= C_00A018_META_DATA_ADDRESS_LO
;
685 desc
[6] |= S_00A018_META_DATA_ADDRESS_LO(tex
->surface
.dcc_offset
>> 8);
686 desc
[7] = tex
->surface
.dcc_offset
>> 16;
692 /* Dwords [2:9] contain the image descriptor. */
693 memcpy(&md
.metadata
[2], desc
, sizeof(desc
));
694 md
.size_metadata
= 10 * 4;
696 /* Dwords [10:..] contain the mipmap level offsets. */
697 if (sscreen
->info
.chip_class
<= GFX8
) {
698 for (unsigned i
= 0; i
<= res
->last_level
; i
++)
699 md
.metadata
[10 + i
] = tex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
701 md
.size_metadata
+= (1 + res
->last_level
) * 4;
704 sscreen
->ws
->buffer_set_metadata(tex
->buffer
.buf
, &md
);
707 static bool si_read_tex_bo_metadata(struct si_screen
*sscreen
, struct si_texture
*tex
,
708 uint64_t offset
, struct radeon_bo_metadata
*md
)
710 uint32_t *desc
= &md
->metadata
[2];
712 if (offset
|| /* Non-zero planes ignore metadata. */
713 md
->size_metadata
< 10 * 4 || /* at least 2(header) + 8(desc) dwords */
714 md
->metadata
[0] == 0 || /* invalid version number */
715 md
->metadata
[1] != si_get_bo_metadata_word1(sscreen
)) /* invalid PCI ID */ {
716 /* Disable DCC because it might not be enabled. */
717 si_texture_zero_dcc_fields(tex
);
719 /* Don't report an error if the texture comes from an incompatible driver,
720 * but this might not work.
725 /* Validate that sample counts and the number of mipmap levels match. */
726 unsigned last_level
= G_008F1C_LAST_LEVEL(desc
[3]);
727 unsigned type
= G_008F1C_TYPE(desc
[3]);
729 if (type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA
|| type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
730 unsigned log_samples
= util_logbase2(MAX2(1, tex
->buffer
.b
.b
.nr_storage_samples
));
732 if (last_level
!= log_samples
) {
734 "radeonsi: invalid MSAA texture import, "
735 "metadata has log2(samples) = %u, the caller set %u\n",
736 last_level
, log_samples
);
740 if (last_level
!= tex
->buffer
.b
.b
.last_level
) {
742 "radeonsi: invalid mipmapped texture import, "
743 "metadata has last_level = %u, the caller set %u\n",
744 last_level
, tex
->buffer
.b
.b
.last_level
);
749 if (sscreen
->info
.chip_class
>= GFX8
&& G_008F28_COMPRESSION_EN(desc
[6])) {
750 /* Read DCC information. */
751 switch (sscreen
->info
.chip_class
) {
753 tex
->surface
.dcc_offset
= (uint64_t)desc
[7] << 8;
757 tex
->surface
.dcc_offset
=
758 ((uint64_t)desc
[7] << 8) | ((uint64_t)G_008F24_META_DATA_ADDRESS(desc
[5]) << 40);
759 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
= G_008F24_META_PIPE_ALIGNED(desc
[5]);
760 tex
->surface
.u
.gfx9
.dcc
.rb_aligned
= G_008F24_META_RB_ALIGNED(desc
[5]);
762 /* If DCC is unaligned, this can only be a displayable image. */
763 if (!tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&& !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
764 assert(tex
->surface
.is_displayable
);
768 tex
->surface
.dcc_offset
=
769 ((uint64_t)G_00A018_META_DATA_ADDRESS_LO(desc
[6]) << 8) | ((uint64_t)desc
[7] << 16);
770 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
= G_00A018_META_PIPE_ALIGNED(desc
[6]);
778 /* Disable DCC. dcc_offset is always set by texture_from_handle
779 * and must be cleared here.
781 si_texture_zero_dcc_fields(tex
);
787 static bool si_has_displayable_dcc(struct si_texture
*tex
)
789 struct si_screen
*sscreen
= (struct si_screen
*)tex
->buffer
.b
.b
.screen
;
791 if (sscreen
->info
.chip_class
<= GFX8
)
794 /* This needs a cache flush before scanout.
795 * (it can't be scanned out and rendered to simultaneously)
797 if (sscreen
->info
.use_display_dcc_unaligned
&& tex
->surface
.dcc_offset
&&
798 !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&& !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
801 /* This needs an explicit flush (flush_resource). */
802 if (sscreen
->info
.use_display_dcc_with_retile_blit
&& tex
->surface
.display_dcc_offset
)
808 static bool si_resource_get_param(struct pipe_screen
*screen
, struct pipe_context
*context
,
809 struct pipe_resource
*resource
, unsigned plane
, unsigned layer
,
810 enum pipe_resource_param param
, unsigned handle_usage
,
813 for (unsigned i
= 0; i
< plane
; i
++)
814 resource
= resource
->next
;
816 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
817 struct si_texture
*tex
= (struct si_texture
*)resource
;
818 struct winsys_handle whandle
;
821 case PIPE_RESOURCE_PARAM_NPLANES
:
822 *value
= resource
->target
== PIPE_BUFFER
? 1 : tex
->num_planes
;
825 case PIPE_RESOURCE_PARAM_STRIDE
:
826 if (resource
->target
== PIPE_BUFFER
)
828 else if (sscreen
->info
.chip_class
>= GFX9
)
829 *value
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
831 *value
= tex
->surface
.u
.legacy
.level
[0].nblk_x
* tex
->surface
.bpe
;
834 case PIPE_RESOURCE_PARAM_OFFSET
:
835 if (resource
->target
== PIPE_BUFFER
)
837 else if (sscreen
->info
.chip_class
>= GFX9
)
838 *value
= tex
->surface
.u
.gfx9
.surf_offset
+ layer
* tex
->surface
.u
.gfx9
.surf_slice_size
;
840 *value
= tex
->surface
.u
.legacy
.level
[0].offset
+
841 layer
* (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
844 case PIPE_RESOURCE_PARAM_MODIFIER
:
845 *value
= DRM_FORMAT_MOD_INVALID
;
848 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
849 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
:
850 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
851 memset(&whandle
, 0, sizeof(whandle
));
853 if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
)
854 whandle
.type
= WINSYS_HANDLE_TYPE_SHARED
;
855 else if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
)
856 whandle
.type
= WINSYS_HANDLE_TYPE_KMS
;
857 else if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
)
858 whandle
.type
= WINSYS_HANDLE_TYPE_FD
;
860 if (!screen
->resource_get_handle(screen
, context
, resource
, &whandle
, handle_usage
))
863 *value
= whandle
.handle
;
869 static void si_texture_get_info(struct pipe_screen
*screen
, struct pipe_resource
*resource
,
870 unsigned *pstride
, unsigned *poffset
)
875 si_resource_get_param(screen
, NULL
, resource
, 0, 0, PIPE_RESOURCE_PARAM_STRIDE
, 0, &value
);
880 si_resource_get_param(screen
, NULL
, resource
, 0, 0, PIPE_RESOURCE_PARAM_OFFSET
, 0, &value
);
885 static bool si_texture_get_handle(struct pipe_screen
*screen
, struct pipe_context
*ctx
,
886 struct pipe_resource
*resource
, struct winsys_handle
*whandle
,
889 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
890 struct si_context
*sctx
;
891 struct si_resource
*res
= si_resource(resource
);
892 struct si_texture
*tex
= (struct si_texture
*)resource
;
893 bool update_metadata
= false;
894 unsigned stride
, offset
, slice_size
;
897 ctx
= threaded_context_unwrap_sync(ctx
);
898 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
900 if (resource
->target
!= PIPE_BUFFER
) {
901 /* Individual planes are chained pipe_resource instances. */
902 for (unsigned i
= 0; i
< whandle
->plane
; i
++) {
903 resource
= resource
->next
;
904 res
= si_resource(resource
);
905 tex
= (struct si_texture
*)resource
;
908 /* This is not supported now, but it might be required for OpenCL
909 * interop in the future.
911 if (resource
->nr_samples
> 1 || tex
->is_depth
)
914 /* Move a suballocated texture into a non-suballocated allocation. */
915 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) || tex
->surface
.tile_swizzle
||
916 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
917 sscreen
->info
.has_local_buffers
)) {
918 assert(!res
->b
.is_shared
);
919 si_reallocate_texture_inplace(sctx
, tex
, PIPE_BIND_SHARED
, false);
921 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
922 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
923 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
924 assert(tex
->surface
.tile_swizzle
== 0);
927 /* Since shader image stores don't support DCC on GFX8,
928 * disable it for external clients that want write
931 if ((usage
& PIPE_HANDLE_USAGE_SHADER_WRITE
&& tex
->surface
.dcc_offset
) ||
932 /* Displayable DCC requires an explicit flush. */
933 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && si_has_displayable_dcc(tex
))) {
934 if (si_texture_disable_dcc(sctx
, tex
)) {
935 update_metadata
= true;
936 /* si_texture_disable_dcc flushes the context */
941 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
942 (tex
->cmask_buffer
|| tex
->surface
.dcc_offset
)) {
943 /* Eliminate fast clear (both CMASK and DCC) */
944 si_eliminate_fast_color_clear(sctx
, tex
);
945 /* eliminate_fast_color_clear flushes the context */
948 /* Disable CMASK if flush_resource isn't going
951 if (tex
->cmask_buffer
)
952 si_texture_discard_cmask(sscreen
, tex
);
956 if ((!res
->b
.is_shared
|| update_metadata
) && whandle
->offset
== 0)
957 si_set_tex_bo_metadata(sscreen
, tex
);
959 if (sscreen
->info
.chip_class
>= GFX9
) {
960 slice_size
= tex
->surface
.u
.gfx9
.surf_slice_size
;
962 slice_size
= (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
965 /* Buffer exports are for the OpenCL interop. */
966 /* Move a suballocated buffer into a non-suballocated allocation. */
967 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
968 /* A DMABUF export always fails if the BO is local. */
969 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
970 sscreen
->info
.has_local_buffers
)) {
971 assert(!res
->b
.is_shared
);
973 /* Allocate a new buffer with PIPE_BIND_SHARED. */
974 struct pipe_resource templ
= res
->b
.b
;
975 templ
.bind
|= PIPE_BIND_SHARED
;
977 struct pipe_resource
*newb
= screen
->resource_create(screen
, &templ
);
981 /* Copy the old buffer contents to the new one. */
983 u_box_1d(0, newb
->width0
, &box
);
984 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0, &res
->b
.b
, 0, &box
);
986 /* Move the new buffer storage to the old pipe_resource. */
987 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
988 pipe_resource_reference(&newb
, NULL
);
990 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
991 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
998 si_texture_get_info(screen
, resource
, &stride
, &offset
);
1001 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
1003 if (res
->b
.is_shared
) {
1004 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
1007 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
1008 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
1009 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
1011 res
->b
.is_shared
= true;
1012 res
->external_usage
= usage
;
1015 whandle
->stride
= stride
;
1016 whandle
->offset
= offset
+ slice_size
* whandle
->layer
;
1018 return sscreen
->ws
->buffer_get_handle(sscreen
->ws
, res
->buf
, whandle
);
1021 static void si_texture_destroy(struct pipe_screen
*screen
, struct pipe_resource
*ptex
)
1023 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1024 struct si_texture
*tex
= (struct si_texture
*)ptex
;
1025 struct si_resource
*resource
= &tex
->buffer
;
1027 if (sscreen
->info
.chip_class
>= GFX9
)
1028 free(tex
->surface
.u
.gfx9
.dcc_retile_map
);
1030 si_texture_reference(&tex
->flushed_depth_texture
, NULL
);
1032 if (tex
->cmask_buffer
!= &tex
->buffer
) {
1033 si_resource_reference(&tex
->cmask_buffer
, NULL
);
1035 pb_reference(&resource
->buf
, NULL
);
1036 si_resource_reference(&tex
->dcc_separate_buffer
, NULL
);
1037 si_resource_reference(&tex
->last_dcc_separate_buffer
, NULL
);
1041 static const struct u_resource_vtbl si_texture_vtbl
;
1043 void si_print_texture_info(struct si_screen
*sscreen
, struct si_texture
*tex
,
1044 struct u_log_context
*log
)
1048 /* Common parameters. */
1050 " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1051 "blk_h=%u, array_size=%u, last_level=%u, "
1052 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1053 tex
->buffer
.b
.b
.width0
, tex
->buffer
.b
.b
.height0
, tex
->buffer
.b
.b
.depth0
,
1054 tex
->surface
.blk_w
, tex
->surface
.blk_h
, tex
->buffer
.b
.b
.array_size
,
1055 tex
->buffer
.b
.b
.last_level
, tex
->surface
.bpe
, tex
->buffer
.b
.b
.nr_samples
,
1056 tex
->surface
.flags
, util_format_short_name(tex
->buffer
.b
.b
.format
));
1058 if (sscreen
->info
.chip_class
>= GFX9
) {
1060 " Surf: size=%" PRIu64
", slice_size=%" PRIu64
", "
1061 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1062 tex
->surface
.surf_size
, tex
->surface
.u
.gfx9
.surf_slice_size
,
1063 tex
->surface
.surf_alignment
, tex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1064 tex
->surface
.u
.gfx9
.surf
.epitch
, tex
->surface
.u
.gfx9
.surf_pitch
);
1066 if (tex
->surface
.fmask_offset
) {
1068 " FMASK: offset=%" PRIu64
", size=%" PRIu64
", "
1069 "alignment=%u, swmode=%u, epitch=%u\n",
1070 tex
->surface
.fmask_offset
, tex
->surface
.fmask_size
,
1071 tex
->surface
.fmask_alignment
, tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1072 tex
->surface
.u
.gfx9
.fmask
.epitch
);
1075 if (tex
->cmask_buffer
) {
1077 " CMask: offset=%" PRIu64
", size=%u, "
1078 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1079 tex
->surface
.cmask_offset
, tex
->surface
.cmask_size
,
1080 tex
->surface
.cmask_alignment
, tex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1081 tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1084 if (tex
->surface
.htile_offset
) {
1086 " HTile: offset=%" PRIu64
", size=%u, alignment=%u, "
1087 "rb_aligned=%u, pipe_aligned=%u\n",
1088 tex
->surface
.htile_offset
, tex
->surface
.htile_size
,
1089 tex
->surface
.htile_alignment
, tex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1090 tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1093 if (tex
->surface
.dcc_offset
) {
1095 " DCC: offset=%" PRIu64
", size=%u, "
1096 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1097 tex
->surface
.dcc_offset
, tex
->surface
.dcc_size
, tex
->surface
.dcc_alignment
,
1098 tex
->surface
.u
.gfx9
.display_dcc_pitch_max
, tex
->surface
.num_dcc_levels
);
1101 if (tex
->surface
.u
.gfx9
.stencil_offset
) {
1102 u_log_printf(log
, " Stencil: offset=%" PRIu64
", swmode=%u, epitch=%u\n",
1103 tex
->surface
.u
.gfx9
.stencil_offset
, tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1104 tex
->surface
.u
.gfx9
.stencil
.epitch
);
1110 " Layout: size=%" PRIu64
", alignment=%u, bankw=%u, "
1111 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1112 tex
->surface
.surf_size
, tex
->surface
.surf_alignment
, tex
->surface
.u
.legacy
.bankw
,
1113 tex
->surface
.u
.legacy
.bankh
, tex
->surface
.u
.legacy
.num_banks
,
1114 tex
->surface
.u
.legacy
.mtilea
, tex
->surface
.u
.legacy
.tile_split
,
1115 tex
->surface
.u
.legacy
.pipe_config
, (tex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1117 if (tex
->surface
.fmask_offset
)
1120 " FMask: offset=%" PRIu64
", size=%" PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1121 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1122 tex
->surface
.fmask_offset
, tex
->surface
.fmask_size
, tex
->surface
.fmask_alignment
,
1123 tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
, tex
->surface
.u
.legacy
.fmask
.bankh
,
1124 tex
->surface
.u
.legacy
.fmask
.slice_tile_max
, tex
->surface
.u
.legacy
.fmask
.tiling_index
);
1126 if (tex
->cmask_buffer
)
1128 " CMask: offset=%" PRIu64
", size=%u, alignment=%u, "
1129 "slice_tile_max=%u\n",
1130 tex
->surface
.cmask_offset
, tex
->surface
.cmask_size
, tex
->surface
.cmask_alignment
,
1131 tex
->surface
.u
.legacy
.cmask_slice_tile_max
);
1133 if (tex
->surface
.htile_offset
)
1135 " HTile: offset=%" PRIu64
", size=%u, "
1136 "alignment=%u, TC_compatible = %u\n",
1137 tex
->surface
.htile_offset
, tex
->surface
.htile_size
, tex
->surface
.htile_alignment
,
1138 tex
->tc_compatible_htile
);
1140 if (tex
->surface
.dcc_offset
) {
1141 u_log_printf(log
, " DCC: offset=%" PRIu64
", size=%u, alignment=%u\n",
1142 tex
->surface
.dcc_offset
, tex
->surface
.dcc_size
, tex
->surface
.dcc_alignment
);
1143 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1145 " DCCLevel[%i]: enabled=%u, offset=%u, "
1146 "fast_clear_size=%u\n",
1147 i
, i
< tex
->surface
.num_dcc_levels
, tex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1148 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1151 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1153 " Level[%i]: offset=%" PRIu64
", slice_size=%" PRIu64
", "
1154 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1155 "mode=%u, tiling_index = %u\n",
1156 i
, tex
->surface
.u
.legacy
.level
[i
].offset
,
1157 (uint64_t)tex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1158 u_minify(tex
->buffer
.b
.b
.width0
, i
), u_minify(tex
->buffer
.b
.b
.height0
, i
),
1159 u_minify(tex
->buffer
.b
.b
.depth0
, i
), tex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1160 tex
->surface
.u
.legacy
.level
[i
].nblk_y
, tex
->surface
.u
.legacy
.level
[i
].mode
,
1161 tex
->surface
.u
.legacy
.tiling_index
[i
]);
1163 if (tex
->surface
.has_stencil
) {
1164 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1165 tex
->surface
.u
.legacy
.stencil_tile_split
);
1166 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++) {
1168 " StencilLevel[%i]: offset=%" PRIu64
", "
1169 "slice_size=%" PRIu64
", npix_x=%u, "
1170 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1171 "mode=%u, tiling_index = %u\n",
1172 i
, tex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1173 (uint64_t)tex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1174 u_minify(tex
->buffer
.b
.b
.width0
, i
), u_minify(tex
->buffer
.b
.b
.height0
, i
),
1175 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1176 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1177 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1178 tex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1179 tex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1185 * Common function for si_texture_create and si_texture_from_handle.
1187 * \param screen screen
1188 * \param base resource template
1189 * \param surface radeon_surf
1190 * \param plane0 if a non-zero plane is being created, this is the first plane
1191 * \param imported_buf from si_texture_from_handle
1192 * \param offset offset for non-zero planes or imported buffers
1193 * \param alloc_size the size to allocate if plane0 != NULL
1194 * \param alignment alignment for the allocation
1196 static struct si_texture
*si_texture_create_object(struct pipe_screen
*screen
,
1197 const struct pipe_resource
*base
,
1198 const struct radeon_surf
*surface
,
1199 const struct si_texture
*plane0
,
1200 struct pb_buffer
*imported_buf
, uint64_t offset
,
1201 uint64_t alloc_size
, unsigned alignment
)
1203 struct si_texture
*tex
;
1204 struct si_resource
*resource
;
1205 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1207 tex
= CALLOC_STRUCT(si_texture
);
1211 resource
= &tex
->buffer
;
1212 resource
->b
.b
= *base
;
1213 resource
->b
.vtbl
= &si_texture_vtbl
;
1214 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1215 resource
->b
.b
.screen
= screen
;
1217 /* don't include stencil-only formats which we don't support for rendering */
1218 tex
->is_depth
= util_format_has_depth(util_format_description(tex
->buffer
.b
.b
.format
));
1219 tex
->surface
= *surface
;
1220 tex
->tc_compatible_htile
=
1221 tex
->surface
.htile_size
!= 0 && (tex
->surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
);
1223 /* TC-compatible HTILE:
1224 * - GFX8 only supports Z32_FLOAT.
1225 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1226 if (tex
->tc_compatible_htile
) {
1227 if (sscreen
->info
.chip_class
>= GFX9
&& base
->format
== PIPE_FORMAT_Z16_UNORM
)
1228 tex
->db_render_format
= base
->format
;
1230 tex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1231 tex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1232 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1235 tex
->db_render_format
= base
->format
;
1238 /* Applies to GCN. */
1239 tex
->last_msaa_resolve_target_micro_mode
= tex
->surface
.micro_tile_mode
;
1241 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1242 * between frames, so the only thing that can enable separate DCC
1243 * with DRI2 is multiple slow clears within a frame.
1245 tex
->ps_draw_ratio
= 0;
1247 if (sscreen
->info
.chip_class
>= GFX9
) {
1248 tex
->surface
.u
.gfx9
.surf_offset
= offset
;
1250 for (unsigned i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
1251 tex
->surface
.u
.legacy
.level
[i
].offset
+= offset
;
1254 if (tex
->is_depth
) {
1255 if (sscreen
->info
.chip_class
>= GFX9
) {
1256 tex
->can_sample_z
= true;
1257 tex
->can_sample_s
= true;
1259 /* Stencil texturing with HTILE doesn't work
1260 * with mipmapping on Navi10-14. */
1261 if (sscreen
->info
.chip_class
== GFX10
&& base
->last_level
> 0)
1262 tex
->htile_stencil_disabled
= true;
1264 tex
->can_sample_z
= !tex
->surface
.u
.legacy
.depth_adjusted
;
1265 tex
->can_sample_s
= !tex
->surface
.u
.legacy
.stencil_adjusted
;
1268 tex
->db_compatible
= surface
->flags
& RADEON_SURF_ZBUFFER
;
1270 if (tex
->surface
.cmask_offset
) {
1271 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
1272 tex
->cmask_buffer
= &tex
->buffer
;
1277 /* The buffer is shared with the first plane. */
1278 resource
->bo_size
= plane0
->buffer
.bo_size
;
1279 resource
->bo_alignment
= plane0
->buffer
.bo_alignment
;
1280 resource
->flags
= plane0
->buffer
.flags
;
1281 resource
->domains
= plane0
->buffer
.domains
;
1282 resource
->vram_usage
= plane0
->buffer
.vram_usage
;
1283 resource
->gart_usage
= plane0
->buffer
.gart_usage
;
1285 pb_reference(&resource
->buf
, plane0
->buffer
.buf
);
1286 resource
->gpu_address
= plane0
->buffer
.gpu_address
;
1287 } else if (!(surface
->flags
& RADEON_SURF_IMPORTED
)) {
1288 /* Create the backing buffer. */
1289 si_init_resource_fields(sscreen
, resource
, alloc_size
, alignment
);
1291 if (!si_alloc_resource(sscreen
, resource
))
1294 resource
->buf
= imported_buf
;
1295 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1296 resource
->bo_size
= imported_buf
->size
;
1297 resource
->bo_alignment
= imported_buf
->alignment
;
1298 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1299 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1300 resource
->vram_usage
= resource
->bo_size
;
1301 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1302 resource
->gart_usage
= resource
->bo_size
;
1303 if (sscreen
->ws
->buffer_get_flags
)
1304 resource
->flags
= sscreen
->ws
->buffer_get_flags(resource
->buf
);
1307 if (tex
->cmask_buffer
) {
1308 /* Initialize the cmask to 0xCC (= compressed state). */
1309 si_screen_clear_buffer(sscreen
, &tex
->cmask_buffer
->b
.b
, tex
->surface
.cmask_offset
,
1310 tex
->surface
.cmask_size
, 0xCCCCCCCC);
1312 if (tex
->surface
.htile_offset
) {
1313 uint32_t clear_value
= 0;
1315 if (sscreen
->info
.chip_class
>= GFX9
|| tex
->tc_compatible_htile
)
1316 clear_value
= 0x0000030F;
1318 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.htile_offset
,
1319 tex
->surface
.htile_size
, clear_value
);
1322 /* Initialize DCC only if the texture is not being imported. */
1323 if (!(surface
->flags
& RADEON_SURF_IMPORTED
) && tex
->surface
.dcc_offset
) {
1324 /* Clear DCC to black for all tiles with DCC enabled.
1326 * This fixes corruption in 3DMark Slingshot Extreme, which
1327 * uses uninitialized textures, causing corruption.
1329 if (tex
->surface
.num_dcc_levels
== tex
->buffer
.b
.b
.last_level
+ 1 &&
1330 tex
->buffer
.b
.b
.nr_samples
<= 2) {
1331 /* Simple case - all tiles have DCC enabled. */
1332 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
,
1333 tex
->surface
.dcc_size
, DCC_CLEAR_COLOR_0000
);
1334 } else if (sscreen
->info
.chip_class
>= GFX9
) {
1335 /* Clear to uncompressed. Clearing this to black is complicated. */
1336 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
,
1337 tex
->surface
.dcc_size
, DCC_UNCOMPRESSED
);
1339 /* GFX8: Initialize mipmap levels and multisamples separately. */
1340 if (tex
->buffer
.b
.b
.nr_samples
>= 2) {
1341 /* Clearing this to black is complicated. */
1342 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
,
1343 tex
->surface
.dcc_size
, DCC_UNCOMPRESSED
);
1345 /* Clear the enabled mipmap levels to black. */
1348 for (unsigned i
= 0; i
< tex
->surface
.num_dcc_levels
; i
++) {
1349 if (!tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
)
1352 size
= tex
->surface
.u
.legacy
.level
[i
].dcc_offset
+
1353 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
;
1356 /* Mipmap levels with DCC. */
1358 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
, size
,
1359 DCC_CLEAR_COLOR_0000
);
1361 /* Mipmap levels without DCC. */
1362 if (size
!= tex
->surface
.dcc_size
) {
1363 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
+ size
,
1364 tex
->surface
.dcc_size
- size
, DCC_UNCOMPRESSED
);
1369 /* Initialize displayable DCC that requires the retile blit. */
1370 if (tex
->surface
.dcc_retile_map_offset
) {
1371 /* Uninitialized DCC can hang the display hw.
1372 * Clear to white to indicate that. */
1373 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.display_dcc_offset
,
1374 tex
->surface
.u
.gfx9
.display_dcc_size
, DCC_CLEAR_COLOR_1111
);
1376 /* Upload the DCC retile map.
1377 * Use a staging buffer for the upload, because
1378 * the buffer backing the texture is unmappable.
1380 bool use_uint16
= tex
->surface
.u
.gfx9
.dcc_retile_use_uint16
;
1381 unsigned num_elements
= tex
->surface
.u
.gfx9
.dcc_retile_num_elements
;
1382 struct si_resource
*buf
= si_aligned_buffer_create(screen
, 0, PIPE_USAGE_STREAM
,
1383 num_elements
* (use_uint16
? 2 : 4),
1384 sscreen
->info
.tcc_cache_line_size
);
1385 uint32_t *ui
= (uint32_t *)sscreen
->ws
->buffer_map(buf
->buf
, NULL
, PIPE_TRANSFER_WRITE
);
1386 uint16_t *us
= (uint16_t *)ui
;
1388 /* Upload the retile map into a staging buffer. */
1390 for (unsigned i
= 0; i
< num_elements
; i
++)
1391 us
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1393 for (unsigned i
= 0; i
< num_elements
; i
++)
1394 ui
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1397 /* Copy the staging buffer to the buffer backing the texture. */
1398 struct si_context
*sctx
= (struct si_context
*)sscreen
->aux_context
;
1400 assert(tex
->surface
.dcc_retile_map_offset
<= UINT_MAX
);
1401 simple_mtx_lock(&sscreen
->aux_context_lock
);
1402 si_sdma_copy_buffer(sctx
, &tex
->buffer
.b
.b
, &buf
->b
.b
, tex
->surface
.dcc_retile_map_offset
,
1403 0, buf
->b
.b
.width0
);
1404 sscreen
->aux_context
->flush(sscreen
->aux_context
, NULL
, 0);
1405 simple_mtx_unlock(&sscreen
->aux_context_lock
);
1407 si_resource_reference(&buf
, NULL
);
1411 /* Initialize the CMASK base register value. */
1412 tex
->cmask_base_address_reg
= (tex
->buffer
.gpu_address
+ tex
->surface
.cmask_offset
) >> 8;
1414 if (sscreen
->debug_flags
& DBG(VM
)) {
1416 "VM start=0x%" PRIX64
" end=0x%" PRIX64
1417 " | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1418 tex
->buffer
.gpu_address
, tex
->buffer
.gpu_address
+ tex
->buffer
.buf
->size
,
1419 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+ 1,
1420 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1423 if (sscreen
->debug_flags
& DBG(TEX
)) {
1425 struct u_log_context log
;
1426 u_log_context_init(&log
);
1427 si_print_texture_info(sscreen
, tex
, &log
);
1428 u_log_new_page_print(&log
, stdout
);
1430 u_log_context_destroy(&log
);
1437 if (sscreen
->info
.chip_class
>= GFX9
)
1438 free(surface
->u
.gfx9
.dcc_retile_map
);
1442 static enum radeon_surf_mode
si_choose_tiling(struct si_screen
*sscreen
,
1443 const struct pipe_resource
*templ
,
1444 bool tc_compatible_htile
)
1446 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1447 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
;
1448 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1449 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1451 /* MSAA resources must be 2D tiled. */
1452 if (templ
->nr_samples
> 1)
1453 return RADEON_SURF_MODE_2D
;
1455 /* Transfer resources should be linear. */
1456 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1457 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1459 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on GFX8,
1460 * which requires 2D tiling.
1462 if (sscreen
->info
.chip_class
== GFX8
&& tc_compatible_htile
)
1463 return RADEON_SURF_MODE_2D
;
1465 /* Handle common candidates for the linear mode.
1466 * Compressed textures and DB surfaces must always be tiled.
1468 if (!force_tiling
&& !is_depth_stencil
&& !util_format_is_compressed(templ
->format
)) {
1469 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1470 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1472 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1473 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1474 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1476 /* Cursors are linear on AMD GCN.
1477 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1478 if (templ
->bind
& PIPE_BIND_CURSOR
)
1479 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1481 if (templ
->bind
& PIPE_BIND_LINEAR
)
1482 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1484 /* Textures with a very small height are recommended to be linear. */
1485 if (templ
->target
== PIPE_TEXTURE_1D
|| templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1486 /* Only very thin and long 2D textures should benefit from
1487 * linear_aligned. */
1488 (templ
->width0
> 8 && templ
->height0
<= 2))
1489 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1491 /* Textures likely to be mapped often. */
1492 if (templ
->usage
== PIPE_USAGE_STAGING
|| templ
->usage
== PIPE_USAGE_STREAM
)
1493 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1496 /* Make small textures 1D tiled. */
1497 if (templ
->width0
<= 16 || templ
->height0
<= 16 || (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1498 return RADEON_SURF_MODE_1D
;
1500 /* The allocator will switch to 1D if needed. */
1501 return RADEON_SURF_MODE_2D
;
1504 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1505 const struct pipe_resource
*templ
)
1507 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1508 bool is_zs
= util_format_is_depth_or_stencil(templ
->format
);
1510 if (templ
->nr_samples
>= 2) {
1511 /* This is hackish (overwriting the const pipe_resource template),
1512 * but should be harmless and state trackers can also see
1513 * the overriden number of samples in the created pipe_resource.
1515 if (is_zs
&& sscreen
->eqaa_force_z_samples
) {
1516 ((struct pipe_resource
*)templ
)->nr_samples
=
1517 ((struct pipe_resource
*)templ
)->nr_storage_samples
= sscreen
->eqaa_force_z_samples
;
1518 } else if (!is_zs
&& sscreen
->eqaa_force_color_samples
) {
1519 ((struct pipe_resource
*)templ
)->nr_samples
= sscreen
->eqaa_force_coverage_samples
;
1520 ((struct pipe_resource
*)templ
)->nr_storage_samples
= sscreen
->eqaa_force_color_samples
;
1524 bool is_flushed_depth
=
1525 templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
|| templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
;
1526 bool tc_compatible_htile
=
1527 sscreen
->info
.chip_class
>= GFX8
&&
1528 /* There are issues with TC-compatible HTILE on Tonga (and
1529 * Iceland is the same design), and documented bug workarounds
1530 * don't help. For example, this fails:
1531 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1533 sscreen
->info
.family
!= CHIP_TONGA
&& sscreen
->info
.family
!= CHIP_ICELAND
&&
1534 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1535 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) && !is_flushed_depth
&&
1536 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1538 enum radeon_surf_mode tile_mode
= si_choose_tiling(sscreen
, templ
, tc_compatible_htile
);
1540 /* This allocates textures with multiple planes like NV12 in 1 buffer. */
1543 SI_TEXTURE_MAX_PLANES
= 3
1545 struct radeon_surf surface
[SI_TEXTURE_MAX_PLANES
] = {};
1546 struct pipe_resource plane_templ
[SI_TEXTURE_MAX_PLANES
];
1547 uint64_t plane_offset
[SI_TEXTURE_MAX_PLANES
] = {};
1548 uint64_t total_size
= 0;
1549 unsigned max_alignment
= 0;
1550 unsigned num_planes
= util_format_get_num_planes(templ
->format
);
1551 assert(num_planes
<= SI_TEXTURE_MAX_PLANES
);
1553 /* Compute texture or plane layouts and offsets. */
1554 for (unsigned i
= 0; i
< num_planes
; i
++) {
1555 plane_templ
[i
] = *templ
;
1556 plane_templ
[i
].format
= util_format_get_plane_format(templ
->format
, i
);
1557 plane_templ
[i
].width0
= util_format_get_plane_width(templ
->format
, i
, templ
->width0
);
1558 plane_templ
[i
].height0
= util_format_get_plane_height(templ
->format
, i
, templ
->height0
);
1560 /* Multi-plane allocations need PIPE_BIND_SHARED, because we can't
1561 * reallocate the storage to add PIPE_BIND_SHARED, because it's
1562 * shared by 3 pipe_resources.
1565 plane_templ
[i
].bind
|= PIPE_BIND_SHARED
;
1567 if (si_init_surface(sscreen
, &surface
[i
], &plane_templ
[i
], tile_mode
, 0, false,
1568 plane_templ
[i
].bind
& PIPE_BIND_SCANOUT
, is_flushed_depth
,
1569 tc_compatible_htile
))
1572 plane_offset
[i
] = align64(total_size
, surface
[i
].surf_alignment
);
1573 total_size
= plane_offset
[i
] + surface
[i
].total_size
;
1574 max_alignment
= MAX2(max_alignment
, surface
[i
].surf_alignment
);
1577 struct si_texture
*plane0
= NULL
, *last_plane
= NULL
;
1579 for (unsigned i
= 0; i
< num_planes
; i
++) {
1580 struct si_texture
*tex
=
1581 si_texture_create_object(screen
, &plane_templ
[i
], &surface
[i
], plane0
, NULL
,
1582 plane_offset
[i
], total_size
, max_alignment
);
1584 si_texture_reference(&plane0
, NULL
);
1588 tex
->plane_index
= i
;
1589 tex
->num_planes
= num_planes
;
1592 plane0
= last_plane
= tex
;
1594 last_plane
->buffer
.b
.b
.next
= &tex
->buffer
.b
.b
;
1599 return (struct pipe_resource
*)plane0
;
1602 static struct pipe_resource
*si_texture_from_winsys_buffer(struct si_screen
*sscreen
,
1603 const struct pipe_resource
*templ
,
1604 struct pb_buffer
*buf
, unsigned stride
,
1605 unsigned offset
, unsigned usage
,
1608 enum radeon_surf_mode array_mode
;
1609 struct radeon_surf surface
= {};
1610 struct radeon_bo_metadata metadata
= {};
1611 struct si_texture
*tex
;
1615 /* Ignore metadata for non-zero planes. */
1620 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1621 si_get_display_metadata(sscreen
, &surface
, &metadata
, &array_mode
, &is_scanout
);
1624 * The bo metadata is unset for un-dedicated images. So we fall
1625 * back to linear. See answer to question 5 of the
1626 * VK_KHX_external_memory spec for some details.
1628 * It is possible that this case isn't going to work if the
1629 * surface pitch isn't correctly aligned by default.
1631 * In order to support it correctly we require multi-image
1632 * metadata to be syncrhonized between radv and radeonsi. The
1633 * semantics of associating multiple image metadata to a memory
1634 * object on the vulkan export side are not concretely defined
1637 * All the use cases we are aware of at the moment for memory
1638 * objects use dedicated allocations. So lets keep the initial
1639 * implementation simple.
1641 * A possible alternative is to attempt to reconstruct the
1642 * tiling information when the TexParameter TEXTURE_TILING_EXT
1645 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1650 si_init_surface(sscreen
, &surface
, templ
, array_mode
, stride
, true, is_scanout
, false, false);
1654 tex
= si_texture_create_object(&sscreen
->b
, templ
, &surface
, NULL
, buf
, offset
, 0, 0);
1658 tex
->buffer
.b
.is_shared
= true;
1659 tex
->buffer
.external_usage
= usage
;
1660 tex
->num_planes
= 1;
1662 if (!si_read_tex_bo_metadata(sscreen
, tex
, offset
, &metadata
)) {
1663 si_texture_reference(&tex
, NULL
);
1667 /* Displayable DCC requires an explicit flush. */
1668 if (dedicated
&& offset
== 0 && !(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
1669 si_has_displayable_dcc(tex
)) {
1670 /* TODO: do we need to decompress DCC? */
1671 if (si_texture_discard_dcc(sscreen
, tex
)) {
1672 /* Update BO metadata after disabling DCC. */
1673 si_set_tex_bo_metadata(sscreen
, tex
);
1677 assert(tex
->surface
.tile_swizzle
== 0);
1678 return &tex
->buffer
.b
.b
;
1681 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1682 const struct pipe_resource
*templ
,
1683 struct winsys_handle
*whandle
, unsigned usage
)
1685 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1686 struct pb_buffer
*buf
= NULL
;
1688 /* Support only 2D textures without mipmaps */
1689 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
&&
1690 templ
->target
!= PIPE_TEXTURE_2D_ARRAY
) ||
1691 templ
->last_level
!= 0)
1694 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, sscreen
->info
.max_alignment
);
1698 return si_texture_from_winsys_buffer(sscreen
, templ
, buf
, whandle
->stride
, whandle
->offset
,
1702 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
, struct pipe_resource
*texture
)
1704 struct si_texture
*tex
= (struct si_texture
*)texture
;
1705 struct pipe_resource resource
;
1706 enum pipe_format pipe_format
= texture
->format
;
1708 assert(!tex
->flushed_depth_texture
);
1710 if (!tex
->can_sample_z
&& tex
->can_sample_s
) {
1711 switch (pipe_format
) {
1712 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1713 /* Save memory by not allocating the S plane. */
1714 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1716 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1717 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1718 /* Save memory bandwidth by not copying the
1719 * stencil part during flush.
1721 * This potentially increases memory bandwidth
1722 * if an application uses both Z and S texturing
1723 * simultaneously (a flushed Z24S8 texture
1724 * would be stored compactly), but how often
1725 * does that really happen?
1727 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1731 } else if (!tex
->can_sample_s
&& tex
->can_sample_z
) {
1732 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1734 /* DB->CB copies to an 8bpp surface don't work. */
1735 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1738 memset(&resource
, 0, sizeof(resource
));
1739 resource
.target
= texture
->target
;
1740 resource
.format
= pipe_format
;
1741 resource
.width0
= texture
->width0
;
1742 resource
.height0
= texture
->height0
;
1743 resource
.depth0
= texture
->depth0
;
1744 resource
.array_size
= texture
->array_size
;
1745 resource
.last_level
= texture
->last_level
;
1746 resource
.nr_samples
= texture
->nr_samples
;
1747 resource
.usage
= PIPE_USAGE_DEFAULT
;
1748 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1749 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1751 tex
->flushed_depth_texture
=
1752 (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1753 if (!tex
->flushed_depth_texture
) {
1754 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1761 * Initialize the pipe_resource descriptor to be of the same size as the box,
1762 * which is supposed to hold a subregion of the texture "orig" at the given
1765 static void si_init_temp_resource_from_box(struct pipe_resource
*res
, struct pipe_resource
*orig
,
1766 const struct pipe_box
*box
, unsigned level
,
1769 memset(res
, 0, sizeof(*res
));
1770 res
->format
= orig
->format
;
1771 res
->width0
= box
->width
;
1772 res
->height0
= box
->height
;
1774 res
->array_size
= 1;
1775 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1778 if (flags
& SI_RESOURCE_FLAG_TRANSFER
&& util_format_is_compressed(orig
->format
)) {
1779 /* Transfer resources are allocated with linear tiling, which is
1780 * not supported for compressed formats.
1782 unsigned blocksize
= util_format_get_blocksize(orig
->format
);
1784 if (blocksize
== 8) {
1785 res
->format
= PIPE_FORMAT_R16G16B16A16_UINT
;
1787 assert(blocksize
== 16);
1788 res
->format
= PIPE_FORMAT_R32G32B32A32_UINT
;
1791 res
->width0
= util_format_get_nblocksx(orig
->format
, box
->width
);
1792 res
->height0
= util_format_get_nblocksy(orig
->format
, box
->height
);
1795 /* We must set the correct texture target and dimensions for a 3D box. */
1796 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1797 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1798 res
->array_size
= box
->depth
;
1800 res
->target
= PIPE_TEXTURE_2D
;
1804 static bool si_can_invalidate_texture(struct si_screen
*sscreen
, struct si_texture
*tex
,
1805 unsigned transfer_usage
, const struct pipe_box
*box
)
1807 return !tex
->buffer
.b
.is_shared
&& !(tex
->surface
.flags
& RADEON_SURF_IMPORTED
) &&
1808 !(transfer_usage
& PIPE_TRANSFER_READ
) && tex
->buffer
.b
.b
.last_level
== 0 &&
1809 util_texrange_covers_whole_level(&tex
->buffer
.b
.b
, 0, box
->x
, box
->y
, box
->z
, box
->width
,
1810 box
->height
, box
->depth
);
1813 static void si_texture_invalidate_storage(struct si_context
*sctx
, struct si_texture
*tex
)
1815 struct si_screen
*sscreen
= sctx
->screen
;
1817 /* There is no point in discarding depth and tiled buffers. */
1818 assert(!tex
->is_depth
);
1819 assert(tex
->surface
.is_linear
);
1821 /* Reallocate the buffer in the same pipe_resource. */
1822 si_alloc_resource(sscreen
, &tex
->buffer
);
1824 /* Initialize the CMASK base address (needed even without CMASK). */
1825 tex
->cmask_base_address_reg
= (tex
->buffer
.gpu_address
+ tex
->surface
.cmask_offset
) >> 8;
1827 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1829 sctx
->num_alloc_tex_transfer_bytes
+= tex
->surface
.total_size
;
1832 static void *si_texture_transfer_map(struct pipe_context
*ctx
, struct pipe_resource
*texture
,
1833 unsigned level
, unsigned usage
, const struct pipe_box
*box
,
1834 struct pipe_transfer
**ptransfer
)
1836 struct si_context
*sctx
= (struct si_context
*)ctx
;
1837 struct si_texture
*tex
= (struct si_texture
*)texture
;
1838 struct si_transfer
*trans
;
1839 struct si_resource
*buf
;
1840 unsigned offset
= 0;
1842 bool use_staging_texture
= false;
1844 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
1845 assert(box
->width
&& box
->height
&& box
->depth
);
1847 if (tex
->is_depth
) {
1848 /* Depth textures use staging unconditionally. */
1849 use_staging_texture
= true;
1851 /* Degrade the tile mode if we get too many transfers on APUs.
1852 * On dGPUs, the staging texture is always faster.
1853 * Only count uploads that are at least 4x4 pixels large.
1855 if (!sctx
->screen
->info
.has_dedicated_vram
&& level
== 0 && box
->width
>= 4 &&
1856 box
->height
>= 4 && p_atomic_inc_return(&tex
->num_level0_transfers
) == 10) {
1857 bool can_invalidate
= si_can_invalidate_texture(sctx
->screen
, tex
, usage
, box
);
1859 si_reallocate_texture_inplace(sctx
, tex
, PIPE_BIND_LINEAR
, can_invalidate
);
1862 /* Tiled textures need to be converted into a linear texture for CPU
1863 * access. The staging texture is always linear and is placed in GART.
1865 * Reading from VRAM or GTT WC is slow, always use the staging
1866 * texture in this case.
1868 * Use the staging texture for uploads if the underlying BO
1871 if (!tex
->surface
.is_linear
)
1872 use_staging_texture
= true;
1873 else if (usage
& PIPE_TRANSFER_READ
)
1874 use_staging_texture
=
1875 tex
->buffer
.domains
& RADEON_DOMAIN_VRAM
|| tex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
1876 /* Write & linear only: */
1877 else if (si_rings_is_buffer_referenced(sctx
, tex
->buffer
.buf
, RADEON_USAGE_READWRITE
) ||
1878 !sctx
->ws
->buffer_wait(tex
->buffer
.buf
, 0, RADEON_USAGE_READWRITE
)) {
1880 if (si_can_invalidate_texture(sctx
->screen
, tex
, usage
, box
))
1881 si_texture_invalidate_storage(sctx
, tex
);
1883 use_staging_texture
= true;
1887 trans
= CALLOC_STRUCT(si_transfer
);
1890 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1891 trans
->b
.b
.level
= level
;
1892 trans
->b
.b
.usage
= usage
;
1893 trans
->b
.b
.box
= *box
;
1895 if (use_staging_texture
) {
1896 struct pipe_resource resource
;
1897 struct si_texture
*staging
;
1899 si_init_temp_resource_from_box(&resource
, texture
, box
, level
, SI_RESOURCE_FLAG_TRANSFER
);
1900 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ? PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1902 /* Since depth-stencil textures don't support linear tiling,
1903 * blit from ZS to color and vice versa. u_blitter will do
1904 * the packing for these formats.
1907 resource
.format
= util_blitter_get_color_format_for_zs(resource
.format
);
1909 /* Create the temporary texture. */
1910 staging
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1912 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1915 trans
->staging
= &staging
->buffer
;
1917 /* Just get the strides. */
1918 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
, &trans
->b
.b
.stride
,
1919 &trans
->b
.b
.layer_stride
);
1921 if (usage
& PIPE_TRANSFER_READ
)
1922 si_copy_to_staging_texture(ctx
, trans
);
1924 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1926 buf
= trans
->staging
;
1928 /* the resource is mapped directly */
1929 offset
= si_texture_get_offset(sctx
->screen
, tex
, level
, box
, &trans
->b
.b
.stride
,
1930 &trans
->b
.b
.layer_stride
);
1934 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1935 * we don't run out of the CPU address space.
1937 if (sizeof(void *) == 4)
1938 usage
|= RADEON_TRANSFER_TEMPORARY
;
1940 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
1943 *ptransfer
= &trans
->b
.b
;
1944 return map
+ offset
;
1947 si_resource_reference(&trans
->staging
, NULL
);
1948 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
1953 static void si_texture_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*transfer
)
1955 struct si_context
*sctx
= (struct si_context
*)ctx
;
1956 struct si_transfer
*stransfer
= (struct si_transfer
*)transfer
;
1957 struct pipe_resource
*texture
= transfer
->resource
;
1958 struct si_texture
*tex
= (struct si_texture
*)texture
;
1960 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1961 * we don't run out of the CPU address space.
1963 if (sizeof(void *) == 4) {
1964 struct si_resource
*buf
= stransfer
->staging
? stransfer
->staging
: &tex
->buffer
;
1966 sctx
->ws
->buffer_unmap(buf
->buf
);
1969 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && stransfer
->staging
)
1970 si_copy_from_staging_texture(ctx
, stransfer
);
1972 if (stransfer
->staging
) {
1973 sctx
->num_alloc_tex_transfer_bytes
+= stransfer
->staging
->buf
->size
;
1974 si_resource_reference(&stransfer
->staging
, NULL
);
1977 /* Heuristic for {upload, draw, upload, draw, ..}:
1979 * Flush the gfx IB if we've allocated too much texture storage.
1981 * The idea is that we don't want to build IBs that use too much
1982 * memory and put pressure on the kernel memory manager and we also
1983 * want to make temporary and invalidated buffers go idle ASAP to
1984 * decrease the total memory usage or make them reusable. The memory
1985 * usage will be slightly higher than given here because of the buffer
1986 * cache in the winsys.
1988 * The result is that the kernel memory manager is never a bottleneck.
1990 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
1991 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1992 sctx
->num_alloc_tex_transfer_bytes
= 0;
1995 pipe_resource_reference(&transfer
->resource
, NULL
);
1999 static const struct u_resource_vtbl si_texture_vtbl
= {
2000 NULL
, /* get_handle */
2001 si_texture_destroy
, /* resource_destroy */
2002 si_texture_transfer_map
, /* transfer_map */
2003 u_default_transfer_flush_region
, /* transfer_flush_region */
2004 si_texture_transfer_unmap
, /* transfer_unmap */
2007 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
2009 bool vi_dcc_formats_compatible(struct si_screen
*sscreen
, enum pipe_format format1
,
2010 enum pipe_format format2
)
2012 const struct util_format_description
*desc1
, *desc2
;
2014 /* No format change - exit early. */
2015 if (format1
== format2
)
2018 format1
= si_simplify_cb_format(format1
);
2019 format2
= si_simplify_cb_format(format2
);
2021 /* Check again after format adjustments. */
2022 if (format1
== format2
)
2025 desc1
= util_format_description(format1
);
2026 desc2
= util_format_description(format2
);
2028 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
|| desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2031 /* Float and non-float are totally incompatible. */
2032 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
2033 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
2036 /* Channel sizes must match across DCC formats.
2037 * Comparing just the first 2 channels should be enough.
2039 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
2040 (desc1
->nr_channels
>= 2 && desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
2043 /* Everything below is not needed if the driver never uses the DCC
2044 * clear code with the value of 1.
2047 /* If the clear values are all 1 or all 0, this constraint can be
2049 if (vi_alpha_is_on_msb(sscreen
, format1
) != vi_alpha_is_on_msb(sscreen
, format2
))
2052 /* Channel types must match if the clear value of 1 is used.
2053 * The type categories are only float, signed, unsigned.
2054 * NORM and INT are always compatible.
2056 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
2057 (desc1
->nr_channels
>= 2 && desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
2063 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
, unsigned level
,
2064 enum pipe_format view_format
)
2066 struct si_texture
*stex
= (struct si_texture
*)tex
;
2068 return vi_dcc_enabled(stex
, level
) &&
2069 !vi_dcc_formats_compatible((struct si_screen
*)tex
->screen
, tex
->format
, view_format
);
2072 /* This can't be merged with the above function, because
2073 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
2074 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
, struct pipe_resource
*tex
,
2075 unsigned level
, enum pipe_format view_format
)
2077 struct si_texture
*stex
= (struct si_texture
*)tex
;
2079 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
2080 if (!si_texture_disable_dcc(sctx
, stex
))
2081 si_decompress_dcc(sctx
, stex
);
2084 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
2085 struct pipe_resource
*texture
,
2086 const struct pipe_surface
*templ
, unsigned width0
,
2087 unsigned height0
, unsigned width
, unsigned height
)
2089 struct si_surface
*surface
= CALLOC_STRUCT(si_surface
);
2094 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2095 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2097 pipe_reference_init(&surface
->base
.reference
, 1);
2098 pipe_resource_reference(&surface
->base
.texture
, texture
);
2099 surface
->base
.context
= pipe
;
2100 surface
->base
.format
= templ
->format
;
2101 surface
->base
.width
= width
;
2102 surface
->base
.height
= height
;
2103 surface
->base
.u
= templ
->u
;
2105 surface
->width0
= width0
;
2106 surface
->height0
= height0
;
2108 surface
->dcc_incompatible
=
2109 texture
->target
!= PIPE_BUFFER
&&
2110 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
, templ
->format
);
2111 return &surface
->base
;
2114 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
, struct pipe_resource
*tex
,
2115 const struct pipe_surface
*templ
)
2117 unsigned level
= templ
->u
.tex
.level
;
2118 unsigned width
= u_minify(tex
->width0
, level
);
2119 unsigned height
= u_minify(tex
->height0
, level
);
2120 unsigned width0
= tex
->width0
;
2121 unsigned height0
= tex
->height0
;
2123 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2124 const struct util_format_description
*tex_desc
= util_format_description(tex
->format
);
2125 const struct util_format_description
*templ_desc
= util_format_description(templ
->format
);
2127 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2129 /* Adjust size of surface if and only if the block width or
2130 * height is changed. */
2131 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2132 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2133 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2134 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2136 width
= nblks_x
* templ_desc
->block
.width
;
2137 height
= nblks_y
* templ_desc
->block
.height
;
2139 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2140 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2144 return si_create_surface_custom(pipe
, tex
, templ
, width0
, height0
, width
, height
);
2147 static void si_surface_destroy(struct pipe_context
*pipe
, struct pipe_surface
*surface
)
2149 pipe_resource_reference(&surface
->texture
, NULL
);
2153 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2155 const struct util_format_description
*desc
= util_format_description(format
);
2157 #define HAS_SWIZZLE(chan, swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2159 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2160 return V_028C70_SWAP_STD
;
2162 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2165 switch (desc
->nr_channels
) {
2167 if (HAS_SWIZZLE(0, X
))
2168 return V_028C70_SWAP_STD
; /* X___ */
2169 else if (HAS_SWIZZLE(3, X
))
2170 return V_028C70_SWAP_ALT_REV
; /* ___X */
2173 if ((HAS_SWIZZLE(0, X
) && HAS_SWIZZLE(1, Y
)) || (HAS_SWIZZLE(0, X
) && HAS_SWIZZLE(1, NONE
)) ||
2174 (HAS_SWIZZLE(0, NONE
) && HAS_SWIZZLE(1, Y
)))
2175 return V_028C70_SWAP_STD
; /* XY__ */
2176 else if ((HAS_SWIZZLE(0, Y
) && HAS_SWIZZLE(1, X
)) ||
2177 (HAS_SWIZZLE(0, Y
) && HAS_SWIZZLE(1, NONE
)) ||
2178 (HAS_SWIZZLE(0, NONE
) && HAS_SWIZZLE(1, X
)))
2180 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2181 else if (HAS_SWIZZLE(0, X
) && HAS_SWIZZLE(3, Y
))
2182 return V_028C70_SWAP_ALT
; /* X__Y */
2183 else if (HAS_SWIZZLE(0, Y
) && HAS_SWIZZLE(3, X
))
2184 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2187 if (HAS_SWIZZLE(0, X
))
2188 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2189 else if (HAS_SWIZZLE(0, Z
))
2190 return V_028C70_SWAP_STD_REV
; /* ZYX */
2193 /* check the middle channels, the 1st and 4th channel can be NONE */
2194 if (HAS_SWIZZLE(1, Y
) && HAS_SWIZZLE(2, Z
)) {
2195 return V_028C70_SWAP_STD
; /* XYZW */
2196 } else if (HAS_SWIZZLE(1, Z
) && HAS_SWIZZLE(2, Y
)) {
2197 return V_028C70_SWAP_STD_REV
; /* WZYX */
2198 } else if (HAS_SWIZZLE(1, Y
) && HAS_SWIZZLE(2, X
)) {
2199 return V_028C70_SWAP_ALT
; /* ZYXW */
2200 } else if (HAS_SWIZZLE(1, Z
) && HAS_SWIZZLE(2, W
)) {
2203 return V_028C70_SWAP_ALT_REV
;
2205 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2212 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2214 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
, int slot
)
2218 if (sctx
->dcc_stats
[slot
].query_active
)
2219 vi_separate_dcc_stop_query(sctx
, sctx
->dcc_stats
[slot
].tex
);
2221 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2222 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2223 sctx
->b
.destroy_query(&sctx
->b
, sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2224 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2227 si_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2231 * Return the per-context slot where DCC statistics queries for the texture live.
2233 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
, struct si_texture
*tex
)
2235 int i
, empty_slot
= -1;
2237 /* Remove zombie textures (textures kept alive by this array only). */
2238 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2239 if (sctx
->dcc_stats
[i
].tex
&& sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2240 vi_dcc_clean_up_context_slot(sctx
, i
);
2242 /* Find the texture. */
2243 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2244 /* Return if found. */
2245 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2246 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2250 /* Record the first seen empty slot. */
2251 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2255 /* Not found. Remove the oldest member to make space in the array. */
2256 if (empty_slot
== -1) {
2257 int oldest_slot
= 0;
2259 /* Find the oldest slot. */
2260 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2261 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2262 sctx
->dcc_stats
[i
].last_use_timestamp
)
2265 /* Clean up the oldest slot. */
2266 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2267 empty_slot
= oldest_slot
;
2270 /* Add the texture to the new slot. */
2271 si_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2272 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2276 static struct pipe_query
*vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2278 struct si_query_hw
*query
=
2279 (struct si_query_hw
*)sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2281 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2282 return (struct pipe_query
*)query
;
2286 * Called when binding a color buffer.
2288 void vi_separate_dcc_start_query(struct si_context
*sctx
, struct si_texture
*tex
)
2290 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2292 assert(!sctx
->dcc_stats
[i
].query_active
);
2294 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2295 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2297 /* begin or resume the query */
2298 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2299 sctx
->dcc_stats
[i
].query_active
= true;
2303 * Called when unbinding a color buffer.
2305 void vi_separate_dcc_stop_query(struct si_context
*sctx
, struct si_texture
*tex
)
2307 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2309 assert(sctx
->dcc_stats
[i
].query_active
);
2310 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2312 /* pause or end the query */
2313 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2314 sctx
->dcc_stats
[i
].query_active
= false;
2317 static bool vi_should_enable_separate_dcc(struct si_texture
*tex
)
2319 /* The minimum number of fullscreen draws per frame that is required
2321 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2324 /* Called by fast clear. */
2325 void vi_separate_dcc_try_enable(struct si_context
*sctx
, struct si_texture
*tex
)
2327 /* The intent is to use this with shared displayable back buffers,
2328 * but it's not strictly limited only to them.
2330 if (!tex
->buffer
.b
.is_shared
||
2331 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2332 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
|| tex
->buffer
.b
.b
.last_level
> 0 ||
2333 !tex
->surface
.dcc_size
|| sctx
->screen
->debug_flags
& DBG(NO_DCC
) ||
2334 sctx
->screen
->debug_flags
& DBG(NO_DCC_FB
))
2337 assert(sctx
->chip_class
>= GFX8
);
2339 if (tex
->surface
.dcc_offset
)
2340 return; /* already enabled */
2342 /* Enable the DCC stat gathering. */
2343 if (!tex
->dcc_gather_statistics
) {
2344 tex
->dcc_gather_statistics
= true;
2345 vi_separate_dcc_start_query(sctx
, tex
);
2348 if (!vi_should_enable_separate_dcc(tex
))
2349 return; /* stats show that DCC decompression is too expensive */
2351 assert(tex
->surface
.num_dcc_levels
);
2352 assert(!tex
->dcc_separate_buffer
);
2354 si_texture_discard_cmask(sctx
->screen
, tex
);
2356 /* Get a DCC buffer. */
2357 if (tex
->last_dcc_separate_buffer
) {
2358 assert(tex
->dcc_gather_statistics
);
2359 assert(!tex
->dcc_separate_buffer
);
2360 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2361 tex
->last_dcc_separate_buffer
= NULL
;
2363 tex
->dcc_separate_buffer
=
2364 si_aligned_buffer_create(sctx
->b
.screen
, SI_RESOURCE_FLAG_UNMAPPABLE
, PIPE_USAGE_DEFAULT
,
2365 tex
->surface
.dcc_size
, tex
->surface
.dcc_alignment
);
2366 if (!tex
->dcc_separate_buffer
)
2370 /* dcc_offset is the absolute GPUVM address. */
2371 tex
->surface
.dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2373 /* no need to flag anything since this is called by fast clear that
2374 * flags framebuffer state
2379 * Called by pipe_context::flush_resource, the place where DCC decompression
2382 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
, struct si_texture
*tex
)
2384 struct si_context
*sctx
= (struct si_context
*)ctx
;
2385 struct pipe_query
*tmp
;
2386 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2387 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2388 bool disable
= false;
2390 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2391 union pipe_query_result result
;
2393 /* Read the results. */
2394 struct pipe_query
*query
= sctx
->dcc_stats
[i
].ps_stats
[2];
2395 ctx
->get_query_result(ctx
, query
, true, &result
);
2396 si_query_buffer_reset(sctx
, &((struct si_query_hw
*)query
)->buffer
);
2398 /* Compute the approximate number of fullscreen draws. */
2399 tex
->ps_draw_ratio
= result
.pipeline_statistics
.ps_invocations
/
2400 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2401 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2403 disable
= tex
->dcc_separate_buffer
&& !vi_should_enable_separate_dcc(tex
);
2406 tex
->num_slow_clears
= 0;
2408 /* stop the statistics query for ps_stats[0] */
2410 vi_separate_dcc_stop_query(sctx
, tex
);
2412 /* Move the queries in the queue by one. */
2413 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2414 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2415 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2416 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2418 /* create and start a new query as ps_stats[0] */
2420 vi_separate_dcc_start_query(sctx
, tex
);
2423 assert(!tex
->last_dcc_separate_buffer
);
2424 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2425 tex
->dcc_separate_buffer
= NULL
;
2426 tex
->surface
.dcc_offset
= 0;
2427 /* no need to flag anything since this is called after
2428 * decompression that re-sets framebuffer state
2433 static struct pipe_memory_object
*
2434 si_memobj_from_handle(struct pipe_screen
*screen
, struct winsys_handle
*whandle
, bool dedicated
)
2436 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2437 struct si_memory_object
*memobj
= CALLOC_STRUCT(si_memory_object
);
2438 struct pb_buffer
*buf
= NULL
;
2443 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, sscreen
->info
.max_alignment
);
2449 memobj
->b
.dedicated
= dedicated
;
2451 memobj
->stride
= whandle
->stride
;
2453 return (struct pipe_memory_object
*)memobj
;
2456 static void si_memobj_destroy(struct pipe_screen
*screen
, struct pipe_memory_object
*_memobj
)
2458 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2460 pb_reference(&memobj
->buf
, NULL
);
2464 static struct pipe_resource
*si_texture_from_memobj(struct pipe_screen
*screen
,
2465 const struct pipe_resource
*templ
,
2466 struct pipe_memory_object
*_memobj
,
2469 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2470 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2471 struct pipe_resource
*tex
= si_texture_from_winsys_buffer(
2472 sscreen
, templ
, memobj
->buf
, memobj
->stride
, offset
,
2473 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
| PIPE_HANDLE_USAGE_SHADER_WRITE
, memobj
->b
.dedicated
);
2477 /* si_texture_from_winsys_buffer doesn't increment refcount of
2478 * memobj->buf, so increment it here.
2480 struct pb_buffer
*buf
= NULL
;
2481 pb_reference(&buf
, memobj
->buf
);
2485 static bool si_check_resource_capability(struct pipe_screen
*screen
, struct pipe_resource
*resource
,
2488 struct si_texture
*tex
= (struct si_texture
*)resource
;
2490 /* Buffers only support the linear flag. */
2491 if (resource
->target
== PIPE_BUFFER
)
2492 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2494 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2497 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2500 /* TODO: PIPE_BIND_CURSOR - do we care? */
2504 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2506 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2507 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2508 sscreen
->b
.resource_get_param
= si_resource_get_param
;
2509 sscreen
->b
.resource_get_info
= si_texture_get_info
;
2510 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2511 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2512 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2513 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2516 void si_init_context_texture_functions(struct si_context
*sctx
)
2518 sctx
->b
.create_surface
= si_create_surface
;
2519 sctx
->b
.surface_destroy
= si_surface_destroy
;