2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include "util/u_resource.h"
33 #include "util/u_surface.h"
34 #include "util/u_transfer.h"
35 #include "util/os_time.h"
38 #include "state_tracker/drm_driver.h"
41 static enum radeon_surf_mode
42 si_choose_tiling(struct si_screen
*sscreen
,
43 const struct pipe_resource
*templ
, bool tc_compatible_htile
);
46 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
47 struct si_texture
*dst
,
48 unsigned dst_level
, unsigned dstx
,
49 unsigned dsty
, unsigned dstz
,
50 struct si_texture
*src
,
52 const struct pipe_box
*src_box
)
57 if (dst
->surface
.bpe
!= src
->surface
.bpe
)
60 /* MSAA: Blits don't exist in the real world. */
61 if (src
->buffer
.b
.b
.nr_samples
> 1 ||
62 dst
->buffer
.b
.b
.nr_samples
> 1)
65 /* Depth-stencil surfaces:
66 * When dst is linear, the DB->CB copy preserves HTILE.
67 * When dst is tiled, the 3D path must be used to update HTILE.
69 if (src
->is_depth
|| dst
->is_depth
)
73 * src: Use the 3D path. DCC decompression is expensive.
74 * dst: Use the 3D path to compress the pixels with DCC.
76 if (vi_dcc_enabled(src
, src_level
) ||
77 vi_dcc_enabled(dst
, dst_level
))
81 * src: Both texture and SDMA paths need decompression. Use SDMA.
82 * dst: If overwriting the whole texture, discard CMASK and use
83 * SDMA. Otherwise, use the 3D path.
85 if (dst
->cmask_buffer
&& dst
->dirty_level_mask
& (1 << dst_level
)) {
86 /* The CMASK clear is only enabled for the first level. */
87 assert(dst_level
== 0);
88 if (!util_texrange_covers_whole_level(&dst
->buffer
.b
.b
, dst_level
,
89 dstx
, dsty
, dstz
, src_box
->width
,
90 src_box
->height
, src_box
->depth
))
93 si_texture_discard_cmask(sctx
->screen
, dst
);
96 /* All requirements are met. Prepare textures for SDMA. */
97 if (src
->cmask_buffer
&& src
->dirty_level_mask
& (1 << src_level
))
98 sctx
->b
.flush_resource(&sctx
->b
, &src
->buffer
.b
.b
);
100 assert(!(src
->dirty_level_mask
& (1 << src_level
)));
101 assert(!(dst
->dirty_level_mask
& (1 << dst_level
)));
106 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
107 static void si_copy_region_with_blit(struct pipe_context
*pipe
,
108 struct pipe_resource
*dst
,
110 unsigned dstx
, unsigned dsty
, unsigned dstz
,
111 struct pipe_resource
*src
,
113 const struct pipe_box
*src_box
)
115 struct pipe_blit_info blit
;
117 memset(&blit
, 0, sizeof(blit
));
118 blit
.src
.resource
= src
;
119 blit
.src
.format
= src
->format
;
120 blit
.src
.level
= src_level
;
121 blit
.src
.box
= *src_box
;
122 blit
.dst
.resource
= dst
;
123 blit
.dst
.format
= dst
->format
;
124 blit
.dst
.level
= dst_level
;
125 blit
.dst
.box
.x
= dstx
;
126 blit
.dst
.box
.y
= dsty
;
127 blit
.dst
.box
.z
= dstz
;
128 blit
.dst
.box
.width
= src_box
->width
;
129 blit
.dst
.box
.height
= src_box
->height
;
130 blit
.dst
.box
.depth
= src_box
->depth
;
131 blit
.mask
= util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
142 struct si_context
*sctx
= (struct si_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
144 struct pipe_resource
*dst
= &stransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1 || ((struct si_texture
*)src
)->is_depth
) {
148 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
160 struct si_context
*sctx
= (struct si_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &stransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1 || ((struct si_texture
*)dst
)->is_depth
) {
169 si_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 if (util_format_is_compressed(dst
->format
)) {
176 sbox
.width
= util_format_get_nblocksx(dst
->format
, sbox
.width
);
177 sbox
.height
= util_format_get_nblocksx(dst
->format
, sbox
.height
);
180 sctx
->dma_copy(ctx
, dst
, transfer
->level
,
181 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
185 static unsigned si_texture_get_offset(struct si_screen
*sscreen
,
186 struct si_texture
*tex
, unsigned level
,
187 const struct pipe_box
*box
,
189 unsigned *layer_stride
)
191 if (sscreen
->info
.chip_class
>= GFX9
) {
192 *stride
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
193 *layer_stride
= tex
->surface
.u
.gfx9
.surf_slice_size
;
198 /* Each texture is an array of slices. Each slice is an array
199 * of mipmap levels. */
200 return box
->z
* tex
->surface
.u
.gfx9
.surf_slice_size
+
201 tex
->surface
.u
.gfx9
.offset
[level
] +
202 (box
->y
/ tex
->surface
.blk_h
*
203 tex
->surface
.u
.gfx9
.surf_pitch
+
204 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
206 *stride
= tex
->surface
.u
.legacy
.level
[level
].nblk_x
*
208 assert((uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
209 *layer_stride
= (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
212 return tex
->surface
.u
.legacy
.level
[level
].offset
;
214 /* Each texture is an array of mipmap levels. Each level is
215 * an array of slices. */
216 return tex
->surface
.u
.legacy
.level
[level
].offset
+
217 box
->z
* (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
218 (box
->y
/ tex
->surface
.blk_h
*
219 tex
->surface
.u
.legacy
.level
[level
].nblk_x
+
220 box
->x
/ tex
->surface
.blk_w
) * tex
->surface
.bpe
;
224 static int si_init_surface(struct si_screen
*sscreen
,
225 struct radeon_surf
*surface
,
226 const struct pipe_resource
*ptex
,
227 enum radeon_surf_mode array_mode
,
228 unsigned pitch_in_bytes_override
,
232 bool is_flushed_depth
,
233 bool tc_compatible_htile
)
235 const struct util_format_description
*desc
=
236 util_format_description(ptex
->format
);
237 bool is_depth
, is_stencil
;
239 unsigned i
, bpe
, flags
= 0;
241 is_depth
= util_format_has_depth(desc
);
242 is_stencil
= util_format_has_stencil(desc
);
244 if (!is_flushed_depth
&&
245 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
246 bpe
= 4; /* stencil is allocated separately */
248 bpe
= util_format_get_blocksize(ptex
->format
);
249 assert(util_is_power_of_two_or_zero(bpe
));
252 if (!is_flushed_depth
&& is_depth
) {
253 flags
|= RADEON_SURF_ZBUFFER
;
255 if (tc_compatible_htile
&&
256 (sscreen
->info
.chip_class
>= GFX9
||
257 array_mode
== RADEON_SURF_MODE_2D
)) {
258 /* TC-compatible HTILE only supports Z32_FLOAT.
259 * GFX9 also supports Z16_UNORM.
260 * On GFX8, promote Z16 to Z32. DB->CB copies will convert
261 * the format for transfers.
263 if (sscreen
->info
.chip_class
== GFX8
)
266 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
270 flags
|= RADEON_SURF_SBUFFER
;
273 if (sscreen
->info
.chip_class
>= GFX8
&&
274 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
||
275 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
276 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
277 flags
|= RADEON_SURF_DISABLE_DCC
;
279 /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */
280 if (sscreen
->info
.family
== CHIP_STONEY
&&
281 bpe
== 16 && ptex
->nr_samples
>= 2)
282 flags
|= RADEON_SURF_DISABLE_DCC
;
284 /* GFX8: DCC clear for 4x and 8x MSAA array textures unimplemented. */
285 if (sscreen
->info
.chip_class
== GFX8
&&
286 ptex
->nr_storage_samples
>= 4 &&
287 ptex
->array_size
> 1)
288 flags
|= RADEON_SURF_DISABLE_DCC
;
290 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
291 if (sscreen
->info
.chip_class
>= GFX9
&&
292 ptex
->nr_storage_samples
>= 4)
293 flags
|= RADEON_SURF_DISABLE_DCC
;
295 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
296 /* This should catch bugs in gallium users setting incorrect flags. */
297 assert(ptex
->nr_samples
<= 1 &&
298 ptex
->array_size
== 1 &&
300 ptex
->last_level
== 0 &&
301 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
303 flags
|= RADEON_SURF_SCANOUT
;
306 if (ptex
->bind
& PIPE_BIND_SHARED
)
307 flags
|= RADEON_SURF_SHAREABLE
;
309 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
310 if (!(ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
))
311 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
313 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
,
314 array_mode
, surface
);
319 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
321 if (sscreen
->info
.chip_class
>= GFX9
) {
323 surface
->u
.gfx9
.surf_pitch
= pitch
;
324 surface
->u
.gfx9
.surf_slice_size
=
325 (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
327 surface
->u
.gfx9
.surf_offset
= offset
;
330 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
331 surface
->u
.legacy
.level
[0].slice_size_dw
=
332 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
335 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
336 surface
->u
.legacy
.level
[i
].offset
+= offset
;
342 static void si_get_display_metadata(struct si_screen
*sscreen
,
343 struct radeon_surf
*surf
,
344 struct radeon_bo_metadata
*metadata
,
345 enum radeon_surf_mode
*array_mode
,
348 if (sscreen
->info
.chip_class
>= GFX9
) {
349 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
350 *array_mode
= RADEON_SURF_MODE_2D
;
352 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
354 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
355 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
357 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
359 if (metadata
->u
.gfx9
.dcc_offset_256B
) {
360 surf
->u
.gfx9
.display_dcc_pitch_max
= metadata
->u
.gfx9
.dcc_pitch_max
;
361 assert(metadata
->u
.gfx9
.dcc_independent_64B
== 1);
364 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
365 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
366 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
367 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
368 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
369 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
371 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
372 *array_mode
= RADEON_SURF_MODE_2D
;
373 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
374 *array_mode
= RADEON_SURF_MODE_1D
;
376 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
378 *is_scanout
= metadata
->u
.legacy
.scanout
;
382 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
383 struct si_texture
*tex
)
385 struct si_screen
*sscreen
= sctx
->screen
;
386 struct pipe_context
*ctx
= &sctx
->b
;
388 if (ctx
== sscreen
->aux_context
)
389 mtx_lock(&sscreen
->aux_context_lock
);
391 unsigned n
= sctx
->num_decompress_calls
;
392 ctx
->flush_resource(ctx
, &tex
->buffer
.b
.b
);
394 /* Flush only if any fast clear elimination took place. */
395 if (n
!= sctx
->num_decompress_calls
)
396 ctx
->flush(ctx
, NULL
, 0);
398 if (ctx
== sscreen
->aux_context
)
399 mtx_unlock(&sscreen
->aux_context_lock
);
402 void si_texture_discard_cmask(struct si_screen
*sscreen
,
403 struct si_texture
*tex
)
405 if (!tex
->cmask_buffer
)
408 assert(tex
->buffer
.b
.b
.nr_samples
<= 1);
411 tex
->cmask_base_address_reg
= tex
->buffer
.gpu_address
>> 8;
412 tex
->dirty_level_mask
= 0;
414 tex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
416 if (tex
->cmask_buffer
!= &tex
->buffer
)
417 si_resource_reference(&tex
->cmask_buffer
, NULL
);
419 tex
->cmask_buffer
= NULL
;
421 /* Notify all contexts about the change. */
422 p_atomic_inc(&sscreen
->dirty_tex_counter
);
423 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
426 static bool si_can_disable_dcc(struct si_texture
*tex
)
428 /* We can't disable DCC if it can be written by another process. */
429 return tex
->dcc_offset
&&
430 (!tex
->buffer
.b
.is_shared
||
431 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
));
434 static bool si_texture_discard_dcc(struct si_screen
*sscreen
,
435 struct si_texture
*tex
)
437 if (!si_can_disable_dcc(tex
)) {
438 assert(tex
->display_dcc_offset
== 0);
442 assert(tex
->dcc_separate_buffer
== NULL
);
446 tex
->display_dcc_offset
= 0;
447 tex
->dcc_retile_map_offset
= 0;
449 /* Notify all contexts about the change. */
450 p_atomic_inc(&sscreen
->dirty_tex_counter
);
455 * Disable DCC for the texture. (first decompress, then discard metadata).
457 * There is unresolved multi-context synchronization issue between
458 * screen::aux_context and the current context. If applications do this with
459 * multiple contexts, it's already undefined behavior for them and we don't
460 * have to worry about that. The scenario is:
462 * If context 1 disables DCC and context 2 has queued commands that write
463 * to the texture via CB with DCC enabled, and the order of operations is
465 * context 2 queues draw calls rendering to the texture, but doesn't flush
466 * context 1 disables DCC and flushes
467 * context 1 & 2 reset descriptors and FB state
468 * context 2 flushes (new compressed tiles written by the draw calls)
469 * context 1 & 2 read garbage, because DCC is disabled, yet there are
472 * \param sctx the current context if you have one, or sscreen->aux_context
475 bool si_texture_disable_dcc(struct si_context
*sctx
,
476 struct si_texture
*tex
)
478 struct si_screen
*sscreen
= sctx
->screen
;
480 if (!sctx
->has_graphics
)
481 return si_texture_discard_dcc(sscreen
, tex
);
483 if (!si_can_disable_dcc(tex
))
486 if (&sctx
->b
== sscreen
->aux_context
)
487 mtx_lock(&sscreen
->aux_context_lock
);
489 /* Decompress DCC. */
490 si_decompress_dcc(sctx
, tex
);
491 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
493 if (&sctx
->b
== sscreen
->aux_context
)
494 mtx_unlock(&sscreen
->aux_context_lock
);
496 return si_texture_discard_dcc(sscreen
, tex
);
499 static void si_reallocate_texture_inplace(struct si_context
*sctx
,
500 struct si_texture
*tex
,
501 unsigned new_bind_flag
,
502 bool invalidate_storage
)
504 struct pipe_screen
*screen
= sctx
->b
.screen
;
505 struct si_texture
*new_tex
;
506 struct pipe_resource templ
= tex
->buffer
.b
.b
;
509 templ
.bind
|= new_bind_flag
;
511 if (tex
->buffer
.b
.is_shared
)
514 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
515 if (tex
->surface
.is_linear
)
518 /* This fails with MSAA, depth, and compressed textures. */
519 if (si_choose_tiling(sctx
->screen
, &templ
, false) !=
520 RADEON_SURF_MODE_LINEAR_ALIGNED
)
524 new_tex
= (struct si_texture
*)screen
->resource_create(screen
, &templ
);
528 /* Copy the pixels to the new texture. */
529 if (!invalidate_storage
) {
530 for (i
= 0; i
<= templ
.last_level
; i
++) {
534 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
535 util_num_layers(&templ
, i
), &box
);
537 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0,
538 &tex
->buffer
.b
.b
, i
, &box
);
542 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
543 si_texture_discard_cmask(sctx
->screen
, tex
);
544 si_texture_discard_dcc(sctx
->screen
, tex
);
547 /* Replace the structure fields of tex. */
548 tex
->buffer
.b
.b
.bind
= templ
.bind
;
549 pb_reference(&tex
->buffer
.buf
, new_tex
->buffer
.buf
);
550 tex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
551 tex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
552 tex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
553 tex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
554 tex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
555 tex
->buffer
.domains
= new_tex
->buffer
.domains
;
556 tex
->buffer
.flags
= new_tex
->buffer
.flags
;
558 tex
->surface
= new_tex
->surface
;
559 tex
->size
= new_tex
->size
;
560 si_texture_reference(&tex
->flushed_depth_texture
,
561 new_tex
->flushed_depth_texture
);
563 tex
->fmask_offset
= new_tex
->fmask_offset
;
564 tex
->cmask_offset
= new_tex
->cmask_offset
;
565 tex
->cmask_base_address_reg
= new_tex
->cmask_base_address_reg
;
567 if (tex
->cmask_buffer
== &tex
->buffer
)
568 tex
->cmask_buffer
= NULL
;
570 si_resource_reference(&tex
->cmask_buffer
, NULL
);
572 if (new_tex
->cmask_buffer
== &new_tex
->buffer
)
573 tex
->cmask_buffer
= &tex
->buffer
;
575 si_resource_reference(&tex
->cmask_buffer
, new_tex
->cmask_buffer
);
577 tex
->dcc_offset
= new_tex
->dcc_offset
;
578 tex
->cb_color_info
= new_tex
->cb_color_info
;
579 memcpy(tex
->color_clear_value
, new_tex
->color_clear_value
,
580 sizeof(tex
->color_clear_value
));
581 tex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
583 tex
->htile_offset
= new_tex
->htile_offset
;
584 tex
->depth_clear_value
= new_tex
->depth_clear_value
;
585 tex
->dirty_level_mask
= new_tex
->dirty_level_mask
;
586 tex
->stencil_dirty_level_mask
= new_tex
->stencil_dirty_level_mask
;
587 tex
->db_render_format
= new_tex
->db_render_format
;
588 tex
->stencil_clear_value
= new_tex
->stencil_clear_value
;
589 tex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
590 tex
->depth_cleared
= new_tex
->depth_cleared
;
591 tex
->stencil_cleared
= new_tex
->stencil_cleared
;
592 tex
->upgraded_depth
= new_tex
->upgraded_depth
;
593 tex
->db_compatible
= new_tex
->db_compatible
;
594 tex
->can_sample_z
= new_tex
->can_sample_z
;
595 tex
->can_sample_s
= new_tex
->can_sample_s
;
597 tex
->separate_dcc_dirty
= new_tex
->separate_dcc_dirty
;
598 tex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
599 si_resource_reference(&tex
->dcc_separate_buffer
,
600 new_tex
->dcc_separate_buffer
);
601 si_resource_reference(&tex
->last_dcc_separate_buffer
,
602 new_tex
->last_dcc_separate_buffer
);
604 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
605 assert(!tex
->htile_offset
);
606 assert(!tex
->cmask_buffer
);
607 assert(!tex
->surface
.fmask_size
);
608 assert(!tex
->dcc_offset
);
609 assert(!tex
->is_depth
);
612 si_texture_reference(&new_tex
, NULL
);
614 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
617 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
619 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
622 static void si_set_tex_bo_metadata(struct si_screen
*sscreen
,
623 struct si_texture
*tex
)
625 struct radeon_surf
*surface
= &tex
->surface
;
626 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
627 struct radeon_bo_metadata md
;
629 memset(&md
, 0, sizeof(md
));
631 if (sscreen
->info
.chip_class
>= GFX9
) {
632 md
.u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
634 if (tex
->dcc_offset
&& !tex
->dcc_separate_buffer
) {
635 uint64_t dcc_offset
=
636 tex
->display_dcc_offset
? tex
->display_dcc_offset
639 assert((dcc_offset
>> 8) != 0 && (dcc_offset
>> 8) < (1 << 24));
640 md
.u
.gfx9
.dcc_offset_256B
= dcc_offset
>> 8;
641 md
.u
.gfx9
.dcc_pitch_max
= tex
->surface
.u
.gfx9
.display_dcc_pitch_max
;
642 md
.u
.gfx9
.dcc_independent_64B
= 1;
645 md
.u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
646 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
647 md
.u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
648 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
649 md
.u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
650 md
.u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
651 md
.u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
652 md
.u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
653 md
.u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
654 md
.u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
655 md
.u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
656 md
.u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
659 assert(tex
->dcc_separate_buffer
== NULL
);
660 assert(tex
->surface
.fmask_size
== 0);
662 /* Metadata image format format version 1:
663 * [0] = 1 (metadata format identifier)
664 * [1] = (VENDOR_ID << 16) | PCI_ID
665 * [2:9] = image descriptor for the whole resource
666 * [2] is always 0, because the base address is cleared
667 * [9] is the DCC offset bits [39:8] from the beginning of
669 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
672 md
.metadata
[0] = 1; /* metadata image format version 1 */
674 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
675 md
.metadata
[1] = si_get_bo_metadata_word1(sscreen
);
677 static const unsigned char swizzle
[] = {
683 bool is_array
= util_texture_is_array(res
->target
);
686 si_make_texture_descriptor(sscreen
, tex
, true,
687 res
->target
, res
->format
,
688 swizzle
, 0, res
->last_level
, 0,
689 is_array
? res
->array_size
- 1 : 0,
690 res
->width0
, res
->height0
, res
->depth0
,
693 si_set_mutable_tex_desc_fields(sscreen
, tex
, &tex
->surface
.u
.legacy
.level
[0],
694 0, 0, tex
->surface
.blk_w
, false, desc
);
696 /* Clear the base address and set the relative DCC offset. */
698 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
699 desc
[7] = tex
->dcc_offset
>> 8;
701 /* Dwords [2:9] contain the image descriptor. */
702 memcpy(&md
.metadata
[2], desc
, sizeof(desc
));
703 md
.size_metadata
= 10 * 4;
705 /* Dwords [10:..] contain the mipmap level offsets. */
706 if (sscreen
->info
.chip_class
<= GFX8
) {
707 for (unsigned i
= 0; i
<= res
->last_level
; i
++)
708 md
.metadata
[10+i
] = tex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
710 md
.size_metadata
+= (1 + res
->last_level
) * 4;
713 sscreen
->ws
->buffer_set_metadata(tex
->buffer
.buf
, &md
);
716 static void si_get_opaque_metadata(struct si_screen
*sscreen
,
717 struct si_texture
*tex
,
718 struct radeon_bo_metadata
*md
)
720 uint32_t *desc
= &md
->metadata
[2];
722 if (sscreen
->info
.chip_class
< GFX8
)
725 /* Return if DCC is enabled. The texture should be set up with it
728 if (md
->size_metadata
>= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
729 md
->metadata
[0] != 0 &&
730 md
->metadata
[1] == si_get_bo_metadata_word1(sscreen
) &&
731 G_008F28_COMPRESSION_EN(desc
[6])) {
732 tex
->dcc_offset
= (uint64_t)desc
[7] << 8;
734 if (sscreen
->info
.chip_class
>= GFX9
) {
735 /* Fix up parameters for displayable DCC. Some state
736 * trackers don't set the SCANOUT flag when importing
737 * displayable images, so we have to recover the correct
740 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
=
741 G_008F24_META_PIPE_ALIGNED(desc
[5]);
742 tex
->surface
.u
.gfx9
.dcc
.rb_aligned
=
743 G_008F24_META_RB_ALIGNED(desc
[5]);
745 /* If DCC is unaligned, this can only be a displayable image. */
746 if (!tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&&
747 !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
748 tex
->surface
.is_displayable
= true;
753 /* Disable DCC. These are always set by texture_from_handle and must
759 static bool si_has_displayable_dcc(struct si_texture
*tex
)
761 struct si_screen
*sscreen
= (struct si_screen
*)tex
->buffer
.b
.b
.screen
;
763 if (sscreen
->info
.chip_class
<= GFX8
)
766 /* This needs a cache flush before scanout.
767 * (it can't be scanned out and rendered to simultaneously)
769 if (sscreen
->info
.use_display_dcc_unaligned
&&
771 !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
&&
772 !tex
->surface
.u
.gfx9
.dcc
.rb_aligned
)
775 /* This needs an explicit flush (flush_resource). */
776 if (sscreen
->info
.use_display_dcc_with_retile_blit
&&
777 tex
->display_dcc_offset
)
783 static void si_texture_get_info(struct pipe_screen
* screen
,
784 struct pipe_resource
*resource
,
788 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
789 struct si_texture
*tex
= (struct si_texture
*)resource
;
793 if (!sscreen
|| !tex
)
796 if (resource
->target
!= PIPE_BUFFER
) {
797 if (sscreen
->info
.chip_class
>= GFX9
) {
798 offset
= tex
->surface
.u
.gfx9
.surf_offset
;
799 stride
= tex
->surface
.u
.gfx9
.surf_pitch
*
802 offset
= tex
->surface
.u
.legacy
.level
[0].offset
;
803 stride
= tex
->surface
.u
.legacy
.level
[0].nblk_x
*
815 static boolean
si_texture_get_handle(struct pipe_screen
* screen
,
816 struct pipe_context
*ctx
,
817 struct pipe_resource
*resource
,
818 struct winsys_handle
*whandle
,
821 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
822 struct si_context
*sctx
;
823 struct si_resource
*res
= si_resource(resource
);
824 struct si_texture
*tex
= (struct si_texture
*)resource
;
825 bool update_metadata
= false;
826 unsigned stride
, offset
, slice_size
;
829 ctx
= threaded_context_unwrap_sync(ctx
);
830 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
832 if (resource
->target
!= PIPE_BUFFER
) {
833 /* This is not supported now, but it might be required for OpenCL
834 * interop in the future.
836 if (resource
->nr_samples
> 1 || tex
->is_depth
)
839 /* Move a suballocated texture into a non-suballocated allocation. */
840 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
841 tex
->surface
.tile_swizzle
||
842 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
843 sscreen
->info
.has_local_buffers
&&
844 whandle
->type
!= WINSYS_HANDLE_TYPE_KMS
)) {
845 assert(!res
->b
.is_shared
);
846 si_reallocate_texture_inplace(sctx
, tex
,
847 PIPE_BIND_SHARED
, false);
849 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
850 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
851 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
852 assert(tex
->surface
.tile_swizzle
== 0);
855 /* Since shader image stores don't support DCC on GFX8,
856 * disable it for external clients that want write
859 if ((usage
& PIPE_HANDLE_USAGE_SHADER_WRITE
&& tex
->dcc_offset
) ||
860 /* Displayable DCC requires an explicit flush. */
861 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
862 si_has_displayable_dcc(tex
))) {
863 if (si_texture_disable_dcc(sctx
, tex
)) {
864 update_metadata
= true;
865 /* si_texture_disable_dcc flushes the context */
870 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
871 (tex
->cmask_buffer
|| tex
->dcc_offset
)) {
872 /* Eliminate fast clear (both CMASK and DCC) */
873 si_eliminate_fast_color_clear(sctx
, tex
);
874 /* eliminate_fast_color_clear flushes the context */
877 /* Disable CMASK if flush_resource isn't going
880 if (tex
->cmask_buffer
)
881 si_texture_discard_cmask(sscreen
, tex
);
885 if (!res
->b
.is_shared
|| update_metadata
)
886 si_set_tex_bo_metadata(sscreen
, tex
);
888 if (sscreen
->info
.chip_class
>= GFX9
) {
889 slice_size
= tex
->surface
.u
.gfx9
.surf_slice_size
;
891 slice_size
= (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
894 /* Buffer exports are for the OpenCL interop. */
895 /* Move a suballocated buffer into a non-suballocated allocation. */
896 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
897 /* A DMABUF export always fails if the BO is local. */
898 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
899 sscreen
->info
.has_local_buffers
)) {
900 assert(!res
->b
.is_shared
);
902 /* Allocate a new buffer with PIPE_BIND_SHARED. */
903 struct pipe_resource templ
= res
->b
.b
;
904 templ
.bind
|= PIPE_BIND_SHARED
;
906 struct pipe_resource
*newb
=
907 screen
->resource_create(screen
, &templ
);
911 /* Copy the old buffer contents to the new one. */
913 u_box_1d(0, newb
->width0
, &box
);
914 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0,
917 /* Move the new buffer storage to the old pipe_resource. */
918 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
919 pipe_resource_reference(&newb
, NULL
);
921 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
922 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
929 si_texture_get_info(screen
, resource
, &stride
, &offset
);
932 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
934 if (res
->b
.is_shared
) {
935 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
938 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
939 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
940 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
942 res
->b
.is_shared
= true;
943 res
->external_usage
= usage
;
946 return sscreen
->ws
->buffer_get_handle(sscreen
->ws
, res
->buf
, stride
,
947 offset
, slice_size
, whandle
);
950 static void si_texture_destroy(struct pipe_screen
*screen
,
951 struct pipe_resource
*ptex
)
953 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
954 struct si_texture
*tex
= (struct si_texture
*)ptex
;
955 struct si_resource
*resource
= &tex
->buffer
;
957 if (sscreen
->info
.chip_class
>= GFX9
)
958 free(tex
->surface
.u
.gfx9
.dcc_retile_map
);
960 si_texture_reference(&tex
->flushed_depth_texture
, NULL
);
962 if (tex
->cmask_buffer
!= &tex
->buffer
) {
963 si_resource_reference(&tex
->cmask_buffer
, NULL
);
965 pb_reference(&resource
->buf
, NULL
);
966 si_resource_reference(&tex
->dcc_separate_buffer
, NULL
);
967 si_resource_reference(&tex
->last_dcc_separate_buffer
, NULL
);
971 static const struct u_resource_vtbl si_texture_vtbl
;
973 static void si_texture_get_htile_size(struct si_screen
*sscreen
,
974 struct si_texture
*tex
)
976 unsigned cl_width
, cl_height
, width
, height
;
977 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
978 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
980 assert(sscreen
->info
.chip_class
<= GFX8
);
982 tex
->surface
.htile_size
= 0;
984 if (tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
985 !sscreen
->info
.htile_cmask_support_1d_tiling
)
988 /* Overalign HTILE on P2 configs to work around GPU hangs in
989 * piglit/depthstencil-render-miplevels 585.
991 * This has been confirmed to help Kabini & Stoney, where the hangs
992 * are always reproducible. I think I have seen the test hang
993 * on Carrizo too, though it was very rare there.
995 if (sscreen
->info
.chip_class
>= GFX7
&& num_pipes
< 4)
1024 width
= align(tex
->surface
.u
.legacy
.level
[0].nblk_x
, cl_width
* 8);
1025 height
= align(tex
->surface
.u
.legacy
.level
[0].nblk_y
, cl_height
* 8);
1027 slice_elements
= (width
* height
) / (8 * 8);
1028 slice_bytes
= slice_elements
* 4;
1030 pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
1031 base_align
= num_pipes
* pipe_interleave_bytes
;
1033 tex
->surface
.htile_alignment
= base_align
;
1034 tex
->surface
.htile_size
=
1035 util_num_layers(&tex
->buffer
.b
.b
, 0) *
1036 align(slice_bytes
, base_align
);
1039 static void si_texture_allocate_htile(struct si_screen
*sscreen
,
1040 struct si_texture
*tex
)
1042 if (sscreen
->info
.chip_class
<= GFX8
&& !tex
->tc_compatible_htile
)
1043 si_texture_get_htile_size(sscreen
, tex
);
1045 if (!tex
->surface
.htile_size
)
1048 tex
->htile_offset
= align(tex
->size
, tex
->surface
.htile_alignment
);
1049 tex
->size
= tex
->htile_offset
+ tex
->surface
.htile_size
;
1052 void si_print_texture_info(struct si_screen
*sscreen
,
1053 struct si_texture
*tex
, struct u_log_context
*log
)
1057 /* Common parameters. */
1058 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1059 "blk_h=%u, array_size=%u, last_level=%u, "
1060 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1061 tex
->buffer
.b
.b
.width0
, tex
->buffer
.b
.b
.height0
,
1062 tex
->buffer
.b
.b
.depth0
, tex
->surface
.blk_w
,
1064 tex
->buffer
.b
.b
.array_size
, tex
->buffer
.b
.b
.last_level
,
1065 tex
->surface
.bpe
, tex
->buffer
.b
.b
.nr_samples
,
1066 tex
->surface
.flags
, util_format_short_name(tex
->buffer
.b
.b
.format
));
1068 if (sscreen
->info
.chip_class
>= GFX9
) {
1069 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1070 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1071 tex
->surface
.surf_size
,
1072 tex
->surface
.u
.gfx9
.surf_slice_size
,
1073 tex
->surface
.surf_alignment
,
1074 tex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1075 tex
->surface
.u
.gfx9
.surf
.epitch
,
1076 tex
->surface
.u
.gfx9
.surf_pitch
);
1078 if (tex
->fmask_offset
) {
1079 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1080 "alignment=%u, swmode=%u, epitch=%u\n",
1082 tex
->surface
.fmask_size
,
1083 tex
->surface
.fmask_alignment
,
1084 tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1085 tex
->surface
.u
.gfx9
.fmask
.epitch
);
1088 if (tex
->cmask_buffer
) {
1089 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, "
1090 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1092 tex
->surface
.cmask_size
,
1093 tex
->surface
.cmask_alignment
,
1094 tex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1095 tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1098 if (tex
->htile_offset
) {
1099 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1100 "rb_aligned=%u, pipe_aligned=%u\n",
1102 tex
->surface
.htile_size
,
1103 tex
->surface
.htile_alignment
,
1104 tex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1105 tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1108 if (tex
->dcc_offset
) {
1109 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1110 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1111 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1112 tex
->surface
.dcc_alignment
,
1113 tex
->surface
.u
.gfx9
.display_dcc_pitch_max
,
1114 tex
->surface
.num_dcc_levels
);
1117 if (tex
->surface
.u
.gfx9
.stencil_offset
) {
1118 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1119 tex
->surface
.u
.gfx9
.stencil_offset
,
1120 tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1121 tex
->surface
.u
.gfx9
.stencil
.epitch
);
1126 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1127 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1128 tex
->surface
.surf_size
, tex
->surface
.surf_alignment
, tex
->surface
.u
.legacy
.bankw
,
1129 tex
->surface
.u
.legacy
.bankh
, tex
->surface
.u
.legacy
.num_banks
, tex
->surface
.u
.legacy
.mtilea
,
1130 tex
->surface
.u
.legacy
.tile_split
, tex
->surface
.u
.legacy
.pipe_config
,
1131 (tex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1133 if (tex
->fmask_offset
)
1134 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1135 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1136 tex
->fmask_offset
, tex
->surface
.fmask_size
, tex
->surface
.fmask_alignment
,
1137 tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
,
1138 tex
->surface
.u
.legacy
.fmask
.bankh
,
1139 tex
->surface
.u
.legacy
.fmask
.slice_tile_max
,
1140 tex
->surface
.u
.legacy
.fmask
.tiling_index
);
1142 if (tex
->cmask_buffer
)
1143 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%u, alignment=%u, "
1144 "slice_tile_max=%u\n",
1145 tex
->cmask_offset
, tex
->surface
.cmask_size
, tex
->surface
.cmask_alignment
,
1146 tex
->surface
.u
.legacy
.cmask_slice_tile_max
);
1148 if (tex
->htile_offset
)
1149 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1150 "alignment=%u, TC_compatible = %u\n",
1151 tex
->htile_offset
, tex
->surface
.htile_size
,
1152 tex
->surface
.htile_alignment
,
1153 tex
->tc_compatible_htile
);
1155 if (tex
->dcc_offset
) {
1156 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1157 tex
->dcc_offset
, tex
->surface
.dcc_size
,
1158 tex
->surface
.dcc_alignment
);
1159 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1160 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1161 "fast_clear_size=%u\n",
1162 i
, i
< tex
->surface
.num_dcc_levels
,
1163 tex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1164 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1167 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
1168 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1169 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1170 "mode=%u, tiling_index = %u\n",
1171 i
, tex
->surface
.u
.legacy
.level
[i
].offset
,
1172 (uint64_t)tex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1173 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1174 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1175 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1176 tex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1177 tex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1178 tex
->surface
.u
.legacy
.level
[i
].mode
,
1179 tex
->surface
.u
.legacy
.tiling_index
[i
]);
1181 if (tex
->surface
.has_stencil
) {
1182 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1183 tex
->surface
.u
.legacy
.stencil_tile_split
);
1184 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++) {
1185 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1186 "slice_size=%"PRIu64
", npix_x=%u, "
1187 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1188 "mode=%u, tiling_index = %u\n",
1189 i
, tex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1190 (uint64_t)tex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1191 u_minify(tex
->buffer
.b
.b
.width0
, i
),
1192 u_minify(tex
->buffer
.b
.b
.height0
, i
),
1193 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
1194 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1195 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1196 tex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1197 tex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1202 /* Common processing for si_texture_create and si_texture_from_handle */
1203 static struct si_texture
*
1204 si_texture_create_object(struct pipe_screen
*screen
,
1205 const struct pipe_resource
*base
,
1206 struct pb_buffer
*buf
,
1207 struct radeon_surf
*surface
)
1209 struct si_texture
*tex
;
1210 struct si_resource
*resource
;
1211 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1213 tex
= CALLOC_STRUCT(si_texture
);
1217 resource
= &tex
->buffer
;
1218 resource
->b
.b
= *base
;
1219 resource
->b
.b
.next
= NULL
;
1220 resource
->b
.vtbl
= &si_texture_vtbl
;
1221 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1222 resource
->b
.b
.screen
= screen
;
1224 /* don't include stencil-only formats which we don't support for rendering */
1225 tex
->is_depth
= util_format_has_depth(util_format_description(tex
->buffer
.b
.b
.format
));
1227 tex
->surface
= *surface
;
1228 tex
->size
= tex
->surface
.surf_size
;
1230 tex
->tc_compatible_htile
= tex
->surface
.htile_size
!= 0 &&
1231 (tex
->surface
.flags
&
1232 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1234 /* TC-compatible HTILE:
1235 * - GFX8 only supports Z32_FLOAT.
1236 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1237 if (tex
->tc_compatible_htile
) {
1238 if (sscreen
->info
.chip_class
>= GFX9
&&
1239 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1240 tex
->db_render_format
= base
->format
;
1242 tex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1243 tex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1244 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1247 tex
->db_render_format
= base
->format
;
1250 /* Applies to GCN. */
1251 tex
->last_msaa_resolve_target_micro_mode
= tex
->surface
.micro_tile_mode
;
1253 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1254 * between frames, so the only thing that can enable separate DCC
1255 * with DRI2 is multiple slow clears within a frame.
1257 tex
->ps_draw_ratio
= 0;
1259 if (tex
->is_depth
) {
1260 if (sscreen
->info
.chip_class
>= GFX9
) {
1261 tex
->can_sample_z
= true;
1262 tex
->can_sample_s
= true;
1264 tex
->can_sample_z
= !tex
->surface
.u
.legacy
.depth_adjusted
;
1265 tex
->can_sample_s
= !tex
->surface
.u
.legacy
.stencil_adjusted
;
1268 if (!(base
->flags
& (SI_RESOURCE_FLAG_TRANSFER
|
1269 SI_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1270 tex
->db_compatible
= true;
1272 if (!(sscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1273 si_texture_allocate_htile(sscreen
, tex
);
1276 if (base
->nr_samples
> 1 &&
1278 !(sscreen
->debug_flags
& DBG(NO_FMASK
))) {
1279 /* Allocate FMASK. */
1280 tex
->fmask_offset
= align64(tex
->size
,
1281 tex
->surface
.fmask_alignment
);
1282 tex
->size
= tex
->fmask_offset
+ tex
->surface
.fmask_size
;
1284 /* Allocate CMASK. */
1285 tex
->cmask_offset
= align64(tex
->size
, tex
->surface
.cmask_alignment
);
1286 tex
->size
= tex
->cmask_offset
+ tex
->surface
.cmask_size
;
1287 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
1288 tex
->cmask_buffer
= &tex
->buffer
;
1290 if (!tex
->surface
.fmask_size
|| !tex
->surface
.cmask_size
)
1294 /* Shared textures must always set up DCC here.
1295 * If it's not present, it will be disabled by
1296 * apply_opaque_metadata later.
1298 if (tex
->surface
.dcc_size
&&
1299 (buf
|| !(sscreen
->debug_flags
& DBG(NO_DCC
))) &&
1300 (sscreen
->info
.use_display_dcc_unaligned
||
1301 sscreen
->info
.use_display_dcc_with_retile_blit
||
1302 !(tex
->surface
.flags
& RADEON_SURF_SCANOUT
))) {
1303 /* Add space for the DCC buffer. */
1304 tex
->dcc_offset
= align64(tex
->size
, tex
->surface
.dcc_alignment
);
1305 tex
->size
= tex
->dcc_offset
+ tex
->surface
.dcc_size
;
1307 if (sscreen
->info
.chip_class
>= GFX9
&&
1308 tex
->surface
.u
.gfx9
.dcc_retile_num_elements
) {
1309 /* Add space for the displayable DCC buffer. */
1310 tex
->display_dcc_offset
=
1311 align64(tex
->size
, tex
->surface
.u
.gfx9
.display_dcc_alignment
);
1312 tex
->size
= tex
->display_dcc_offset
+
1313 tex
->surface
.u
.gfx9
.display_dcc_size
;
1315 /* Add space for the DCC retile buffer. (16-bit or 32-bit elements) */
1316 tex
->dcc_retile_map_offset
=
1317 align64(tex
->size
, sscreen
->info
.tcc_cache_line_size
);
1319 if (tex
->surface
.u
.gfx9
.dcc_retile_use_uint16
) {
1320 tex
->size
= tex
->dcc_retile_map_offset
+
1321 tex
->surface
.u
.gfx9
.dcc_retile_num_elements
* 2;
1323 tex
->size
= tex
->dcc_retile_map_offset
+
1324 tex
->surface
.u
.gfx9
.dcc_retile_num_elements
* 4;
1330 /* Now create the backing buffer. */
1332 si_init_resource_fields(sscreen
, resource
, tex
->size
,
1333 tex
->surface
.surf_alignment
);
1335 if (!si_alloc_resource(sscreen
, resource
))
1338 resource
->buf
= buf
;
1339 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1340 resource
->bo_size
= buf
->size
;
1341 resource
->bo_alignment
= buf
->alignment
;
1342 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1343 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1344 resource
->vram_usage
= buf
->size
;
1345 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1346 resource
->gart_usage
= buf
->size
;
1349 if (tex
->cmask_buffer
) {
1350 /* Initialize the cmask to 0xCC (= compressed state). */
1351 si_screen_clear_buffer(sscreen
, &tex
->cmask_buffer
->b
.b
,
1352 tex
->cmask_offset
, tex
->surface
.cmask_size
,
1355 if (tex
->htile_offset
) {
1356 uint32_t clear_value
= 0;
1358 if (sscreen
->info
.chip_class
>= GFX9
|| tex
->tc_compatible_htile
)
1359 clear_value
= 0x0000030F;
1361 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1363 tex
->surface
.htile_size
,
1367 /* Initialize DCC only if the texture is not being imported. */
1368 if (!buf
&& tex
->dcc_offset
) {
1369 /* Clear DCC to black for all tiles with DCC enabled.
1371 * This fixes corruption in 3DMark Slingshot Extreme, which
1372 * uses uninitialized textures, causing corruption.
1374 if (tex
->surface
.num_dcc_levels
== tex
->buffer
.b
.b
.last_level
+ 1 &&
1375 tex
->buffer
.b
.b
.nr_samples
<= 2) {
1376 /* Simple case - all tiles have DCC enabled. */
1377 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1379 tex
->surface
.dcc_size
,
1380 DCC_CLEAR_COLOR_0000
);
1381 } else if (sscreen
->info
.chip_class
>= GFX9
) {
1382 /* Clear to uncompressed. Clearing this to black is complicated. */
1383 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1385 tex
->surface
.dcc_size
,
1388 /* GFX8: Initialize mipmap levels and multisamples separately. */
1389 if (tex
->buffer
.b
.b
.nr_samples
>= 2) {
1390 /* Clearing this to black is complicated. */
1391 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1393 tex
->surface
.dcc_size
,
1396 /* Clear the enabled mipmap levels to black. */
1399 for (unsigned i
= 0; i
< tex
->surface
.num_dcc_levels
; i
++) {
1400 if (!tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
)
1403 size
= tex
->surface
.u
.legacy
.level
[i
].dcc_offset
+
1404 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
;
1407 /* Mipmap levels with DCC. */
1409 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1410 tex
->dcc_offset
, size
,
1411 DCC_CLEAR_COLOR_0000
);
1413 /* Mipmap levels without DCC. */
1414 if (size
!= tex
->surface
.dcc_size
) {
1415 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
,
1416 tex
->dcc_offset
+ size
,
1417 tex
->surface
.dcc_size
- size
,
1423 /* Upload the DCC retile map. */
1424 if (tex
->dcc_retile_map_offset
) {
1425 /* Use a staging buffer for the upload, because
1426 * the buffer backing the texture is unmappable.
1428 bool use_uint16
= tex
->surface
.u
.gfx9
.dcc_retile_use_uint16
;
1429 unsigned num_elements
= tex
->surface
.u
.gfx9
.dcc_retile_num_elements
;
1430 struct si_resource
*buf
=
1431 si_aligned_buffer_create(screen
, 0, PIPE_USAGE_STREAM
,
1432 num_elements
* (use_uint16
? 2 : 4),
1433 sscreen
->info
.tcc_cache_line_size
);
1434 uint32_t *ui
= (uint32_t*)sscreen
->ws
->buffer_map(buf
->buf
, NULL
,
1435 PIPE_TRANSFER_WRITE
);
1436 uint16_t *us
= (uint16_t*)ui
;
1438 /* Upload the retile map into a staging buffer. */
1440 for (unsigned i
= 0; i
< num_elements
; i
++)
1441 us
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1443 for (unsigned i
= 0; i
< num_elements
; i
++)
1444 ui
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1447 /* Copy the staging buffer to the buffer backing the texture. */
1448 struct si_context
*sctx
= (struct si_context
*)sscreen
->aux_context
;
1449 struct pipe_box box
;
1450 u_box_1d(0, buf
->b
.b
.width0
, &box
);
1452 assert(tex
->dcc_retile_map_offset
<= UINT_MAX
);
1453 mtx_lock(&sscreen
->aux_context_lock
);
1454 sctx
->dma_copy(&sctx
->b
, &tex
->buffer
.b
.b
, 0,
1455 tex
->dcc_retile_map_offset
, 0, 0,
1456 &buf
->b
.b
, 0, &box
);
1457 sscreen
->aux_context
->flush(sscreen
->aux_context
, NULL
, 0);
1458 mtx_unlock(&sscreen
->aux_context_lock
);
1460 si_resource_reference(&buf
, NULL
);
1464 /* Initialize the CMASK base register value. */
1465 tex
->cmask_base_address_reg
=
1466 (tex
->buffer
.gpu_address
+ tex
->cmask_offset
) >> 8;
1468 if (sscreen
->debug_flags
& DBG(VM
)) {
1469 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1470 tex
->buffer
.gpu_address
,
1471 tex
->buffer
.gpu_address
+ tex
->buffer
.buf
->size
,
1472 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1473 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1476 if (sscreen
->debug_flags
& DBG(TEX
)) {
1478 struct u_log_context log
;
1479 u_log_context_init(&log
);
1480 si_print_texture_info(sscreen
, tex
, &log
);
1481 u_log_new_page_print(&log
, stdout
);
1483 u_log_context_destroy(&log
);
1490 if (sscreen
->info
.chip_class
>= GFX9
)
1491 free(surface
->u
.gfx9
.dcc_retile_map
);
1495 static enum radeon_surf_mode
1496 si_choose_tiling(struct si_screen
*sscreen
,
1497 const struct pipe_resource
*templ
, bool tc_compatible_htile
)
1499 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1500 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
;
1501 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1502 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1504 /* MSAA resources must be 2D tiled. */
1505 if (templ
->nr_samples
> 1)
1506 return RADEON_SURF_MODE_2D
;
1508 /* Transfer resources should be linear. */
1509 if (templ
->flags
& SI_RESOURCE_FLAG_TRANSFER
)
1510 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1512 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on GFX8,
1513 * which requires 2D tiling.
1515 if (sscreen
->info
.chip_class
== GFX8
&& tc_compatible_htile
)
1516 return RADEON_SURF_MODE_2D
;
1518 /* Handle common candidates for the linear mode.
1519 * Compressed textures and DB surfaces must always be tiled.
1521 if (!force_tiling
&&
1522 !is_depth_stencil
&&
1523 !util_format_is_compressed(templ
->format
)) {
1524 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1525 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1527 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1528 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1529 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1531 /* Cursors are linear on AMD GCN.
1532 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1533 if (templ
->bind
& PIPE_BIND_CURSOR
)
1534 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1536 if (templ
->bind
& PIPE_BIND_LINEAR
)
1537 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1539 /* Textures with a very small height are recommended to be linear. */
1540 if (templ
->target
== PIPE_TEXTURE_1D
||
1541 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1542 /* Only very thin and long 2D textures should benefit from
1543 * linear_aligned. */
1544 (templ
->width0
> 8 && templ
->height0
<= 2))
1545 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1547 /* Textures likely to be mapped often. */
1548 if (templ
->usage
== PIPE_USAGE_STAGING
||
1549 templ
->usage
== PIPE_USAGE_STREAM
)
1550 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1553 /* Make small textures 1D tiled. */
1554 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1555 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1556 return RADEON_SURF_MODE_1D
;
1558 /* The allocator will switch to 1D if needed. */
1559 return RADEON_SURF_MODE_2D
;
1562 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1563 const struct pipe_resource
*templ
)
1565 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1566 bool is_zs
= util_format_is_depth_or_stencil(templ
->format
);
1568 if (templ
->nr_samples
>= 2) {
1569 /* This is hackish (overwriting the const pipe_resource template),
1570 * but should be harmless and state trackers can also see
1571 * the overriden number of samples in the created pipe_resource.
1573 if (is_zs
&& sscreen
->eqaa_force_z_samples
) {
1574 ((struct pipe_resource
*)templ
)->nr_samples
=
1575 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1576 sscreen
->eqaa_force_z_samples
;
1577 } else if (!is_zs
&& sscreen
->eqaa_force_color_samples
) {
1578 ((struct pipe_resource
*)templ
)->nr_samples
=
1579 sscreen
->eqaa_force_coverage_samples
;
1580 ((struct pipe_resource
*)templ
)->nr_storage_samples
=
1581 sscreen
->eqaa_force_color_samples
;
1585 struct radeon_surf surface
= {0};
1586 bool is_flushed_depth
= templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1587 bool tc_compatible_htile
=
1588 sscreen
->info
.chip_class
>= GFX8
&&
1589 /* There are issues with TC-compatible HTILE on Tonga (and
1590 * Iceland is the same design), and documented bug workarounds
1591 * don't help. For example, this fails:
1592 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1594 sscreen
->info
.family
!= CHIP_TONGA
&&
1595 sscreen
->info
.family
!= CHIP_ICELAND
&&
1596 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1597 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1598 !is_flushed_depth
&&
1599 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1603 r
= si_init_surface(sscreen
, &surface
, templ
,
1604 si_choose_tiling(sscreen
, templ
, tc_compatible_htile
),
1605 0, 0, false, false, is_flushed_depth
,
1606 tc_compatible_htile
);
1611 return (struct pipe_resource
*)
1612 si_texture_create_object(screen
, templ
, NULL
, &surface
);
1615 static struct pipe_resource
*si_texture_from_winsys_buffer(struct si_screen
*sscreen
,
1616 const struct pipe_resource
*templ
,
1617 struct pb_buffer
*buf
,
1623 enum radeon_surf_mode array_mode
;
1624 struct radeon_surf surface
= {};
1625 struct radeon_bo_metadata metadata
= {};
1626 struct si_texture
*tex
;
1631 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1632 si_get_display_metadata(sscreen
, &surface
, &metadata
,
1633 &array_mode
, &is_scanout
);
1636 * The bo metadata is unset for un-dedicated images. So we fall
1637 * back to linear. See answer to question 5 of the
1638 * VK_KHX_external_memory spec for some details.
1640 * It is possible that this case isn't going to work if the
1641 * surface pitch isn't correctly aligned by default.
1643 * In order to support it correctly we require multi-image
1644 * metadata to be syncrhonized between radv and radeonsi. The
1645 * semantics of associating multiple image metadata to a memory
1646 * object on the vulkan export side are not concretely defined
1649 * All the use cases we are aware of at the moment for memory
1650 * objects use dedicated allocations. So lets keep the initial
1651 * implementation simple.
1653 * A possible alternative is to attempt to reconstruct the
1654 * tiling information when the TexParameter TEXTURE_TILING_EXT
1657 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1661 r
= si_init_surface(sscreen
, &surface
, templ
,
1662 array_mode
, stride
, offset
, true, is_scanout
,
1667 tex
= si_texture_create_object(&sscreen
->b
, templ
, buf
, &surface
);
1671 tex
->buffer
.b
.is_shared
= true;
1672 tex
->buffer
.external_usage
= usage
;
1674 si_get_opaque_metadata(sscreen
, tex
, &metadata
);
1676 /* Displayable DCC requires an explicit flush. */
1678 !(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
1679 si_has_displayable_dcc(tex
)) {
1680 /* TODO: do we need to decompress DCC? */
1681 if (si_texture_discard_dcc(sscreen
, tex
)) {
1682 /* Update BO metadata after disabling DCC. */
1683 si_set_tex_bo_metadata(sscreen
, tex
);
1687 assert(tex
->surface
.tile_swizzle
== 0);
1688 return &tex
->buffer
.b
.b
;
1691 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1692 const struct pipe_resource
*templ
,
1693 struct winsys_handle
*whandle
,
1696 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1697 struct pb_buffer
*buf
= NULL
;
1698 unsigned stride
= 0, offset
= 0;
1700 /* Support only 2D textures without mipmaps */
1701 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1702 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1705 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
1706 sscreen
->info
.max_alignment
,
1711 return si_texture_from_winsys_buffer(sscreen
, templ
, buf
, stride
,
1712 offset
, usage
, true);
1715 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1716 struct pipe_resource
*texture
)
1718 struct si_texture
*tex
= (struct si_texture
*)texture
;
1719 struct pipe_resource resource
;
1720 enum pipe_format pipe_format
= texture
->format
;
1722 assert(!tex
->flushed_depth_texture
);
1724 if (!tex
->can_sample_z
&& tex
->can_sample_s
) {
1725 switch (pipe_format
) {
1726 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1727 /* Save memory by not allocating the S plane. */
1728 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1730 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1731 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1732 /* Save memory bandwidth by not copying the
1733 * stencil part during flush.
1735 * This potentially increases memory bandwidth
1736 * if an application uses both Z and S texturing
1737 * simultaneously (a flushed Z24S8 texture
1738 * would be stored compactly), but how often
1739 * does that really happen?
1741 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1745 } else if (!tex
->can_sample_s
&& tex
->can_sample_z
) {
1746 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1748 /* DB->CB copies to an 8bpp surface don't work. */
1749 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1752 memset(&resource
, 0, sizeof(resource
));
1753 resource
.target
= texture
->target
;
1754 resource
.format
= pipe_format
;
1755 resource
.width0
= texture
->width0
;
1756 resource
.height0
= texture
->height0
;
1757 resource
.depth0
= texture
->depth0
;
1758 resource
.array_size
= texture
->array_size
;
1759 resource
.last_level
= texture
->last_level
;
1760 resource
.nr_samples
= texture
->nr_samples
;
1761 resource
.usage
= PIPE_USAGE_DEFAULT
;
1762 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1763 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1765 tex
->flushed_depth_texture
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1766 if (!tex
->flushed_depth_texture
) {
1767 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1774 * Initialize the pipe_resource descriptor to be of the same size as the box,
1775 * which is supposed to hold a subregion of the texture "orig" at the given
1778 static void si_init_temp_resource_from_box(struct pipe_resource
*res
,
1779 struct pipe_resource
*orig
,
1780 const struct pipe_box
*box
,
1781 unsigned level
, unsigned flags
)
1783 memset(res
, 0, sizeof(*res
));
1784 res
->format
= orig
->format
;
1785 res
->width0
= box
->width
;
1786 res
->height0
= box
->height
;
1788 res
->array_size
= 1;
1789 res
->usage
= flags
& SI_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1792 if (flags
& SI_RESOURCE_FLAG_TRANSFER
&&
1793 util_format_is_compressed(orig
->format
)) {
1794 /* Transfer resources are allocated with linear tiling, which is
1795 * not supported for compressed formats.
1797 unsigned blocksize
=
1798 util_format_get_blocksize(orig
->format
);
1800 if (blocksize
== 8) {
1801 res
->format
= PIPE_FORMAT_R16G16B16A16_UINT
;
1803 assert(blocksize
== 16);
1804 res
->format
= PIPE_FORMAT_R32G32B32A32_UINT
;
1807 res
->width0
= util_format_get_nblocksx(orig
->format
, box
->width
);
1808 res
->height0
= util_format_get_nblocksy(orig
->format
, box
->height
);
1811 /* We must set the correct texture target and dimensions for a 3D box. */
1812 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1813 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1814 res
->array_size
= box
->depth
;
1816 res
->target
= PIPE_TEXTURE_2D
;
1820 static bool si_can_invalidate_texture(struct si_screen
*sscreen
,
1821 struct si_texture
*tex
,
1822 unsigned transfer_usage
,
1823 const struct pipe_box
*box
)
1825 return !tex
->buffer
.b
.is_shared
&&
1826 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1827 tex
->buffer
.b
.b
.last_level
== 0 &&
1828 util_texrange_covers_whole_level(&tex
->buffer
.b
.b
, 0,
1829 box
->x
, box
->y
, box
->z
,
1830 box
->width
, box
->height
,
1834 static void si_texture_invalidate_storage(struct si_context
*sctx
,
1835 struct si_texture
*tex
)
1837 struct si_screen
*sscreen
= sctx
->screen
;
1839 /* There is no point in discarding depth and tiled buffers. */
1840 assert(!tex
->is_depth
);
1841 assert(tex
->surface
.is_linear
);
1843 /* Reallocate the buffer in the same pipe_resource. */
1844 si_alloc_resource(sscreen
, &tex
->buffer
);
1846 /* Initialize the CMASK base address (needed even without CMASK). */
1847 tex
->cmask_base_address_reg
=
1848 (tex
->buffer
.gpu_address
+ tex
->cmask_offset
) >> 8;
1850 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1852 sctx
->num_alloc_tex_transfer_bytes
+= tex
->size
;
1855 static void *si_texture_transfer_map(struct pipe_context
*ctx
,
1856 struct pipe_resource
*texture
,
1859 const struct pipe_box
*box
,
1860 struct pipe_transfer
**ptransfer
)
1862 struct si_context
*sctx
= (struct si_context
*)ctx
;
1863 struct si_texture
*tex
= (struct si_texture
*)texture
;
1864 struct si_transfer
*trans
;
1865 struct si_resource
*buf
;
1866 unsigned offset
= 0;
1868 bool use_staging_texture
= false;
1870 assert(!(texture
->flags
& SI_RESOURCE_FLAG_TRANSFER
));
1871 assert(box
->width
&& box
->height
&& box
->depth
);
1873 if (tex
->is_depth
) {
1874 /* Depth textures use staging unconditionally. */
1875 use_staging_texture
= true;
1877 /* Degrade the tile mode if we get too many transfers on APUs.
1878 * On dGPUs, the staging texture is always faster.
1879 * Only count uploads that are at least 4x4 pixels large.
1881 if (!sctx
->screen
->info
.has_dedicated_vram
&&
1883 box
->width
>= 4 && box
->height
>= 4 &&
1884 p_atomic_inc_return(&tex
->num_level0_transfers
) == 10) {
1885 bool can_invalidate
=
1886 si_can_invalidate_texture(sctx
->screen
, tex
,
1889 si_reallocate_texture_inplace(sctx
, tex
,
1894 /* Tiled textures need to be converted into a linear texture for CPU
1895 * access. The staging texture is always linear and is placed in GART.
1897 * Reading from VRAM or GTT WC is slow, always use the staging
1898 * texture in this case.
1900 * Use the staging texture for uploads if the underlying BO
1903 if (!tex
->surface
.is_linear
)
1904 use_staging_texture
= true;
1905 else if (usage
& PIPE_TRANSFER_READ
)
1906 use_staging_texture
=
1907 tex
->buffer
.domains
& RADEON_DOMAIN_VRAM
||
1908 tex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
1909 /* Write & linear only: */
1910 else if (si_rings_is_buffer_referenced(sctx
, tex
->buffer
.buf
,
1911 RADEON_USAGE_READWRITE
) ||
1912 !sctx
->ws
->buffer_wait(tex
->buffer
.buf
, 0,
1913 RADEON_USAGE_READWRITE
)) {
1915 if (si_can_invalidate_texture(sctx
->screen
, tex
,
1917 si_texture_invalidate_storage(sctx
, tex
);
1919 use_staging_texture
= true;
1923 trans
= CALLOC_STRUCT(si_transfer
);
1926 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1927 trans
->b
.b
.level
= level
;
1928 trans
->b
.b
.usage
= usage
;
1929 trans
->b
.b
.box
= *box
;
1931 if (use_staging_texture
) {
1932 struct pipe_resource resource
;
1933 struct si_texture
*staging
;
1935 si_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1936 SI_RESOURCE_FLAG_TRANSFER
);
1937 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1938 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1940 /* Since depth-stencil textures don't support linear tiling,
1941 * blit from ZS to color and vice versa. u_blitter will do
1942 * the packing for these formats.
1945 resource
.format
= util_blitter_get_color_format_for_zs(resource
.format
);
1947 /* Create the temporary texture. */
1948 staging
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1950 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1953 trans
->staging
= &staging
->buffer
;
1955 /* Just get the strides. */
1956 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
,
1958 &trans
->b
.b
.layer_stride
);
1960 if (usage
& PIPE_TRANSFER_READ
)
1961 si_copy_to_staging_texture(ctx
, trans
);
1963 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1965 buf
= trans
->staging
;
1967 /* the resource is mapped directly */
1968 offset
= si_texture_get_offset(sctx
->screen
, tex
, level
, box
,
1970 &trans
->b
.b
.layer_stride
);
1974 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1975 * we don't run out of the CPU address space.
1977 if (sizeof(void*) == 4)
1978 usage
|= RADEON_TRANSFER_TEMPORARY
;
1980 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
1983 *ptransfer
= &trans
->b
.b
;
1984 return map
+ offset
;
1987 si_resource_reference(&trans
->staging
, NULL
);
1988 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
1993 static void si_texture_transfer_unmap(struct pipe_context
*ctx
,
1994 struct pipe_transfer
* transfer
)
1996 struct si_context
*sctx
= (struct si_context
*)ctx
;
1997 struct si_transfer
*stransfer
= (struct si_transfer
*)transfer
;
1998 struct pipe_resource
*texture
= transfer
->resource
;
1999 struct si_texture
*tex
= (struct si_texture
*)texture
;
2001 /* Always unmap texture CPU mappings on 32-bit architectures, so that
2002 * we don't run out of the CPU address space.
2004 if (sizeof(void*) == 4) {
2005 struct si_resource
*buf
=
2006 stransfer
->staging
? stransfer
->staging
: &tex
->buffer
;
2008 sctx
->ws
->buffer_unmap(buf
->buf
);
2011 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && stransfer
->staging
)
2012 si_copy_from_staging_texture(ctx
, stransfer
);
2014 if (stransfer
->staging
) {
2015 sctx
->num_alloc_tex_transfer_bytes
+= stransfer
->staging
->buf
->size
;
2016 si_resource_reference(&stransfer
->staging
, NULL
);
2019 /* Heuristic for {upload, draw, upload, draw, ..}:
2021 * Flush the gfx IB if we've allocated too much texture storage.
2023 * The idea is that we don't want to build IBs that use too much
2024 * memory and put pressure on the kernel memory manager and we also
2025 * want to make temporary and invalidated buffers go idle ASAP to
2026 * decrease the total memory usage or make them reusable. The memory
2027 * usage will be slightly higher than given here because of the buffer
2028 * cache in the winsys.
2030 * The result is that the kernel memory manager is never a bottleneck.
2032 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
2033 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
2034 sctx
->num_alloc_tex_transfer_bytes
= 0;
2037 pipe_resource_reference(&transfer
->resource
, NULL
);
2041 static const struct u_resource_vtbl si_texture_vtbl
=
2043 NULL
, /* get_handle */
2044 si_texture_destroy
, /* resource_destroy */
2045 si_texture_transfer_map
, /* transfer_map */
2046 u_default_transfer_flush_region
, /* transfer_flush_region */
2047 si_texture_transfer_unmap
, /* transfer_unmap */
2050 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
2052 bool vi_dcc_formats_compatible(enum pipe_format format1
,
2053 enum pipe_format format2
)
2055 const struct util_format_description
*desc1
, *desc2
;
2057 /* No format change - exit early. */
2058 if (format1
== format2
)
2061 format1
= si_simplify_cb_format(format1
);
2062 format2
= si_simplify_cb_format(format2
);
2064 /* Check again after format adjustments. */
2065 if (format1
== format2
)
2068 desc1
= util_format_description(format1
);
2069 desc2
= util_format_description(format2
);
2071 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2072 desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2075 /* Float and non-float are totally incompatible. */
2076 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
2077 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
2080 /* Channel sizes must match across DCC formats.
2081 * Comparing just the first 2 channels should be enough.
2083 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
2084 (desc1
->nr_channels
>= 2 &&
2085 desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
2088 /* Everything below is not needed if the driver never uses the DCC
2089 * clear code with the value of 1.
2092 /* If the clear values are all 1 or all 0, this constraint can be
2094 if (vi_alpha_is_on_msb(format1
) != vi_alpha_is_on_msb(format2
))
2097 /* Channel types must match if the clear value of 1 is used.
2098 * The type categories are only float, signed, unsigned.
2099 * NORM and INT are always compatible.
2101 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
2102 (desc1
->nr_channels
>= 2 &&
2103 desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
2109 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
2111 enum pipe_format view_format
)
2113 struct si_texture
*stex
= (struct si_texture
*)tex
;
2115 return vi_dcc_enabled(stex
, level
) &&
2116 !vi_dcc_formats_compatible(tex
->format
, view_format
);
2119 /* This can't be merged with the above function, because
2120 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
2121 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
2122 struct pipe_resource
*tex
,
2124 enum pipe_format view_format
)
2126 struct si_texture
*stex
= (struct si_texture
*)tex
;
2128 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
2129 if (!si_texture_disable_dcc(sctx
, stex
))
2130 si_decompress_dcc(sctx
, stex
);
2133 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
2134 struct pipe_resource
*texture
,
2135 const struct pipe_surface
*templ
,
2136 unsigned width0
, unsigned height0
,
2137 unsigned width
, unsigned height
)
2139 struct si_surface
*surface
= CALLOC_STRUCT(si_surface
);
2144 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2145 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
2147 pipe_reference_init(&surface
->base
.reference
, 1);
2148 pipe_resource_reference(&surface
->base
.texture
, texture
);
2149 surface
->base
.context
= pipe
;
2150 surface
->base
.format
= templ
->format
;
2151 surface
->base
.width
= width
;
2152 surface
->base
.height
= height
;
2153 surface
->base
.u
= templ
->u
;
2155 surface
->width0
= width0
;
2156 surface
->height0
= height0
;
2158 surface
->dcc_incompatible
=
2159 texture
->target
!= PIPE_BUFFER
&&
2160 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
2162 return &surface
->base
;
2165 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
,
2166 struct pipe_resource
*tex
,
2167 const struct pipe_surface
*templ
)
2169 unsigned level
= templ
->u
.tex
.level
;
2170 unsigned width
= u_minify(tex
->width0
, level
);
2171 unsigned height
= u_minify(tex
->height0
, level
);
2172 unsigned width0
= tex
->width0
;
2173 unsigned height0
= tex
->height0
;
2175 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2176 const struct util_format_description
*tex_desc
2177 = util_format_description(tex
->format
);
2178 const struct util_format_description
*templ_desc
2179 = util_format_description(templ
->format
);
2181 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2183 /* Adjust size of surface if and only if the block width or
2184 * height is changed. */
2185 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2186 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2187 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2188 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2190 width
= nblks_x
* templ_desc
->block
.width
;
2191 height
= nblks_y
* templ_desc
->block
.height
;
2193 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2194 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2198 return si_create_surface_custom(pipe
, tex
, templ
,
2203 static void si_surface_destroy(struct pipe_context
*pipe
,
2204 struct pipe_surface
*surface
)
2206 pipe_resource_reference(&surface
->texture
, NULL
);
2210 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2212 const struct util_format_description
*desc
= util_format_description(format
);
2214 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2216 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2217 return V_028C70_SWAP_STD
;
2219 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2222 switch (desc
->nr_channels
) {
2224 if (HAS_SWIZZLE(0,X
))
2225 return V_028C70_SWAP_STD
; /* X___ */
2226 else if (HAS_SWIZZLE(3,X
))
2227 return V_028C70_SWAP_ALT_REV
; /* ___X */
2230 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2231 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2232 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2233 return V_028C70_SWAP_STD
; /* XY__ */
2234 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2235 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2236 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2238 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2239 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2240 return V_028C70_SWAP_ALT
; /* X__Y */
2241 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2242 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2245 if (HAS_SWIZZLE(0,X
))
2246 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2247 else if (HAS_SWIZZLE(0,Z
))
2248 return V_028C70_SWAP_STD_REV
; /* ZYX */
2251 /* check the middle channels, the 1st and 4th channel can be NONE */
2252 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2253 return V_028C70_SWAP_STD
; /* XYZW */
2254 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2255 return V_028C70_SWAP_STD_REV
; /* WZYX */
2256 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2257 return V_028C70_SWAP_ALT
; /* ZYXW */
2258 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2261 return V_028C70_SWAP_ALT_REV
;
2263 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2270 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2272 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
,
2277 if (sctx
->dcc_stats
[slot
].query_active
)
2278 vi_separate_dcc_stop_query(sctx
,
2279 sctx
->dcc_stats
[slot
].tex
);
2281 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2282 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2283 sctx
->b
.destroy_query(&sctx
->b
,
2284 sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2285 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2288 si_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2292 * Return the per-context slot where DCC statistics queries for the texture live.
2294 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
,
2295 struct si_texture
*tex
)
2297 int i
, empty_slot
= -1;
2299 /* Remove zombie textures (textures kept alive by this array only). */
2300 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2301 if (sctx
->dcc_stats
[i
].tex
&&
2302 sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2303 vi_dcc_clean_up_context_slot(sctx
, i
);
2305 /* Find the texture. */
2306 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2307 /* Return if found. */
2308 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2309 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2313 /* Record the first seen empty slot. */
2314 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2318 /* Not found. Remove the oldest member to make space in the array. */
2319 if (empty_slot
== -1) {
2320 int oldest_slot
= 0;
2322 /* Find the oldest slot. */
2323 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2324 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2325 sctx
->dcc_stats
[i
].last_use_timestamp
)
2328 /* Clean up the oldest slot. */
2329 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2330 empty_slot
= oldest_slot
;
2333 /* Add the texture to the new slot. */
2334 si_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2335 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2339 static struct pipe_query
*
2340 vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2342 struct si_query_hw
*query
= (struct si_query_hw
*)
2343 sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2345 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2346 return (struct pipe_query
*)query
;
2350 * Called when binding a color buffer.
2352 void vi_separate_dcc_start_query(struct si_context
*sctx
,
2353 struct si_texture
*tex
)
2355 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2357 assert(!sctx
->dcc_stats
[i
].query_active
);
2359 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2360 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2362 /* begin or resume the query */
2363 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2364 sctx
->dcc_stats
[i
].query_active
= true;
2368 * Called when unbinding a color buffer.
2370 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
2371 struct si_texture
*tex
)
2373 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2375 assert(sctx
->dcc_stats
[i
].query_active
);
2376 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2378 /* pause or end the query */
2379 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2380 sctx
->dcc_stats
[i
].query_active
= false;
2383 static bool vi_should_enable_separate_dcc(struct si_texture
*tex
)
2385 /* The minimum number of fullscreen draws per frame that is required
2387 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2390 /* Called by fast clear. */
2391 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
2392 struct si_texture
*tex
)
2394 /* The intent is to use this with shared displayable back buffers,
2395 * but it's not strictly limited only to them.
2397 if (!tex
->buffer
.b
.is_shared
||
2398 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2399 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2400 tex
->buffer
.b
.b
.last_level
> 0 ||
2401 !tex
->surface
.dcc_size
||
2402 sctx
->screen
->debug_flags
& DBG(NO_DCC
) ||
2403 sctx
->screen
->debug_flags
& DBG(NO_DCC_FB
))
2406 assert(sctx
->chip_class
>= GFX8
);
2408 if (tex
->dcc_offset
)
2409 return; /* already enabled */
2411 /* Enable the DCC stat gathering. */
2412 if (!tex
->dcc_gather_statistics
) {
2413 tex
->dcc_gather_statistics
= true;
2414 vi_separate_dcc_start_query(sctx
, tex
);
2417 if (!vi_should_enable_separate_dcc(tex
))
2418 return; /* stats show that DCC decompression is too expensive */
2420 assert(tex
->surface
.num_dcc_levels
);
2421 assert(!tex
->dcc_separate_buffer
);
2423 si_texture_discard_cmask(sctx
->screen
, tex
);
2425 /* Get a DCC buffer. */
2426 if (tex
->last_dcc_separate_buffer
) {
2427 assert(tex
->dcc_gather_statistics
);
2428 assert(!tex
->dcc_separate_buffer
);
2429 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2430 tex
->last_dcc_separate_buffer
= NULL
;
2432 tex
->dcc_separate_buffer
=
2433 si_aligned_buffer_create(sctx
->b
.screen
,
2434 SI_RESOURCE_FLAG_UNMAPPABLE
,
2436 tex
->surface
.dcc_size
,
2437 tex
->surface
.dcc_alignment
);
2438 if (!tex
->dcc_separate_buffer
)
2442 /* dcc_offset is the absolute GPUVM address. */
2443 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2445 /* no need to flag anything since this is called by fast clear that
2446 * flags framebuffer state
2451 * Called by pipe_context::flush_resource, the place where DCC decompression
2454 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2455 struct si_texture
*tex
)
2457 struct si_context
*sctx
= (struct si_context
*)ctx
;
2458 struct pipe_query
*tmp
;
2459 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2460 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2461 bool disable
= false;
2463 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2464 union pipe_query_result result
;
2466 /* Read the results. */
2467 struct pipe_query
*query
= sctx
->dcc_stats
[i
].ps_stats
[2];
2468 ctx
->get_query_result(ctx
, query
,
2470 si_query_buffer_reset(sctx
, &((struct si_query_hw
*)query
)->buffer
);
2472 /* Compute the approximate number of fullscreen draws. */
2473 tex
->ps_draw_ratio
=
2474 result
.pipeline_statistics
.ps_invocations
/
2475 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2476 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2478 disable
= tex
->dcc_separate_buffer
&&
2479 !vi_should_enable_separate_dcc(tex
);
2482 tex
->num_slow_clears
= 0;
2484 /* stop the statistics query for ps_stats[0] */
2486 vi_separate_dcc_stop_query(sctx
, tex
);
2488 /* Move the queries in the queue by one. */
2489 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2490 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2491 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2492 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2494 /* create and start a new query as ps_stats[0] */
2496 vi_separate_dcc_start_query(sctx
, tex
);
2499 assert(!tex
->last_dcc_separate_buffer
);
2500 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2501 tex
->dcc_separate_buffer
= NULL
;
2502 tex
->dcc_offset
= 0;
2503 /* no need to flag anything since this is called after
2504 * decompression that re-sets framebuffer state
2509 static struct pipe_memory_object
*
2510 si_memobj_from_handle(struct pipe_screen
*screen
,
2511 struct winsys_handle
*whandle
,
2514 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2515 struct si_memory_object
*memobj
= CALLOC_STRUCT(si_memory_object
);
2516 struct pb_buffer
*buf
= NULL
;
2517 uint32_t stride
, offset
;
2522 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2523 sscreen
->info
.max_alignment
,
2530 memobj
->b
.dedicated
= dedicated
;
2532 memobj
->stride
= stride
;
2534 return (struct pipe_memory_object
*)memobj
;
2539 si_memobj_destroy(struct pipe_screen
*screen
,
2540 struct pipe_memory_object
*_memobj
)
2542 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2544 pb_reference(&memobj
->buf
, NULL
);
2548 static struct pipe_resource
*
2549 si_texture_from_memobj(struct pipe_screen
*screen
,
2550 const struct pipe_resource
*templ
,
2551 struct pipe_memory_object
*_memobj
,
2554 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2555 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2556 struct pipe_resource
*tex
=
2557 si_texture_from_winsys_buffer(sscreen
, templ
, memobj
->buf
,
2558 memobj
->stride
, offset
,
2559 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
|
2560 PIPE_HANDLE_USAGE_SHADER_WRITE
,
2561 memobj
->b
.dedicated
);
2565 /* si_texture_from_winsys_buffer doesn't increment refcount of
2566 * memobj->buf, so increment it here.
2568 struct pb_buffer
*buf
= NULL
;
2569 pb_reference(&buf
, memobj
->buf
);
2573 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2574 struct pipe_resource
*resource
,
2577 struct si_texture
*tex
= (struct si_texture
*)resource
;
2579 /* Buffers only support the linear flag. */
2580 if (resource
->target
== PIPE_BUFFER
)
2581 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2583 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2586 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2589 /* TODO: PIPE_BIND_CURSOR - do we care? */
2593 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2595 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2596 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2597 sscreen
->b
.resource_get_info
= si_texture_get_info
;
2598 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2599 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2600 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2601 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2604 void si_init_context_texture_functions(struct si_context
*sctx
)
2606 sctx
->b
.create_surface
= si_create_surface
;
2607 sctx
->b
.surface_destroy
= si_surface_destroy
;