src/gallium/drivers/radeonsi/si_uvd.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2011 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "si_pipe.h"
  29 #include "radeon/radeon_video.h"
  30 #include "radeon/radeon_uvd.h"
  31 #include "radeon/radeon_vce.h"
  32 #include "radeon/radeon_vcn_dec.h"
  33 #include "radeon/radeon_vcn_enc.h"
  34 #include "radeon/radeon_uvd_enc.h"
  35 #include "util/u_video.h"
  36
  37 /**
  38  * creates an video buffer with an UVD compatible memory layout
  39  */
  40 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
  41                                                  const struct pipe_video_buffer *tmpl)
  42 {
  43         struct si_context *ctx = (struct si_context *)pipe;
  44         struct si_texture *resources[VL_NUM_COMPONENTS] = {};
  45         struct radeon_surf *surfaces[VL_NUM_COMPONENTS] = {};
  46         struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {};
  47         enum pipe_format resource_formats[VL_NUM_COMPONENTS];
  48         struct pipe_video_buffer vidtemplate;
  49         struct pipe_resource templ;
  50         unsigned i, array_size;
  51
  52         assert(pipe);
  53
  54         /* first create the needed resources as "normal" textures */
  55         vl_get_video_buffer_formats(pipe->screen, tmpl->buffer_format, resource_formats);
  56
  57         array_size = tmpl->interlaced ? 2 : 1;
  58         vidtemplate = *tmpl;
  59         vidtemplate.width = align(tmpl->width, VL_MACROBLOCK_WIDTH);
  60         vidtemplate.height = align(tmpl->height / array_size, VL_MACROBLOCK_HEIGHT);
  61
  62         assert(resource_formats[0] != PIPE_FORMAT_NONE);
  63
  64         for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
  65                 if (resource_formats[i] != PIPE_FORMAT_NONE) {
  66                         vl_video_buffer_template(&templ, &vidtemplate,
  67                                                  resource_formats[i], 1,
  68                                                  array_size, PIPE_USAGE_DEFAULT, i);
  69                         /* Set PIPE_BIND_SHARED to avoid reallocation in si_texture_get_handle,
  70                          * which can't handle joined surfaces. */
  71                         /* TODO: get tiling working */
  72                         templ.bind = PIPE_BIND_LINEAR | PIPE_BIND_SHARED;
  73                         resources[i] = (struct si_texture *)
  74                                         pipe->screen->resource_create(pipe->screen, &templ);
  75                         if (!resources[i])
  76                                 goto error;
  77                 }
  78         }
  79
  80         for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
  81                 if (!resources[i])
  82                         continue;
  83
  84                 surfaces[i] = & resources[i]->surface;
  85                 pbs[i] = &resources[i]->buffer.buf;
  86         }
  87
  88         si_vid_join_surfaces(ctx, pbs, surfaces);
  89
  90         for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
  91                 if (!resources[i])
  92                         continue;
  93
  94                 /* reset the address */
  95                 resources[i]->buffer.gpu_address = ctx->ws->buffer_get_virtual_address(
  96                         resources[i]->buffer.buf);
  97                 resources[i]->buffer.bo_size = resources[i]->buffer.buf->size;
  98         }
  99
 100         vidtemplate.height *= array_size;
 101         return vl_video_buffer_create_ex2(pipe, &vidtemplate, (struct pipe_resource **)resources);
 102
 103 error:
 104         for (i = 0; i < VL_NUM_COMPONENTS; ++i)
 105                 si_texture_reference(&resources[i], NULL);
 106
 107         return NULL;
 108 }
 109
 110 /* set the decoding target buffer offsets */
 111 static struct pb_buffer* si_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf)
 112 {
 113         struct si_screen *sscreen = (struct si_screen*)buf->base.context->screen;
 114         struct si_texture *luma = (struct si_texture *)buf->resources[0];
 115         struct si_texture *chroma = (struct si_texture *)buf->resources[1];
 116         enum ruvd_surface_type type =  (sscreen->info.chip_class >= GFX9) ?
 117                                         RUVD_SURFACE_TYPE_GFX9 :
 118                                         RUVD_SURFACE_TYPE_LEGACY;
 119
 120         msg->body.decode.dt_field_mode = buf->base.interlaced;
 121
 122         si_uvd_set_dt_surfaces(msg, &luma->surface, (chroma) ? &chroma->surface : NULL, type);
 123
 124         return luma->buffer.buf;
 125 }
 126
 127 /* get the radeon resources for VCE */
 128 static void si_vce_get_buffer(struct pipe_resource *resource,
 129                               struct pb_buffer **handle,
 130                               struct radeon_surf **surface)
 131 {
 132         struct si_texture *res = (struct si_texture *)resource;
 133
 134         if (handle)
 135                 *handle = res->buffer.buf;
 136
 137         if (surface)
 138                 *surface = &res->surface;
 139 }
 140
 141 /**
 142  * creates an UVD compatible decoder
 143  */
 144 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 145                                                const struct pipe_video_codec *templ)
 146 {
 147         struct si_context *ctx = (struct si_context *)context;
 148         bool vcn = ctx->family >= CHIP_RAVEN;
 149
 150         if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 151                 if (vcn) {
 152                         return radeon_create_encoder(context, templ, ctx->ws, si_vce_get_buffer);
 153                 } else {
 154                         if (u_reduce_video_profile(templ->profile) == PIPE_VIDEO_FORMAT_HEVC)
 155                                 return radeon_uvd_create_encoder(context, templ, ctx->ws, si_vce_get_buffer);
 156                         else
 157                                 return si_vce_create_encoder(context, templ, ctx->ws, si_vce_get_buffer);
 158                 }
 159         }
 160
 161         return (vcn) ?  radeon_create_decoder(context, templ) :
 162                 si_common_uvd_create_decoder(context, templ, si_uvd_set_dtb);
 163 }