1 /**************************************************************************
3 * Copyright 2011 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 * Christian König <christian.koenig@amd.com>
35 #include "radeon/radeon_video.h"
36 #include "radeon/radeon_uvd.h"
37 #include "radeon/radeon_vce.h"
38 #include "radeon/radeon_vcn_dec.h"
41 * creates an video buffer with an UVD compatible memory layout
43 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
44 const struct pipe_video_buffer
*tmpl
)
46 struct si_context
*ctx
= (struct si_context
*)pipe
;
47 struct r600_texture
*resources
[VL_NUM_COMPONENTS
] = {};
48 struct radeon_surf
*surfaces
[VL_NUM_COMPONENTS
] = {};
49 struct pb_buffer
**pbs
[VL_NUM_COMPONENTS
] = {};
50 const enum pipe_format
*resource_formats
;
51 struct pipe_video_buffer
template;
52 struct pipe_resource templ
;
53 unsigned i
, array_size
;
57 /* first create the needed resources as "normal" textures */
58 resource_formats
= vl_video_buffer_formats(pipe
->screen
, tmpl
->buffer_format
);
59 if (!resource_formats
)
62 array_size
= tmpl
->interlaced
? 2 : 1;
64 template.width
= align(tmpl
->width
, VL_MACROBLOCK_WIDTH
);
65 template.height
= align(tmpl
->height
/ array_size
, VL_MACROBLOCK_HEIGHT
);
67 vl_video_buffer_template(&templ
, &template, resource_formats
[0], 1, array_size
, PIPE_USAGE_DEFAULT
, 0);
68 /* TODO: get tiling working */
69 templ
.bind
= PIPE_BIND_LINEAR
;
70 resources
[0] = (struct r600_texture
*)
71 pipe
->screen
->resource_create(pipe
->screen
, &templ
);
75 if (resource_formats
[1] != PIPE_FORMAT_NONE
) {
76 vl_video_buffer_template(&templ
, &template, resource_formats
[1], 1, array_size
, PIPE_USAGE_DEFAULT
, 1);
77 templ
.bind
= PIPE_BIND_LINEAR
;
78 resources
[1] = (struct r600_texture
*)
79 pipe
->screen
->resource_create(pipe
->screen
, &templ
);
84 if (resource_formats
[2] != PIPE_FORMAT_NONE
) {
85 vl_video_buffer_template(&templ
, &template, resource_formats
[2], 1, array_size
, PIPE_USAGE_DEFAULT
, 2);
86 templ
.bind
= PIPE_BIND_LINEAR
;
87 resources
[2] = (struct r600_texture
*)
88 pipe
->screen
->resource_create(pipe
->screen
, &templ
);
93 for (i
= 0; i
< VL_NUM_COMPONENTS
; ++i
) {
97 surfaces
[i
] = & resources
[i
]->surface
;
98 pbs
[i
] = &resources
[i
]->resource
.buf
;
101 si_vid_join_surfaces(&ctx
->b
, pbs
, surfaces
);
103 for (i
= 0; i
< VL_NUM_COMPONENTS
; ++i
) {
107 /* reset the address */
108 resources
[i
]->resource
.gpu_address
= ctx
->b
.ws
->buffer_get_virtual_address(
109 resources
[i
]->resource
.buf
);
112 template.height
*= array_size
;
113 return vl_video_buffer_create_ex2(pipe
, &template, (struct pipe_resource
**)resources
);
116 for (i
= 0; i
< VL_NUM_COMPONENTS
; ++i
)
117 r600_texture_reference(&resources
[i
], NULL
);
122 /* set the decoding target buffer offsets */
123 static struct pb_buffer
* si_uvd_set_dtb(struct ruvd_msg
*msg
, struct vl_video_buffer
*buf
)
125 struct si_screen
*sscreen
= (struct si_screen
*)buf
->base
.context
->screen
;
126 struct r600_texture
*luma
= (struct r600_texture
*)buf
->resources
[0];
127 struct r600_texture
*chroma
= (struct r600_texture
*)buf
->resources
[1];
128 enum ruvd_surface_type type
= (sscreen
->b
.chip_class
>= GFX9
) ?
129 RUVD_SURFACE_TYPE_GFX9
:
130 RUVD_SURFACE_TYPE_LEGACY
;
132 msg
->body
.decode
.dt_field_mode
= buf
->base
.interlaced
;
134 si_uvd_set_dt_surfaces(msg
, &luma
->surface
, (chroma
) ? &chroma
->surface
: NULL
, type
);
136 return luma
->resource
.buf
;
139 /* get the radeon resources for VCE */
140 static void si_vce_get_buffer(struct pipe_resource
*resource
,
141 struct pb_buffer
**handle
,
142 struct radeon_surf
**surface
)
144 struct r600_texture
*res
= (struct r600_texture
*)resource
;
147 *handle
= res
->resource
.buf
;
150 *surface
= &res
->surface
;
154 * creates an UVD compatible decoder
156 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
157 const struct pipe_video_codec
*templ
)
159 struct si_context
*ctx
= (struct si_context
*)context
;
160 bool vcn
= (ctx
->b
.family
== CHIP_RAVEN
) ? true : false;
162 if (templ
->entrypoint
== PIPE_VIDEO_ENTRYPOINT_ENCODE
)
163 return si_vce_create_encoder(context
, templ
, ctx
->b
.ws
, si_vce_get_buffer
);
165 return (vcn
) ? radeon_create_decoder(context
, templ
) :
166 si_common_uvd_create_decoder(context
, templ
, si_uvd_set_dtb
);