radeonsi: emit GS_OUT_PRIM_TYPE only if it changes
[mesa.git] / src / gallium / drivers / radeonsi / sid.h
1 /*
2 * Southern Islands Register documentation
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef SID_H
25 #define SID_H
26
27 /* si values */
28 #define SI_CONFIG_REG_OFFSET 0x00008000
29 #define SI_CONFIG_REG_END 0x0000B000
30 #define SI_SH_REG_OFFSET 0x0000B000
31 #define SI_SH_REG_END 0x0000C000
32 #define SI_CONTEXT_REG_OFFSET 0x00028000
33 #define SI_CONTEXT_REG_END 0x00029000
34 #define CIK_UCONFIG_REG_OFFSET 0x00030000
35 #define CIK_UCONFIG_REG_END 0x00031000
36
37 #define EVENT_TYPE_CACHE_FLUSH 0x6
38 #define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10
39 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14
40 #define EVENT_TYPE_ZPASS_DONE 0x15
41 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16
42 #define EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH 0x1f
43 #define EVENT_TYPE_SAMPLE_STREAMOUTSTATS 0x20
44 #define EVENT_TYPE(x) ((x) << 0)
45 #define EVENT_INDEX(x) ((x) << 8)
46 /* 0 - any non-TS event
47 * 1 - ZPASS_DONE
48 * 2 - SAMPLE_PIPELINESTAT
49 * 3 - SAMPLE_STREAMOUTSTAT*
50 * 4 - *S_PARTIAL_FLUSH
51 * 5 - TS events
52 */
53 #define EVENT_WRITE_INV_L2 0x100000
54
55
56 #define PREDICATION_OP_CLEAR 0x0
57 #define PREDICATION_OP_ZPASS 0x1
58 #define PREDICATION_OP_PRIMCOUNT 0x2
59
60 #define PRED_OP(x) ((x) << 16)
61
62 #define PREDICATION_CONTINUE (1 << 31)
63
64 #define PREDICATION_HINT_WAIT (0 << 12)
65 #define PREDICATION_HINT_NOWAIT_DRAW (1 << 12)
66
67 #define PREDICATION_DRAW_NOT_VISIBLE (0 << 8)
68 #define PREDICATION_DRAW_VISIBLE (1 << 8)
69
70 #define R600_TEXEL_PITCH_ALIGNMENT_MASK 0x7
71
72 #define PKT3_NOP 0x10
73 #define PKT3_SET_BASE 0x11
74 #define PKT3_CLEAR_STATE 0x12
75 #define PKT3_INDEX_BUFFER_SIZE 0x13
76 #define PKT3_DISPATCH_DIRECT 0x15
77 #define PKT3_DISPATCH_INDIRECT 0x16
78 #define PKT3_OCCLUSION_QUERY 0x1F /* new for CIK */
79 #define PKT3_SET_PREDICATION 0x20
80 #define PKT3_COND_EXEC 0x22
81 #define PKT3_PRED_EXEC 0x23
82 #define PKT3_DRAW_INDIRECT 0x24
83 #define PKT3_DRAW_INDEX_INDIRECT 0x25
84 #define PKT3_INDEX_BASE 0x26
85 #define PKT3_DRAW_INDEX_2 0x27
86 #define PKT3_CONTEXT_CONTROL 0x28
87 #define PKT3_INDEX_TYPE 0x2A
88 #define PKT3_DRAW_INDIRECT_MULTI 0x2C
89 #define PKT3_DRAW_INDEX_AUTO 0x2D
90 #define PKT3_DRAW_INDEX_IMMD 0x2E /* not on CIK */
91 #define PKT3_NUM_INSTANCES 0x2F
92 #define PKT3_DRAW_INDEX_MULTI_AUTO 0x30
93 #define PKT3_INDIRECT_BUFFER 0x32
94 #define PKT3_STRMOUT_BUFFER_UPDATE 0x34
95 #define PKT3_DRAW_INDEX_OFFSET_2 0x35
96 #define PKT3_DRAW_PREAMBLE 0x36 /* new on CIK, required on GFX7.2 and later */
97 #define PKT3_WRITE_DATA 0x37
98 #define PKT3_WRITE_DATA_DST_SEL(x) ((x) << 8)
99 #define PKT3_WRITE_DATA_DST_SEL_REG 0
100 #define PKT3_WRITE_DATA_DST_SEL_MEM_SYNC 1
101 #define PKT3_WRITE_DATA_DST_SEL_TC_OR_L2 2
102 #define PKT3_WRITE_DATA_DST_SEL_GDS 3
103 #define PKT3_WRITE_DATA_DST_SEL_RESERVED_4 4
104 #define PKT3_WRITE_DATA_DST_SEL_MEM_ASYNC 5
105 #define PKT3_WR_ONE_ADDR (1 << 16)
106 #define PKT3_WRITE_DATA_WR_CONFIRM (1 << 20)
107 #define PKT3_WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
108 #define PKT3_WRITE_DATA_ENGINE_SEL_ME 0
109 #define PKT3_WRITE_DATA_ENGINE_SEL_PFP 1
110 #define PKT3_WRITE_DATA_ENGINE_SEL_CE 2
111 #define PKT3_DRAW_INDEX_INDIRECT_MULTI 0x38
112 #define PKT3_MEM_SEMAPHORE 0x39
113 #define PKT3_MPEG_INDEX 0x3A /* not on CIK */
114 #define PKT3_WAIT_REG_MEM 0x3C
115 #define WAIT_REG_MEM_EQUAL 3
116 #define PKT3_MEM_WRITE 0x3D /* not on CIK */
117 #define PKT3_COPY_DATA 0x40
118 #define COPY_DATA_SRC_SEL(x) ((x) & 0xf)
119 #define COPY_DATA_REG 0
120 #define COPY_DATA_MEM 1
121 #define COPY_DATA_DST_SEL(x) (((x) & 0xf) << 8)
122 #define COPY_DATA_WR_CONFIRM (1 << 20)
123 #define PKT3_SURFACE_SYNC 0x43 /* deprecated on CIK, use ACQUIRE_MEM */
124 #define PKT3_ME_INITIALIZE 0x44 /* not on CIK */
125 #define PKT3_COND_WRITE 0x45
126 #define PKT3_EVENT_WRITE 0x46
127 #define PKT3_EVENT_WRITE_EOP 0x47
128 #define PKT3_EVENT_WRITE_EOS 0x48
129 #define PKT3_ONE_REG_WRITE 0x57 /* not on CIK */
130 #define PKT3_ACQUIRE_MEM 0x58 /* new for CIK */
131 #define PKT3_SET_CONFIG_REG 0x68
132 #define PKT3_SET_CONTEXT_REG 0x69
133 #define PKT3_SET_SH_REG 0x76
134 #define PKT3_SET_SH_REG_OFFSET 0x77
135 #define PKT3_SET_UCONFIG_REG 0x79 /* new for CIK */
136
137 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
138 #define PKT_TYPE_G(x) (((x) >> 30) & 0x3)
139 #define PKT_TYPE_C 0x3FFFFFFF
140 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
141 #define PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF)
142 #define PKT_COUNT_C 0xC000FFFF
143 #define PKT0_BASE_INDEX_S(x) (((x) & 0xFFFF) << 0)
144 #define PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF)
145 #define PKT0_BASE_INDEX_C 0xFFFF0000
146 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
147 #define PKT3_IT_OPCODE_G(x) (((x) >> 8) & 0xFF)
148 #define PKT3_IT_OPCODE_C 0xFFFF00FF
149 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
150 #define PKT3_SHADER_TYPE_S(x) (((x) & 0x1) << 1)
151 #define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count))
152 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
153
154 #define PKT3_CP_DMA 0x41
155 /* 1. header
156 * 2. SRC_ADDR_LO [31:0] or DATA [31:0]
157 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | SRC_ADDR_HI [15:0]
158 * 4. DST_ADDR_LO [31:0]
159 * 5. DST_ADDR_HI [15:0]
160 * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
161 */
162 #define PKT3_CP_DMA_CP_SYNC (1 << 31)
163 #define PKT3_CP_DMA_SRC_SEL(x) ((x) << 29)
164 /* 0 - SRC_ADDR
165 * 1 - GDS (program SAS to 1 as well)
166 * 2 - DATA
167 */
168 #define PKT3_CP_DMA_DST_SEL(x) ((x) << 20)
169 /* 0 - DST_ADDR
170 * 1 - GDS (program DAS to 1 as well)
171 */
172 /* COMMAND */
173 #define PKT3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
174 /* 0 - none
175 * 1 - 8 in 16
176 * 2 - 8 in 32
177 * 3 - 8 in 64
178 */
179 #define PKT3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
180 /* 0 - none
181 * 1 - 8 in 16
182 * 2 - 8 in 32
183 * 3 - 8 in 64
184 */
185 #define PKT3_CP_DMA_CMD_SAS (1 << 26)
186 /* 0 - memory
187 * 1 - register
188 */
189 #define PKT3_CP_DMA_CMD_DAS (1 << 27)
190 /* 0 - memory
191 * 1 - register
192 */
193 #define PKT3_CP_DMA_CMD_SAIC (1 << 28)
194 #define PKT3_CP_DMA_CMD_DAIC (1 << 29)
195 #define PKT3_CP_DMA_CMD_RAW_WAIT (1 << 30)
196
197 #define PKT3_DMA_DATA 0x50 /* new for CIK */
198 /* 1. header
199 * 2. CP_SYNC [31] | SRC_SEL [30:29] | DST_SEL [21:20] | ENGINE [0]
200 * 2. SRC_ADDR_LO [31:0] or DATA [31:0]
201 * 3. SRC_ADDR_HI [31:0]
202 * 4. DST_ADDR_LO [31:0]
203 * 5. DST_ADDR_HI [31:0]
204 * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
205 */
206
207 #define GRBM_GFX_INDEX 0x802C
208 #define INSTANCE_INDEX(x) ((x) << 0)
209 #define SH_INDEX(x) ((x) << 8)
210 #define SE_INDEX(x) ((x) << 16)
211 #define SH_BROADCAST_WRITES (1 << 29)
212 #define INSTANCE_BROADCAST_WRITES (1 << 30)
213 #define SE_BROADCAST_WRITES (1 << 31)
214 #define R_0084FC_CP_STRMOUT_CNTL 0x0084FC
215 #define S_0084FC_OFFSET_UPDATE_DONE(x) (((x) & 0x1) << 0)
216 #define R_0085F0_CP_COHER_CNTL 0x0085F0
217 #define S_0085F0_DEST_BASE_0_ENA(x) (((x) & 0x1) << 0)
218 #define G_0085F0_DEST_BASE_0_ENA(x) (((x) >> 0) & 0x1)
219 #define C_0085F0_DEST_BASE_0_ENA 0xFFFFFFFE
220 #define S_0085F0_DEST_BASE_1_ENA(x) (((x) & 0x1) << 1)
221 #define G_0085F0_DEST_BASE_1_ENA(x) (((x) >> 1) & 0x1)
222 #define C_0085F0_DEST_BASE_1_ENA 0xFFFFFFFD
223 #define S_0085F0_CB0_DEST_BASE_ENA_SHIFT 6
224 #define S_0085F0_CB0_DEST_BASE_ENA(x) (((x) & 0x1) << 6)
225 #define G_0085F0_CB0_DEST_BASE_ENA(x) (((x) >> 6) & 0x1)
226 #define C_0085F0_CB0_DEST_BASE_ENA 0xFFFFFFBF
227 #define S_0085F0_CB1_DEST_BASE_ENA(x) (((x) & 0x1) << 7)
228 #define G_0085F0_CB1_DEST_BASE_ENA(x) (((x) >> 7) & 0x1)
229 #define C_0085F0_CB1_DEST_BASE_ENA 0xFFFFFF7F
230 #define S_0085F0_CB2_DEST_BASE_ENA(x) (((x) & 0x1) << 8)
231 #define G_0085F0_CB2_DEST_BASE_ENA(x) (((x) >> 8) & 0x1)
232 #define C_0085F0_CB2_DEST_BASE_ENA 0xFFFFFEFF
233 #define S_0085F0_CB3_DEST_BASE_ENA(x) (((x) & 0x1) << 9)
234 #define G_0085F0_CB3_DEST_BASE_ENA(x) (((x) >> 9) & 0x1)
235 #define C_0085F0_CB3_DEST_BASE_ENA 0xFFFFFDFF
236 #define S_0085F0_CB4_DEST_BASE_ENA(x) (((x) & 0x1) << 10)
237 #define G_0085F0_CB4_DEST_BASE_ENA(x) (((x) >> 10) & 0x1)
238 #define C_0085F0_CB4_DEST_BASE_ENA 0xFFFFFBFF
239 #define S_0085F0_CB5_DEST_BASE_ENA(x) (((x) & 0x1) << 11)
240 #define G_0085F0_CB5_DEST_BASE_ENA(x) (((x) >> 11) & 0x1)
241 #define C_0085F0_CB5_DEST_BASE_ENA 0xFFFFF7FF
242 #define S_0085F0_CB6_DEST_BASE_ENA(x) (((x) & 0x1) << 12)
243 #define G_0085F0_CB6_DEST_BASE_ENA(x) (((x) >> 12) & 0x1)
244 #define C_0085F0_CB6_DEST_BASE_ENA 0xFFFFEFFF
245 #define S_0085F0_CB7_DEST_BASE_ENA(x) (((x) & 0x1) << 13)
246 #define G_0085F0_CB7_DEST_BASE_ENA(x) (((x) >> 13) & 0x1)
247 #define C_0085F0_CB7_DEST_BASE_ENA 0xFFFFDFFF
248 #define S_0085F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14)
249 #define G_0085F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1)
250 #define C_0085F0_DB_DEST_BASE_ENA 0xFFFFBFFF
251 #define S_0085F0_DEST_BASE_2_ENA(x) (((x) & 0x1) << 19)
252 #define G_0085F0_DEST_BASE_2_ENA(x) (((x) >> 19) & 0x1)
253 #define C_0085F0_DEST_BASE_2_ENA 0xFFF7FFFF
254 #define S_0085F0_DEST_BASE_3_ENA(x) (((x) & 0x1) << 21)
255 #define G_0085F0_DEST_BASE_3_ENA(x) (((x) >> 21) & 0x1)
256 #define C_0085F0_DEST_BASE_3_ENA 0xFFDFFFFF
257 #define S_0085F0_TCL1_ACTION_ENA(x) (((x) & 0x1) << 22)
258 #define G_0085F0_TCL1_ACTION_ENA(x) (((x) >> 22) & 0x1)
259 #define C_0085F0_TCL1_ACTION_ENA 0xFFBFFFFF
260 #define S_0085F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23)
261 #define G_0085F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1)
262 #define C_0085F0_TC_ACTION_ENA 0xFF7FFFFF
263 #define S_0085F0_CB_ACTION_ENA(x) (((x) & 0x1) << 25)
264 #define G_0085F0_CB_ACTION_ENA(x) (((x) >> 25) & 0x1)
265 #define C_0085F0_CB_ACTION_ENA 0xFDFFFFFF
266 #define S_0085F0_DB_ACTION_ENA(x) (((x) & 0x1) << 26)
267 #define G_0085F0_DB_ACTION_ENA(x) (((x) >> 26) & 0x1)
268 #define C_0085F0_DB_ACTION_ENA 0xFBFFFFFF
269 #define S_0085F0_SH_KCACHE_ACTION_ENA(x) (((x) & 0x1) << 27)
270 #define G_0085F0_SH_KCACHE_ACTION_ENA(x) (((x) >> 27) & 0x1)
271 #define C_0085F0_SH_KCACHE_ACTION_ENA 0xF7FFFFFF
272 #define S_0085F0_SH_ICACHE_ACTION_ENA(x) (((x) & 0x1) << 29)
273 #define G_0085F0_SH_ICACHE_ACTION_ENA(x) (((x) >> 29) & 0x1)
274 #define C_0085F0_SH_ICACHE_ACTION_ENA 0xDFFFFFFF
275 #define R_0085F4_CP_COHER_SIZE 0x0085F4
276 #define R_0085F8_CP_COHER_BASE 0x0085F8
277
278 /* CIK */
279 #define R_0301E4_CP_COHER_BASE_HI 0x0301E4
280 #define S_0301E4_COHER_BASE_HI_256B(x) (((x) & 0xFF) << 0)
281 #define G_0301E4_COHER_BASE_HI_256B(x) (((x) >> 0) & 0xFF)
282 #define C_0301E4_COHER_BASE_HI_256B 0xFFFFFF00
283 #define R_0301F0_CP_COHER_CNTL 0x0301F0
284 #define S_0301F0_DEST_BASE_0_ENA(x) (((x) & 0x1) << 0)
285 #define G_0301F0_DEST_BASE_0_ENA(x) (((x) >> 0) & 0x1)
286 #define C_0301F0_DEST_BASE_0_ENA 0xFFFFFFFE
287 #define S_0301F0_DEST_BASE_1_ENA(x) (((x) & 0x1) << 1)
288 #define G_0301F0_DEST_BASE_1_ENA(x) (((x) >> 1) & 0x1)
289 #define C_0301F0_DEST_BASE_1_ENA 0xFFFFFFFD
290 #define S_0301F0_CB0_DEST_BASE_ENA(x) (((x) & 0x1) << 6)
291 #define G_0301F0_CB0_DEST_BASE_ENA(x) (((x) >> 6) & 0x1)
292 #define C_0301F0_CB0_DEST_BASE_ENA 0xFFFFFFBF
293 #define S_0301F0_CB1_DEST_BASE_ENA(x) (((x) & 0x1) << 7)
294 #define G_0301F0_CB1_DEST_BASE_ENA(x) (((x) >> 7) & 0x1)
295 #define C_0301F0_CB1_DEST_BASE_ENA 0xFFFFFF7F
296 #define S_0301F0_CB2_DEST_BASE_ENA(x) (((x) & 0x1) << 8)
297 #define G_0301F0_CB2_DEST_BASE_ENA(x) (((x) >> 8) & 0x1)
298 #define C_0301F0_CB2_DEST_BASE_ENA 0xFFFFFEFF
299 #define S_0301F0_CB3_DEST_BASE_ENA(x) (((x) & 0x1) << 9)
300 #define G_0301F0_CB3_DEST_BASE_ENA(x) (((x) >> 9) & 0x1)
301 #define C_0301F0_CB3_DEST_BASE_ENA 0xFFFFFDFF
302 #define S_0301F0_CB4_DEST_BASE_ENA(x) (((x) & 0x1) << 10)
303 #define G_0301F0_CB4_DEST_BASE_ENA(x) (((x) >> 10) & 0x1)
304 #define C_0301F0_CB4_DEST_BASE_ENA 0xFFFFFBFF
305 #define S_0301F0_CB5_DEST_BASE_ENA(x) (((x) & 0x1) << 11)
306 #define G_0301F0_CB5_DEST_BASE_ENA(x) (((x) >> 11) & 0x1)
307 #define C_0301F0_CB5_DEST_BASE_ENA 0xFFFFF7FF
308 #define S_0301F0_CB6_DEST_BASE_ENA(x) (((x) & 0x1) << 12)
309 #define G_0301F0_CB6_DEST_BASE_ENA(x) (((x) >> 12) & 0x1)
310 #define C_0301F0_CB6_DEST_BASE_ENA 0xFFFFEFFF
311 #define S_0301F0_CB7_DEST_BASE_ENA(x) (((x) & 0x1) << 13)
312 #define G_0301F0_CB7_DEST_BASE_ENA(x) (((x) >> 13) & 0x1)
313 #define C_0301F0_CB7_DEST_BASE_ENA 0xFFFFDFFF
314 #define S_0301F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14)
315 #define G_0301F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1)
316 #define C_0301F0_DB_DEST_BASE_ENA 0xFFFFBFFF
317 #define S_0301F0_TCL1_VOL_ACTION_ENA(x) (((x) & 0x1) << 15)
318 #define G_0301F0_TCL1_VOL_ACTION_ENA(x) (((x) >> 15) & 0x1)
319 #define C_0301F0_TCL1_VOL_ACTION_ENA 0xFFFF7FFF
320 #define S_0301F0_TC_VOL_ACTION_ENA(x) (((x) & 0x1) << 16)
321 #define G_0301F0_TC_VOL_ACTION_ENA(x) (((x) >> 16) & 0x1)
322 #define C_0301F0_TC_VOL_ACTION_ENA 0xFFFEFFFF
323 #define S_0301F0_TC_WB_ACTION_ENA(x) (((x) & 0x1) << 18)
324 #define G_0301F0_TC_WB_ACTION_ENA(x) (((x) >> 18) & 0x1)
325 #define C_0301F0_TC_WB_ACTION_ENA 0xFFFBFFFF
326 #define S_0301F0_DEST_BASE_2_ENA(x) (((x) & 0x1) << 19)
327 #define G_0301F0_DEST_BASE_2_ENA(x) (((x) >> 19) & 0x1)
328 #define C_0301F0_DEST_BASE_2_ENA 0xFFF7FFFF
329 #define S_0301F0_DEST_BASE_3_ENA(x) (((x) & 0x1) << 21)
330 #define G_0301F0_DEST_BASE_3_ENA(x) (((x) >> 21) & 0x1)
331 #define C_0301F0_DEST_BASE_3_ENA 0xFFDFFFFF
332 #define S_0301F0_TCL1_ACTION_ENA(x) (((x) & 0x1) << 22)
333 #define G_0301F0_TCL1_ACTION_ENA(x) (((x) >> 22) & 0x1)
334 #define C_0301F0_TCL1_ACTION_ENA 0xFFBFFFFF
335 #define S_0301F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23)
336 #define G_0301F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1)
337 #define C_0301F0_TC_ACTION_ENA 0xFF7FFFFF
338 #define S_0301F0_CB_ACTION_ENA(x) (((x) & 0x1) << 25)
339 #define G_0301F0_CB_ACTION_ENA(x) (((x) >> 25) & 0x1)
340 #define C_0301F0_CB_ACTION_ENA 0xFDFFFFFF
341 #define S_0301F0_DB_ACTION_ENA(x) (((x) & 0x1) << 26)
342 #define G_0301F0_DB_ACTION_ENA(x) (((x) >> 26) & 0x1)
343 #define C_0301F0_DB_ACTION_ENA 0xFBFFFFFF
344 #define S_0301F0_SH_KCACHE_ACTION_ENA(x) (((x) & 0x1) << 27)
345 #define G_0301F0_SH_KCACHE_ACTION_ENA(x) (((x) >> 27) & 0x1)
346 #define C_0301F0_SH_KCACHE_ACTION_ENA 0xF7FFFFFF
347 #define S_0301F0_SH_KCACHE_VOL_ACTION_ENA(x) (((x) & 0x1) << 28)
348 #define G_0301F0_SH_KCACHE_VOL_ACTION_ENA(x) (((x) >> 28) & 0x1)
349 #define C_0301F0_SH_KCACHE_VOL_ACTION_ENA 0xEFFFFFFF
350 #define S_0301F0_SH_ICACHE_ACTION_ENA(x) (((x) & 0x1) << 29)
351 #define G_0301F0_SH_ICACHE_ACTION_ENA(x) (((x) >> 29) & 0x1)
352 #define C_0301F0_SH_ICACHE_ACTION_ENA 0xDFFFFFFF
353 #define R_0301F4_CP_COHER_SIZE 0x0301F4
354 #define R_0301F8_CP_COHER_BASE 0x0301F8
355 #define R_030230_CP_COHER_SIZE_HI 0x030230
356 #define S_030230_COHER_SIZE_HI_256B(x) (((x) & 0xFF) << 0)
357 #define G_030230_COHER_SIZE_HI_256B(x) (((x) >> 0) & 0xFF)
358 #define C_030230_COHER_SIZE_HI_256B 0xFFFFFF00
359 /* */
360 #define R_0088B0_VGT_VTX_VECT_EJECT_REG 0x0088B0
361 #define S_0088B0_PRIM_COUNT(x) (((x) & 0x3FF) << 0)
362 #define G_0088B0_PRIM_COUNT(x) (((x) >> 0) & 0x3FF)
363 #define C_0088B0_PRIM_COUNT 0xFFFFFC00
364 #define R_0088C4_VGT_CACHE_INVALIDATION 0x0088C4
365 #define S_0088C4_VS_NO_EXTRA_BUFFER(x) (((x) & 0x1) << 5)
366 #define G_0088C4_VS_NO_EXTRA_BUFFER(x) (((x) >> 5) & 0x1)
367 #define C_0088C4_VS_NO_EXTRA_BUFFER 0xFFFFFFDF
368 #define S_0088C4_STREAMOUT_FULL_FLUSH(x) (((x) & 0x1) << 13)
369 #define G_0088C4_STREAMOUT_FULL_FLUSH(x) (((x) >> 13) & 0x1)
370 #define C_0088C4_STREAMOUT_FULL_FLUSH 0xFFFFDFFF
371 #define S_0088C4_ES_LIMIT(x) (((x) & 0x1F) << 16)
372 #define G_0088C4_ES_LIMIT(x) (((x) >> 16) & 0x1F)
373 #define C_0088C4_ES_LIMIT 0xFFE0FFFF
374 #define R_0088C8_VGT_ESGS_RING_SIZE 0x0088C8
375 #define R_0088CC_VGT_GSVS_RING_SIZE 0x0088CC
376 /* CIK */
377 #define R_030900_VGT_ESGS_RING_SIZE 0x030900
378 #define R_030904_VGT_GSVS_RING_SIZE 0x030904
379 /* */
380 #define R_0088D4_VGT_GS_VERTEX_REUSE 0x0088D4
381 #define S_0088D4_VERT_REUSE(x) (((x) & 0x1F) << 0)
382 #define G_0088D4_VERT_REUSE(x) (((x) >> 0) & 0x1F)
383 #define C_0088D4_VERT_REUSE 0xFFFFFFE0
384 #define R_008958_VGT_PRIMITIVE_TYPE 0x008958
385 #define S_008958_PRIM_TYPE(x) (((x) & 0x3F) << 0)
386 #define G_008958_PRIM_TYPE(x) (((x) >> 0) & 0x3F)
387 #define C_008958_PRIM_TYPE 0xFFFFFFC0
388 #define V_008958_DI_PT_NONE 0x00
389 #define V_008958_DI_PT_POINTLIST 0x01
390 #define V_008958_DI_PT_LINELIST 0x02
391 #define V_008958_DI_PT_LINESTRIP 0x03
392 #define V_008958_DI_PT_TRILIST 0x04
393 #define V_008958_DI_PT_TRIFAN 0x05
394 #define V_008958_DI_PT_TRISTRIP 0x06
395 #define V_008958_DI_PT_UNUSED_0 0x07
396 #define V_008958_DI_PT_UNUSED_1 0x08
397 #define V_008958_DI_PT_PATCH 0x09
398 #define V_008958_DI_PT_LINELIST_ADJ 0x0A
399 #define V_008958_DI_PT_LINESTRIP_ADJ 0x0B
400 #define V_008958_DI_PT_TRILIST_ADJ 0x0C
401 #define V_008958_DI_PT_TRISTRIP_ADJ 0x0D
402 #define V_008958_DI_PT_UNUSED_3 0x0E
403 #define V_008958_DI_PT_UNUSED_4 0x0F
404 #define V_008958_DI_PT_TRI_WITH_WFLAGS 0x10
405 #define V_008958_DI_PT_RECTLIST 0x11
406 #define V_008958_DI_PT_LINELOOP 0x12
407 #define V_008958_DI_PT_QUADLIST 0x13
408 #define V_008958_DI_PT_QUADSTRIP 0x14
409 #define V_008958_DI_PT_POLYGON 0x15
410 #define V_008958_DI_PT_2D_COPY_RECT_LIST_V0 0x16
411 #define V_008958_DI_PT_2D_COPY_RECT_LIST_V1 0x17
412 #define V_008958_DI_PT_2D_COPY_RECT_LIST_V2 0x18
413 #define V_008958_DI_PT_2D_COPY_RECT_LIST_V3 0x19
414 #define V_008958_DI_PT_2D_FILL_RECT_LIST 0x1A
415 #define V_008958_DI_PT_2D_LINE_STRIP 0x1B
416 #define V_008958_DI_PT_2D_TRI_STRIP 0x1C
417 #define R_00895C_VGT_INDEX_TYPE 0x00895C
418 #define S_00895C_INDEX_TYPE(x) (((x) & 0x03) << 0)
419 #define G_00895C_INDEX_TYPE(x) (((x) >> 0) & 0x03)
420 #define C_00895C_INDEX_TYPE 0xFFFFFFFC
421 #define V_00895C_DI_INDEX_SIZE_16_BIT 0x00
422 #define V_00895C_DI_INDEX_SIZE_32_BIT 0x01
423 #define R_008960_VGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x008960
424 #define R_008964_VGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x008964
425 #define R_008968_VGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x008968
426 #define R_00896C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x00896C
427 #define R_008970_VGT_NUM_INDICES 0x008970
428 #define R_008974_VGT_NUM_INSTANCES 0x008974
429 #define R_008988_VGT_TF_RING_SIZE 0x008988
430 #define S_008988_SIZE(x) (((x) & 0xFFFF) << 0)
431 #define G_008988_SIZE(x) (((x) >> 0) & 0xFFFF)
432 #define C_008988_SIZE 0xFFFF0000
433 #define R_0089B0_VGT_HS_OFFCHIP_PARAM 0x0089B0
434 #define S_0089B0_OFFCHIP_BUFFERING(x) (((x) & 0x7F) << 0)
435 #define G_0089B0_OFFCHIP_BUFFERING(x) (((x) >> 0) & 0x7F)
436 #define C_0089B0_OFFCHIP_BUFFERING 0xFFFFFF80
437 #define R_0089B8_VGT_TF_MEMORY_BASE 0x0089B8
438 #define R_008A14_PA_CL_ENHANCE 0x008A14
439 #define S_008A14_CLIP_VTX_REORDER_ENA(x) (((x) & 0x1) << 0)
440 #define G_008A14_CLIP_VTX_REORDER_ENA(x) (((x) >> 0) & 0x1)
441 #define C_008A14_CLIP_VTX_REORDER_ENA 0xFFFFFFFE
442 #define S_008A14_NUM_CLIP_SEQ(x) (((x) & 0x03) << 1)
443 #define G_008A14_NUM_CLIP_SEQ(x) (((x) >> 1) & 0x03)
444 #define C_008A14_NUM_CLIP_SEQ 0xFFFFFFF9
445 #define S_008A14_CLIPPED_PRIM_SEQ_STALL(x) (((x) & 0x1) << 3)
446 #define G_008A14_CLIPPED_PRIM_SEQ_STALL(x) (((x) >> 3) & 0x1)
447 #define C_008A14_CLIPPED_PRIM_SEQ_STALL 0xFFFFFFF7
448 #define S_008A14_VE_NAN_PROC_DISABLE(x) (((x) & 0x1) << 4)
449 #define G_008A14_VE_NAN_PROC_DISABLE(x) (((x) >> 4) & 0x1)
450 #define C_008A14_VE_NAN_PROC_DISABLE 0xFFFFFFEF
451 #define R_008A60_PA_SU_LINE_STIPPLE_VALUE 0x008A60
452 #define S_008A60_LINE_STIPPLE_VALUE(x) (((x) & 0xFFFFFF) << 0)
453 #define G_008A60_LINE_STIPPLE_VALUE(x) (((x) >> 0) & 0xFFFFFF)
454 #define C_008A60_LINE_STIPPLE_VALUE 0xFF000000
455 #define R_008B10_PA_SC_LINE_STIPPLE_STATE 0x008B10
456 #define S_008B10_CURRENT_PTR(x) (((x) & 0x0F) << 0)
457 #define G_008B10_CURRENT_PTR(x) (((x) >> 0) & 0x0F)
458 #define C_008B10_CURRENT_PTR 0xFFFFFFF0
459 #define S_008B10_CURRENT_COUNT(x) (((x) & 0xFF) << 8)
460 #define G_008B10_CURRENT_COUNT(x) (((x) >> 8) & 0xFF)
461 #define C_008B10_CURRENT_COUNT 0xFFFF00FF
462 /* CIK */
463 #define R_030908_VGT_PRIMITIVE_TYPE 0x030908
464 #define S_030908_PRIM_TYPE(x) (((x) & 0x3F) << 0)
465 #define G_030908_PRIM_TYPE(x) (((x) >> 0) & 0x3F)
466 #define C_030908_PRIM_TYPE 0xFFFFFFC0
467 #define V_030908_DI_PT_NONE 0x00
468 #define V_030908_DI_PT_POINTLIST 0x01
469 #define V_030908_DI_PT_LINELIST 0x02
470 #define V_030908_DI_PT_LINESTRIP 0x03
471 #define V_030908_DI_PT_TRILIST 0x04
472 #define V_030908_DI_PT_TRIFAN 0x05
473 #define V_030908_DI_PT_TRISTRIP 0x06
474 #define V_030908_DI_PT_PATCH 0x09
475 #define V_030908_DI_PT_LINELIST_ADJ 0x0A
476 #define V_030908_DI_PT_LINESTRIP_ADJ 0x0B
477 #define V_030908_DI_PT_TRILIST_ADJ 0x0C
478 #define V_030908_DI_PT_TRISTRIP_ADJ 0x0D
479 #define V_030908_DI_PT_TRI_WITH_WFLAGS 0x10
480 #define V_030908_DI_PT_RECTLIST 0x11
481 #define V_030908_DI_PT_LINELOOP 0x12
482 #define V_030908_DI_PT_QUADLIST 0x13
483 #define V_030908_DI_PT_QUADSTRIP 0x14
484 #define V_030908_DI_PT_POLYGON 0x15
485 #define V_030908_DI_PT_2D_COPY_RECT_LIST_V0 0x16
486 #define V_030908_DI_PT_2D_COPY_RECT_LIST_V1 0x17
487 #define V_030908_DI_PT_2D_COPY_RECT_LIST_V2 0x18
488 #define V_030908_DI_PT_2D_COPY_RECT_LIST_V3 0x19
489 #define V_030908_DI_PT_2D_FILL_RECT_LIST 0x1A
490 #define V_030908_DI_PT_2D_LINE_STRIP 0x1B
491 #define V_030908_DI_PT_2D_TRI_STRIP 0x1C
492 #define R_03090C_VGT_INDEX_TYPE 0x03090C
493 #define S_03090C_INDEX_TYPE(x) (((x) & 0x03) << 0)
494 #define G_03090C_INDEX_TYPE(x) (((x) >> 0) & 0x03)
495 #define C_03090C_INDEX_TYPE 0xFFFFFFFC
496 #define V_03090C_DI_INDEX_SIZE_16_BIT 0x00
497 #define V_03090C_DI_INDEX_SIZE_32_BIT 0x01
498 #define R_030910_VGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x030910
499 #define R_030914_VGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x030914
500 #define R_030918_VGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x030918
501 #define R_03091C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x03091C
502 #define R_030930_VGT_NUM_INDICES 0x030930
503 #define R_030934_VGT_NUM_INSTANCES 0x030934
504 #define R_030938_VGT_TF_RING_SIZE 0x030938
505 #define S_030938_SIZE(x) (((x) & 0xFFFF) << 0)
506 #define G_030938_SIZE(x) (((x) >> 0) & 0xFFFF)
507 #define C_030938_SIZE 0xFFFF0000
508 #define R_03093C_VGT_HS_OFFCHIP_PARAM 0x03093C
509 #define S_03093C_OFFCHIP_BUFFERING(x) (((x) & 0x1FF) << 0)
510 #define G_03093C_OFFCHIP_BUFFERING(x) (((x) >> 0) & 0x1FF)
511 #define C_03093C_OFFCHIP_BUFFERING 0xFFFFFE00
512 #define S_03093C_OFFCHIP_GRANULARITY(x) (((x) & 0x03) << 9)
513 #define G_03093C_OFFCHIP_GRANULARITY(x) (((x) >> 9) & 0x03)
514 #define C_03093C_OFFCHIP_GRANULARITY 0xFFFFF9FF
515 #define V_03093C_X_8K_DWORDS 0x00
516 #define V_03093C_X_4K_DWORDS 0x01
517 #define V_03093C_X_2K_DWORDS 0x02
518 #define V_03093C_X_1K_DWORDS 0x03
519 #define R_030940_VGT_TF_MEMORY_BASE 0x030940
520 #define R_030A00_PA_SU_LINE_STIPPLE_VALUE 0x030A00
521 #define S_030A00_LINE_STIPPLE_VALUE(x) (((x) & 0xFFFFFF) << 0)
522 #define G_030A00_LINE_STIPPLE_VALUE(x) (((x) >> 0) & 0xFFFFFF)
523 #define C_030A00_LINE_STIPPLE_VALUE 0xFF000000
524 #define R_030A04_PA_SC_LINE_STIPPLE_STATE 0x030A04
525 #define S_030A04_CURRENT_PTR(x) (((x) & 0x0F) << 0)
526 #define G_030A04_CURRENT_PTR(x) (((x) >> 0) & 0x0F)
527 #define C_030A04_CURRENT_PTR 0xFFFFFFF0
528 #define S_030A04_CURRENT_COUNT(x) (((x) & 0xFF) << 8)
529 #define G_030A04_CURRENT_COUNT(x) (((x) >> 8) & 0xFF)
530 #define C_030A04_CURRENT_COUNT 0xFFFF00FF
531 /* */
532 #define R_008BF0_PA_SC_ENHANCE 0x008BF0
533 #define S_008BF0_ENABLE_PA_SC_OUT_OF_ORDER(x) (((x) & 0x1) << 0)
534 #define G_008BF0_ENABLE_PA_SC_OUT_OF_ORDER(x) (((x) >> 0) & 0x1)
535 #define C_008BF0_ENABLE_PA_SC_OUT_OF_ORDER 0xFFFFFFFE
536 #define S_008BF0_DISABLE_SC_DB_TILE_FIX(x) (((x) & 0x1) << 1)
537 #define G_008BF0_DISABLE_SC_DB_TILE_FIX(x) (((x) >> 1) & 0x1)
538 #define C_008BF0_DISABLE_SC_DB_TILE_FIX 0xFFFFFFFD
539 #define S_008BF0_DISABLE_AA_MASK_FULL_FIX(x) (((x) & 0x1) << 2)
540 #define G_008BF0_DISABLE_AA_MASK_FULL_FIX(x) (((x) >> 2) & 0x1)
541 #define C_008BF0_DISABLE_AA_MASK_FULL_FIX 0xFFFFFFFB
542 #define S_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS(x) (((x) & 0x1) << 3)
543 #define G_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS(x) (((x) >> 3) & 0x1)
544 #define C_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS 0xFFFFFFF7
545 #define S_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID(x) (((x) & 0x1) << 4)
546 #define G_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID(x) (((x) >> 4) & 0x1)
547 #define C_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID 0xFFFFFFEF
548 #define S_008BF0_DISABLE_SCISSOR_FIX(x) (((x) & 0x1) << 5)
549 #define G_008BF0_DISABLE_SCISSOR_FIX(x) (((x) >> 5) & 0x1)
550 #define C_008BF0_DISABLE_SCISSOR_FIX 0xFFFFFFDF
551 #define S_008BF0_DISABLE_PW_BUBBLE_COLLAPSE(x) (((x) & 0x03) << 6)
552 #define G_008BF0_DISABLE_PW_BUBBLE_COLLAPSE(x) (((x) >> 6) & 0x03)
553 #define C_008BF0_DISABLE_PW_BUBBLE_COLLAPSE 0xFFFFFF3F
554 #define S_008BF0_SEND_UNLIT_STILES_TO_PACKER(x) (((x) & 0x1) << 8)
555 #define G_008BF0_SEND_UNLIT_STILES_TO_PACKER(x) (((x) >> 8) & 0x1)
556 #define C_008BF0_SEND_UNLIT_STILES_TO_PACKER 0xFFFFFEFF
557 #define S_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION(x) (((x) & 0x1) << 9)
558 #define G_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION(x) (((x) >> 9) & 0x1)
559 #define C_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION 0xFFFFFDFF
560 #define R_008C08_SQC_CACHES 0x008C08
561 #define S_008C08_INST_INVALIDATE(x) (((x) & 0x1) << 0)
562 #define G_008C08_INST_INVALIDATE(x) (((x) >> 0) & 0x1)
563 #define C_008C08_INST_INVALIDATE 0xFFFFFFFE
564 #define S_008C08_DATA_INVALIDATE(x) (((x) & 0x1) << 1)
565 #define G_008C08_DATA_INVALIDATE(x) (((x) >> 1) & 0x1)
566 #define C_008C08_DATA_INVALIDATE 0xFFFFFFFD
567 /* CIK */
568 #define R_030D20_SQC_CACHES 0x030D20
569 #define S_030D20_INST_INVALIDATE(x) (((x) & 0x1) << 0)
570 #define G_030D20_INST_INVALIDATE(x) (((x) >> 0) & 0x1)
571 #define C_030D20_INST_INVALIDATE 0xFFFFFFFE
572 #define S_030D20_DATA_INVALIDATE(x) (((x) & 0x1) << 1)
573 #define G_030D20_DATA_INVALIDATE(x) (((x) >> 1) & 0x1)
574 #define C_030D20_DATA_INVALIDATE 0xFFFFFFFD
575 #define S_030D20_INVALIDATE_VOLATILE(x) (((x) & 0x1) << 2)
576 #define G_030D20_INVALIDATE_VOLATILE(x) (((x) >> 2) & 0x1)
577 #define C_030D20_INVALIDATE_VOLATILE 0xFFFFFFFB
578 /* */
579 #define R_008C0C_SQ_RANDOM_WAVE_PRI 0x008C0C
580 #define S_008C0C_RET(x) (((x) & 0x7F) << 0)
581 #define G_008C0C_RET(x) (((x) >> 0) & 0x7F)
582 #define C_008C0C_RET 0xFFFFFF80
583 #define S_008C0C_RUI(x) (((x) & 0x07) << 7)
584 #define G_008C0C_RUI(x) (((x) >> 7) & 0x07)
585 #define C_008C0C_RUI 0xFFFFFC7F
586 #define S_008C0C_RNG(x) (((x) & 0x7FF) << 10)
587 #define G_008C0C_RNG(x) (((x) >> 10) & 0x7FF)
588 #define C_008C0C_RNG 0xFFE003FF
589 #if 0
590 /* CIK */
591 #define R_008DFC_SQ_FLAT_1 0x008DFC
592 #define S_008DFC_ADDR(x) (((x) & 0xFF) << 0)
593 #define G_008DFC_ADDR(x) (((x) >> 0) & 0xFF)
594 #define C_008DFC_ADDR 0xFFFFFF00
595 #define V_008DFC_SQ_VGPR 0x00
596 #define S_008DFC_DATA(x) (((x) & 0xFF) << 8)
597 #define G_008DFC_DATA(x) (((x) >> 8) & 0xFF)
598 #define C_008DFC_DATA 0xFFFF00FF
599 #define V_008DFC_SQ_VGPR 0x00
600 #define S_008DFC_TFE(x) (((x) & 0x1) << 23)
601 #define G_008DFC_TFE(x) (((x) >> 23) & 0x1)
602 #define C_008DFC_TFE 0xFF7FFFFF
603 #define S_008DFC_VDST(x) (((x) & 0xFF) << 24)
604 #define G_008DFC_VDST(x) (((x) >> 24) & 0xFF)
605 #define C_008DFC_VDST 0x00FFFFFF
606 #define V_008DFC_SQ_VGPR 0x00
607 /* */
608 #define R_008DFC_SQ_INST 0x008DFC
609 #define R_008DFC_SQ_VOP1 0x008DFC
610 #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0)
611 #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF)
612 #define C_008DFC_SRC0 0xFFFFFE00
613 #define V_008DFC_SQ_SGPR 0x00
614 /* CIK */
615 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
616 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
617 /* */
618 #define V_008DFC_SQ_VCC_LO 0x6A
619 #define V_008DFC_SQ_VCC_HI 0x6B
620 #define V_008DFC_SQ_TBA_LO 0x6C
621 #define V_008DFC_SQ_TBA_HI 0x6D
622 #define V_008DFC_SQ_TMA_LO 0x6E
623 #define V_008DFC_SQ_TMA_HI 0x6F
624 #define V_008DFC_SQ_TTMP0 0x70
625 #define V_008DFC_SQ_TTMP1 0x71
626 #define V_008DFC_SQ_TTMP2 0x72
627 #define V_008DFC_SQ_TTMP3 0x73
628 #define V_008DFC_SQ_TTMP4 0x74
629 #define V_008DFC_SQ_TTMP5 0x75
630 #define V_008DFC_SQ_TTMP6 0x76
631 #define V_008DFC_SQ_TTMP7 0x77
632 #define V_008DFC_SQ_TTMP8 0x78
633 #define V_008DFC_SQ_TTMP9 0x79
634 #define V_008DFC_SQ_TTMP10 0x7A
635 #define V_008DFC_SQ_TTMP11 0x7B
636 #define V_008DFC_SQ_M0 0x7C
637 #define V_008DFC_SQ_EXEC_LO 0x7E
638 #define V_008DFC_SQ_EXEC_HI 0x7F
639 #define V_008DFC_SQ_SRC_0 0x80
640 #define V_008DFC_SQ_SRC_1_INT 0x81
641 #define V_008DFC_SQ_SRC_2_INT 0x82
642 #define V_008DFC_SQ_SRC_3_INT 0x83
643 #define V_008DFC_SQ_SRC_4_INT 0x84
644 #define V_008DFC_SQ_SRC_5_INT 0x85
645 #define V_008DFC_SQ_SRC_6_INT 0x86
646 #define V_008DFC_SQ_SRC_7_INT 0x87
647 #define V_008DFC_SQ_SRC_8_INT 0x88
648 #define V_008DFC_SQ_SRC_9_INT 0x89
649 #define V_008DFC_SQ_SRC_10_INT 0x8A
650 #define V_008DFC_SQ_SRC_11_INT 0x8B
651 #define V_008DFC_SQ_SRC_12_INT 0x8C
652 #define V_008DFC_SQ_SRC_13_INT 0x8D
653 #define V_008DFC_SQ_SRC_14_INT 0x8E
654 #define V_008DFC_SQ_SRC_15_INT 0x8F
655 #define V_008DFC_SQ_SRC_16_INT 0x90
656 #define V_008DFC_SQ_SRC_17_INT 0x91
657 #define V_008DFC_SQ_SRC_18_INT 0x92
658 #define V_008DFC_SQ_SRC_19_INT 0x93
659 #define V_008DFC_SQ_SRC_20_INT 0x94
660 #define V_008DFC_SQ_SRC_21_INT 0x95
661 #define V_008DFC_SQ_SRC_22_INT 0x96
662 #define V_008DFC_SQ_SRC_23_INT 0x97
663 #define V_008DFC_SQ_SRC_24_INT 0x98
664 #define V_008DFC_SQ_SRC_25_INT 0x99
665 #define V_008DFC_SQ_SRC_26_INT 0x9A
666 #define V_008DFC_SQ_SRC_27_INT 0x9B
667 #define V_008DFC_SQ_SRC_28_INT 0x9C
668 #define V_008DFC_SQ_SRC_29_INT 0x9D
669 #define V_008DFC_SQ_SRC_30_INT 0x9E
670 #define V_008DFC_SQ_SRC_31_INT 0x9F
671 #define V_008DFC_SQ_SRC_32_INT 0xA0
672 #define V_008DFC_SQ_SRC_33_INT 0xA1
673 #define V_008DFC_SQ_SRC_34_INT 0xA2
674 #define V_008DFC_SQ_SRC_35_INT 0xA3
675 #define V_008DFC_SQ_SRC_36_INT 0xA4
676 #define V_008DFC_SQ_SRC_37_INT 0xA5
677 #define V_008DFC_SQ_SRC_38_INT 0xA6
678 #define V_008DFC_SQ_SRC_39_INT 0xA7
679 #define V_008DFC_SQ_SRC_40_INT 0xA8
680 #define V_008DFC_SQ_SRC_41_INT 0xA9
681 #define V_008DFC_SQ_SRC_42_INT 0xAA
682 #define V_008DFC_SQ_SRC_43_INT 0xAB
683 #define V_008DFC_SQ_SRC_44_INT 0xAC
684 #define V_008DFC_SQ_SRC_45_INT 0xAD
685 #define V_008DFC_SQ_SRC_46_INT 0xAE
686 #define V_008DFC_SQ_SRC_47_INT 0xAF
687 #define V_008DFC_SQ_SRC_48_INT 0xB0
688 #define V_008DFC_SQ_SRC_49_INT 0xB1
689 #define V_008DFC_SQ_SRC_50_INT 0xB2
690 #define V_008DFC_SQ_SRC_51_INT 0xB3
691 #define V_008DFC_SQ_SRC_52_INT 0xB4
692 #define V_008DFC_SQ_SRC_53_INT 0xB5
693 #define V_008DFC_SQ_SRC_54_INT 0xB6
694 #define V_008DFC_SQ_SRC_55_INT 0xB7
695 #define V_008DFC_SQ_SRC_56_INT 0xB8
696 #define V_008DFC_SQ_SRC_57_INT 0xB9
697 #define V_008DFC_SQ_SRC_58_INT 0xBA
698 #define V_008DFC_SQ_SRC_59_INT 0xBB
699 #define V_008DFC_SQ_SRC_60_INT 0xBC
700 #define V_008DFC_SQ_SRC_61_INT 0xBD
701 #define V_008DFC_SQ_SRC_62_INT 0xBE
702 #define V_008DFC_SQ_SRC_63_INT 0xBF
703 #define V_008DFC_SQ_SRC_64_INT 0xC0
704 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
705 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
706 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
707 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
708 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
709 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
710 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
711 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
712 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
713 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
714 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
715 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
716 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
717 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
718 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
719 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
720 #define V_008DFC_SQ_SRC_0_5 0xF0
721 #define V_008DFC_SQ_SRC_M_0_5 0xF1
722 #define V_008DFC_SQ_SRC_1 0xF2
723 #define V_008DFC_SQ_SRC_M_1 0xF3
724 #define V_008DFC_SQ_SRC_2 0xF4
725 #define V_008DFC_SQ_SRC_M_2 0xF5
726 #define V_008DFC_SQ_SRC_4 0xF6
727 #define V_008DFC_SQ_SRC_M_4 0xF7
728 #define V_008DFC_SQ_SRC_VCCZ 0xFB
729 #define V_008DFC_SQ_SRC_EXECZ 0xFC
730 #define V_008DFC_SQ_SRC_SCC 0xFD
731 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
732 #define V_008DFC_SQ_SRC_VGPR 0x100
733 #define S_008DFC_OP(x) (((x) & 0xFF) << 9)
734 #define G_008DFC_OP(x) (((x) >> 9) & 0xFF)
735 #define C_008DFC_OP 0xFFFE01FF
736 #define V_008DFC_SQ_V_NOP 0x00
737 #define V_008DFC_SQ_V_MOV_B32 0x01
738 #define V_008DFC_SQ_V_READFIRSTLANE_B32 0x02
739 #define V_008DFC_SQ_V_CVT_I32_F64 0x03
740 #define V_008DFC_SQ_V_CVT_F64_I32 0x04
741 #define V_008DFC_SQ_V_CVT_F32_I32 0x05
742 #define V_008DFC_SQ_V_CVT_F32_U32 0x06
743 #define V_008DFC_SQ_V_CVT_U32_F32 0x07
744 #define V_008DFC_SQ_V_CVT_I32_F32 0x08
745 #define V_008DFC_SQ_V_MOV_FED_B32 0x09
746 #define V_008DFC_SQ_V_CVT_F16_F32 0x0A
747 #define V_008DFC_SQ_V_CVT_F32_F16 0x0B
748 #define V_008DFC_SQ_V_CVT_RPI_I32_F32 0x0C
749 #define V_008DFC_SQ_V_CVT_FLR_I32_F32 0x0D
750 #define V_008DFC_SQ_V_CVT_OFF_F32_I4 0x0E
751 #define V_008DFC_SQ_V_CVT_F32_F64 0x0F
752 #define V_008DFC_SQ_V_CVT_F64_F32 0x10
753 #define V_008DFC_SQ_V_CVT_F32_UBYTE0 0x11
754 #define V_008DFC_SQ_V_CVT_F32_UBYTE1 0x12
755 #define V_008DFC_SQ_V_CVT_F32_UBYTE2 0x13
756 #define V_008DFC_SQ_V_CVT_F32_UBYTE3 0x14
757 #define V_008DFC_SQ_V_CVT_U32_F64 0x15
758 #define V_008DFC_SQ_V_CVT_F64_U32 0x16
759 /* CIK */
760 #define V_008DFC_SQ_V_TRUNC_F64 0x17
761 #define V_008DFC_SQ_V_CEIL_F64 0x18
762 #define V_008DFC_SQ_V_RNDNE_F64 0x19
763 #define V_008DFC_SQ_V_FLOOR_F64 0x1A
764 /* */
765 #define V_008DFC_SQ_V_FRACT_F32 0x20
766 #define V_008DFC_SQ_V_TRUNC_F32 0x21
767 #define V_008DFC_SQ_V_CEIL_F32 0x22
768 #define V_008DFC_SQ_V_RNDNE_F32 0x23
769 #define V_008DFC_SQ_V_FLOOR_F32 0x24
770 #define V_008DFC_SQ_V_EXP_F32 0x25
771 #define V_008DFC_SQ_V_LOG_CLAMP_F32 0x26
772 #define V_008DFC_SQ_V_LOG_F32 0x27
773 #define V_008DFC_SQ_V_RCP_CLAMP_F32 0x28
774 #define V_008DFC_SQ_V_RCP_LEGACY_F32 0x29
775 #define V_008DFC_SQ_V_RCP_F32 0x2A
776 #define V_008DFC_SQ_V_RCP_IFLAG_F32 0x2B
777 #define V_008DFC_SQ_V_RSQ_CLAMP_F32 0x2C
778 #define V_008DFC_SQ_V_RSQ_LEGACY_F32 0x2D
779 #define V_008DFC_SQ_V_RSQ_F32 0x2E
780 #define V_008DFC_SQ_V_RCP_F64 0x2F
781 #define V_008DFC_SQ_V_RCP_CLAMP_F64 0x30
782 #define V_008DFC_SQ_V_RSQ_F64 0x31
783 #define V_008DFC_SQ_V_RSQ_CLAMP_F64 0x32
784 #define V_008DFC_SQ_V_SQRT_F32 0x33
785 #define V_008DFC_SQ_V_SQRT_F64 0x34
786 #define V_008DFC_SQ_V_SIN_F32 0x35
787 #define V_008DFC_SQ_V_COS_F32 0x36
788 #define V_008DFC_SQ_V_NOT_B32 0x37
789 #define V_008DFC_SQ_V_BFREV_B32 0x38
790 #define V_008DFC_SQ_V_FFBH_U32 0x39
791 #define V_008DFC_SQ_V_FFBL_B32 0x3A
792 #define V_008DFC_SQ_V_FFBH_I32 0x3B
793 #define V_008DFC_SQ_V_FREXP_EXP_I32_F64 0x3C
794 #define V_008DFC_SQ_V_FREXP_MANT_F64 0x3D
795 #define V_008DFC_SQ_V_FRACT_F64 0x3E
796 #define V_008DFC_SQ_V_FREXP_EXP_I32_F32 0x3F
797 #define V_008DFC_SQ_V_FREXP_MANT_F32 0x40
798 #define V_008DFC_SQ_V_CLREXCP 0x41
799 #define V_008DFC_SQ_V_MOVRELD_B32 0x42
800 #define V_008DFC_SQ_V_MOVRELS_B32 0x43
801 #define V_008DFC_SQ_V_MOVRELSD_B32 0x44
802 /* CIK */
803 #define V_008DFC_SQ_V_LOG_LEGACY_F32 0x45
804 #define V_008DFC_SQ_V_EXP_LEGACY_F32 0x46
805 /* */
806 #define S_008DFC_VDST(x) (((x) & 0xFF) << 17)
807 #define G_008DFC_VDST(x) (((x) >> 17) & 0xFF)
808 #define C_008DFC_VDST 0xFE01FFFF
809 #define V_008DFC_SQ_VGPR 0x00
810 #define S_008DFC_ENCODING(x) (((x) & 0x7F) << 25)
811 #define G_008DFC_ENCODING(x) (((x) >> 25) & 0x7F)
812 #define C_008DFC_ENCODING 0x01FFFFFF
813 #define V_008DFC_SQ_ENC_VOP1_FIELD 0x3F
814 #define R_008DFC_SQ_MIMG_1 0x008DFC
815 #define S_008DFC_VADDR(x) (((x) & 0xFF) << 0)
816 #define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF)
817 #define C_008DFC_VADDR 0xFFFFFF00
818 #define V_008DFC_SQ_VGPR 0x00
819 #define S_008DFC_VDATA(x) (((x) & 0xFF) << 8)
820 #define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF)
821 #define C_008DFC_VDATA 0xFFFF00FF
822 #define V_008DFC_SQ_VGPR 0x00
823 #define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16)
824 #define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F)
825 #define C_008DFC_SRSRC 0xFFE0FFFF
826 #define S_008DFC_SSAMP(x) (((x) & 0x1F) << 21)
827 #define G_008DFC_SSAMP(x) (((x) >> 21) & 0x1F)
828 #define C_008DFC_SSAMP 0xFC1FFFFF
829 #define R_008DFC_SQ_VOP3_1 0x008DFC
830 #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0)
831 #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF)
832 #define C_008DFC_SRC0 0xFFFFFE00
833 #define V_008DFC_SQ_SGPR 0x00
834 /* CIK */
835 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
836 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
837 /* */
838 #define V_008DFC_SQ_VCC_LO 0x6A
839 #define V_008DFC_SQ_VCC_HI 0x6B
840 #define V_008DFC_SQ_TBA_LO 0x6C
841 #define V_008DFC_SQ_TBA_HI 0x6D
842 #define V_008DFC_SQ_TMA_LO 0x6E
843 #define V_008DFC_SQ_TMA_HI 0x6F
844 #define V_008DFC_SQ_TTMP0 0x70
845 #define V_008DFC_SQ_TTMP1 0x71
846 #define V_008DFC_SQ_TTMP2 0x72
847 #define V_008DFC_SQ_TTMP3 0x73
848 #define V_008DFC_SQ_TTMP4 0x74
849 #define V_008DFC_SQ_TTMP5 0x75
850 #define V_008DFC_SQ_TTMP6 0x76
851 #define V_008DFC_SQ_TTMP7 0x77
852 #define V_008DFC_SQ_TTMP8 0x78
853 #define V_008DFC_SQ_TTMP9 0x79
854 #define V_008DFC_SQ_TTMP10 0x7A
855 #define V_008DFC_SQ_TTMP11 0x7B
856 #define V_008DFC_SQ_M0 0x7C
857 #define V_008DFC_SQ_EXEC_LO 0x7E
858 #define V_008DFC_SQ_EXEC_HI 0x7F
859 #define V_008DFC_SQ_SRC_0 0x80
860 #define V_008DFC_SQ_SRC_1_INT 0x81
861 #define V_008DFC_SQ_SRC_2_INT 0x82
862 #define V_008DFC_SQ_SRC_3_INT 0x83
863 #define V_008DFC_SQ_SRC_4_INT 0x84
864 #define V_008DFC_SQ_SRC_5_INT 0x85
865 #define V_008DFC_SQ_SRC_6_INT 0x86
866 #define V_008DFC_SQ_SRC_7_INT 0x87
867 #define V_008DFC_SQ_SRC_8_INT 0x88
868 #define V_008DFC_SQ_SRC_9_INT 0x89
869 #define V_008DFC_SQ_SRC_10_INT 0x8A
870 #define V_008DFC_SQ_SRC_11_INT 0x8B
871 #define V_008DFC_SQ_SRC_12_INT 0x8C
872 #define V_008DFC_SQ_SRC_13_INT 0x8D
873 #define V_008DFC_SQ_SRC_14_INT 0x8E
874 #define V_008DFC_SQ_SRC_15_INT 0x8F
875 #define V_008DFC_SQ_SRC_16_INT 0x90
876 #define V_008DFC_SQ_SRC_17_INT 0x91
877 #define V_008DFC_SQ_SRC_18_INT 0x92
878 #define V_008DFC_SQ_SRC_19_INT 0x93
879 #define V_008DFC_SQ_SRC_20_INT 0x94
880 #define V_008DFC_SQ_SRC_21_INT 0x95
881 #define V_008DFC_SQ_SRC_22_INT 0x96
882 #define V_008DFC_SQ_SRC_23_INT 0x97
883 #define V_008DFC_SQ_SRC_24_INT 0x98
884 #define V_008DFC_SQ_SRC_25_INT 0x99
885 #define V_008DFC_SQ_SRC_26_INT 0x9A
886 #define V_008DFC_SQ_SRC_27_INT 0x9B
887 #define V_008DFC_SQ_SRC_28_INT 0x9C
888 #define V_008DFC_SQ_SRC_29_INT 0x9D
889 #define V_008DFC_SQ_SRC_30_INT 0x9E
890 #define V_008DFC_SQ_SRC_31_INT 0x9F
891 #define V_008DFC_SQ_SRC_32_INT 0xA0
892 #define V_008DFC_SQ_SRC_33_INT 0xA1
893 #define V_008DFC_SQ_SRC_34_INT 0xA2
894 #define V_008DFC_SQ_SRC_35_INT 0xA3
895 #define V_008DFC_SQ_SRC_36_INT 0xA4
896 #define V_008DFC_SQ_SRC_37_INT 0xA5
897 #define V_008DFC_SQ_SRC_38_INT 0xA6
898 #define V_008DFC_SQ_SRC_39_INT 0xA7
899 #define V_008DFC_SQ_SRC_40_INT 0xA8
900 #define V_008DFC_SQ_SRC_41_INT 0xA9
901 #define V_008DFC_SQ_SRC_42_INT 0xAA
902 #define V_008DFC_SQ_SRC_43_INT 0xAB
903 #define V_008DFC_SQ_SRC_44_INT 0xAC
904 #define V_008DFC_SQ_SRC_45_INT 0xAD
905 #define V_008DFC_SQ_SRC_46_INT 0xAE
906 #define V_008DFC_SQ_SRC_47_INT 0xAF
907 #define V_008DFC_SQ_SRC_48_INT 0xB0
908 #define V_008DFC_SQ_SRC_49_INT 0xB1
909 #define V_008DFC_SQ_SRC_50_INT 0xB2
910 #define V_008DFC_SQ_SRC_51_INT 0xB3
911 #define V_008DFC_SQ_SRC_52_INT 0xB4
912 #define V_008DFC_SQ_SRC_53_INT 0xB5
913 #define V_008DFC_SQ_SRC_54_INT 0xB6
914 #define V_008DFC_SQ_SRC_55_INT 0xB7
915 #define V_008DFC_SQ_SRC_56_INT 0xB8
916 #define V_008DFC_SQ_SRC_57_INT 0xB9
917 #define V_008DFC_SQ_SRC_58_INT 0xBA
918 #define V_008DFC_SQ_SRC_59_INT 0xBB
919 #define V_008DFC_SQ_SRC_60_INT 0xBC
920 #define V_008DFC_SQ_SRC_61_INT 0xBD
921 #define V_008DFC_SQ_SRC_62_INT 0xBE
922 #define V_008DFC_SQ_SRC_63_INT 0xBF
923 #define V_008DFC_SQ_SRC_64_INT 0xC0
924 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
925 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
926 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
927 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
928 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
929 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
930 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
931 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
932 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
933 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
934 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
935 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
936 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
937 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
938 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
939 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
940 #define V_008DFC_SQ_SRC_0_5 0xF0
941 #define V_008DFC_SQ_SRC_M_0_5 0xF1
942 #define V_008DFC_SQ_SRC_1 0xF2
943 #define V_008DFC_SQ_SRC_M_1 0xF3
944 #define V_008DFC_SQ_SRC_2 0xF4
945 #define V_008DFC_SQ_SRC_M_2 0xF5
946 #define V_008DFC_SQ_SRC_4 0xF6
947 #define V_008DFC_SQ_SRC_M_4 0xF7
948 #define V_008DFC_SQ_SRC_VCCZ 0xFB
949 #define V_008DFC_SQ_SRC_EXECZ 0xFC
950 #define V_008DFC_SQ_SRC_SCC 0xFD
951 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
952 #define V_008DFC_SQ_SRC_VGPR 0x100
953 #define S_008DFC_SRC1(x) (((x) & 0x1FF) << 9)
954 #define G_008DFC_SRC1(x) (((x) >> 9) & 0x1FF)
955 #define C_008DFC_SRC1 0xFFFC01FF
956 #define V_008DFC_SQ_SGPR 0x00
957 /* CIK */
958 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
959 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
960 /* */
961 #define V_008DFC_SQ_VCC_LO 0x6A
962 #define V_008DFC_SQ_VCC_HI 0x6B
963 #define V_008DFC_SQ_TBA_LO 0x6C
964 #define V_008DFC_SQ_TBA_HI 0x6D
965 #define V_008DFC_SQ_TMA_LO 0x6E
966 #define V_008DFC_SQ_TMA_HI 0x6F
967 #define V_008DFC_SQ_TTMP0 0x70
968 #define V_008DFC_SQ_TTMP1 0x71
969 #define V_008DFC_SQ_TTMP2 0x72
970 #define V_008DFC_SQ_TTMP3 0x73
971 #define V_008DFC_SQ_TTMP4 0x74
972 #define V_008DFC_SQ_TTMP5 0x75
973 #define V_008DFC_SQ_TTMP6 0x76
974 #define V_008DFC_SQ_TTMP7 0x77
975 #define V_008DFC_SQ_TTMP8 0x78
976 #define V_008DFC_SQ_TTMP9 0x79
977 #define V_008DFC_SQ_TTMP10 0x7A
978 #define V_008DFC_SQ_TTMP11 0x7B
979 #define V_008DFC_SQ_M0 0x7C
980 #define V_008DFC_SQ_EXEC_LO 0x7E
981 #define V_008DFC_SQ_EXEC_HI 0x7F
982 #define V_008DFC_SQ_SRC_0 0x80
983 #define V_008DFC_SQ_SRC_1_INT 0x81
984 #define V_008DFC_SQ_SRC_2_INT 0x82
985 #define V_008DFC_SQ_SRC_3_INT 0x83
986 #define V_008DFC_SQ_SRC_4_INT 0x84
987 #define V_008DFC_SQ_SRC_5_INT 0x85
988 #define V_008DFC_SQ_SRC_6_INT 0x86
989 #define V_008DFC_SQ_SRC_7_INT 0x87
990 #define V_008DFC_SQ_SRC_8_INT 0x88
991 #define V_008DFC_SQ_SRC_9_INT 0x89
992 #define V_008DFC_SQ_SRC_10_INT 0x8A
993 #define V_008DFC_SQ_SRC_11_INT 0x8B
994 #define V_008DFC_SQ_SRC_12_INT 0x8C
995 #define V_008DFC_SQ_SRC_13_INT 0x8D
996 #define V_008DFC_SQ_SRC_14_INT 0x8E
997 #define V_008DFC_SQ_SRC_15_INT 0x8F
998 #define V_008DFC_SQ_SRC_16_INT 0x90
999 #define V_008DFC_SQ_SRC_17_INT 0x91
1000 #define V_008DFC_SQ_SRC_18_INT 0x92
1001 #define V_008DFC_SQ_SRC_19_INT 0x93
1002 #define V_008DFC_SQ_SRC_20_INT 0x94
1003 #define V_008DFC_SQ_SRC_21_INT 0x95
1004 #define V_008DFC_SQ_SRC_22_INT 0x96
1005 #define V_008DFC_SQ_SRC_23_INT 0x97
1006 #define V_008DFC_SQ_SRC_24_INT 0x98
1007 #define V_008DFC_SQ_SRC_25_INT 0x99
1008 #define V_008DFC_SQ_SRC_26_INT 0x9A
1009 #define V_008DFC_SQ_SRC_27_INT 0x9B
1010 #define V_008DFC_SQ_SRC_28_INT 0x9C
1011 #define V_008DFC_SQ_SRC_29_INT 0x9D
1012 #define V_008DFC_SQ_SRC_30_INT 0x9E
1013 #define V_008DFC_SQ_SRC_31_INT 0x9F
1014 #define V_008DFC_SQ_SRC_32_INT 0xA0
1015 #define V_008DFC_SQ_SRC_33_INT 0xA1
1016 #define V_008DFC_SQ_SRC_34_INT 0xA2
1017 #define V_008DFC_SQ_SRC_35_INT 0xA3
1018 #define V_008DFC_SQ_SRC_36_INT 0xA4
1019 #define V_008DFC_SQ_SRC_37_INT 0xA5
1020 #define V_008DFC_SQ_SRC_38_INT 0xA6
1021 #define V_008DFC_SQ_SRC_39_INT 0xA7
1022 #define V_008DFC_SQ_SRC_40_INT 0xA8
1023 #define V_008DFC_SQ_SRC_41_INT 0xA9
1024 #define V_008DFC_SQ_SRC_42_INT 0xAA
1025 #define V_008DFC_SQ_SRC_43_INT 0xAB
1026 #define V_008DFC_SQ_SRC_44_INT 0xAC
1027 #define V_008DFC_SQ_SRC_45_INT 0xAD
1028 #define V_008DFC_SQ_SRC_46_INT 0xAE
1029 #define V_008DFC_SQ_SRC_47_INT 0xAF
1030 #define V_008DFC_SQ_SRC_48_INT 0xB0
1031 #define V_008DFC_SQ_SRC_49_INT 0xB1
1032 #define V_008DFC_SQ_SRC_50_INT 0xB2
1033 #define V_008DFC_SQ_SRC_51_INT 0xB3
1034 #define V_008DFC_SQ_SRC_52_INT 0xB4
1035 #define V_008DFC_SQ_SRC_53_INT 0xB5
1036 #define V_008DFC_SQ_SRC_54_INT 0xB6
1037 #define V_008DFC_SQ_SRC_55_INT 0xB7
1038 #define V_008DFC_SQ_SRC_56_INT 0xB8
1039 #define V_008DFC_SQ_SRC_57_INT 0xB9
1040 #define V_008DFC_SQ_SRC_58_INT 0xBA
1041 #define V_008DFC_SQ_SRC_59_INT 0xBB
1042 #define V_008DFC_SQ_SRC_60_INT 0xBC
1043 #define V_008DFC_SQ_SRC_61_INT 0xBD
1044 #define V_008DFC_SQ_SRC_62_INT 0xBE
1045 #define V_008DFC_SQ_SRC_63_INT 0xBF
1046 #define V_008DFC_SQ_SRC_64_INT 0xC0
1047 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
1048 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
1049 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
1050 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
1051 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
1052 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
1053 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
1054 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
1055 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
1056 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
1057 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
1058 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
1059 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
1060 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
1061 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
1062 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
1063 #define V_008DFC_SQ_SRC_0_5 0xF0
1064 #define V_008DFC_SQ_SRC_M_0_5 0xF1
1065 #define V_008DFC_SQ_SRC_1 0xF2
1066 #define V_008DFC_SQ_SRC_M_1 0xF3
1067 #define V_008DFC_SQ_SRC_2 0xF4
1068 #define V_008DFC_SQ_SRC_M_2 0xF5
1069 #define V_008DFC_SQ_SRC_4 0xF6
1070 #define V_008DFC_SQ_SRC_M_4 0xF7
1071 #define V_008DFC_SQ_SRC_VCCZ 0xFB
1072 #define V_008DFC_SQ_SRC_EXECZ 0xFC
1073 #define V_008DFC_SQ_SRC_SCC 0xFD
1074 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
1075 #define V_008DFC_SQ_SRC_VGPR 0x100
1076 #define S_008DFC_SRC2(x) (((x) & 0x1FF) << 18)
1077 #define G_008DFC_SRC2(x) (((x) >> 18) & 0x1FF)
1078 #define C_008DFC_SRC2 0xF803FFFF
1079 #define V_008DFC_SQ_SGPR 0x00
1080 /* CIK */
1081 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
1082 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
1083 /* */
1084 #define V_008DFC_SQ_VCC_LO 0x6A
1085 #define V_008DFC_SQ_VCC_HI 0x6B
1086 #define V_008DFC_SQ_TBA_LO 0x6C
1087 #define V_008DFC_SQ_TBA_HI 0x6D
1088 #define V_008DFC_SQ_TMA_LO 0x6E
1089 #define V_008DFC_SQ_TMA_HI 0x6F
1090 #define V_008DFC_SQ_TTMP0 0x70
1091 #define V_008DFC_SQ_TTMP1 0x71
1092 #define V_008DFC_SQ_TTMP2 0x72
1093 #define V_008DFC_SQ_TTMP3 0x73
1094 #define V_008DFC_SQ_TTMP4 0x74
1095 #define V_008DFC_SQ_TTMP5 0x75
1096 #define V_008DFC_SQ_TTMP6 0x76
1097 #define V_008DFC_SQ_TTMP7 0x77
1098 #define V_008DFC_SQ_TTMP8 0x78
1099 #define V_008DFC_SQ_TTMP9 0x79
1100 #define V_008DFC_SQ_TTMP10 0x7A
1101 #define V_008DFC_SQ_TTMP11 0x7B
1102 #define V_008DFC_SQ_M0 0x7C
1103 #define V_008DFC_SQ_EXEC_LO 0x7E
1104 #define V_008DFC_SQ_EXEC_HI 0x7F
1105 #define V_008DFC_SQ_SRC_0 0x80
1106 #define V_008DFC_SQ_SRC_1_INT 0x81
1107 #define V_008DFC_SQ_SRC_2_INT 0x82
1108 #define V_008DFC_SQ_SRC_3_INT 0x83
1109 #define V_008DFC_SQ_SRC_4_INT 0x84
1110 #define V_008DFC_SQ_SRC_5_INT 0x85
1111 #define V_008DFC_SQ_SRC_6_INT 0x86
1112 #define V_008DFC_SQ_SRC_7_INT 0x87
1113 #define V_008DFC_SQ_SRC_8_INT 0x88
1114 #define V_008DFC_SQ_SRC_9_INT 0x89
1115 #define V_008DFC_SQ_SRC_10_INT 0x8A
1116 #define V_008DFC_SQ_SRC_11_INT 0x8B
1117 #define V_008DFC_SQ_SRC_12_INT 0x8C
1118 #define V_008DFC_SQ_SRC_13_INT 0x8D
1119 #define V_008DFC_SQ_SRC_14_INT 0x8E
1120 #define V_008DFC_SQ_SRC_15_INT 0x8F
1121 #define V_008DFC_SQ_SRC_16_INT 0x90
1122 #define V_008DFC_SQ_SRC_17_INT 0x91
1123 #define V_008DFC_SQ_SRC_18_INT 0x92
1124 #define V_008DFC_SQ_SRC_19_INT 0x93
1125 #define V_008DFC_SQ_SRC_20_INT 0x94
1126 #define V_008DFC_SQ_SRC_21_INT 0x95
1127 #define V_008DFC_SQ_SRC_22_INT 0x96
1128 #define V_008DFC_SQ_SRC_23_INT 0x97
1129 #define V_008DFC_SQ_SRC_24_INT 0x98
1130 #define V_008DFC_SQ_SRC_25_INT 0x99
1131 #define V_008DFC_SQ_SRC_26_INT 0x9A
1132 #define V_008DFC_SQ_SRC_27_INT 0x9B
1133 #define V_008DFC_SQ_SRC_28_INT 0x9C
1134 #define V_008DFC_SQ_SRC_29_INT 0x9D
1135 #define V_008DFC_SQ_SRC_30_INT 0x9E
1136 #define V_008DFC_SQ_SRC_31_INT 0x9F
1137 #define V_008DFC_SQ_SRC_32_INT 0xA0
1138 #define V_008DFC_SQ_SRC_33_INT 0xA1
1139 #define V_008DFC_SQ_SRC_34_INT 0xA2
1140 #define V_008DFC_SQ_SRC_35_INT 0xA3
1141 #define V_008DFC_SQ_SRC_36_INT 0xA4
1142 #define V_008DFC_SQ_SRC_37_INT 0xA5
1143 #define V_008DFC_SQ_SRC_38_INT 0xA6
1144 #define V_008DFC_SQ_SRC_39_INT 0xA7
1145 #define V_008DFC_SQ_SRC_40_INT 0xA8
1146 #define V_008DFC_SQ_SRC_41_INT 0xA9
1147 #define V_008DFC_SQ_SRC_42_INT 0xAA
1148 #define V_008DFC_SQ_SRC_43_INT 0xAB
1149 #define V_008DFC_SQ_SRC_44_INT 0xAC
1150 #define V_008DFC_SQ_SRC_45_INT 0xAD
1151 #define V_008DFC_SQ_SRC_46_INT 0xAE
1152 #define V_008DFC_SQ_SRC_47_INT 0xAF
1153 #define V_008DFC_SQ_SRC_48_INT 0xB0
1154 #define V_008DFC_SQ_SRC_49_INT 0xB1
1155 #define V_008DFC_SQ_SRC_50_INT 0xB2
1156 #define V_008DFC_SQ_SRC_51_INT 0xB3
1157 #define V_008DFC_SQ_SRC_52_INT 0xB4
1158 #define V_008DFC_SQ_SRC_53_INT 0xB5
1159 #define V_008DFC_SQ_SRC_54_INT 0xB6
1160 #define V_008DFC_SQ_SRC_55_INT 0xB7
1161 #define V_008DFC_SQ_SRC_56_INT 0xB8
1162 #define V_008DFC_SQ_SRC_57_INT 0xB9
1163 #define V_008DFC_SQ_SRC_58_INT 0xBA
1164 #define V_008DFC_SQ_SRC_59_INT 0xBB
1165 #define V_008DFC_SQ_SRC_60_INT 0xBC
1166 #define V_008DFC_SQ_SRC_61_INT 0xBD
1167 #define V_008DFC_SQ_SRC_62_INT 0xBE
1168 #define V_008DFC_SQ_SRC_63_INT 0xBF
1169 #define V_008DFC_SQ_SRC_64_INT 0xC0
1170 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
1171 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
1172 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
1173 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
1174 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
1175 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
1176 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
1177 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
1178 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
1179 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
1180 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
1181 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
1182 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
1183 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
1184 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
1185 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
1186 #define V_008DFC_SQ_SRC_0_5 0xF0
1187 #define V_008DFC_SQ_SRC_M_0_5 0xF1
1188 #define V_008DFC_SQ_SRC_1 0xF2
1189 #define V_008DFC_SQ_SRC_M_1 0xF3
1190 #define V_008DFC_SQ_SRC_2 0xF4
1191 #define V_008DFC_SQ_SRC_M_2 0xF5
1192 #define V_008DFC_SQ_SRC_4 0xF6
1193 #define V_008DFC_SQ_SRC_M_4 0xF7
1194 #define V_008DFC_SQ_SRC_VCCZ 0xFB
1195 #define V_008DFC_SQ_SRC_EXECZ 0xFC
1196 #define V_008DFC_SQ_SRC_SCC 0xFD
1197 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
1198 #define V_008DFC_SQ_SRC_VGPR 0x100
1199 #define S_008DFC_OMOD(x) (((x) & 0x03) << 27)
1200 #define G_008DFC_OMOD(x) (((x) >> 27) & 0x03)
1201 #define C_008DFC_OMOD 0xE7FFFFFF
1202 #define V_008DFC_SQ_OMOD_OFF 0x00
1203 #define V_008DFC_SQ_OMOD_M2 0x01
1204 #define V_008DFC_SQ_OMOD_M4 0x02
1205 #define V_008DFC_SQ_OMOD_D2 0x03
1206 #define S_008DFC_NEG(x) (((x) & 0x07) << 29)
1207 #define G_008DFC_NEG(x) (((x) >> 29) & 0x07)
1208 #define C_008DFC_NEG 0x1FFFFFFF
1209 #define R_008DFC_SQ_MUBUF_1 0x008DFC
1210 #define S_008DFC_VADDR(x) (((x) & 0xFF) << 0)
1211 #define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF)
1212 #define C_008DFC_VADDR 0xFFFFFF00
1213 #define V_008DFC_SQ_VGPR 0x00
1214 #define S_008DFC_VDATA(x) (((x) & 0xFF) << 8)
1215 #define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF)
1216 #define C_008DFC_VDATA 0xFFFF00FF
1217 #define V_008DFC_SQ_VGPR 0x00
1218 #define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16)
1219 #define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F)
1220 #define C_008DFC_SRSRC 0xFFE0FFFF
1221 #define S_008DFC_SLC(x) (((x) & 0x1) << 22)
1222 #define G_008DFC_SLC(x) (((x) >> 22) & 0x1)
1223 #define C_008DFC_SLC 0xFFBFFFFF
1224 #define S_008DFC_TFE(x) (((x) & 0x1) << 23)
1225 #define G_008DFC_TFE(x) (((x) >> 23) & 0x1)
1226 #define C_008DFC_TFE 0xFF7FFFFF
1227 #define S_008DFC_SOFFSET(x) (((x) & 0xFF) << 24)
1228 #define G_008DFC_SOFFSET(x) (((x) >> 24) & 0xFF)
1229 #define C_008DFC_SOFFSET 0x00FFFFFF
1230 #define V_008DFC_SQ_SGPR 0x00
1231 /* CIK */
1232 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
1233 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
1234 /* */
1235 #define V_008DFC_SQ_VCC_LO 0x6A
1236 #define V_008DFC_SQ_VCC_HI 0x6B
1237 #define V_008DFC_SQ_TBA_LO 0x6C
1238 #define V_008DFC_SQ_TBA_HI 0x6D
1239 #define V_008DFC_SQ_TMA_LO 0x6E
1240 #define V_008DFC_SQ_TMA_HI 0x6F
1241 #define V_008DFC_SQ_TTMP0 0x70
1242 #define V_008DFC_SQ_TTMP1 0x71
1243 #define V_008DFC_SQ_TTMP2 0x72
1244 #define V_008DFC_SQ_TTMP3 0x73
1245 #define V_008DFC_SQ_TTMP4 0x74
1246 #define V_008DFC_SQ_TTMP5 0x75
1247 #define V_008DFC_SQ_TTMP6 0x76
1248 #define V_008DFC_SQ_TTMP7 0x77
1249 #define V_008DFC_SQ_TTMP8 0x78
1250 #define V_008DFC_SQ_TTMP9 0x79
1251 #define V_008DFC_SQ_TTMP10 0x7A
1252 #define V_008DFC_SQ_TTMP11 0x7B
1253 #define V_008DFC_SQ_M0 0x7C
1254 #define V_008DFC_SQ_EXEC_LO 0x7E
1255 #define V_008DFC_SQ_EXEC_HI 0x7F
1256 #define V_008DFC_SQ_SRC_0 0x80
1257 #define V_008DFC_SQ_SRC_1_INT 0x81
1258 #define V_008DFC_SQ_SRC_2_INT 0x82
1259 #define V_008DFC_SQ_SRC_3_INT 0x83
1260 #define V_008DFC_SQ_SRC_4_INT 0x84
1261 #define V_008DFC_SQ_SRC_5_INT 0x85
1262 #define V_008DFC_SQ_SRC_6_INT 0x86
1263 #define V_008DFC_SQ_SRC_7_INT 0x87
1264 #define V_008DFC_SQ_SRC_8_INT 0x88
1265 #define V_008DFC_SQ_SRC_9_INT 0x89
1266 #define V_008DFC_SQ_SRC_10_INT 0x8A
1267 #define V_008DFC_SQ_SRC_11_INT 0x8B
1268 #define V_008DFC_SQ_SRC_12_INT 0x8C
1269 #define V_008DFC_SQ_SRC_13_INT 0x8D
1270 #define V_008DFC_SQ_SRC_14_INT 0x8E
1271 #define V_008DFC_SQ_SRC_15_INT 0x8F
1272 #define V_008DFC_SQ_SRC_16_INT 0x90
1273 #define V_008DFC_SQ_SRC_17_INT 0x91
1274 #define V_008DFC_SQ_SRC_18_INT 0x92
1275 #define V_008DFC_SQ_SRC_19_INT 0x93
1276 #define V_008DFC_SQ_SRC_20_INT 0x94
1277 #define V_008DFC_SQ_SRC_21_INT 0x95
1278 #define V_008DFC_SQ_SRC_22_INT 0x96
1279 #define V_008DFC_SQ_SRC_23_INT 0x97
1280 #define V_008DFC_SQ_SRC_24_INT 0x98
1281 #define V_008DFC_SQ_SRC_25_INT 0x99
1282 #define V_008DFC_SQ_SRC_26_INT 0x9A
1283 #define V_008DFC_SQ_SRC_27_INT 0x9B
1284 #define V_008DFC_SQ_SRC_28_INT 0x9C
1285 #define V_008DFC_SQ_SRC_29_INT 0x9D
1286 #define V_008DFC_SQ_SRC_30_INT 0x9E
1287 #define V_008DFC_SQ_SRC_31_INT 0x9F
1288 #define V_008DFC_SQ_SRC_32_INT 0xA0
1289 #define V_008DFC_SQ_SRC_33_INT 0xA1
1290 #define V_008DFC_SQ_SRC_34_INT 0xA2
1291 #define V_008DFC_SQ_SRC_35_INT 0xA3
1292 #define V_008DFC_SQ_SRC_36_INT 0xA4
1293 #define V_008DFC_SQ_SRC_37_INT 0xA5
1294 #define V_008DFC_SQ_SRC_38_INT 0xA6
1295 #define V_008DFC_SQ_SRC_39_INT 0xA7
1296 #define V_008DFC_SQ_SRC_40_INT 0xA8
1297 #define V_008DFC_SQ_SRC_41_INT 0xA9
1298 #define V_008DFC_SQ_SRC_42_INT 0xAA
1299 #define V_008DFC_SQ_SRC_43_INT 0xAB
1300 #define V_008DFC_SQ_SRC_44_INT 0xAC
1301 #define V_008DFC_SQ_SRC_45_INT 0xAD
1302 #define V_008DFC_SQ_SRC_46_INT 0xAE
1303 #define V_008DFC_SQ_SRC_47_INT 0xAF
1304 #define V_008DFC_SQ_SRC_48_INT 0xB0
1305 #define V_008DFC_SQ_SRC_49_INT 0xB1
1306 #define V_008DFC_SQ_SRC_50_INT 0xB2
1307 #define V_008DFC_SQ_SRC_51_INT 0xB3
1308 #define V_008DFC_SQ_SRC_52_INT 0xB4
1309 #define V_008DFC_SQ_SRC_53_INT 0xB5
1310 #define V_008DFC_SQ_SRC_54_INT 0xB6
1311 #define V_008DFC_SQ_SRC_55_INT 0xB7
1312 #define V_008DFC_SQ_SRC_56_INT 0xB8
1313 #define V_008DFC_SQ_SRC_57_INT 0xB9
1314 #define V_008DFC_SQ_SRC_58_INT 0xBA
1315 #define V_008DFC_SQ_SRC_59_INT 0xBB
1316 #define V_008DFC_SQ_SRC_60_INT 0xBC
1317 #define V_008DFC_SQ_SRC_61_INT 0xBD
1318 #define V_008DFC_SQ_SRC_62_INT 0xBE
1319 #define V_008DFC_SQ_SRC_63_INT 0xBF
1320 #define V_008DFC_SQ_SRC_64_INT 0xC0
1321 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
1322 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
1323 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
1324 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
1325 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
1326 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
1327 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
1328 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
1329 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
1330 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
1331 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
1332 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
1333 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
1334 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
1335 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
1336 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
1337 #define V_008DFC_SQ_SRC_0_5 0xF0
1338 #define V_008DFC_SQ_SRC_M_0_5 0xF1
1339 #define V_008DFC_SQ_SRC_1 0xF2
1340 #define V_008DFC_SQ_SRC_M_1 0xF3
1341 #define V_008DFC_SQ_SRC_2 0xF4
1342 #define V_008DFC_SQ_SRC_M_2 0xF5
1343 #define V_008DFC_SQ_SRC_4 0xF6
1344 #define V_008DFC_SQ_SRC_M_4 0xF7
1345 #define V_008DFC_SQ_SRC_VCCZ 0xFB
1346 #define V_008DFC_SQ_SRC_EXECZ 0xFC
1347 #define V_008DFC_SQ_SRC_SCC 0xFD
1348 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
1349 #define R_008DFC_SQ_DS_0 0x008DFC
1350 #define S_008DFC_OFFSET0(x) (((x) & 0xFF) << 0)
1351 #define G_008DFC_OFFSET0(x) (((x) >> 0) & 0xFF)
1352 #define C_008DFC_OFFSET0 0xFFFFFF00
1353 #define S_008DFC_OFFSET1(x) (((x) & 0xFF) << 8)
1354 #define G_008DFC_OFFSET1(x) (((x) >> 8) & 0xFF)
1355 #define C_008DFC_OFFSET1 0xFFFF00FF
1356 #define S_008DFC_GDS(x) (((x) & 0x1) << 17)
1357 #define G_008DFC_GDS(x) (((x) >> 17) & 0x1)
1358 #define C_008DFC_GDS 0xFFFDFFFF
1359 #define S_008DFC_OP(x) (((x) & 0xFF) << 18)
1360 #define G_008DFC_OP(x) (((x) >> 18) & 0xFF)
1361 #define C_008DFC_OP 0xFC03FFFF
1362 #define V_008DFC_SQ_DS_ADD_U32 0x00
1363 #define V_008DFC_SQ_DS_SUB_U32 0x01
1364 #define V_008DFC_SQ_DS_RSUB_U32 0x02
1365 #define V_008DFC_SQ_DS_INC_U32 0x03
1366 #define V_008DFC_SQ_DS_DEC_U32 0x04
1367 #define V_008DFC_SQ_DS_MIN_I32 0x05
1368 #define V_008DFC_SQ_DS_MAX_I32 0x06
1369 #define V_008DFC_SQ_DS_MIN_U32 0x07
1370 #define V_008DFC_SQ_DS_MAX_U32 0x08
1371 #define V_008DFC_SQ_DS_AND_B32 0x09
1372 #define V_008DFC_SQ_DS_OR_B32 0x0A
1373 #define V_008DFC_SQ_DS_XOR_B32 0x0B
1374 #define V_008DFC_SQ_DS_MSKOR_B32 0x0C
1375 #define V_008DFC_SQ_DS_WRITE_B32 0x0D
1376 #define V_008DFC_SQ_DS_WRITE2_B32 0x0E
1377 #define V_008DFC_SQ_DS_WRITE2ST64_B32 0x0F
1378 #define V_008DFC_SQ_DS_CMPST_B32 0x10
1379 #define V_008DFC_SQ_DS_CMPST_F32 0x11
1380 #define V_008DFC_SQ_DS_MIN_F32 0x12
1381 #define V_008DFC_SQ_DS_MAX_F32 0x13
1382 /* CIK */
1383 #define V_008DFC_SQ_DS_NOP 0x14
1384 /* */
1385 #define V_008DFC_SQ_DS_GWS_INIT 0x19
1386 #define V_008DFC_SQ_DS_GWS_SEMA_V 0x1A
1387 #define V_008DFC_SQ_DS_GWS_SEMA_BR 0x1B
1388 #define V_008DFC_SQ_DS_GWS_SEMA_P 0x1C
1389 #define V_008DFC_SQ_DS_GWS_BARRIER 0x1D
1390 #define V_008DFC_SQ_DS_WRITE_B8 0x1E
1391 #define V_008DFC_SQ_DS_WRITE_B16 0x1F
1392 #define V_008DFC_SQ_DS_ADD_RTN_U32 0x20
1393 #define V_008DFC_SQ_DS_SUB_RTN_U32 0x21
1394 #define V_008DFC_SQ_DS_RSUB_RTN_U32 0x22
1395 #define V_008DFC_SQ_DS_INC_RTN_U32 0x23
1396 #define V_008DFC_SQ_DS_DEC_RTN_U32 0x24
1397 #define V_008DFC_SQ_DS_MIN_RTN_I32 0x25
1398 #define V_008DFC_SQ_DS_MAX_RTN_I32 0x26
1399 #define V_008DFC_SQ_DS_MIN_RTN_U32 0x27
1400 #define V_008DFC_SQ_DS_MAX_RTN_U32 0x28
1401 #define V_008DFC_SQ_DS_AND_RTN_B32 0x29
1402 #define V_008DFC_SQ_DS_OR_RTN_B32 0x2A
1403 #define V_008DFC_SQ_DS_XOR_RTN_B32 0x2B
1404 #define V_008DFC_SQ_DS_MSKOR_RTN_B32 0x2C
1405 #define V_008DFC_SQ_DS_WRXCHG_RTN_B32 0x2D
1406 #define V_008DFC_SQ_DS_WRXCHG2_RTN_B32 0x2E
1407 #define V_008DFC_SQ_DS_WRXCHG2ST64_RTN_B32 0x2F
1408 #define V_008DFC_SQ_DS_CMPST_RTN_B32 0x30
1409 #define V_008DFC_SQ_DS_CMPST_RTN_F32 0x31
1410 #define V_008DFC_SQ_DS_MIN_RTN_F32 0x32
1411 #define V_008DFC_SQ_DS_MAX_RTN_F32 0x33
1412 #define V_008DFC_SQ_DS_SWIZZLE_B32 0x35
1413 #define V_008DFC_SQ_DS_READ_B32 0x36
1414 #define V_008DFC_SQ_DS_READ2_B32 0x37
1415 #define V_008DFC_SQ_DS_READ2ST64_B32 0x38
1416 #define V_008DFC_SQ_DS_READ_I8 0x39
1417 #define V_008DFC_SQ_DS_READ_U8 0x3A
1418 #define V_008DFC_SQ_DS_READ_I16 0x3B
1419 #define V_008DFC_SQ_DS_READ_U16 0x3C
1420 #define V_008DFC_SQ_DS_CONSUME 0x3D
1421 #define V_008DFC_SQ_DS_APPEND 0x3E
1422 #define V_008DFC_SQ_DS_ORDERED_COUNT 0x3F
1423 #define V_008DFC_SQ_DS_ADD_U64 0x40
1424 #define V_008DFC_SQ_DS_SUB_U64 0x41
1425 #define V_008DFC_SQ_DS_RSUB_U64 0x42
1426 #define V_008DFC_SQ_DS_INC_U64 0x43
1427 #define V_008DFC_SQ_DS_DEC_U64 0x44
1428 #define V_008DFC_SQ_DS_MIN_I64 0x45
1429 #define V_008DFC_SQ_DS_MAX_I64 0x46
1430 #define V_008DFC_SQ_DS_MIN_U64 0x47
1431 #define V_008DFC_SQ_DS_MAX_U64 0x48
1432 #define V_008DFC_SQ_DS_AND_B64 0x49
1433 #define V_008DFC_SQ_DS_OR_B64 0x4A
1434 #define V_008DFC_SQ_DS_XOR_B64 0x4B
1435 #define V_008DFC_SQ_DS_MSKOR_B64 0x4C
1436 #define V_008DFC_SQ_DS_WRITE_B64 0x4D
1437 #define V_008DFC_SQ_DS_WRITE2_B64 0x4E
1438 #define V_008DFC_SQ_DS_WRITE2ST64_B64 0x4F
1439 #define V_008DFC_SQ_DS_CMPST_B64 0x50
1440 #define V_008DFC_SQ_DS_CMPST_F64 0x51
1441 #define V_008DFC_SQ_DS_MIN_F64 0x52
1442 #define V_008DFC_SQ_DS_MAX_F64 0x53
1443 #define V_008DFC_SQ_DS_ADD_RTN_U64 0x60
1444 #define V_008DFC_SQ_DS_SUB_RTN_U64 0x61
1445 #define V_008DFC_SQ_DS_RSUB_RTN_U64 0x62
1446 #define V_008DFC_SQ_DS_INC_RTN_U64 0x63
1447 #define V_008DFC_SQ_DS_DEC_RTN_U64 0x64
1448 #define V_008DFC_SQ_DS_MIN_RTN_I64 0x65
1449 #define V_008DFC_SQ_DS_MAX_RTN_I64 0x66
1450 #define V_008DFC_SQ_DS_MIN_RTN_U64 0x67
1451 #define V_008DFC_SQ_DS_MAX_RTN_U64 0x68
1452 #define V_008DFC_SQ_DS_AND_RTN_B64 0x69
1453 #define V_008DFC_SQ_DS_OR_RTN_B64 0x6A
1454 #define V_008DFC_SQ_DS_XOR_RTN_B64 0x6B
1455 #define V_008DFC_SQ_DS_MSKOR_RTN_B64 0x6C
1456 #define V_008DFC_SQ_DS_WRXCHG_RTN_B64 0x6D
1457 #define V_008DFC_SQ_DS_WRXCHG2_RTN_B64 0x6E
1458 #define V_008DFC_SQ_DS_WRXCHG2ST64_RTN_B64 0x6F
1459 #define V_008DFC_SQ_DS_CMPST_RTN_B64 0x70
1460 #define V_008DFC_SQ_DS_CMPST_RTN_F64 0x71
1461 #define V_008DFC_SQ_DS_MIN_RTN_F64 0x72
1462 #define V_008DFC_SQ_DS_MAX_RTN_F64 0x73
1463 #define V_008DFC_SQ_DS_READ_B64 0x76
1464 #define V_008DFC_SQ_DS_READ2_B64 0x77
1465 #define V_008DFC_SQ_DS_READ2ST64_B64 0x78
1466 /* CIK */
1467 #define V_008DFC_SQ_DS_CONDXCHG32_RTN_B64 0x7E
1468 /* */
1469 #define V_008DFC_SQ_DS_ADD_SRC2_U32 0x80
1470 #define V_008DFC_SQ_DS_SUB_SRC2_U32 0x81
1471 #define V_008DFC_SQ_DS_RSUB_SRC2_U32 0x82
1472 #define V_008DFC_SQ_DS_INC_SRC2_U32 0x83
1473 #define V_008DFC_SQ_DS_DEC_SRC2_U32 0x84
1474 #define V_008DFC_SQ_DS_MIN_SRC2_I32 0x85
1475 #define V_008DFC_SQ_DS_MAX_SRC2_I32 0x86
1476 #define V_008DFC_SQ_DS_MIN_SRC2_U32 0x87
1477 #define V_008DFC_SQ_DS_MAX_SRC2_U32 0x88
1478 #define V_008DFC_SQ_DS_AND_SRC2_B32 0x89
1479 #define V_008DFC_SQ_DS_OR_SRC2_B32 0x8A
1480 #define V_008DFC_SQ_DS_XOR_SRC2_B32 0x8B
1481 #define V_008DFC_SQ_DS_WRITE_SRC2_B32 0x8D
1482 #define V_008DFC_SQ_DS_MIN_SRC2_F32 0x92
1483 #define V_008DFC_SQ_DS_MAX_SRC2_F32 0x93
1484 #define V_008DFC_SQ_DS_ADD_SRC2_U64 0xC0
1485 #define V_008DFC_SQ_DS_SUB_SRC2_U64 0xC1
1486 #define V_008DFC_SQ_DS_RSUB_SRC2_U64 0xC2
1487 #define V_008DFC_SQ_DS_INC_SRC2_U64 0xC3
1488 #define V_008DFC_SQ_DS_DEC_SRC2_U64 0xC4
1489 #define V_008DFC_SQ_DS_MIN_SRC2_I64 0xC5
1490 #define V_008DFC_SQ_DS_MAX_SRC2_I64 0xC6
1491 #define V_008DFC_SQ_DS_MIN_SRC2_U64 0xC7
1492 #define V_008DFC_SQ_DS_MAX_SRC2_U64 0xC8
1493 #define V_008DFC_SQ_DS_AND_SRC2_B64 0xC9
1494 #define V_008DFC_SQ_DS_OR_SRC2_B64 0xCA
1495 #define V_008DFC_SQ_DS_XOR_SRC2_B64 0xCB
1496 #define V_008DFC_SQ_DS_WRITE_SRC2_B64 0xCD
1497 #define V_008DFC_SQ_DS_MIN_SRC2_F64 0xD2
1498 #define V_008DFC_SQ_DS_MAX_SRC2_F64 0xD3
1499 /* CIK */
1500 #define V_008DFC_SQ_DS_WRITE_B96 0xDE
1501 #define V_008DFC_SQ_DS_WRITE_B128 0xDF
1502 #define V_008DFC_SQ_DS_CONDXCHG32_RTN_B128 0xFD
1503 #define V_008DFC_SQ_DS_READ_B96 0xFE
1504 #define V_008DFC_SQ_DS_READ_B128 0xFF
1505 /* */
1506 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
1507 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
1508 #define C_008DFC_ENCODING 0x03FFFFFF
1509 #define V_008DFC_SQ_ENC_DS_FIELD 0x36
1510 #define R_008DFC_SQ_SOPC 0x008DFC
1511 #define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0)
1512 #define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF)
1513 #define C_008DFC_SSRC0 0xFFFFFF00
1514 #define V_008DFC_SQ_SGPR 0x00
1515 /* CIK */
1516 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
1517 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
1518 /* */
1519 #define V_008DFC_SQ_VCC_LO 0x6A
1520 #define V_008DFC_SQ_VCC_HI 0x6B
1521 #define V_008DFC_SQ_TBA_LO 0x6C
1522 #define V_008DFC_SQ_TBA_HI 0x6D
1523 #define V_008DFC_SQ_TMA_LO 0x6E
1524 #define V_008DFC_SQ_TMA_HI 0x6F
1525 #define V_008DFC_SQ_TTMP0 0x70
1526 #define V_008DFC_SQ_TTMP1 0x71
1527 #define V_008DFC_SQ_TTMP2 0x72
1528 #define V_008DFC_SQ_TTMP3 0x73
1529 #define V_008DFC_SQ_TTMP4 0x74
1530 #define V_008DFC_SQ_TTMP5 0x75
1531 #define V_008DFC_SQ_TTMP6 0x76
1532 #define V_008DFC_SQ_TTMP7 0x77
1533 #define V_008DFC_SQ_TTMP8 0x78
1534 #define V_008DFC_SQ_TTMP9 0x79
1535 #define V_008DFC_SQ_TTMP10 0x7A
1536 #define V_008DFC_SQ_TTMP11 0x7B
1537 #define V_008DFC_SQ_M0 0x7C
1538 #define V_008DFC_SQ_EXEC_LO 0x7E
1539 #define V_008DFC_SQ_EXEC_HI 0x7F
1540 #define V_008DFC_SQ_SRC_0 0x80
1541 #define V_008DFC_SQ_SRC_1_INT 0x81
1542 #define V_008DFC_SQ_SRC_2_INT 0x82
1543 #define V_008DFC_SQ_SRC_3_INT 0x83
1544 #define V_008DFC_SQ_SRC_4_INT 0x84
1545 #define V_008DFC_SQ_SRC_5_INT 0x85
1546 #define V_008DFC_SQ_SRC_6_INT 0x86
1547 #define V_008DFC_SQ_SRC_7_INT 0x87
1548 #define V_008DFC_SQ_SRC_8_INT 0x88
1549 #define V_008DFC_SQ_SRC_9_INT 0x89
1550 #define V_008DFC_SQ_SRC_10_INT 0x8A
1551 #define V_008DFC_SQ_SRC_11_INT 0x8B
1552 #define V_008DFC_SQ_SRC_12_INT 0x8C
1553 #define V_008DFC_SQ_SRC_13_INT 0x8D
1554 #define V_008DFC_SQ_SRC_14_INT 0x8E
1555 #define V_008DFC_SQ_SRC_15_INT 0x8F
1556 #define V_008DFC_SQ_SRC_16_INT 0x90
1557 #define V_008DFC_SQ_SRC_17_INT 0x91
1558 #define V_008DFC_SQ_SRC_18_INT 0x92
1559 #define V_008DFC_SQ_SRC_19_INT 0x93
1560 #define V_008DFC_SQ_SRC_20_INT 0x94
1561 #define V_008DFC_SQ_SRC_21_INT 0x95
1562 #define V_008DFC_SQ_SRC_22_INT 0x96
1563 #define V_008DFC_SQ_SRC_23_INT 0x97
1564 #define V_008DFC_SQ_SRC_24_INT 0x98
1565 #define V_008DFC_SQ_SRC_25_INT 0x99
1566 #define V_008DFC_SQ_SRC_26_INT 0x9A
1567 #define V_008DFC_SQ_SRC_27_INT 0x9B
1568 #define V_008DFC_SQ_SRC_28_INT 0x9C
1569 #define V_008DFC_SQ_SRC_29_INT 0x9D
1570 #define V_008DFC_SQ_SRC_30_INT 0x9E
1571 #define V_008DFC_SQ_SRC_31_INT 0x9F
1572 #define V_008DFC_SQ_SRC_32_INT 0xA0
1573 #define V_008DFC_SQ_SRC_33_INT 0xA1
1574 #define V_008DFC_SQ_SRC_34_INT 0xA2
1575 #define V_008DFC_SQ_SRC_35_INT 0xA3
1576 #define V_008DFC_SQ_SRC_36_INT 0xA4
1577 #define V_008DFC_SQ_SRC_37_INT 0xA5
1578 #define V_008DFC_SQ_SRC_38_INT 0xA6
1579 #define V_008DFC_SQ_SRC_39_INT 0xA7
1580 #define V_008DFC_SQ_SRC_40_INT 0xA8
1581 #define V_008DFC_SQ_SRC_41_INT 0xA9
1582 #define V_008DFC_SQ_SRC_42_INT 0xAA
1583 #define V_008DFC_SQ_SRC_43_INT 0xAB
1584 #define V_008DFC_SQ_SRC_44_INT 0xAC
1585 #define V_008DFC_SQ_SRC_45_INT 0xAD
1586 #define V_008DFC_SQ_SRC_46_INT 0xAE
1587 #define V_008DFC_SQ_SRC_47_INT 0xAF
1588 #define V_008DFC_SQ_SRC_48_INT 0xB0
1589 #define V_008DFC_SQ_SRC_49_INT 0xB1
1590 #define V_008DFC_SQ_SRC_50_INT 0xB2
1591 #define V_008DFC_SQ_SRC_51_INT 0xB3
1592 #define V_008DFC_SQ_SRC_52_INT 0xB4
1593 #define V_008DFC_SQ_SRC_53_INT 0xB5
1594 #define V_008DFC_SQ_SRC_54_INT 0xB6
1595 #define V_008DFC_SQ_SRC_55_INT 0xB7
1596 #define V_008DFC_SQ_SRC_56_INT 0xB8
1597 #define V_008DFC_SQ_SRC_57_INT 0xB9
1598 #define V_008DFC_SQ_SRC_58_INT 0xBA
1599 #define V_008DFC_SQ_SRC_59_INT 0xBB
1600 #define V_008DFC_SQ_SRC_60_INT 0xBC
1601 #define V_008DFC_SQ_SRC_61_INT 0xBD
1602 #define V_008DFC_SQ_SRC_62_INT 0xBE
1603 #define V_008DFC_SQ_SRC_63_INT 0xBF
1604 #define V_008DFC_SQ_SRC_64_INT 0xC0
1605 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
1606 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
1607 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
1608 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
1609 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
1610 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
1611 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
1612 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
1613 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
1614 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
1615 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
1616 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
1617 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
1618 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
1619 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
1620 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
1621 #define V_008DFC_SQ_SRC_0_5 0xF0
1622 #define V_008DFC_SQ_SRC_M_0_5 0xF1
1623 #define V_008DFC_SQ_SRC_1 0xF2
1624 #define V_008DFC_SQ_SRC_M_1 0xF3
1625 #define V_008DFC_SQ_SRC_2 0xF4
1626 #define V_008DFC_SQ_SRC_M_2 0xF5
1627 #define V_008DFC_SQ_SRC_4 0xF6
1628 #define V_008DFC_SQ_SRC_M_4 0xF7
1629 #define V_008DFC_SQ_SRC_VCCZ 0xFB
1630 #define V_008DFC_SQ_SRC_EXECZ 0xFC
1631 #define V_008DFC_SQ_SRC_SCC 0xFD
1632 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
1633 #define S_008DFC_SSRC1(x) (((x) & 0xFF) << 8)
1634 #define G_008DFC_SSRC1(x) (((x) >> 8) & 0xFF)
1635 #define C_008DFC_SSRC1 0xFFFF00FF
1636 #define V_008DFC_SQ_SGPR 0x00
1637 /* CIK */
1638 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
1639 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
1640 /* */
1641 #define V_008DFC_SQ_VCC_LO 0x6A
1642 #define V_008DFC_SQ_VCC_HI 0x6B
1643 #define V_008DFC_SQ_TBA_LO 0x6C
1644 #define V_008DFC_SQ_TBA_HI 0x6D
1645 #define V_008DFC_SQ_TMA_LO 0x6E
1646 #define V_008DFC_SQ_TMA_HI 0x6F
1647 #define V_008DFC_SQ_TTMP0 0x70
1648 #define V_008DFC_SQ_TTMP1 0x71
1649 #define V_008DFC_SQ_TTMP2 0x72
1650 #define V_008DFC_SQ_TTMP3 0x73
1651 #define V_008DFC_SQ_TTMP4 0x74
1652 #define V_008DFC_SQ_TTMP5 0x75
1653 #define V_008DFC_SQ_TTMP6 0x76
1654 #define V_008DFC_SQ_TTMP7 0x77
1655 #define V_008DFC_SQ_TTMP8 0x78
1656 #define V_008DFC_SQ_TTMP9 0x79
1657 #define V_008DFC_SQ_TTMP10 0x7A
1658 #define V_008DFC_SQ_TTMP11 0x7B
1659 #define V_008DFC_SQ_M0 0x7C
1660 #define V_008DFC_SQ_EXEC_LO 0x7E
1661 #define V_008DFC_SQ_EXEC_HI 0x7F
1662 #define V_008DFC_SQ_SRC_0 0x80
1663 #define V_008DFC_SQ_SRC_1_INT 0x81
1664 #define V_008DFC_SQ_SRC_2_INT 0x82
1665 #define V_008DFC_SQ_SRC_3_INT 0x83
1666 #define V_008DFC_SQ_SRC_4_INT 0x84
1667 #define V_008DFC_SQ_SRC_5_INT 0x85
1668 #define V_008DFC_SQ_SRC_6_INT 0x86
1669 #define V_008DFC_SQ_SRC_7_INT 0x87
1670 #define V_008DFC_SQ_SRC_8_INT 0x88
1671 #define V_008DFC_SQ_SRC_9_INT 0x89
1672 #define V_008DFC_SQ_SRC_10_INT 0x8A
1673 #define V_008DFC_SQ_SRC_11_INT 0x8B
1674 #define V_008DFC_SQ_SRC_12_INT 0x8C
1675 #define V_008DFC_SQ_SRC_13_INT 0x8D
1676 #define V_008DFC_SQ_SRC_14_INT 0x8E
1677 #define V_008DFC_SQ_SRC_15_INT 0x8F
1678 #define V_008DFC_SQ_SRC_16_INT 0x90
1679 #define V_008DFC_SQ_SRC_17_INT 0x91
1680 #define V_008DFC_SQ_SRC_18_INT 0x92
1681 #define V_008DFC_SQ_SRC_19_INT 0x93
1682 #define V_008DFC_SQ_SRC_20_INT 0x94
1683 #define V_008DFC_SQ_SRC_21_INT 0x95
1684 #define V_008DFC_SQ_SRC_22_INT 0x96
1685 #define V_008DFC_SQ_SRC_23_INT 0x97
1686 #define V_008DFC_SQ_SRC_24_INT 0x98
1687 #define V_008DFC_SQ_SRC_25_INT 0x99
1688 #define V_008DFC_SQ_SRC_26_INT 0x9A
1689 #define V_008DFC_SQ_SRC_27_INT 0x9B
1690 #define V_008DFC_SQ_SRC_28_INT 0x9C
1691 #define V_008DFC_SQ_SRC_29_INT 0x9D
1692 #define V_008DFC_SQ_SRC_30_INT 0x9E
1693 #define V_008DFC_SQ_SRC_31_INT 0x9F
1694 #define V_008DFC_SQ_SRC_32_INT 0xA0
1695 #define V_008DFC_SQ_SRC_33_INT 0xA1
1696 #define V_008DFC_SQ_SRC_34_INT 0xA2
1697 #define V_008DFC_SQ_SRC_35_INT 0xA3
1698 #define V_008DFC_SQ_SRC_36_INT 0xA4
1699 #define V_008DFC_SQ_SRC_37_INT 0xA5
1700 #define V_008DFC_SQ_SRC_38_INT 0xA6
1701 #define V_008DFC_SQ_SRC_39_INT 0xA7
1702 #define V_008DFC_SQ_SRC_40_INT 0xA8
1703 #define V_008DFC_SQ_SRC_41_INT 0xA9
1704 #define V_008DFC_SQ_SRC_42_INT 0xAA
1705 #define V_008DFC_SQ_SRC_43_INT 0xAB
1706 #define V_008DFC_SQ_SRC_44_INT 0xAC
1707 #define V_008DFC_SQ_SRC_45_INT 0xAD
1708 #define V_008DFC_SQ_SRC_46_INT 0xAE
1709 #define V_008DFC_SQ_SRC_47_INT 0xAF
1710 #define V_008DFC_SQ_SRC_48_INT 0xB0
1711 #define V_008DFC_SQ_SRC_49_INT 0xB1
1712 #define V_008DFC_SQ_SRC_50_INT 0xB2
1713 #define V_008DFC_SQ_SRC_51_INT 0xB3
1714 #define V_008DFC_SQ_SRC_52_INT 0xB4
1715 #define V_008DFC_SQ_SRC_53_INT 0xB5
1716 #define V_008DFC_SQ_SRC_54_INT 0xB6
1717 #define V_008DFC_SQ_SRC_55_INT 0xB7
1718 #define V_008DFC_SQ_SRC_56_INT 0xB8
1719 #define V_008DFC_SQ_SRC_57_INT 0xB9
1720 #define V_008DFC_SQ_SRC_58_INT 0xBA
1721 #define V_008DFC_SQ_SRC_59_INT 0xBB
1722 #define V_008DFC_SQ_SRC_60_INT 0xBC
1723 #define V_008DFC_SQ_SRC_61_INT 0xBD
1724 #define V_008DFC_SQ_SRC_62_INT 0xBE
1725 #define V_008DFC_SQ_SRC_63_INT 0xBF
1726 #define V_008DFC_SQ_SRC_64_INT 0xC0
1727 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
1728 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
1729 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
1730 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
1731 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
1732 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
1733 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
1734 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
1735 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
1736 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
1737 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
1738 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
1739 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
1740 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
1741 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
1742 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
1743 #define V_008DFC_SQ_SRC_0_5 0xF0
1744 #define V_008DFC_SQ_SRC_M_0_5 0xF1
1745 #define V_008DFC_SQ_SRC_1 0xF2
1746 #define V_008DFC_SQ_SRC_M_1 0xF3
1747 #define V_008DFC_SQ_SRC_2 0xF4
1748 #define V_008DFC_SQ_SRC_M_2 0xF5
1749 #define V_008DFC_SQ_SRC_4 0xF6
1750 #define V_008DFC_SQ_SRC_M_4 0xF7
1751 #define V_008DFC_SQ_SRC_VCCZ 0xFB
1752 #define V_008DFC_SQ_SRC_EXECZ 0xFC
1753 #define V_008DFC_SQ_SRC_SCC 0xFD
1754 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
1755 #define S_008DFC_OP(x) (((x) & 0x7F) << 16)
1756 #define G_008DFC_OP(x) (((x) >> 16) & 0x7F)
1757 #define C_008DFC_OP 0xFF80FFFF
1758 #define V_008DFC_SQ_S_CMP_EQ_I32 0x00
1759 #define V_008DFC_SQ_S_CMP_LG_I32 0x01
1760 #define V_008DFC_SQ_S_CMP_GT_I32 0x02
1761 #define V_008DFC_SQ_S_CMP_GE_I32 0x03
1762 #define V_008DFC_SQ_S_CMP_LT_I32 0x04
1763 #define V_008DFC_SQ_S_CMP_LE_I32 0x05
1764 #define V_008DFC_SQ_S_CMP_EQ_U32 0x06
1765 #define V_008DFC_SQ_S_CMP_LG_U32 0x07
1766 #define V_008DFC_SQ_S_CMP_GT_U32 0x08
1767 #define V_008DFC_SQ_S_CMP_GE_U32 0x09
1768 #define V_008DFC_SQ_S_CMP_LT_U32 0x0A
1769 #define V_008DFC_SQ_S_CMP_LE_U32 0x0B
1770 #define V_008DFC_SQ_S_BITCMP0_B32 0x0C
1771 #define V_008DFC_SQ_S_BITCMP1_B32 0x0D
1772 #define V_008DFC_SQ_S_BITCMP0_B64 0x0E
1773 #define V_008DFC_SQ_S_BITCMP1_B64 0x0F
1774 #define V_008DFC_SQ_S_SETVSKIP 0x10
1775 #define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23)
1776 #define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF)
1777 #define C_008DFC_ENCODING 0x007FFFFF
1778 #define V_008DFC_SQ_ENC_SOPC_FIELD 0x17E
1779 #endif
1780 #define R_008DFC_SQ_EXP_0 0x008DFC
1781 #define S_008DFC_EN(x) (((x) & 0x0F) << 0)
1782 #define G_008DFC_EN(x) (((x) >> 0) & 0x0F)
1783 #define C_008DFC_EN 0xFFFFFFF0
1784 #define S_008DFC_TGT(x) (((x) & 0x3F) << 4)
1785 #define G_008DFC_TGT(x) (((x) >> 4) & 0x3F)
1786 #define C_008DFC_TGT 0xFFFFFC0F
1787 #define V_008DFC_SQ_EXP_MRT 0x00
1788 #define V_008DFC_SQ_EXP_MRTZ 0x08
1789 #define V_008DFC_SQ_EXP_NULL 0x09
1790 #define V_008DFC_SQ_EXP_POS 0x0C
1791 #define V_008DFC_SQ_EXP_PARAM 0x20
1792 #define S_008DFC_COMPR(x) (((x) & 0x1) << 10)
1793 #define G_008DFC_COMPR(x) (((x) >> 10) & 0x1)
1794 #define C_008DFC_COMPR 0xFFFFFBFF
1795 #define S_008DFC_DONE(x) (((x) & 0x1) << 11)
1796 #define G_008DFC_DONE(x) (((x) >> 11) & 0x1)
1797 #define C_008DFC_DONE 0xFFFFF7FF
1798 #define S_008DFC_VM(x) (((x) & 0x1) << 12)
1799 #define G_008DFC_VM(x) (((x) >> 12) & 0x1)
1800 #define C_008DFC_VM 0xFFFFEFFF
1801 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
1802 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
1803 #define C_008DFC_ENCODING 0x03FFFFFF
1804 #define V_008DFC_SQ_ENC_EXP_FIELD 0x3E
1805 #if 0
1806 #define R_008DFC_SQ_MIMG_0 0x008DFC
1807 #define S_008DFC_DMASK(x) (((x) & 0x0F) << 8)
1808 #define G_008DFC_DMASK(x) (((x) >> 8) & 0x0F)
1809 #define C_008DFC_DMASK 0xFFFFF0FF
1810 #define S_008DFC_UNORM(x) (((x) & 0x1) << 12)
1811 #define G_008DFC_UNORM(x) (((x) >> 12) & 0x1)
1812 #define C_008DFC_UNORM 0xFFFFEFFF
1813 #define S_008DFC_GLC(x) (((x) & 0x1) << 13)
1814 #define G_008DFC_GLC(x) (((x) >> 13) & 0x1)
1815 #define C_008DFC_GLC 0xFFFFDFFF
1816 #define S_008DFC_DA(x) (((x) & 0x1) << 14)
1817 #define G_008DFC_DA(x) (((x) >> 14) & 0x1)
1818 #define C_008DFC_DA 0xFFFFBFFF
1819 #define S_008DFC_R128(x) (((x) & 0x1) << 15)
1820 #define G_008DFC_R128(x) (((x) >> 15) & 0x1)
1821 #define C_008DFC_R128 0xFFFF7FFF
1822 #define S_008DFC_TFE(x) (((x) & 0x1) << 16)
1823 #define G_008DFC_TFE(x) (((x) >> 16) & 0x1)
1824 #define C_008DFC_TFE 0xFFFEFFFF
1825 #define S_008DFC_LWE(x) (((x) & 0x1) << 17)
1826 #define G_008DFC_LWE(x) (((x) >> 17) & 0x1)
1827 #define C_008DFC_LWE 0xFFFDFFFF
1828 #define S_008DFC_OP(x) (((x) & 0x7F) << 18)
1829 #define G_008DFC_OP(x) (((x) >> 18) & 0x7F)
1830 #define C_008DFC_OP 0xFE03FFFF
1831 #define V_008DFC_SQ_IMAGE_LOAD 0x00
1832 #define V_008DFC_SQ_IMAGE_LOAD_MIP 0x01
1833 #define V_008DFC_SQ_IMAGE_LOAD_PCK 0x02
1834 #define V_008DFC_SQ_IMAGE_LOAD_PCK_SGN 0x03
1835 #define V_008DFC_SQ_IMAGE_LOAD_MIP_PCK 0x04
1836 #define V_008DFC_SQ_IMAGE_LOAD_MIP_PCK_SGN 0x05
1837 #define V_008DFC_SQ_IMAGE_STORE 0x08
1838 #define V_008DFC_SQ_IMAGE_STORE_MIP 0x09
1839 #define V_008DFC_SQ_IMAGE_STORE_PCK 0x0A
1840 #define V_008DFC_SQ_IMAGE_STORE_MIP_PCK 0x0B
1841 #define V_008DFC_SQ_IMAGE_GET_RESINFO 0x0E
1842 #define V_008DFC_SQ_IMAGE_ATOMIC_SWAP 0x0F
1843 #define V_008DFC_SQ_IMAGE_ATOMIC_CMPSWAP 0x10
1844 #define V_008DFC_SQ_IMAGE_ATOMIC_ADD 0x11
1845 #define V_008DFC_SQ_IMAGE_ATOMIC_SUB 0x12
1846 #define V_008DFC_SQ_IMAGE_ATOMIC_RSUB 0x13 /* not on CIK */
1847 #define V_008DFC_SQ_IMAGE_ATOMIC_SMIN 0x14
1848 #define V_008DFC_SQ_IMAGE_ATOMIC_UMIN 0x15
1849 #define V_008DFC_SQ_IMAGE_ATOMIC_SMAX 0x16
1850 #define V_008DFC_SQ_IMAGE_ATOMIC_UMAX 0x17
1851 #define V_008DFC_SQ_IMAGE_ATOMIC_AND 0x18
1852 #define V_008DFC_SQ_IMAGE_ATOMIC_OR 0x19
1853 #define V_008DFC_SQ_IMAGE_ATOMIC_XOR 0x1A
1854 #define V_008DFC_SQ_IMAGE_ATOMIC_INC 0x1B
1855 #define V_008DFC_SQ_IMAGE_ATOMIC_DEC 0x1C
1856 #define V_008DFC_SQ_IMAGE_ATOMIC_FCMPSWAP 0x1D
1857 #define V_008DFC_SQ_IMAGE_ATOMIC_FMIN 0x1E
1858 #define V_008DFC_SQ_IMAGE_ATOMIC_FMAX 0x1F
1859 #define V_008DFC_SQ_IMAGE_SAMPLE 0x20
1860 #define V_008DFC_SQ_IMAGE_SAMPLE_CL 0x21
1861 #define V_008DFC_SQ_IMAGE_SAMPLE_D 0x22
1862 #define V_008DFC_SQ_IMAGE_SAMPLE_D_CL 0x23
1863 #define V_008DFC_SQ_IMAGE_SAMPLE_L 0x24
1864 #define V_008DFC_SQ_IMAGE_SAMPLE_B 0x25
1865 #define V_008DFC_SQ_IMAGE_SAMPLE_B_CL 0x26
1866 #define V_008DFC_SQ_IMAGE_SAMPLE_LZ 0x27
1867 #define V_008DFC_SQ_IMAGE_SAMPLE_C 0x28
1868 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CL 0x29
1869 #define V_008DFC_SQ_IMAGE_SAMPLE_C_D 0x2A
1870 #define V_008DFC_SQ_IMAGE_SAMPLE_C_D_CL 0x2B
1871 #define V_008DFC_SQ_IMAGE_SAMPLE_C_L 0x2C
1872 #define V_008DFC_SQ_IMAGE_SAMPLE_C_B 0x2D
1873 #define V_008DFC_SQ_IMAGE_SAMPLE_C_B_CL 0x2E
1874 #define V_008DFC_SQ_IMAGE_SAMPLE_C_LZ 0x2F
1875 #define V_008DFC_SQ_IMAGE_SAMPLE_O 0x30
1876 #define V_008DFC_SQ_IMAGE_SAMPLE_CL_O 0x31
1877 #define V_008DFC_SQ_IMAGE_SAMPLE_D_O 0x32
1878 #define V_008DFC_SQ_IMAGE_SAMPLE_D_CL_O 0x33
1879 #define V_008DFC_SQ_IMAGE_SAMPLE_L_O 0x34
1880 #define V_008DFC_SQ_IMAGE_SAMPLE_B_O 0x35
1881 #define V_008DFC_SQ_IMAGE_SAMPLE_B_CL_O 0x36
1882 #define V_008DFC_SQ_IMAGE_SAMPLE_LZ_O 0x37
1883 #define V_008DFC_SQ_IMAGE_SAMPLE_C_O 0x38
1884 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CL_O 0x39
1885 #define V_008DFC_SQ_IMAGE_SAMPLE_C_D_O 0x3A
1886 #define V_008DFC_SQ_IMAGE_SAMPLE_C_D_CL_O 0x3B
1887 #define V_008DFC_SQ_IMAGE_SAMPLE_C_L_O 0x3C
1888 #define V_008DFC_SQ_IMAGE_SAMPLE_C_B_O 0x3D
1889 #define V_008DFC_SQ_IMAGE_SAMPLE_C_B_CL_O 0x3E
1890 #define V_008DFC_SQ_IMAGE_SAMPLE_C_LZ_O 0x3F
1891 #define V_008DFC_SQ_IMAGE_GATHER4 0x40
1892 #define V_008DFC_SQ_IMAGE_GATHER4_CL 0x41
1893 #define V_008DFC_SQ_IMAGE_GATHER4_L 0x44
1894 #define V_008DFC_SQ_IMAGE_GATHER4_B 0x45
1895 #define V_008DFC_SQ_IMAGE_GATHER4_B_CL 0x46
1896 #define V_008DFC_SQ_IMAGE_GATHER4_LZ 0x47
1897 #define V_008DFC_SQ_IMAGE_GATHER4_C 0x48
1898 #define V_008DFC_SQ_IMAGE_GATHER4_C_CL 0x49
1899 #define V_008DFC_SQ_IMAGE_GATHER4_C_L 0x4C
1900 #define V_008DFC_SQ_IMAGE_GATHER4_C_B 0x4D
1901 #define V_008DFC_SQ_IMAGE_GATHER4_C_B_CL 0x4E
1902 #define V_008DFC_SQ_IMAGE_GATHER4_C_LZ 0x4F
1903 #define V_008DFC_SQ_IMAGE_GATHER4_O 0x50
1904 #define V_008DFC_SQ_IMAGE_GATHER4_CL_O 0x51
1905 #define V_008DFC_SQ_IMAGE_GATHER4_L_O 0x54
1906 #define V_008DFC_SQ_IMAGE_GATHER4_B_O 0x55
1907 #define V_008DFC_SQ_IMAGE_GATHER4_B_CL_O 0x56
1908 #define V_008DFC_SQ_IMAGE_GATHER4_LZ_O 0x57
1909 #define V_008DFC_SQ_IMAGE_GATHER4_C_O 0x58
1910 #define V_008DFC_SQ_IMAGE_GATHER4_C_CL_O 0x59
1911 #define V_008DFC_SQ_IMAGE_GATHER4_C_L_O 0x5C
1912 #define V_008DFC_SQ_IMAGE_GATHER4_C_B_O 0x5D
1913 #define V_008DFC_SQ_IMAGE_GATHER4_C_B_CL_O 0x5E
1914 #define V_008DFC_SQ_IMAGE_GATHER4_C_LZ_O 0x5F
1915 #define V_008DFC_SQ_IMAGE_GET_LOD 0x60
1916 #define V_008DFC_SQ_IMAGE_SAMPLE_CD 0x68
1917 #define V_008DFC_SQ_IMAGE_SAMPLE_CD_CL 0x69
1918 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD 0x6A
1919 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_CL 0x6B
1920 #define V_008DFC_SQ_IMAGE_SAMPLE_CD_O 0x6C
1921 #define V_008DFC_SQ_IMAGE_SAMPLE_CD_CL_O 0x6D
1922 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_O 0x6E
1923 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_CL_O 0x6F
1924 #define S_008DFC_SLC(x) (((x) & 0x1) << 25)
1925 #define G_008DFC_SLC(x) (((x) >> 25) & 0x1)
1926 #define C_008DFC_SLC 0xFDFFFFFF
1927 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
1928 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
1929 #define C_008DFC_ENCODING 0x03FFFFFF
1930 #define V_008DFC_SQ_ENC_MIMG_FIELD 0x3C
1931 #define R_008DFC_SQ_SOPP 0x008DFC
1932 #define S_008DFC_SIMM16(x) (((x) & 0xFFFF) << 0)
1933 #define G_008DFC_SIMM16(x) (((x) >> 0) & 0xFFFF)
1934 #define C_008DFC_SIMM16 0xFFFF0000
1935 #define S_008DFC_OP(x) (((x) & 0x7F) << 16)
1936 #define G_008DFC_OP(x) (((x) >> 16) & 0x7F)
1937 #define C_008DFC_OP 0xFF80FFFF
1938 #define V_008DFC_SQ_S_NOP 0x00
1939 #define V_008DFC_SQ_S_ENDPGM 0x01
1940 #define V_008DFC_SQ_S_BRANCH 0x02
1941 #define V_008DFC_SQ_S_CBRANCH_SCC0 0x04
1942 #define V_008DFC_SQ_S_CBRANCH_SCC1 0x05
1943 #define V_008DFC_SQ_S_CBRANCH_VCCZ 0x06
1944 #define V_008DFC_SQ_S_CBRANCH_VCCNZ 0x07
1945 #define V_008DFC_SQ_S_CBRANCH_EXECZ 0x08
1946 #define V_008DFC_SQ_S_CBRANCH_EXECNZ 0x09
1947 #define V_008DFC_SQ_S_BARRIER 0x0A
1948 /* CIK */
1949 #define V_008DFC_SQ_S_SETKILL 0x0B
1950 /* */
1951 #define V_008DFC_SQ_S_WAITCNT 0x0C
1952 #define V_008DFC_SQ_S_SETHALT 0x0D
1953 #define V_008DFC_SQ_S_SLEEP 0x0E
1954 #define V_008DFC_SQ_S_SETPRIO 0x0F
1955 #define V_008DFC_SQ_S_SENDMSG 0x10
1956 #define V_008DFC_SQ_S_SENDMSGHALT 0x11
1957 #define V_008DFC_SQ_S_TRAP 0x12
1958 #define V_008DFC_SQ_S_ICACHE_INV 0x13
1959 #define V_008DFC_SQ_S_INCPERFLEVEL 0x14
1960 #define V_008DFC_SQ_S_DECPERFLEVEL 0x15
1961 #define V_008DFC_SQ_S_TTRACEDATA 0x16
1962 /* CIK */
1963 #define V_008DFC_SQ_S_CBRANCH_CDBGSYS 0x17
1964 #define V_008DFC_SQ_S_CBRANCH_CDBGUSER 0x18
1965 #define V_008DFC_SQ_S_CBRANCH_CDBGSYS_OR_USER 0x19
1966 #define V_008DFC_SQ_S_CBRANCH_CDBGSYS_AND_USER 0x1A
1967 /* */
1968 #define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23)
1969 #define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF)
1970 #define C_008DFC_ENCODING 0x007FFFFF
1971 #define V_008DFC_SQ_ENC_SOPP_FIELD 0x17F
1972 #define R_008DFC_SQ_VINTRP 0x008DFC
1973 #define S_008DFC_VSRC(x) (((x) & 0xFF) << 0)
1974 #define G_008DFC_VSRC(x) (((x) >> 0) & 0xFF)
1975 #define C_008DFC_VSRC 0xFFFFFF00
1976 #define V_008DFC_SQ_VGPR 0x00
1977 #define S_008DFC_ATTRCHAN(x) (((x) & 0x03) << 8)
1978 #define G_008DFC_ATTRCHAN(x) (((x) >> 8) & 0x03)
1979 #define C_008DFC_ATTRCHAN 0xFFFFFCFF
1980 #define V_008DFC_SQ_CHAN_X 0x00
1981 #define V_008DFC_SQ_CHAN_Y 0x01
1982 #define V_008DFC_SQ_CHAN_Z 0x02
1983 #define V_008DFC_SQ_CHAN_W 0x03
1984 #define S_008DFC_ATTR(x) (((x) & 0x3F) << 10)
1985 #define G_008DFC_ATTR(x) (((x) >> 10) & 0x3F)
1986 #define C_008DFC_ATTR 0xFFFF03FF
1987 #define V_008DFC_SQ_ATTR 0x00
1988 #define S_008DFC_OP(x) (((x) & 0x03) << 16)
1989 #define G_008DFC_OP(x) (((x) >> 16) & 0x03)
1990 #define C_008DFC_OP 0xFFFCFFFF
1991 #define V_008DFC_SQ_V_INTERP_P1_F32 0x00
1992 #define V_008DFC_SQ_V_INTERP_P2_F32 0x01
1993 #define V_008DFC_SQ_V_INTERP_MOV_F32 0x02
1994 #define S_008DFC_VDST(x) (((x) & 0xFF) << 18)
1995 #define G_008DFC_VDST(x) (((x) >> 18) & 0xFF)
1996 #define C_008DFC_VDST 0xFC03FFFF
1997 #define V_008DFC_SQ_VGPR 0x00
1998 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
1999 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
2000 #define C_008DFC_ENCODING 0x03FFFFFF
2001 #define V_008DFC_SQ_ENC_VINTRP_FIELD 0x32
2002 #define R_008DFC_SQ_MTBUF_0 0x008DFC
2003 #define S_008DFC_OFFSET(x) (((x) & 0xFFF) << 0)
2004 #define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFFF)
2005 #define C_008DFC_OFFSET 0xFFFFF000
2006 #define S_008DFC_OFFEN(x) (((x) & 0x1) << 12)
2007 #define G_008DFC_OFFEN(x) (((x) >> 12) & 0x1)
2008 #define C_008DFC_OFFEN 0xFFFFEFFF
2009 #define S_008DFC_IDXEN(x) (((x) & 0x1) << 13)
2010 #define G_008DFC_IDXEN(x) (((x) >> 13) & 0x1)
2011 #define C_008DFC_IDXEN 0xFFFFDFFF
2012 #define S_008DFC_GLC(x) (((x) & 0x1) << 14)
2013 #define G_008DFC_GLC(x) (((x) >> 14) & 0x1)
2014 #define C_008DFC_GLC 0xFFFFBFFF
2015 #define S_008DFC_ADDR64(x) (((x) & 0x1) << 15)
2016 #define G_008DFC_ADDR64(x) (((x) >> 15) & 0x1)
2017 #define C_008DFC_ADDR64 0xFFFF7FFF
2018 #define S_008DFC_OP(x) (((x) & 0x07) << 16)
2019 #define G_008DFC_OP(x) (((x) >> 16) & 0x07)
2020 #define C_008DFC_OP 0xFFF8FFFF
2021 #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_X 0x00
2022 #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XY 0x01
2023 #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XYZ 0x02
2024 #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XYZW 0x03
2025 #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_X 0x04
2026 #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XY 0x05
2027 #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XYZ 0x06
2028 #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XYZW 0x07
2029 #define S_008DFC_DFMT(x) (((x) & 0x0F) << 19)
2030 #define G_008DFC_DFMT(x) (((x) >> 19) & 0x0F)
2031 #define C_008DFC_DFMT 0xFF87FFFF
2032 #define S_008DFC_NFMT(x) (((x) & 0x07) << 23)
2033 #define G_008DFC_NFMT(x) (((x) >> 23) & 0x07)
2034 #define C_008DFC_NFMT 0xFC7FFFFF
2035 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
2036 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
2037 #define C_008DFC_ENCODING 0x03FFFFFF
2038 #define V_008DFC_SQ_ENC_MTBUF_FIELD 0x3A
2039 #define R_008DFC_SQ_SMRD 0x008DFC
2040 #define S_008DFC_OFFSET(x) (((x) & 0xFF) << 0)
2041 #define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFF)
2042 #define C_008DFC_OFFSET 0xFFFFFF00
2043 #define V_008DFC_SQ_SGPR 0x00
2044 /* CIK */
2045 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
2046 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
2047 /* */
2048 #define V_008DFC_SQ_VCC_LO 0x6A
2049 #define V_008DFC_SQ_VCC_HI 0x6B
2050 #define V_008DFC_SQ_TBA_LO 0x6C
2051 #define V_008DFC_SQ_TBA_HI 0x6D
2052 #define V_008DFC_SQ_TMA_LO 0x6E
2053 #define V_008DFC_SQ_TMA_HI 0x6F
2054 #define V_008DFC_SQ_TTMP0 0x70
2055 #define V_008DFC_SQ_TTMP1 0x71
2056 #define V_008DFC_SQ_TTMP2 0x72
2057 #define V_008DFC_SQ_TTMP3 0x73
2058 #define V_008DFC_SQ_TTMP4 0x74
2059 #define V_008DFC_SQ_TTMP5 0x75
2060 #define V_008DFC_SQ_TTMP6 0x76
2061 #define V_008DFC_SQ_TTMP7 0x77
2062 #define V_008DFC_SQ_TTMP8 0x78
2063 #define V_008DFC_SQ_TTMP9 0x79
2064 #define V_008DFC_SQ_TTMP10 0x7A
2065 #define V_008DFC_SQ_TTMP11 0x7B
2066 /* CIK */
2067 #define V_008DFC_SQ_SRC_LITERAL 0xFF
2068 /* */
2069 #define S_008DFC_IMM(x) (((x) & 0x1) << 8)
2070 #define G_008DFC_IMM(x) (((x) >> 8) & 0x1)
2071 #define C_008DFC_IMM 0xFFFFFEFF
2072 #define S_008DFC_SBASE(x) (((x) & 0x3F) << 9)
2073 #define G_008DFC_SBASE(x) (((x) >> 9) & 0x3F)
2074 #define C_008DFC_SBASE 0xFFFF81FF
2075 #define S_008DFC_SDST(x) (((x) & 0x7F) << 15)
2076 #define G_008DFC_SDST(x) (((x) >> 15) & 0x7F)
2077 #define C_008DFC_SDST 0xFFC07FFF
2078 #define V_008DFC_SQ_SGPR 0x00
2079 /* CIK */
2080 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
2081 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
2082 /* */
2083 #define V_008DFC_SQ_VCC_LO 0x6A
2084 #define V_008DFC_SQ_VCC_HI 0x6B
2085 #define V_008DFC_SQ_TBA_LO 0x6C
2086 #define V_008DFC_SQ_TBA_HI 0x6D
2087 #define V_008DFC_SQ_TMA_LO 0x6E
2088 #define V_008DFC_SQ_TMA_HI 0x6F
2089 #define V_008DFC_SQ_TTMP0 0x70
2090 #define V_008DFC_SQ_TTMP1 0x71
2091 #define V_008DFC_SQ_TTMP2 0x72
2092 #define V_008DFC_SQ_TTMP3 0x73
2093 #define V_008DFC_SQ_TTMP4 0x74
2094 #define V_008DFC_SQ_TTMP5 0x75
2095 #define V_008DFC_SQ_TTMP6 0x76
2096 #define V_008DFC_SQ_TTMP7 0x77
2097 #define V_008DFC_SQ_TTMP8 0x78
2098 #define V_008DFC_SQ_TTMP9 0x79
2099 #define V_008DFC_SQ_TTMP10 0x7A
2100 #define V_008DFC_SQ_TTMP11 0x7B
2101 #define V_008DFC_SQ_M0 0x7C
2102 #define V_008DFC_SQ_EXEC_LO 0x7E
2103 #define V_008DFC_SQ_EXEC_HI 0x7F
2104 #define S_008DFC_OP(x) (((x) & 0x1F) << 22)
2105 #define G_008DFC_OP(x) (((x) >> 22) & 0x1F)
2106 #define C_008DFC_OP 0xF83FFFFF
2107 #define V_008DFC_SQ_S_LOAD_DWORD 0x00
2108 #define V_008DFC_SQ_S_LOAD_DWORDX2 0x01
2109 #define V_008DFC_SQ_S_LOAD_DWORDX4 0x02
2110 #define V_008DFC_SQ_S_LOAD_DWORDX8 0x03
2111 #define V_008DFC_SQ_S_LOAD_DWORDX16 0x04
2112 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORD 0x08
2113 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX2 0x09
2114 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX4 0x0A
2115 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX8 0x0B
2116 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX16 0x0C
2117 /* CIK */
2118 #define V_008DFC_SQ_S_DCACHE_INV_VOL 0x1D
2119 /* */
2120 #define V_008DFC_SQ_S_MEMTIME 0x1E
2121 #define V_008DFC_SQ_S_DCACHE_INV 0x1F
2122 #define S_008DFC_ENCODING(x) (((x) & 0x1F) << 27)
2123 #define G_008DFC_ENCODING(x) (((x) >> 27) & 0x1F)
2124 #define C_008DFC_ENCODING 0x07FFFFFF
2125 #define V_008DFC_SQ_ENC_SMRD_FIELD 0x18
2126 /* CIK */
2127 #define R_008DFC_SQ_FLAT_0 0x008DFC
2128 #define S_008DFC_GLC(x) (((x) & 0x1) << 16)
2129 #define G_008DFC_GLC(x) (((x) >> 16) & 0x1)
2130 #define C_008DFC_GLC 0xFFFEFFFF
2131 #define S_008DFC_SLC(x) (((x) & 0x1) << 17)
2132 #define G_008DFC_SLC(x) (((x) >> 17) & 0x1)
2133 #define C_008DFC_SLC 0xFFFDFFFF
2134 #define S_008DFC_OP(x) (((x) & 0x7F) << 18)
2135 #define G_008DFC_OP(x) (((x) >> 18) & 0x7F)
2136 #define C_008DFC_OP 0xFE03FFFF
2137 #define V_008DFC_SQ_FLAT_LOAD_UBYTE 0x08
2138 #define V_008DFC_SQ_FLAT_LOAD_SBYTE 0x09
2139 #define V_008DFC_SQ_FLAT_LOAD_USHORT 0x0A
2140 #define V_008DFC_SQ_FLAT_LOAD_SSHORT 0x0B
2141 #define V_008DFC_SQ_FLAT_LOAD_DWORD 0x0C
2142 #define V_008DFC_SQ_FLAT_LOAD_DWORDX2 0x0D
2143 #define V_008DFC_SQ_FLAT_LOAD_DWORDX4 0x0E
2144 #define V_008DFC_SQ_FLAT_LOAD_DWORDX3 0x0F
2145 #define V_008DFC_SQ_FLAT_STORE_BYTE 0x18
2146 #define V_008DFC_SQ_FLAT_STORE_SHORT 0x1A
2147 #define V_008DFC_SQ_FLAT_STORE_DWORD 0x1C
2148 #define V_008DFC_SQ_FLAT_STORE_DWORDX2 0x1D
2149 #define V_008DFC_SQ_FLAT_STORE_DWORDX4 0x1E
2150 #define V_008DFC_SQ_FLAT_STORE_DWORDX3 0x1F
2151 #define V_008DFC_SQ_FLAT_ATOMIC_SWAP 0x30
2152 #define V_008DFC_SQ_FLAT_ATOMIC_CMPSWAP 0x31
2153 #define V_008DFC_SQ_FLAT_ATOMIC_ADD 0x32
2154 #define V_008DFC_SQ_FLAT_ATOMIC_SUB 0x33
2155 #define V_008DFC_SQ_FLAT_ATOMIC_SMIN 0x35
2156 #define V_008DFC_SQ_FLAT_ATOMIC_UMIN 0x36
2157 #define V_008DFC_SQ_FLAT_ATOMIC_SMAX 0x37
2158 #define V_008DFC_SQ_FLAT_ATOMIC_UMAX 0x38
2159 #define V_008DFC_SQ_FLAT_ATOMIC_AND 0x39
2160 #define V_008DFC_SQ_FLAT_ATOMIC_OR 0x3A
2161 #define V_008DFC_SQ_FLAT_ATOMIC_XOR 0x3B
2162 #define V_008DFC_SQ_FLAT_ATOMIC_INC 0x3C
2163 #define V_008DFC_SQ_FLAT_ATOMIC_DEC 0x3D
2164 #define V_008DFC_SQ_FLAT_ATOMIC_FCMPSWAP 0x3E
2165 #define V_008DFC_SQ_FLAT_ATOMIC_FMIN 0x3F
2166 #define V_008DFC_SQ_FLAT_ATOMIC_FMAX 0x40
2167 #define V_008DFC_SQ_FLAT_ATOMIC_SWAP_X2 0x50
2168 #define V_008DFC_SQ_FLAT_ATOMIC_CMPSWAP_X2 0x51
2169 #define V_008DFC_SQ_FLAT_ATOMIC_ADD_X2 0x52
2170 #define V_008DFC_SQ_FLAT_ATOMIC_SUB_X2 0x53
2171 #define V_008DFC_SQ_FLAT_ATOMIC_SMIN_X2 0x55
2172 #define V_008DFC_SQ_FLAT_ATOMIC_UMIN_X2 0x56
2173 #define V_008DFC_SQ_FLAT_ATOMIC_SMAX_X2 0x57
2174 #define V_008DFC_SQ_FLAT_ATOMIC_UMAX_X2 0x58
2175 #define V_008DFC_SQ_FLAT_ATOMIC_AND_X2 0x59
2176 #define V_008DFC_SQ_FLAT_ATOMIC_OR_X2 0x5A
2177 #define V_008DFC_SQ_FLAT_ATOMIC_XOR_X2 0x5B
2178 #define V_008DFC_SQ_FLAT_ATOMIC_INC_X2 0x5C
2179 #define V_008DFC_SQ_FLAT_ATOMIC_DEC_X2 0x5D
2180 #define V_008DFC_SQ_FLAT_ATOMIC_FCMPSWAP_X2 0x5E
2181 #define V_008DFC_SQ_FLAT_ATOMIC_FMIN_X2 0x5F
2182 #define V_008DFC_SQ_FLAT_ATOMIC_FMAX_X2 0x60
2183 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
2184 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
2185 #define C_008DFC_ENCODING 0x03FFFFFF
2186 #define V_008DFC_SQ_ENC_FLAT_FIELD 0x37
2187 /* */
2188 #define R_008DFC_SQ_EXP_1 0x008DFC
2189 #define S_008DFC_VSRC0(x) (((x) & 0xFF) << 0)
2190 #define G_008DFC_VSRC0(x) (((x) >> 0) & 0xFF)
2191 #define C_008DFC_VSRC0 0xFFFFFF00
2192 #define V_008DFC_SQ_VGPR 0x00
2193 #define S_008DFC_VSRC1(x) (((x) & 0xFF) << 8)
2194 #define G_008DFC_VSRC1(x) (((x) >> 8) & 0xFF)
2195 #define C_008DFC_VSRC1 0xFFFF00FF
2196 #define V_008DFC_SQ_VGPR 0x00
2197 #define S_008DFC_VSRC2(x) (((x) & 0xFF) << 16)
2198 #define G_008DFC_VSRC2(x) (((x) >> 16) & 0xFF)
2199 #define C_008DFC_VSRC2 0xFF00FFFF
2200 #define V_008DFC_SQ_VGPR 0x00
2201 #define S_008DFC_VSRC3(x) (((x) & 0xFF) << 24)
2202 #define G_008DFC_VSRC3(x) (((x) >> 24) & 0xFF)
2203 #define C_008DFC_VSRC3 0x00FFFFFF
2204 #define V_008DFC_SQ_VGPR 0x00
2205 #define R_008DFC_SQ_DS_1 0x008DFC
2206 #define S_008DFC_ADDR(x) (((x) & 0xFF) << 0)
2207 #define G_008DFC_ADDR(x) (((x) >> 0) & 0xFF)
2208 #define C_008DFC_ADDR 0xFFFFFF00
2209 #define V_008DFC_SQ_VGPR 0x00
2210 #define S_008DFC_DATA0(x) (((x) & 0xFF) << 8)
2211 #define G_008DFC_DATA0(x) (((x) >> 8) & 0xFF)
2212 #define C_008DFC_DATA0 0xFFFF00FF
2213 #define V_008DFC_SQ_VGPR 0x00
2214 #define S_008DFC_DATA1(x) (((x) & 0xFF) << 16)
2215 #define G_008DFC_DATA1(x) (((x) >> 16) & 0xFF)
2216 #define C_008DFC_DATA1 0xFF00FFFF
2217 #define V_008DFC_SQ_VGPR 0x00
2218 #define S_008DFC_VDST(x) (((x) & 0xFF) << 24)
2219 #define G_008DFC_VDST(x) (((x) >> 24) & 0xFF)
2220 #define C_008DFC_VDST 0x00FFFFFF
2221 #define V_008DFC_SQ_VGPR 0x00
2222 #define R_008DFC_SQ_VOPC 0x008DFC
2223 #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0)
2224 #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF)
2225 #define C_008DFC_SRC0 0xFFFFFE00
2226 #define V_008DFC_SQ_SGPR 0x00
2227 #define V_008DFC_SQ_VCC_LO 0x6A
2228 #define V_008DFC_SQ_VCC_HI 0x6B
2229 #define V_008DFC_SQ_TBA_LO 0x6C
2230 #define V_008DFC_SQ_TBA_HI 0x6D
2231 #define V_008DFC_SQ_TMA_LO 0x6E
2232 #define V_008DFC_SQ_TMA_HI 0x6F
2233 #define V_008DFC_SQ_TTMP0 0x70
2234 #define V_008DFC_SQ_TTMP1 0x71
2235 #define V_008DFC_SQ_TTMP2 0x72
2236 #define V_008DFC_SQ_TTMP3 0x73
2237 #define V_008DFC_SQ_TTMP4 0x74
2238 #define V_008DFC_SQ_TTMP5 0x75
2239 #define V_008DFC_SQ_TTMP6 0x76
2240 #define V_008DFC_SQ_TTMP7 0x77
2241 #define V_008DFC_SQ_TTMP8 0x78
2242 #define V_008DFC_SQ_TTMP9 0x79
2243 #define V_008DFC_SQ_TTMP10 0x7A
2244 #define V_008DFC_SQ_TTMP11 0x7B
2245 #define V_008DFC_SQ_M0 0x7C
2246 #define V_008DFC_SQ_EXEC_LO 0x7E
2247 #define V_008DFC_SQ_EXEC_HI 0x7F
2248 #define V_008DFC_SQ_SRC_0 0x80
2249 #define V_008DFC_SQ_SRC_1_INT 0x81
2250 #define V_008DFC_SQ_SRC_2_INT 0x82
2251 #define V_008DFC_SQ_SRC_3_INT 0x83
2252 #define V_008DFC_SQ_SRC_4_INT 0x84
2253 #define V_008DFC_SQ_SRC_5_INT 0x85
2254 #define V_008DFC_SQ_SRC_6_INT 0x86
2255 #define V_008DFC_SQ_SRC_7_INT 0x87
2256 #define V_008DFC_SQ_SRC_8_INT 0x88
2257 #define V_008DFC_SQ_SRC_9_INT 0x89
2258 #define V_008DFC_SQ_SRC_10_INT 0x8A
2259 #define V_008DFC_SQ_SRC_11_INT 0x8B
2260 #define V_008DFC_SQ_SRC_12_INT 0x8C
2261 #define V_008DFC_SQ_SRC_13_INT 0x8D
2262 #define V_008DFC_SQ_SRC_14_INT 0x8E
2263 #define V_008DFC_SQ_SRC_15_INT 0x8F
2264 #define V_008DFC_SQ_SRC_16_INT 0x90
2265 #define V_008DFC_SQ_SRC_17_INT 0x91
2266 #define V_008DFC_SQ_SRC_18_INT 0x92
2267 #define V_008DFC_SQ_SRC_19_INT 0x93
2268 #define V_008DFC_SQ_SRC_20_INT 0x94
2269 #define V_008DFC_SQ_SRC_21_INT 0x95
2270 #define V_008DFC_SQ_SRC_22_INT 0x96
2271 #define V_008DFC_SQ_SRC_23_INT 0x97
2272 #define V_008DFC_SQ_SRC_24_INT 0x98
2273 #define V_008DFC_SQ_SRC_25_INT 0x99
2274 #define V_008DFC_SQ_SRC_26_INT 0x9A
2275 #define V_008DFC_SQ_SRC_27_INT 0x9B
2276 #define V_008DFC_SQ_SRC_28_INT 0x9C
2277 #define V_008DFC_SQ_SRC_29_INT 0x9D
2278 #define V_008DFC_SQ_SRC_30_INT 0x9E
2279 #define V_008DFC_SQ_SRC_31_INT 0x9F
2280 #define V_008DFC_SQ_SRC_32_INT 0xA0
2281 #define V_008DFC_SQ_SRC_33_INT 0xA1
2282 #define V_008DFC_SQ_SRC_34_INT 0xA2
2283 #define V_008DFC_SQ_SRC_35_INT 0xA3
2284 #define V_008DFC_SQ_SRC_36_INT 0xA4
2285 #define V_008DFC_SQ_SRC_37_INT 0xA5
2286 #define V_008DFC_SQ_SRC_38_INT 0xA6
2287 #define V_008DFC_SQ_SRC_39_INT 0xA7
2288 #define V_008DFC_SQ_SRC_40_INT 0xA8
2289 #define V_008DFC_SQ_SRC_41_INT 0xA9
2290 #define V_008DFC_SQ_SRC_42_INT 0xAA
2291 #define V_008DFC_SQ_SRC_43_INT 0xAB
2292 #define V_008DFC_SQ_SRC_44_INT 0xAC
2293 #define V_008DFC_SQ_SRC_45_INT 0xAD
2294 #define V_008DFC_SQ_SRC_46_INT 0xAE
2295 #define V_008DFC_SQ_SRC_47_INT 0xAF
2296 #define V_008DFC_SQ_SRC_48_INT 0xB0
2297 #define V_008DFC_SQ_SRC_49_INT 0xB1
2298 #define V_008DFC_SQ_SRC_50_INT 0xB2
2299 #define V_008DFC_SQ_SRC_51_INT 0xB3
2300 #define V_008DFC_SQ_SRC_52_INT 0xB4
2301 #define V_008DFC_SQ_SRC_53_INT 0xB5
2302 #define V_008DFC_SQ_SRC_54_INT 0xB6
2303 #define V_008DFC_SQ_SRC_55_INT 0xB7
2304 #define V_008DFC_SQ_SRC_56_INT 0xB8
2305 #define V_008DFC_SQ_SRC_57_INT 0xB9
2306 #define V_008DFC_SQ_SRC_58_INT 0xBA
2307 #define V_008DFC_SQ_SRC_59_INT 0xBB
2308 #define V_008DFC_SQ_SRC_60_INT 0xBC
2309 #define V_008DFC_SQ_SRC_61_INT 0xBD
2310 #define V_008DFC_SQ_SRC_62_INT 0xBE
2311 #define V_008DFC_SQ_SRC_63_INT 0xBF
2312 #define V_008DFC_SQ_SRC_64_INT 0xC0
2313 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
2314 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
2315 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
2316 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
2317 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
2318 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
2319 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
2320 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
2321 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
2322 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
2323 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
2324 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
2325 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
2326 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
2327 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
2328 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
2329 #define V_008DFC_SQ_SRC_0_5 0xF0
2330 #define V_008DFC_SQ_SRC_M_0_5 0xF1
2331 #define V_008DFC_SQ_SRC_1 0xF2
2332 #define V_008DFC_SQ_SRC_M_1 0xF3
2333 #define V_008DFC_SQ_SRC_2 0xF4
2334 #define V_008DFC_SQ_SRC_M_2 0xF5
2335 #define V_008DFC_SQ_SRC_4 0xF6
2336 #define V_008DFC_SQ_SRC_M_4 0xF7
2337 #define V_008DFC_SQ_SRC_VCCZ 0xFB
2338 #define V_008DFC_SQ_SRC_EXECZ 0xFC
2339 #define V_008DFC_SQ_SRC_SCC 0xFD
2340 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
2341 #define V_008DFC_SQ_SRC_VGPR 0x100
2342 #define S_008DFC_VSRC1(x) (((x) & 0xFF) << 9)
2343 #define G_008DFC_VSRC1(x) (((x) >> 9) & 0xFF)
2344 #define C_008DFC_VSRC1 0xFFFE01FF
2345 #define V_008DFC_SQ_VGPR 0x00
2346 #define S_008DFC_OP(x) (((x) & 0xFF) << 17)
2347 #define G_008DFC_OP(x) (((x) >> 17) & 0xFF)
2348 #define C_008DFC_OP 0xFE01FFFF
2349 #define V_008DFC_SQ_V_CMP_F_F32 0x00
2350 #define V_008DFC_SQ_V_CMP_LT_F32 0x01
2351 #define V_008DFC_SQ_V_CMP_EQ_F32 0x02
2352 #define V_008DFC_SQ_V_CMP_LE_F32 0x03
2353 #define V_008DFC_SQ_V_CMP_GT_F32 0x04
2354 #define V_008DFC_SQ_V_CMP_LG_F32 0x05
2355 #define V_008DFC_SQ_V_CMP_GE_F32 0x06
2356 #define V_008DFC_SQ_V_CMP_O_F32 0x07
2357 #define V_008DFC_SQ_V_CMP_U_F32 0x08
2358 #define V_008DFC_SQ_V_CMP_NGE_F32 0x09
2359 #define V_008DFC_SQ_V_CMP_NLG_F32 0x0A
2360 #define V_008DFC_SQ_V_CMP_NGT_F32 0x0B
2361 #define V_008DFC_SQ_V_CMP_NLE_F32 0x0C
2362 #define V_008DFC_SQ_V_CMP_NEQ_F32 0x0D
2363 #define V_008DFC_SQ_V_CMP_NLT_F32 0x0E
2364 #define V_008DFC_SQ_V_CMP_TRU_F32 0x0F
2365 #define V_008DFC_SQ_V_CMPX_F_F32 0x10
2366 #define V_008DFC_SQ_V_CMPX_LT_F32 0x11
2367 #define V_008DFC_SQ_V_CMPX_EQ_F32 0x12
2368 #define V_008DFC_SQ_V_CMPX_LE_F32 0x13
2369 #define V_008DFC_SQ_V_CMPX_GT_F32 0x14
2370 #define V_008DFC_SQ_V_CMPX_LG_F32 0x15
2371 #define V_008DFC_SQ_V_CMPX_GE_F32 0x16
2372 #define V_008DFC_SQ_V_CMPX_O_F32 0x17
2373 #define V_008DFC_SQ_V_CMPX_U_F32 0x18
2374 #define V_008DFC_SQ_V_CMPX_NGE_F32 0x19
2375 #define V_008DFC_SQ_V_CMPX_NLG_F32 0x1A
2376 #define V_008DFC_SQ_V_CMPX_NGT_F32 0x1B
2377 #define V_008DFC_SQ_V_CMPX_NLE_F32 0x1C
2378 #define V_008DFC_SQ_V_CMPX_NEQ_F32 0x1D
2379 #define V_008DFC_SQ_V_CMPX_NLT_F32 0x1E
2380 #define V_008DFC_SQ_V_CMPX_TRU_F32 0x1F
2381 #define V_008DFC_SQ_V_CMP_F_F64 0x20
2382 #define V_008DFC_SQ_V_CMP_LT_F64 0x21
2383 #define V_008DFC_SQ_V_CMP_EQ_F64 0x22
2384 #define V_008DFC_SQ_V_CMP_LE_F64 0x23
2385 #define V_008DFC_SQ_V_CMP_GT_F64 0x24
2386 #define V_008DFC_SQ_V_CMP_LG_F64 0x25
2387 #define V_008DFC_SQ_V_CMP_GE_F64 0x26
2388 #define V_008DFC_SQ_V_CMP_O_F64 0x27
2389 #define V_008DFC_SQ_V_CMP_U_F64 0x28
2390 #define V_008DFC_SQ_V_CMP_NGE_F64 0x29
2391 #define V_008DFC_SQ_V_CMP_NLG_F64 0x2A
2392 #define V_008DFC_SQ_V_CMP_NGT_F64 0x2B
2393 #define V_008DFC_SQ_V_CMP_NLE_F64 0x2C
2394 #define V_008DFC_SQ_V_CMP_NEQ_F64 0x2D
2395 #define V_008DFC_SQ_V_CMP_NLT_F64 0x2E
2396 #define V_008DFC_SQ_V_CMP_TRU_F64 0x2F
2397 #define V_008DFC_SQ_V_CMPX_F_F64 0x30
2398 #define V_008DFC_SQ_V_CMPX_LT_F64 0x31
2399 #define V_008DFC_SQ_V_CMPX_EQ_F64 0x32
2400 #define V_008DFC_SQ_V_CMPX_LE_F64 0x33
2401 #define V_008DFC_SQ_V_CMPX_GT_F64 0x34
2402 #define V_008DFC_SQ_V_CMPX_LG_F64 0x35
2403 #define V_008DFC_SQ_V_CMPX_GE_F64 0x36
2404 #define V_008DFC_SQ_V_CMPX_O_F64 0x37
2405 #define V_008DFC_SQ_V_CMPX_U_F64 0x38
2406 #define V_008DFC_SQ_V_CMPX_NGE_F64 0x39
2407 #define V_008DFC_SQ_V_CMPX_NLG_F64 0x3A
2408 #define V_008DFC_SQ_V_CMPX_NGT_F64 0x3B
2409 #define V_008DFC_SQ_V_CMPX_NLE_F64 0x3C
2410 #define V_008DFC_SQ_V_CMPX_NEQ_F64 0x3D
2411 #define V_008DFC_SQ_V_CMPX_NLT_F64 0x3E
2412 #define V_008DFC_SQ_V_CMPX_TRU_F64 0x3F
2413 #define V_008DFC_SQ_V_CMPS_F_F32 0x40
2414 #define V_008DFC_SQ_V_CMPS_LT_F32 0x41
2415 #define V_008DFC_SQ_V_CMPS_EQ_F32 0x42
2416 #define V_008DFC_SQ_V_CMPS_LE_F32 0x43
2417 #define V_008DFC_SQ_V_CMPS_GT_F32 0x44
2418 #define V_008DFC_SQ_V_CMPS_LG_F32 0x45
2419 #define V_008DFC_SQ_V_CMPS_GE_F32 0x46
2420 #define V_008DFC_SQ_V_CMPS_O_F32 0x47
2421 #define V_008DFC_SQ_V_CMPS_U_F32 0x48
2422 #define V_008DFC_SQ_V_CMPS_NGE_F32 0x49
2423 #define V_008DFC_SQ_V_CMPS_NLG_F32 0x4A
2424 #define V_008DFC_SQ_V_CMPS_NGT_F32 0x4B
2425 #define V_008DFC_SQ_V_CMPS_NLE_F32 0x4C
2426 #define V_008DFC_SQ_V_CMPS_NEQ_F32 0x4D
2427 #define V_008DFC_SQ_V_CMPS_NLT_F32 0x4E
2428 #define V_008DFC_SQ_V_CMPS_TRU_F32 0x4F
2429 #define V_008DFC_SQ_V_CMPSX_F_F32 0x50
2430 #define V_008DFC_SQ_V_CMPSX_LT_F32 0x51
2431 #define V_008DFC_SQ_V_CMPSX_EQ_F32 0x52
2432 #define V_008DFC_SQ_V_CMPSX_LE_F32 0x53
2433 #define V_008DFC_SQ_V_CMPSX_GT_F32 0x54
2434 #define V_008DFC_SQ_V_CMPSX_LG_F32 0x55
2435 #define V_008DFC_SQ_V_CMPSX_GE_F32 0x56
2436 #define V_008DFC_SQ_V_CMPSX_O_F32 0x57
2437 #define V_008DFC_SQ_V_CMPSX_U_F32 0x58
2438 #define V_008DFC_SQ_V_CMPSX_NGE_F32 0x59
2439 #define V_008DFC_SQ_V_CMPSX_NLG_F32 0x5A
2440 #define V_008DFC_SQ_V_CMPSX_NGT_F32 0x5B
2441 #define V_008DFC_SQ_V_CMPSX_NLE_F32 0x5C
2442 #define V_008DFC_SQ_V_CMPSX_NEQ_F32 0x5D
2443 #define V_008DFC_SQ_V_CMPSX_NLT_F32 0x5E
2444 #define V_008DFC_SQ_V_CMPSX_TRU_F32 0x5F
2445 #define V_008DFC_SQ_V_CMPS_F_F64 0x60
2446 #define V_008DFC_SQ_V_CMPS_LT_F64 0x61
2447 #define V_008DFC_SQ_V_CMPS_EQ_F64 0x62
2448 #define V_008DFC_SQ_V_CMPS_LE_F64 0x63
2449 #define V_008DFC_SQ_V_CMPS_GT_F64 0x64
2450 #define V_008DFC_SQ_V_CMPS_LG_F64 0x65
2451 #define V_008DFC_SQ_V_CMPS_GE_F64 0x66
2452 #define V_008DFC_SQ_V_CMPS_O_F64 0x67
2453 #define V_008DFC_SQ_V_CMPS_U_F64 0x68
2454 #define V_008DFC_SQ_V_CMPS_NGE_F64 0x69
2455 #define V_008DFC_SQ_V_CMPS_NLG_F64 0x6A
2456 #define V_008DFC_SQ_V_CMPS_NGT_F64 0x6B
2457 #define V_008DFC_SQ_V_CMPS_NLE_F64 0x6C
2458 #define V_008DFC_SQ_V_CMPS_NEQ_F64 0x6D
2459 #define V_008DFC_SQ_V_CMPS_NLT_F64 0x6E
2460 #define V_008DFC_SQ_V_CMPS_TRU_F64 0x6F
2461 #define V_008DFC_SQ_V_CMPSX_F_F64 0x70
2462 #define V_008DFC_SQ_V_CMPSX_LT_F64 0x71
2463 #define V_008DFC_SQ_V_CMPSX_EQ_F64 0x72
2464 #define V_008DFC_SQ_V_CMPSX_LE_F64 0x73
2465 #define V_008DFC_SQ_V_CMPSX_GT_F64 0x74
2466 #define V_008DFC_SQ_V_CMPSX_LG_F64 0x75
2467 #define V_008DFC_SQ_V_CMPSX_GE_F64 0x76
2468 #define V_008DFC_SQ_V_CMPSX_O_F64 0x77
2469 #define V_008DFC_SQ_V_CMPSX_U_F64 0x78
2470 #define V_008DFC_SQ_V_CMPSX_NGE_F64 0x79
2471 #define V_008DFC_SQ_V_CMPSX_NLG_F64 0x7A
2472 #define V_008DFC_SQ_V_CMPSX_NGT_F64 0x7B
2473 #define V_008DFC_SQ_V_CMPSX_NLE_F64 0x7C
2474 #define V_008DFC_SQ_V_CMPSX_NEQ_F64 0x7D
2475 #define V_008DFC_SQ_V_CMPSX_NLT_F64 0x7E
2476 #define V_008DFC_SQ_V_CMPSX_TRU_F64 0x7F
2477 #define V_008DFC_SQ_V_CMP_F_I32 0x80
2478 #define V_008DFC_SQ_V_CMP_LT_I32 0x81
2479 #define V_008DFC_SQ_V_CMP_EQ_I32 0x82
2480 #define V_008DFC_SQ_V_CMP_LE_I32 0x83
2481 #define V_008DFC_SQ_V_CMP_GT_I32 0x84
2482 #define V_008DFC_SQ_V_CMP_NE_I32 0x85
2483 #define V_008DFC_SQ_V_CMP_GE_I32 0x86
2484 #define V_008DFC_SQ_V_CMP_T_I32 0x87
2485 #define V_008DFC_SQ_V_CMP_CLASS_F32 0x88
2486 #define V_008DFC_SQ_V_CMPX_F_I32 0x90
2487 #define V_008DFC_SQ_V_CMPX_LT_I32 0x91
2488 #define V_008DFC_SQ_V_CMPX_EQ_I32 0x92
2489 #define V_008DFC_SQ_V_CMPX_LE_I32 0x93
2490 #define V_008DFC_SQ_V_CMPX_GT_I32 0x94
2491 #define V_008DFC_SQ_V_CMPX_NE_I32 0x95
2492 #define V_008DFC_SQ_V_CMPX_GE_I32 0x96
2493 #define V_008DFC_SQ_V_CMPX_T_I32 0x97
2494 #define V_008DFC_SQ_V_CMPX_CLASS_F32 0x98
2495 #define V_008DFC_SQ_V_CMP_F_I64 0xA0
2496 #define V_008DFC_SQ_V_CMP_LT_I64 0xA1
2497 #define V_008DFC_SQ_V_CMP_EQ_I64 0xA2
2498 #define V_008DFC_SQ_V_CMP_LE_I64 0xA3
2499 #define V_008DFC_SQ_V_CMP_GT_I64 0xA4
2500 #define V_008DFC_SQ_V_CMP_NE_I64 0xA5
2501 #define V_008DFC_SQ_V_CMP_GE_I64 0xA6
2502 #define V_008DFC_SQ_V_CMP_T_I64 0xA7
2503 #define V_008DFC_SQ_V_CMP_CLASS_F64 0xA8
2504 #define V_008DFC_SQ_V_CMPX_F_I64 0xB0
2505 #define V_008DFC_SQ_V_CMPX_LT_I64 0xB1
2506 #define V_008DFC_SQ_V_CMPX_EQ_I64 0xB2
2507 #define V_008DFC_SQ_V_CMPX_LE_I64 0xB3
2508 #define V_008DFC_SQ_V_CMPX_GT_I64 0xB4
2509 #define V_008DFC_SQ_V_CMPX_NE_I64 0xB5
2510 #define V_008DFC_SQ_V_CMPX_GE_I64 0xB6
2511 #define V_008DFC_SQ_V_CMPX_T_I64 0xB7
2512 #define V_008DFC_SQ_V_CMPX_CLASS_F64 0xB8
2513 #define V_008DFC_SQ_V_CMP_F_U32 0xC0
2514 #define V_008DFC_SQ_V_CMP_LT_U32 0xC1
2515 #define V_008DFC_SQ_V_CMP_EQ_U32 0xC2
2516 #define V_008DFC_SQ_V_CMP_LE_U32 0xC3
2517 #define V_008DFC_SQ_V_CMP_GT_U32 0xC4
2518 #define V_008DFC_SQ_V_CMP_NE_U32 0xC5
2519 #define V_008DFC_SQ_V_CMP_GE_U32 0xC6
2520 #define V_008DFC_SQ_V_CMP_T_U32 0xC7
2521 #define V_008DFC_SQ_V_CMPX_F_U32 0xD0
2522 #define V_008DFC_SQ_V_CMPX_LT_U32 0xD1
2523 #define V_008DFC_SQ_V_CMPX_EQ_U32 0xD2
2524 #define V_008DFC_SQ_V_CMPX_LE_U32 0xD3
2525 #define V_008DFC_SQ_V_CMPX_GT_U32 0xD4
2526 #define V_008DFC_SQ_V_CMPX_NE_U32 0xD5
2527 #define V_008DFC_SQ_V_CMPX_GE_U32 0xD6
2528 #define V_008DFC_SQ_V_CMPX_T_U32 0xD7
2529 #define V_008DFC_SQ_V_CMP_F_U64 0xE0
2530 #define V_008DFC_SQ_V_CMP_LT_U64 0xE1
2531 #define V_008DFC_SQ_V_CMP_EQ_U64 0xE2
2532 #define V_008DFC_SQ_V_CMP_LE_U64 0xE3
2533 #define V_008DFC_SQ_V_CMP_GT_U64 0xE4
2534 #define V_008DFC_SQ_V_CMP_NE_U64 0xE5
2535 #define V_008DFC_SQ_V_CMP_GE_U64 0xE6
2536 #define V_008DFC_SQ_V_CMP_T_U64 0xE7
2537 #define V_008DFC_SQ_V_CMPX_F_U64 0xF0
2538 #define V_008DFC_SQ_V_CMPX_LT_U64 0xF1
2539 #define V_008DFC_SQ_V_CMPX_EQ_U64 0xF2
2540 #define V_008DFC_SQ_V_CMPX_LE_U64 0xF3
2541 #define V_008DFC_SQ_V_CMPX_GT_U64 0xF4
2542 #define V_008DFC_SQ_V_CMPX_NE_U64 0xF5
2543 #define V_008DFC_SQ_V_CMPX_GE_U64 0xF6
2544 #define V_008DFC_SQ_V_CMPX_T_U64 0xF7
2545 #define S_008DFC_ENCODING(x) (((x) & 0x7F) << 25)
2546 #define G_008DFC_ENCODING(x) (((x) >> 25) & 0x7F)
2547 #define C_008DFC_ENCODING 0x01FFFFFF
2548 #define V_008DFC_SQ_ENC_VOPC_FIELD 0x3E
2549 #define R_008DFC_SQ_SOP1 0x008DFC
2550 #define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0)
2551 #define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF)
2552 #define C_008DFC_SSRC0 0xFFFFFF00
2553 #define V_008DFC_SQ_SGPR 0x00
2554 /* CIK */
2555 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
2556 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
2557 /* */
2558 #define V_008DFC_SQ_VCC_LO 0x6A
2559 #define V_008DFC_SQ_VCC_HI 0x6B
2560 #define V_008DFC_SQ_TBA_LO 0x6C
2561 #define V_008DFC_SQ_TBA_HI 0x6D
2562 #define V_008DFC_SQ_TMA_LO 0x6E
2563 #define V_008DFC_SQ_TMA_HI 0x6F
2564 #define V_008DFC_SQ_TTMP0 0x70
2565 #define V_008DFC_SQ_TTMP1 0x71
2566 #define V_008DFC_SQ_TTMP2 0x72
2567 #define V_008DFC_SQ_TTMP3 0x73
2568 #define V_008DFC_SQ_TTMP4 0x74
2569 #define V_008DFC_SQ_TTMP5 0x75
2570 #define V_008DFC_SQ_TTMP6 0x76
2571 #define V_008DFC_SQ_TTMP7 0x77
2572 #define V_008DFC_SQ_TTMP8 0x78
2573 #define V_008DFC_SQ_TTMP9 0x79
2574 #define V_008DFC_SQ_TTMP10 0x7A
2575 #define V_008DFC_SQ_TTMP11 0x7B
2576 #define V_008DFC_SQ_M0 0x7C
2577 #define V_008DFC_SQ_EXEC_LO 0x7E
2578 #define V_008DFC_SQ_EXEC_HI 0x7F
2579 #define V_008DFC_SQ_SRC_0 0x80
2580 #define V_008DFC_SQ_SRC_1_INT 0x81
2581 #define V_008DFC_SQ_SRC_2_INT 0x82
2582 #define V_008DFC_SQ_SRC_3_INT 0x83
2583 #define V_008DFC_SQ_SRC_4_INT 0x84
2584 #define V_008DFC_SQ_SRC_5_INT 0x85
2585 #define V_008DFC_SQ_SRC_6_INT 0x86
2586 #define V_008DFC_SQ_SRC_7_INT 0x87
2587 #define V_008DFC_SQ_SRC_8_INT 0x88
2588 #define V_008DFC_SQ_SRC_9_INT 0x89
2589 #define V_008DFC_SQ_SRC_10_INT 0x8A
2590 #define V_008DFC_SQ_SRC_11_INT 0x8B
2591 #define V_008DFC_SQ_SRC_12_INT 0x8C
2592 #define V_008DFC_SQ_SRC_13_INT 0x8D
2593 #define V_008DFC_SQ_SRC_14_INT 0x8E
2594 #define V_008DFC_SQ_SRC_15_INT 0x8F
2595 #define V_008DFC_SQ_SRC_16_INT 0x90
2596 #define V_008DFC_SQ_SRC_17_INT 0x91
2597 #define V_008DFC_SQ_SRC_18_INT 0x92
2598 #define V_008DFC_SQ_SRC_19_INT 0x93
2599 #define V_008DFC_SQ_SRC_20_INT 0x94
2600 #define V_008DFC_SQ_SRC_21_INT 0x95
2601 #define V_008DFC_SQ_SRC_22_INT 0x96
2602 #define V_008DFC_SQ_SRC_23_INT 0x97
2603 #define V_008DFC_SQ_SRC_24_INT 0x98
2604 #define V_008DFC_SQ_SRC_25_INT 0x99
2605 #define V_008DFC_SQ_SRC_26_INT 0x9A
2606 #define V_008DFC_SQ_SRC_27_INT 0x9B
2607 #define V_008DFC_SQ_SRC_28_INT 0x9C
2608 #define V_008DFC_SQ_SRC_29_INT 0x9D
2609 #define V_008DFC_SQ_SRC_30_INT 0x9E
2610 #define V_008DFC_SQ_SRC_31_INT 0x9F
2611 #define V_008DFC_SQ_SRC_32_INT 0xA0
2612 #define V_008DFC_SQ_SRC_33_INT 0xA1
2613 #define V_008DFC_SQ_SRC_34_INT 0xA2
2614 #define V_008DFC_SQ_SRC_35_INT 0xA3
2615 #define V_008DFC_SQ_SRC_36_INT 0xA4
2616 #define V_008DFC_SQ_SRC_37_INT 0xA5
2617 #define V_008DFC_SQ_SRC_38_INT 0xA6
2618 #define V_008DFC_SQ_SRC_39_INT 0xA7
2619 #define V_008DFC_SQ_SRC_40_INT 0xA8
2620 #define V_008DFC_SQ_SRC_41_INT 0xA9
2621 #define V_008DFC_SQ_SRC_42_INT 0xAA
2622 #define V_008DFC_SQ_SRC_43_INT 0xAB
2623 #define V_008DFC_SQ_SRC_44_INT 0xAC
2624 #define V_008DFC_SQ_SRC_45_INT 0xAD
2625 #define V_008DFC_SQ_SRC_46_INT 0xAE
2626 #define V_008DFC_SQ_SRC_47_INT 0xAF
2627 #define V_008DFC_SQ_SRC_48_INT 0xB0
2628 #define V_008DFC_SQ_SRC_49_INT 0xB1
2629 #define V_008DFC_SQ_SRC_50_INT 0xB2
2630 #define V_008DFC_SQ_SRC_51_INT 0xB3
2631 #define V_008DFC_SQ_SRC_52_INT 0xB4
2632 #define V_008DFC_SQ_SRC_53_INT 0xB5
2633 #define V_008DFC_SQ_SRC_54_INT 0xB6
2634 #define V_008DFC_SQ_SRC_55_INT 0xB7
2635 #define V_008DFC_SQ_SRC_56_INT 0xB8
2636 #define V_008DFC_SQ_SRC_57_INT 0xB9
2637 #define V_008DFC_SQ_SRC_58_INT 0xBA
2638 #define V_008DFC_SQ_SRC_59_INT 0xBB
2639 #define V_008DFC_SQ_SRC_60_INT 0xBC
2640 #define V_008DFC_SQ_SRC_61_INT 0xBD
2641 #define V_008DFC_SQ_SRC_62_INT 0xBE
2642 #define V_008DFC_SQ_SRC_63_INT 0xBF
2643 #define V_008DFC_SQ_SRC_64_INT 0xC0
2644 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
2645 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
2646 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
2647 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
2648 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
2649 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
2650 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
2651 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
2652 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
2653 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
2654 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
2655 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
2656 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
2657 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
2658 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
2659 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
2660 #define V_008DFC_SQ_SRC_0_5 0xF0
2661 #define V_008DFC_SQ_SRC_M_0_5 0xF1
2662 #define V_008DFC_SQ_SRC_1 0xF2
2663 #define V_008DFC_SQ_SRC_M_1 0xF3
2664 #define V_008DFC_SQ_SRC_2 0xF4
2665 #define V_008DFC_SQ_SRC_M_2 0xF5
2666 #define V_008DFC_SQ_SRC_4 0xF6
2667 #define V_008DFC_SQ_SRC_M_4 0xF7
2668 #define V_008DFC_SQ_SRC_VCCZ 0xFB
2669 #define V_008DFC_SQ_SRC_EXECZ 0xFC
2670 #define V_008DFC_SQ_SRC_SCC 0xFD
2671 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
2672 #define S_008DFC_OP(x) (((x) & 0xFF) << 8)
2673 #define G_008DFC_OP(x) (((x) >> 8) & 0xFF)
2674 #define C_008DFC_OP 0xFFFF00FF
2675 #define V_008DFC_SQ_S_MOV_B32 0x03
2676 #define V_008DFC_SQ_S_MOV_B64 0x04
2677 #define V_008DFC_SQ_S_CMOV_B32 0x05
2678 #define V_008DFC_SQ_S_CMOV_B64 0x06
2679 #define V_008DFC_SQ_S_NOT_B32 0x07
2680 #define V_008DFC_SQ_S_NOT_B64 0x08
2681 #define V_008DFC_SQ_S_WQM_B32 0x09
2682 #define V_008DFC_SQ_S_WQM_B64 0x0A
2683 #define V_008DFC_SQ_S_BREV_B32 0x0B
2684 #define V_008DFC_SQ_S_BREV_B64 0x0C
2685 #define V_008DFC_SQ_S_BCNT0_I32_B32 0x0D
2686 #define V_008DFC_SQ_S_BCNT0_I32_B64 0x0E
2687 #define V_008DFC_SQ_S_BCNT1_I32_B32 0x0F
2688 #define V_008DFC_SQ_S_BCNT1_I32_B64 0x10
2689 #define V_008DFC_SQ_S_FF0_I32_B32 0x11
2690 #define V_008DFC_SQ_S_FF0_I32_B64 0x12
2691 #define V_008DFC_SQ_S_FF1_I32_B32 0x13
2692 #define V_008DFC_SQ_S_FF1_I32_B64 0x14
2693 #define V_008DFC_SQ_S_FLBIT_I32_B32 0x15
2694 #define V_008DFC_SQ_S_FLBIT_I32_B64 0x16
2695 #define V_008DFC_SQ_S_FLBIT_I32 0x17
2696 #define V_008DFC_SQ_S_FLBIT_I32_I64 0x18
2697 #define V_008DFC_SQ_S_SEXT_I32_I8 0x19
2698 #define V_008DFC_SQ_S_SEXT_I32_I16 0x1A
2699 #define V_008DFC_SQ_S_BITSET0_B32 0x1B
2700 #define V_008DFC_SQ_S_BITSET0_B64 0x1C
2701 #define V_008DFC_SQ_S_BITSET1_B32 0x1D
2702 #define V_008DFC_SQ_S_BITSET1_B64 0x1E
2703 #define V_008DFC_SQ_S_GETPC_B64 0x1F
2704 #define V_008DFC_SQ_S_SETPC_B64 0x20
2705 #define V_008DFC_SQ_S_SWAPPC_B64 0x21
2706 #define V_008DFC_SQ_S_RFE_B64 0x22
2707 #define V_008DFC_SQ_S_AND_SAVEEXEC_B64 0x24
2708 #define V_008DFC_SQ_S_OR_SAVEEXEC_B64 0x25
2709 #define V_008DFC_SQ_S_XOR_SAVEEXEC_B64 0x26
2710 #define V_008DFC_SQ_S_ANDN2_SAVEEXEC_B64 0x27
2711 #define V_008DFC_SQ_S_ORN2_SAVEEXEC_B64 0x28
2712 #define V_008DFC_SQ_S_NAND_SAVEEXEC_B64 0x29
2713 #define V_008DFC_SQ_S_NOR_SAVEEXEC_B64 0x2A
2714 #define V_008DFC_SQ_S_XNOR_SAVEEXEC_B64 0x2B
2715 #define V_008DFC_SQ_S_QUADMASK_B32 0x2C
2716 #define V_008DFC_SQ_S_QUADMASK_B64 0x2D
2717 #define V_008DFC_SQ_S_MOVRELS_B32 0x2E
2718 #define V_008DFC_SQ_S_MOVRELS_B64 0x2F
2719 #define V_008DFC_SQ_S_MOVRELD_B32 0x30
2720 #define V_008DFC_SQ_S_MOVRELD_B64 0x31
2721 #define V_008DFC_SQ_S_CBRANCH_JOIN 0x32
2722 #define V_008DFC_SQ_S_MOV_REGRD_B32 0x33
2723 #define V_008DFC_SQ_S_ABS_I32 0x34
2724 #define V_008DFC_SQ_S_MOV_FED_B32 0x35
2725 #define S_008DFC_SDST(x) (((x) & 0x7F) << 16)
2726 #define G_008DFC_SDST(x) (((x) >> 16) & 0x7F)
2727 #define C_008DFC_SDST 0xFF80FFFF
2728 #define V_008DFC_SQ_SGPR 0x00
2729 /* CIK */
2730 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
2731 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
2732 /* */
2733 #define V_008DFC_SQ_VCC_LO 0x6A
2734 #define V_008DFC_SQ_VCC_HI 0x6B
2735 #define V_008DFC_SQ_TBA_LO 0x6C
2736 #define V_008DFC_SQ_TBA_HI 0x6D
2737 #define V_008DFC_SQ_TMA_LO 0x6E
2738 #define V_008DFC_SQ_TMA_HI 0x6F
2739 #define V_008DFC_SQ_TTMP0 0x70
2740 #define V_008DFC_SQ_TTMP1 0x71
2741 #define V_008DFC_SQ_TTMP2 0x72
2742 #define V_008DFC_SQ_TTMP3 0x73
2743 #define V_008DFC_SQ_TTMP4 0x74
2744 #define V_008DFC_SQ_TTMP5 0x75
2745 #define V_008DFC_SQ_TTMP6 0x76
2746 #define V_008DFC_SQ_TTMP7 0x77
2747 #define V_008DFC_SQ_TTMP8 0x78
2748 #define V_008DFC_SQ_TTMP9 0x79
2749 #define V_008DFC_SQ_TTMP10 0x7A
2750 #define V_008DFC_SQ_TTMP11 0x7B
2751 #define V_008DFC_SQ_M0 0x7C
2752 #define V_008DFC_SQ_EXEC_LO 0x7E
2753 #define V_008DFC_SQ_EXEC_HI 0x7F
2754 #define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23)
2755 #define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF)
2756 #define C_008DFC_ENCODING 0x007FFFFF
2757 #define V_008DFC_SQ_ENC_SOP1_FIELD 0x17D
2758 #define R_008DFC_SQ_MTBUF_1 0x008DFC
2759 #define S_008DFC_VADDR(x) (((x) & 0xFF) << 0)
2760 #define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF)
2761 #define C_008DFC_VADDR 0xFFFFFF00
2762 #define V_008DFC_SQ_VGPR 0x00
2763 #define S_008DFC_VDATA(x) (((x) & 0xFF) << 8)
2764 #define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF)
2765 #define C_008DFC_VDATA 0xFFFF00FF
2766 #define V_008DFC_SQ_VGPR 0x00
2767 #define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16)
2768 #define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F)
2769 #define C_008DFC_SRSRC 0xFFE0FFFF
2770 #define S_008DFC_SLC(x) (((x) & 0x1) << 22)
2771 #define G_008DFC_SLC(x) (((x) >> 22) & 0x1)
2772 #define C_008DFC_SLC 0xFFBFFFFF
2773 #define S_008DFC_TFE(x) (((x) & 0x1) << 23)
2774 #define G_008DFC_TFE(x) (((x) >> 23) & 0x1)
2775 #define C_008DFC_TFE 0xFF7FFFFF
2776 #define S_008DFC_SOFFSET(x) (((x) & 0xFF) << 24)
2777 #define G_008DFC_SOFFSET(x) (((x) >> 24) & 0xFF)
2778 #define C_008DFC_SOFFSET 0x00FFFFFF
2779 #define V_008DFC_SQ_SGPR 0x00
2780 /* CIK */
2781 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
2782 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
2783 /* */
2784 #define V_008DFC_SQ_VCC_LO 0x6A
2785 #define V_008DFC_SQ_VCC_HI 0x6B
2786 #define V_008DFC_SQ_TBA_LO 0x6C
2787 #define V_008DFC_SQ_TBA_HI 0x6D
2788 #define V_008DFC_SQ_TMA_LO 0x6E
2789 #define V_008DFC_SQ_TMA_HI 0x6F
2790 #define V_008DFC_SQ_TTMP0 0x70
2791 #define V_008DFC_SQ_TTMP1 0x71
2792 #define V_008DFC_SQ_TTMP2 0x72
2793 #define V_008DFC_SQ_TTMP3 0x73
2794 #define V_008DFC_SQ_TTMP4 0x74
2795 #define V_008DFC_SQ_TTMP5 0x75
2796 #define V_008DFC_SQ_TTMP6 0x76
2797 #define V_008DFC_SQ_TTMP7 0x77
2798 #define V_008DFC_SQ_TTMP8 0x78
2799 #define V_008DFC_SQ_TTMP9 0x79
2800 #define V_008DFC_SQ_TTMP10 0x7A
2801 #define V_008DFC_SQ_TTMP11 0x7B
2802 #define V_008DFC_SQ_M0 0x7C
2803 #define V_008DFC_SQ_EXEC_LO 0x7E
2804 #define V_008DFC_SQ_EXEC_HI 0x7F
2805 #define V_008DFC_SQ_SRC_0 0x80
2806 #define V_008DFC_SQ_SRC_1_INT 0x81
2807 #define V_008DFC_SQ_SRC_2_INT 0x82
2808 #define V_008DFC_SQ_SRC_3_INT 0x83
2809 #define V_008DFC_SQ_SRC_4_INT 0x84
2810 #define V_008DFC_SQ_SRC_5_INT 0x85
2811 #define V_008DFC_SQ_SRC_6_INT 0x86
2812 #define V_008DFC_SQ_SRC_7_INT 0x87
2813 #define V_008DFC_SQ_SRC_8_INT 0x88
2814 #define V_008DFC_SQ_SRC_9_INT 0x89
2815 #define V_008DFC_SQ_SRC_10_INT 0x8A
2816 #define V_008DFC_SQ_SRC_11_INT 0x8B
2817 #define V_008DFC_SQ_SRC_12_INT 0x8C
2818 #define V_008DFC_SQ_SRC_13_INT 0x8D
2819 #define V_008DFC_SQ_SRC_14_INT 0x8E
2820 #define V_008DFC_SQ_SRC_15_INT 0x8F
2821 #define V_008DFC_SQ_SRC_16_INT 0x90
2822 #define V_008DFC_SQ_SRC_17_INT 0x91
2823 #define V_008DFC_SQ_SRC_18_INT 0x92
2824 #define V_008DFC_SQ_SRC_19_INT 0x93
2825 #define V_008DFC_SQ_SRC_20_INT 0x94
2826 #define V_008DFC_SQ_SRC_21_INT 0x95
2827 #define V_008DFC_SQ_SRC_22_INT 0x96
2828 #define V_008DFC_SQ_SRC_23_INT 0x97
2829 #define V_008DFC_SQ_SRC_24_INT 0x98
2830 #define V_008DFC_SQ_SRC_25_INT 0x99
2831 #define V_008DFC_SQ_SRC_26_INT 0x9A
2832 #define V_008DFC_SQ_SRC_27_INT 0x9B
2833 #define V_008DFC_SQ_SRC_28_INT 0x9C
2834 #define V_008DFC_SQ_SRC_29_INT 0x9D
2835 #define V_008DFC_SQ_SRC_30_INT 0x9E
2836 #define V_008DFC_SQ_SRC_31_INT 0x9F
2837 #define V_008DFC_SQ_SRC_32_INT 0xA0
2838 #define V_008DFC_SQ_SRC_33_INT 0xA1
2839 #define V_008DFC_SQ_SRC_34_INT 0xA2
2840 #define V_008DFC_SQ_SRC_35_INT 0xA3
2841 #define V_008DFC_SQ_SRC_36_INT 0xA4
2842 #define V_008DFC_SQ_SRC_37_INT 0xA5
2843 #define V_008DFC_SQ_SRC_38_INT 0xA6
2844 #define V_008DFC_SQ_SRC_39_INT 0xA7
2845 #define V_008DFC_SQ_SRC_40_INT 0xA8
2846 #define V_008DFC_SQ_SRC_41_INT 0xA9
2847 #define V_008DFC_SQ_SRC_42_INT 0xAA
2848 #define V_008DFC_SQ_SRC_43_INT 0xAB
2849 #define V_008DFC_SQ_SRC_44_INT 0xAC
2850 #define V_008DFC_SQ_SRC_45_INT 0xAD
2851 #define V_008DFC_SQ_SRC_46_INT 0xAE
2852 #define V_008DFC_SQ_SRC_47_INT 0xAF
2853 #define V_008DFC_SQ_SRC_48_INT 0xB0
2854 #define V_008DFC_SQ_SRC_49_INT 0xB1
2855 #define V_008DFC_SQ_SRC_50_INT 0xB2
2856 #define V_008DFC_SQ_SRC_51_INT 0xB3
2857 #define V_008DFC_SQ_SRC_52_INT 0xB4
2858 #define V_008DFC_SQ_SRC_53_INT 0xB5
2859 #define V_008DFC_SQ_SRC_54_INT 0xB6
2860 #define V_008DFC_SQ_SRC_55_INT 0xB7
2861 #define V_008DFC_SQ_SRC_56_INT 0xB8
2862 #define V_008DFC_SQ_SRC_57_INT 0xB9
2863 #define V_008DFC_SQ_SRC_58_INT 0xBA
2864 #define V_008DFC_SQ_SRC_59_INT 0xBB
2865 #define V_008DFC_SQ_SRC_60_INT 0xBC
2866 #define V_008DFC_SQ_SRC_61_INT 0xBD
2867 #define V_008DFC_SQ_SRC_62_INT 0xBE
2868 #define V_008DFC_SQ_SRC_63_INT 0xBF
2869 #define V_008DFC_SQ_SRC_64_INT 0xC0
2870 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
2871 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
2872 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
2873 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
2874 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
2875 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
2876 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
2877 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
2878 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
2879 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
2880 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
2881 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
2882 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
2883 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
2884 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
2885 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
2886 #define V_008DFC_SQ_SRC_0_5 0xF0
2887 #define V_008DFC_SQ_SRC_M_0_5 0xF1
2888 #define V_008DFC_SQ_SRC_1 0xF2
2889 #define V_008DFC_SQ_SRC_M_1 0xF3
2890 #define V_008DFC_SQ_SRC_2 0xF4
2891 #define V_008DFC_SQ_SRC_M_2 0xF5
2892 #define V_008DFC_SQ_SRC_4 0xF6
2893 #define V_008DFC_SQ_SRC_M_4 0xF7
2894 #define V_008DFC_SQ_SRC_VCCZ 0xFB
2895 #define V_008DFC_SQ_SRC_EXECZ 0xFC
2896 #define V_008DFC_SQ_SRC_SCC 0xFD
2897 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
2898 #define R_008DFC_SQ_SOP2 0x008DFC
2899 #define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0)
2900 #define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF)
2901 #define C_008DFC_SSRC0 0xFFFFFF00
2902 #define V_008DFC_SQ_SGPR 0x00
2903 /* CIK */
2904 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
2905 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
2906 /* */
2907 #define V_008DFC_SQ_VCC_LO 0x6A
2908 #define V_008DFC_SQ_VCC_HI 0x6B
2909 #define V_008DFC_SQ_TBA_LO 0x6C
2910 #define V_008DFC_SQ_TBA_HI 0x6D
2911 #define V_008DFC_SQ_TMA_LO 0x6E
2912 #define V_008DFC_SQ_TMA_HI 0x6F
2913 #define V_008DFC_SQ_TTMP0 0x70
2914 #define V_008DFC_SQ_TTMP1 0x71
2915 #define V_008DFC_SQ_TTMP2 0x72
2916 #define V_008DFC_SQ_TTMP3 0x73
2917 #define V_008DFC_SQ_TTMP4 0x74
2918 #define V_008DFC_SQ_TTMP5 0x75
2919 #define V_008DFC_SQ_TTMP6 0x76
2920 #define V_008DFC_SQ_TTMP7 0x77
2921 #define V_008DFC_SQ_TTMP8 0x78
2922 #define V_008DFC_SQ_TTMP9 0x79
2923 #define V_008DFC_SQ_TTMP10 0x7A
2924 #define V_008DFC_SQ_TTMP11 0x7B
2925 #define V_008DFC_SQ_M0 0x7C
2926 #define V_008DFC_SQ_EXEC_LO 0x7E
2927 #define V_008DFC_SQ_EXEC_HI 0x7F
2928 #define V_008DFC_SQ_SRC_0 0x80
2929 #define V_008DFC_SQ_SRC_1_INT 0x81
2930 #define V_008DFC_SQ_SRC_2_INT 0x82
2931 #define V_008DFC_SQ_SRC_3_INT 0x83
2932 #define V_008DFC_SQ_SRC_4_INT 0x84
2933 #define V_008DFC_SQ_SRC_5_INT 0x85
2934 #define V_008DFC_SQ_SRC_6_INT 0x86
2935 #define V_008DFC_SQ_SRC_7_INT 0x87
2936 #define V_008DFC_SQ_SRC_8_INT 0x88
2937 #define V_008DFC_SQ_SRC_9_INT 0x89
2938 #define V_008DFC_SQ_SRC_10_INT 0x8A
2939 #define V_008DFC_SQ_SRC_11_INT 0x8B
2940 #define V_008DFC_SQ_SRC_12_INT 0x8C
2941 #define V_008DFC_SQ_SRC_13_INT 0x8D
2942 #define V_008DFC_SQ_SRC_14_INT 0x8E
2943 #define V_008DFC_SQ_SRC_15_INT 0x8F
2944 #define V_008DFC_SQ_SRC_16_INT 0x90
2945 #define V_008DFC_SQ_SRC_17_INT 0x91
2946 #define V_008DFC_SQ_SRC_18_INT 0x92
2947 #define V_008DFC_SQ_SRC_19_INT 0x93
2948 #define V_008DFC_SQ_SRC_20_INT 0x94
2949 #define V_008DFC_SQ_SRC_21_INT 0x95
2950 #define V_008DFC_SQ_SRC_22_INT 0x96
2951 #define V_008DFC_SQ_SRC_23_INT 0x97
2952 #define V_008DFC_SQ_SRC_24_INT 0x98
2953 #define V_008DFC_SQ_SRC_25_INT 0x99
2954 #define V_008DFC_SQ_SRC_26_INT 0x9A
2955 #define V_008DFC_SQ_SRC_27_INT 0x9B
2956 #define V_008DFC_SQ_SRC_28_INT 0x9C
2957 #define V_008DFC_SQ_SRC_29_INT 0x9D
2958 #define V_008DFC_SQ_SRC_30_INT 0x9E
2959 #define V_008DFC_SQ_SRC_31_INT 0x9F
2960 #define V_008DFC_SQ_SRC_32_INT 0xA0
2961 #define V_008DFC_SQ_SRC_33_INT 0xA1
2962 #define V_008DFC_SQ_SRC_34_INT 0xA2
2963 #define V_008DFC_SQ_SRC_35_INT 0xA3
2964 #define V_008DFC_SQ_SRC_36_INT 0xA4
2965 #define V_008DFC_SQ_SRC_37_INT 0xA5
2966 #define V_008DFC_SQ_SRC_38_INT 0xA6
2967 #define V_008DFC_SQ_SRC_39_INT 0xA7
2968 #define V_008DFC_SQ_SRC_40_INT 0xA8
2969 #define V_008DFC_SQ_SRC_41_INT 0xA9
2970 #define V_008DFC_SQ_SRC_42_INT 0xAA
2971 #define V_008DFC_SQ_SRC_43_INT 0xAB
2972 #define V_008DFC_SQ_SRC_44_INT 0xAC
2973 #define V_008DFC_SQ_SRC_45_INT 0xAD
2974 #define V_008DFC_SQ_SRC_46_INT 0xAE
2975 #define V_008DFC_SQ_SRC_47_INT 0xAF
2976 #define V_008DFC_SQ_SRC_48_INT 0xB0
2977 #define V_008DFC_SQ_SRC_49_INT 0xB1
2978 #define V_008DFC_SQ_SRC_50_INT 0xB2
2979 #define V_008DFC_SQ_SRC_51_INT 0xB3
2980 #define V_008DFC_SQ_SRC_52_INT 0xB4
2981 #define V_008DFC_SQ_SRC_53_INT 0xB5
2982 #define V_008DFC_SQ_SRC_54_INT 0xB6
2983 #define V_008DFC_SQ_SRC_55_INT 0xB7
2984 #define V_008DFC_SQ_SRC_56_INT 0xB8
2985 #define V_008DFC_SQ_SRC_57_INT 0xB9
2986 #define V_008DFC_SQ_SRC_58_INT 0xBA
2987 #define V_008DFC_SQ_SRC_59_INT 0xBB
2988 #define V_008DFC_SQ_SRC_60_INT 0xBC
2989 #define V_008DFC_SQ_SRC_61_INT 0xBD
2990 #define V_008DFC_SQ_SRC_62_INT 0xBE
2991 #define V_008DFC_SQ_SRC_63_INT 0xBF
2992 #define V_008DFC_SQ_SRC_64_INT 0xC0
2993 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
2994 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
2995 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
2996 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
2997 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
2998 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
2999 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
3000 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
3001 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
3002 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
3003 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
3004 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
3005 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
3006 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
3007 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
3008 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
3009 #define V_008DFC_SQ_SRC_0_5 0xF0
3010 #define V_008DFC_SQ_SRC_M_0_5 0xF1
3011 #define V_008DFC_SQ_SRC_1 0xF2
3012 #define V_008DFC_SQ_SRC_M_1 0xF3
3013 #define V_008DFC_SQ_SRC_2 0xF4
3014 #define V_008DFC_SQ_SRC_M_2 0xF5
3015 #define V_008DFC_SQ_SRC_4 0xF6
3016 #define V_008DFC_SQ_SRC_M_4 0xF7
3017 #define V_008DFC_SQ_SRC_VCCZ 0xFB
3018 #define V_008DFC_SQ_SRC_EXECZ 0xFC
3019 #define V_008DFC_SQ_SRC_SCC 0xFD
3020 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
3021 #define S_008DFC_SSRC1(x) (((x) & 0xFF) << 8)
3022 #define G_008DFC_SSRC1(x) (((x) >> 8) & 0xFF)
3023 #define C_008DFC_SSRC1 0xFFFF00FF
3024 #define V_008DFC_SQ_SGPR 0x00
3025 /* CIK */
3026 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
3027 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
3028 /* */
3029 #define V_008DFC_SQ_VCC_LO 0x6A
3030 #define V_008DFC_SQ_VCC_HI 0x6B
3031 #define V_008DFC_SQ_TBA_LO 0x6C
3032 #define V_008DFC_SQ_TBA_HI 0x6D
3033 #define V_008DFC_SQ_TMA_LO 0x6E
3034 #define V_008DFC_SQ_TMA_HI 0x6F
3035 #define V_008DFC_SQ_TTMP0 0x70
3036 #define V_008DFC_SQ_TTMP1 0x71
3037 #define V_008DFC_SQ_TTMP2 0x72
3038 #define V_008DFC_SQ_TTMP3 0x73
3039 #define V_008DFC_SQ_TTMP4 0x74
3040 #define V_008DFC_SQ_TTMP5 0x75
3041 #define V_008DFC_SQ_TTMP6 0x76
3042 #define V_008DFC_SQ_TTMP7 0x77
3043 #define V_008DFC_SQ_TTMP8 0x78
3044 #define V_008DFC_SQ_TTMP9 0x79
3045 #define V_008DFC_SQ_TTMP10 0x7A
3046 #define V_008DFC_SQ_TTMP11 0x7B
3047 #define V_008DFC_SQ_M0 0x7C
3048 #define V_008DFC_SQ_EXEC_LO 0x7E
3049 #define V_008DFC_SQ_EXEC_HI 0x7F
3050 #define V_008DFC_SQ_SRC_0 0x80
3051 #define V_008DFC_SQ_SRC_1_INT 0x81
3052 #define V_008DFC_SQ_SRC_2_INT 0x82
3053 #define V_008DFC_SQ_SRC_3_INT 0x83
3054 #define V_008DFC_SQ_SRC_4_INT 0x84
3055 #define V_008DFC_SQ_SRC_5_INT 0x85
3056 #define V_008DFC_SQ_SRC_6_INT 0x86
3057 #define V_008DFC_SQ_SRC_7_INT 0x87
3058 #define V_008DFC_SQ_SRC_8_INT 0x88
3059 #define V_008DFC_SQ_SRC_9_INT 0x89
3060 #define V_008DFC_SQ_SRC_10_INT 0x8A
3061 #define V_008DFC_SQ_SRC_11_INT 0x8B
3062 #define V_008DFC_SQ_SRC_12_INT 0x8C
3063 #define V_008DFC_SQ_SRC_13_INT 0x8D
3064 #define V_008DFC_SQ_SRC_14_INT 0x8E
3065 #define V_008DFC_SQ_SRC_15_INT 0x8F
3066 #define V_008DFC_SQ_SRC_16_INT 0x90
3067 #define V_008DFC_SQ_SRC_17_INT 0x91
3068 #define V_008DFC_SQ_SRC_18_INT 0x92
3069 #define V_008DFC_SQ_SRC_19_INT 0x93
3070 #define V_008DFC_SQ_SRC_20_INT 0x94
3071 #define V_008DFC_SQ_SRC_21_INT 0x95
3072 #define V_008DFC_SQ_SRC_22_INT 0x96
3073 #define V_008DFC_SQ_SRC_23_INT 0x97
3074 #define V_008DFC_SQ_SRC_24_INT 0x98
3075 #define V_008DFC_SQ_SRC_25_INT 0x99
3076 #define V_008DFC_SQ_SRC_26_INT 0x9A
3077 #define V_008DFC_SQ_SRC_27_INT 0x9B
3078 #define V_008DFC_SQ_SRC_28_INT 0x9C
3079 #define V_008DFC_SQ_SRC_29_INT 0x9D
3080 #define V_008DFC_SQ_SRC_30_INT 0x9E
3081 #define V_008DFC_SQ_SRC_31_INT 0x9F
3082 #define V_008DFC_SQ_SRC_32_INT 0xA0
3083 #define V_008DFC_SQ_SRC_33_INT 0xA1
3084 #define V_008DFC_SQ_SRC_34_INT 0xA2
3085 #define V_008DFC_SQ_SRC_35_INT 0xA3
3086 #define V_008DFC_SQ_SRC_36_INT 0xA4
3087 #define V_008DFC_SQ_SRC_37_INT 0xA5
3088 #define V_008DFC_SQ_SRC_38_INT 0xA6
3089 #define V_008DFC_SQ_SRC_39_INT 0xA7
3090 #define V_008DFC_SQ_SRC_40_INT 0xA8
3091 #define V_008DFC_SQ_SRC_41_INT 0xA9
3092 #define V_008DFC_SQ_SRC_42_INT 0xAA
3093 #define V_008DFC_SQ_SRC_43_INT 0xAB
3094 #define V_008DFC_SQ_SRC_44_INT 0xAC
3095 #define V_008DFC_SQ_SRC_45_INT 0xAD
3096 #define V_008DFC_SQ_SRC_46_INT 0xAE
3097 #define V_008DFC_SQ_SRC_47_INT 0xAF
3098 #define V_008DFC_SQ_SRC_48_INT 0xB0
3099 #define V_008DFC_SQ_SRC_49_INT 0xB1
3100 #define V_008DFC_SQ_SRC_50_INT 0xB2
3101 #define V_008DFC_SQ_SRC_51_INT 0xB3
3102 #define V_008DFC_SQ_SRC_52_INT 0xB4
3103 #define V_008DFC_SQ_SRC_53_INT 0xB5
3104 #define V_008DFC_SQ_SRC_54_INT 0xB6
3105 #define V_008DFC_SQ_SRC_55_INT 0xB7
3106 #define V_008DFC_SQ_SRC_56_INT 0xB8
3107 #define V_008DFC_SQ_SRC_57_INT 0xB9
3108 #define V_008DFC_SQ_SRC_58_INT 0xBA
3109 #define V_008DFC_SQ_SRC_59_INT 0xBB
3110 #define V_008DFC_SQ_SRC_60_INT 0xBC
3111 #define V_008DFC_SQ_SRC_61_INT 0xBD
3112 #define V_008DFC_SQ_SRC_62_INT 0xBE
3113 #define V_008DFC_SQ_SRC_63_INT 0xBF
3114 #define V_008DFC_SQ_SRC_64_INT 0xC0
3115 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
3116 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
3117 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
3118 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
3119 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
3120 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
3121 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
3122 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
3123 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
3124 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
3125 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
3126 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
3127 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
3128 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
3129 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
3130 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
3131 #define V_008DFC_SQ_SRC_0_5 0xF0
3132 #define V_008DFC_SQ_SRC_M_0_5 0xF1
3133 #define V_008DFC_SQ_SRC_1 0xF2
3134 #define V_008DFC_SQ_SRC_M_1 0xF3
3135 #define V_008DFC_SQ_SRC_2 0xF4
3136 #define V_008DFC_SQ_SRC_M_2 0xF5
3137 #define V_008DFC_SQ_SRC_4 0xF6
3138 #define V_008DFC_SQ_SRC_M_4 0xF7
3139 #define V_008DFC_SQ_SRC_VCCZ 0xFB
3140 #define V_008DFC_SQ_SRC_EXECZ 0xFC
3141 #define V_008DFC_SQ_SRC_SCC 0xFD
3142 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
3143 #define S_008DFC_SDST(x) (((x) & 0x7F) << 16)
3144 #define G_008DFC_SDST(x) (((x) >> 16) & 0x7F)
3145 #define C_008DFC_SDST 0xFF80FFFF
3146 #define V_008DFC_SQ_SGPR 0x00
3147 /* CIK */
3148 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
3149 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
3150 /* */
3151 #define V_008DFC_SQ_VCC_LO 0x6A
3152 #define V_008DFC_SQ_VCC_HI 0x6B
3153 #define V_008DFC_SQ_TBA_LO 0x6C
3154 #define V_008DFC_SQ_TBA_HI 0x6D
3155 #define V_008DFC_SQ_TMA_LO 0x6E
3156 #define V_008DFC_SQ_TMA_HI 0x6F
3157 #define V_008DFC_SQ_TTMP0 0x70
3158 #define V_008DFC_SQ_TTMP1 0x71
3159 #define V_008DFC_SQ_TTMP2 0x72
3160 #define V_008DFC_SQ_TTMP3 0x73
3161 #define V_008DFC_SQ_TTMP4 0x74
3162 #define V_008DFC_SQ_TTMP5 0x75
3163 #define V_008DFC_SQ_TTMP6 0x76
3164 #define V_008DFC_SQ_TTMP7 0x77
3165 #define V_008DFC_SQ_TTMP8 0x78
3166 #define V_008DFC_SQ_TTMP9 0x79
3167 #define V_008DFC_SQ_TTMP10 0x7A
3168 #define V_008DFC_SQ_TTMP11 0x7B
3169 #define V_008DFC_SQ_M0 0x7C
3170 #define V_008DFC_SQ_EXEC_LO 0x7E
3171 #define V_008DFC_SQ_EXEC_HI 0x7F
3172 #define S_008DFC_OP(x) (((x) & 0x7F) << 23)
3173 #define G_008DFC_OP(x) (((x) >> 23) & 0x7F)
3174 #define C_008DFC_OP 0xC07FFFFF
3175 #define V_008DFC_SQ_S_ADD_U32 0x00
3176 #define V_008DFC_SQ_S_SUB_U32 0x01
3177 #define V_008DFC_SQ_S_ADD_I32 0x02
3178 #define V_008DFC_SQ_S_SUB_I32 0x03
3179 #define V_008DFC_SQ_S_ADDC_U32 0x04
3180 #define V_008DFC_SQ_S_SUBB_U32 0x05
3181 #define V_008DFC_SQ_S_MIN_I32 0x06
3182 #define V_008DFC_SQ_S_MIN_U32 0x07
3183 #define V_008DFC_SQ_S_MAX_I32 0x08
3184 #define V_008DFC_SQ_S_MAX_U32 0x09
3185 #define V_008DFC_SQ_S_CSELECT_B32 0x0A
3186 #define V_008DFC_SQ_S_CSELECT_B64 0x0B
3187 #define V_008DFC_SQ_S_AND_B32 0x0E
3188 #define V_008DFC_SQ_S_AND_B64 0x0F
3189 #define V_008DFC_SQ_S_OR_B32 0x10
3190 #define V_008DFC_SQ_S_OR_B64 0x11
3191 #define V_008DFC_SQ_S_XOR_B32 0x12
3192 #define V_008DFC_SQ_S_XOR_B64 0x13
3193 #define V_008DFC_SQ_S_ANDN2_B32 0x14
3194 #define V_008DFC_SQ_S_ANDN2_B64 0x15
3195 #define V_008DFC_SQ_S_ORN2_B32 0x16
3196 #define V_008DFC_SQ_S_ORN2_B64 0x17
3197 #define V_008DFC_SQ_S_NAND_B32 0x18
3198 #define V_008DFC_SQ_S_NAND_B64 0x19
3199 #define V_008DFC_SQ_S_NOR_B32 0x1A
3200 #define V_008DFC_SQ_S_NOR_B64 0x1B
3201 #define V_008DFC_SQ_S_XNOR_B32 0x1C
3202 #define V_008DFC_SQ_S_XNOR_B64 0x1D
3203 #define V_008DFC_SQ_S_LSHL_B32 0x1E
3204 #define V_008DFC_SQ_S_LSHL_B64 0x1F
3205 #define V_008DFC_SQ_S_LSHR_B32 0x20
3206 #define V_008DFC_SQ_S_LSHR_B64 0x21
3207 #define V_008DFC_SQ_S_ASHR_I32 0x22
3208 #define V_008DFC_SQ_S_ASHR_I64 0x23
3209 #define V_008DFC_SQ_S_BFM_B32 0x24
3210 #define V_008DFC_SQ_S_BFM_B64 0x25
3211 #define V_008DFC_SQ_S_MUL_I32 0x26
3212 #define V_008DFC_SQ_S_BFE_U32 0x27
3213 #define V_008DFC_SQ_S_BFE_I32 0x28
3214 #define V_008DFC_SQ_S_BFE_U64 0x29
3215 #define V_008DFC_SQ_S_BFE_I64 0x2A
3216 #define V_008DFC_SQ_S_CBRANCH_G_FORK 0x2B
3217 #define V_008DFC_SQ_S_ABSDIFF_I32 0x2C
3218 #define S_008DFC_ENCODING(x) (((x) & 0x03) << 30)
3219 #define G_008DFC_ENCODING(x) (((x) >> 30) & 0x03)
3220 #define C_008DFC_ENCODING 0x3FFFFFFF
3221 #define V_008DFC_SQ_ENC_SOP2_FIELD 0x02
3222 #define R_008DFC_SQ_SOPK 0x008DFC
3223 #define S_008DFC_SIMM16(x) (((x) & 0xFFFF) << 0)
3224 #define G_008DFC_SIMM16(x) (((x) >> 0) & 0xFFFF)
3225 #define C_008DFC_SIMM16 0xFFFF0000
3226 #define S_008DFC_SDST(x) (((x) & 0x7F) << 16)
3227 #define G_008DFC_SDST(x) (((x) >> 16) & 0x7F)
3228 #define C_008DFC_SDST 0xFF80FFFF
3229 #define V_008DFC_SQ_SGPR 0x00
3230 /* CIK */
3231 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
3232 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
3233 /* */
3234 #define V_008DFC_SQ_VCC_LO 0x6A
3235 #define V_008DFC_SQ_VCC_HI 0x6B
3236 #define V_008DFC_SQ_TBA_LO 0x6C
3237 #define V_008DFC_SQ_TBA_HI 0x6D
3238 #define V_008DFC_SQ_TMA_LO 0x6E
3239 #define V_008DFC_SQ_TMA_HI 0x6F
3240 #define V_008DFC_SQ_TTMP0 0x70
3241 #define V_008DFC_SQ_TTMP1 0x71
3242 #define V_008DFC_SQ_TTMP2 0x72
3243 #define V_008DFC_SQ_TTMP3 0x73
3244 #define V_008DFC_SQ_TTMP4 0x74
3245 #define V_008DFC_SQ_TTMP5 0x75
3246 #define V_008DFC_SQ_TTMP6 0x76
3247 #define V_008DFC_SQ_TTMP7 0x77
3248 #define V_008DFC_SQ_TTMP8 0x78
3249 #define V_008DFC_SQ_TTMP9 0x79
3250 #define V_008DFC_SQ_TTMP10 0x7A
3251 #define V_008DFC_SQ_TTMP11 0x7B
3252 #define V_008DFC_SQ_M0 0x7C
3253 #define V_008DFC_SQ_EXEC_LO 0x7E
3254 #define V_008DFC_SQ_EXEC_HI 0x7F
3255 #define S_008DFC_OP(x) (((x) & 0x1F) << 23)
3256 #define G_008DFC_OP(x) (((x) >> 23) & 0x1F)
3257 #define C_008DFC_OP 0xF07FFFFF
3258 #define V_008DFC_SQ_S_MOVK_I32 0x00
3259 #define V_008DFC_SQ_S_CMOVK_I32 0x02
3260 #define V_008DFC_SQ_S_CMPK_EQ_I32 0x03
3261 #define V_008DFC_SQ_S_CMPK_LG_I32 0x04
3262 #define V_008DFC_SQ_S_CMPK_GT_I32 0x05
3263 #define V_008DFC_SQ_S_CMPK_GE_I32 0x06
3264 #define V_008DFC_SQ_S_CMPK_LT_I32 0x07
3265 #define V_008DFC_SQ_S_CMPK_LE_I32 0x08
3266 #define V_008DFC_SQ_S_CMPK_EQ_U32 0x09
3267 #define V_008DFC_SQ_S_CMPK_LG_U32 0x0A
3268 #define V_008DFC_SQ_S_CMPK_GT_U32 0x0B
3269 #define V_008DFC_SQ_S_CMPK_GE_U32 0x0C
3270 #define V_008DFC_SQ_S_CMPK_LT_U32 0x0D
3271 #define V_008DFC_SQ_S_CMPK_LE_U32 0x0E
3272 #define V_008DFC_SQ_S_ADDK_I32 0x0F
3273 #define V_008DFC_SQ_S_MULK_I32 0x10
3274 #define V_008DFC_SQ_S_CBRANCH_I_FORK 0x11
3275 #define V_008DFC_SQ_S_GETREG_B32 0x12
3276 #define V_008DFC_SQ_S_SETREG_B32 0x13
3277 #define V_008DFC_SQ_S_GETREG_REGRD_B32 0x14
3278 #define V_008DFC_SQ_S_SETREG_IMM32_B32 0x15
3279 #define S_008DFC_ENCODING(x) (((x) & 0x0F) << 28)
3280 #define G_008DFC_ENCODING(x) (((x) >> 28) & 0x0F)
3281 #define C_008DFC_ENCODING 0x0FFFFFFF
3282 #define V_008DFC_SQ_ENC_SOPK_FIELD 0x0B
3283 #define R_008DFC_SQ_VOP3_0 0x008DFC
3284 #define S_008DFC_VDST(x) (((x) & 0xFF) << 0)
3285 #define G_008DFC_VDST(x) (((x) >> 0) & 0xFF)
3286 #define C_008DFC_VDST 0xFFFFFF00
3287 #define V_008DFC_SQ_VGPR 0x00
3288 #define S_008DFC_ABS(x) (((x) & 0x07) << 8)
3289 #define G_008DFC_ABS(x) (((x) >> 8) & 0x07)
3290 #define C_008DFC_ABS 0xFFFFF8FF
3291 #define S_008DFC_CLAMP(x) (((x) & 0x1) << 11)
3292 #define G_008DFC_CLAMP(x) (((x) >> 11) & 0x1)
3293 #define C_008DFC_CLAMP 0xFFFFF7FF
3294 #define S_008DFC_OP(x) (((x) & 0x1FF) << 17)
3295 #define G_008DFC_OP(x) (((x) >> 17) & 0x1FF)
3296 #define C_008DFC_OP 0xFC01FFFF
3297 #define V_008DFC_SQ_V_OPC_OFFSET 0x00
3298 #define V_008DFC_SQ_V_OP2_OFFSET 0x100
3299 #define V_008DFC_SQ_V_MAD_LEGACY_F32 0x140
3300 #define V_008DFC_SQ_V_MAD_F32 0x141
3301 #define V_008DFC_SQ_V_MAD_I32_I24 0x142
3302 #define V_008DFC_SQ_V_MAD_U32_U24 0x143
3303 #define V_008DFC_SQ_V_CUBEID_F32 0x144
3304 #define V_008DFC_SQ_V_CUBESC_F32 0x145
3305 #define V_008DFC_SQ_V_CUBETC_F32 0x146
3306 #define V_008DFC_SQ_V_CUBEMA_F32 0x147
3307 #define V_008DFC_SQ_V_BFE_U32 0x148
3308 #define V_008DFC_SQ_V_BFE_I32 0x149
3309 #define V_008DFC_SQ_V_BFI_B32 0x14A
3310 #define V_008DFC_SQ_V_FMA_F32 0x14B
3311 #define V_008DFC_SQ_V_FMA_F64 0x14C
3312 #define V_008DFC_SQ_V_LERP_U8 0x14D
3313 #define V_008DFC_SQ_V_ALIGNBIT_B32 0x14E
3314 #define V_008DFC_SQ_V_ALIGNBYTE_B32 0x14F
3315 #define V_008DFC_SQ_V_MULLIT_F32 0x150
3316 #define V_008DFC_SQ_V_MIN3_F32 0x151
3317 #define V_008DFC_SQ_V_MIN3_I32 0x152
3318 #define V_008DFC_SQ_V_MIN3_U32 0x153
3319 #define V_008DFC_SQ_V_MAX3_F32 0x154
3320 #define V_008DFC_SQ_V_MAX3_I32 0x155
3321 #define V_008DFC_SQ_V_MAX3_U32 0x156
3322 #define V_008DFC_SQ_V_MED3_F32 0x157
3323 #define V_008DFC_SQ_V_MED3_I32 0x158
3324 #define V_008DFC_SQ_V_MED3_U32 0x159
3325 #define V_008DFC_SQ_V_SAD_U8 0x15A
3326 #define V_008DFC_SQ_V_SAD_HI_U8 0x15B
3327 #define V_008DFC_SQ_V_SAD_U16 0x15C
3328 #define V_008DFC_SQ_V_SAD_U32 0x15D
3329 #define V_008DFC_SQ_V_CVT_PK_U8_F32 0x15E
3330 #define V_008DFC_SQ_V_DIV_FIXUP_F32 0x15F
3331 #define V_008DFC_SQ_V_DIV_FIXUP_F64 0x160
3332 #define V_008DFC_SQ_V_LSHL_B64 0x161
3333 #define V_008DFC_SQ_V_LSHR_B64 0x162
3334 #define V_008DFC_SQ_V_ASHR_I64 0x163
3335 #define V_008DFC_SQ_V_ADD_F64 0x164
3336 #define V_008DFC_SQ_V_MUL_F64 0x165
3337 #define V_008DFC_SQ_V_MIN_F64 0x166
3338 #define V_008DFC_SQ_V_MAX_F64 0x167
3339 #define V_008DFC_SQ_V_LDEXP_F64 0x168
3340 #define V_008DFC_SQ_V_MUL_LO_U32 0x169
3341 #define V_008DFC_SQ_V_MUL_HI_U32 0x16A
3342 #define V_008DFC_SQ_V_MUL_LO_I32 0x16B
3343 #define V_008DFC_SQ_V_MUL_HI_I32 0x16C
3344 #define V_008DFC_SQ_V_DIV_SCALE_F32 0x16D
3345 #define V_008DFC_SQ_V_DIV_SCALE_F64 0x16E
3346 #define V_008DFC_SQ_V_DIV_FMAS_F32 0x16F
3347 #define V_008DFC_SQ_V_DIV_FMAS_F64 0x170
3348 #define V_008DFC_SQ_V_MSAD_U8 0x171
3349 #define V_008DFC_SQ_V_QSAD_U8 0x172
3350 #define V_008DFC_SQ_V_MQSAD_U8 0x173
3351 #define V_008DFC_SQ_V_TRIG_PREOP_F64 0x174
3352 /* CIK */
3353 #define V_008DFC_SQ_V_MQSAD_U32_U8 0x175
3354 #define V_008DFC_SQ_V_MAD_U64_U32 0x176
3355 #define V_008DFC_SQ_V_MAD_I64_I32 0x177
3356 /* */
3357 #define V_008DFC_SQ_V_OP1_OFFSET 0x180
3358 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
3359 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
3360 #define C_008DFC_ENCODING 0x03FFFFFF
3361 #define V_008DFC_SQ_ENC_VOP3_FIELD 0x34
3362 #define R_008DFC_SQ_VOP2 0x008DFC
3363 #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0)
3364 #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF)
3365 #define C_008DFC_SRC0 0xFFFFFE00
3366 #define V_008DFC_SQ_SGPR 0x00
3367 /* CIK */
3368 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
3369 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
3370 /* */
3371 #define V_008DFC_SQ_VCC_LO 0x6A
3372 #define V_008DFC_SQ_VCC_HI 0x6B
3373 #define V_008DFC_SQ_TBA_LO 0x6C
3374 #define V_008DFC_SQ_TBA_HI 0x6D
3375 #define V_008DFC_SQ_TMA_LO 0x6E
3376 #define V_008DFC_SQ_TMA_HI 0x6F
3377 #define V_008DFC_SQ_TTMP0 0x70
3378 #define V_008DFC_SQ_TTMP1 0x71
3379 #define V_008DFC_SQ_TTMP2 0x72
3380 #define V_008DFC_SQ_TTMP3 0x73
3381 #define V_008DFC_SQ_TTMP4 0x74
3382 #define V_008DFC_SQ_TTMP5 0x75
3383 #define V_008DFC_SQ_TTMP6 0x76
3384 #define V_008DFC_SQ_TTMP7 0x77
3385 #define V_008DFC_SQ_TTMP8 0x78
3386 #define V_008DFC_SQ_TTMP9 0x79
3387 #define V_008DFC_SQ_TTMP10 0x7A
3388 #define V_008DFC_SQ_TTMP11 0x7B
3389 #define V_008DFC_SQ_M0 0x7C
3390 #define V_008DFC_SQ_EXEC_LO 0x7E
3391 #define V_008DFC_SQ_EXEC_HI 0x7F
3392 #define V_008DFC_SQ_SRC_0 0x80
3393 #define V_008DFC_SQ_SRC_1_INT 0x81
3394 #define V_008DFC_SQ_SRC_2_INT 0x82
3395 #define V_008DFC_SQ_SRC_3_INT 0x83
3396 #define V_008DFC_SQ_SRC_4_INT 0x84
3397 #define V_008DFC_SQ_SRC_5_INT 0x85
3398 #define V_008DFC_SQ_SRC_6_INT 0x86
3399 #define V_008DFC_SQ_SRC_7_INT 0x87
3400 #define V_008DFC_SQ_SRC_8_INT 0x88
3401 #define V_008DFC_SQ_SRC_9_INT 0x89
3402 #define V_008DFC_SQ_SRC_10_INT 0x8A
3403 #define V_008DFC_SQ_SRC_11_INT 0x8B
3404 #define V_008DFC_SQ_SRC_12_INT 0x8C
3405 #define V_008DFC_SQ_SRC_13_INT 0x8D
3406 #define V_008DFC_SQ_SRC_14_INT 0x8E
3407 #define V_008DFC_SQ_SRC_15_INT 0x8F
3408 #define V_008DFC_SQ_SRC_16_INT 0x90
3409 #define V_008DFC_SQ_SRC_17_INT 0x91
3410 #define V_008DFC_SQ_SRC_18_INT 0x92
3411 #define V_008DFC_SQ_SRC_19_INT 0x93
3412 #define V_008DFC_SQ_SRC_20_INT 0x94
3413 #define V_008DFC_SQ_SRC_21_INT 0x95
3414 #define V_008DFC_SQ_SRC_22_INT 0x96
3415 #define V_008DFC_SQ_SRC_23_INT 0x97
3416 #define V_008DFC_SQ_SRC_24_INT 0x98
3417 #define V_008DFC_SQ_SRC_25_INT 0x99
3418 #define V_008DFC_SQ_SRC_26_INT 0x9A
3419 #define V_008DFC_SQ_SRC_27_INT 0x9B
3420 #define V_008DFC_SQ_SRC_28_INT 0x9C
3421 #define V_008DFC_SQ_SRC_29_INT 0x9D
3422 #define V_008DFC_SQ_SRC_30_INT 0x9E
3423 #define V_008DFC_SQ_SRC_31_INT 0x9F
3424 #define V_008DFC_SQ_SRC_32_INT 0xA0
3425 #define V_008DFC_SQ_SRC_33_INT 0xA1
3426 #define V_008DFC_SQ_SRC_34_INT 0xA2
3427 #define V_008DFC_SQ_SRC_35_INT 0xA3
3428 #define V_008DFC_SQ_SRC_36_INT 0xA4
3429 #define V_008DFC_SQ_SRC_37_INT 0xA5
3430 #define V_008DFC_SQ_SRC_38_INT 0xA6
3431 #define V_008DFC_SQ_SRC_39_INT 0xA7
3432 #define V_008DFC_SQ_SRC_40_INT 0xA8
3433 #define V_008DFC_SQ_SRC_41_INT 0xA9
3434 #define V_008DFC_SQ_SRC_42_INT 0xAA
3435 #define V_008DFC_SQ_SRC_43_INT 0xAB
3436 #define V_008DFC_SQ_SRC_44_INT 0xAC
3437 #define V_008DFC_SQ_SRC_45_INT 0xAD
3438 #define V_008DFC_SQ_SRC_46_INT 0xAE
3439 #define V_008DFC_SQ_SRC_47_INT 0xAF
3440 #define V_008DFC_SQ_SRC_48_INT 0xB0
3441 #define V_008DFC_SQ_SRC_49_INT 0xB1
3442 #define V_008DFC_SQ_SRC_50_INT 0xB2
3443 #define V_008DFC_SQ_SRC_51_INT 0xB3
3444 #define V_008DFC_SQ_SRC_52_INT 0xB4
3445 #define V_008DFC_SQ_SRC_53_INT 0xB5
3446 #define V_008DFC_SQ_SRC_54_INT 0xB6
3447 #define V_008DFC_SQ_SRC_55_INT 0xB7
3448 #define V_008DFC_SQ_SRC_56_INT 0xB8
3449 #define V_008DFC_SQ_SRC_57_INT 0xB9
3450 #define V_008DFC_SQ_SRC_58_INT 0xBA
3451 #define V_008DFC_SQ_SRC_59_INT 0xBB
3452 #define V_008DFC_SQ_SRC_60_INT 0xBC
3453 #define V_008DFC_SQ_SRC_61_INT 0xBD
3454 #define V_008DFC_SQ_SRC_62_INT 0xBE
3455 #define V_008DFC_SQ_SRC_63_INT 0xBF
3456 #define V_008DFC_SQ_SRC_64_INT 0xC0
3457 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
3458 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
3459 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
3460 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
3461 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
3462 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
3463 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
3464 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
3465 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
3466 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
3467 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
3468 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
3469 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
3470 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
3471 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
3472 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
3473 #define V_008DFC_SQ_SRC_0_5 0xF0
3474 #define V_008DFC_SQ_SRC_M_0_5 0xF1
3475 #define V_008DFC_SQ_SRC_1 0xF2
3476 #define V_008DFC_SQ_SRC_M_1 0xF3
3477 #define V_008DFC_SQ_SRC_2 0xF4
3478 #define V_008DFC_SQ_SRC_M_2 0xF5
3479 #define V_008DFC_SQ_SRC_4 0xF6
3480 #define V_008DFC_SQ_SRC_M_4 0xF7
3481 #define V_008DFC_SQ_SRC_VCCZ 0xFB
3482 #define V_008DFC_SQ_SRC_EXECZ 0xFC
3483 #define V_008DFC_SQ_SRC_SCC 0xFD
3484 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
3485 #define V_008DFC_SQ_SRC_VGPR 0x100
3486 #define S_008DFC_VSRC1(x) (((x) & 0xFF) << 9)
3487 #define G_008DFC_VSRC1(x) (((x) >> 9) & 0xFF)
3488 #define C_008DFC_VSRC1 0xFFFE01FF
3489 #define V_008DFC_SQ_VGPR 0x00
3490 #define S_008DFC_VDST(x) (((x) & 0xFF) << 17)
3491 #define G_008DFC_VDST(x) (((x) >> 17) & 0xFF)
3492 #define C_008DFC_VDST 0xFE01FFFF
3493 #define V_008DFC_SQ_VGPR 0x00
3494 #define S_008DFC_OP(x) (((x) & 0x3F) << 25)
3495 #define G_008DFC_OP(x) (((x) >> 25) & 0x3F)
3496 #define C_008DFC_OP 0x81FFFFFF
3497 #define V_008DFC_SQ_V_CNDMASK_B32 0x00
3498 #define V_008DFC_SQ_V_READLANE_B32 0x01
3499 #define V_008DFC_SQ_V_WRITELANE_B32 0x02
3500 #define V_008DFC_SQ_V_ADD_F32 0x03
3501 #define V_008DFC_SQ_V_SUB_F32 0x04
3502 #define V_008DFC_SQ_V_SUBREV_F32 0x05
3503 #define V_008DFC_SQ_V_MAC_LEGACY_F32 0x06
3504 #define V_008DFC_SQ_V_MUL_LEGACY_F32 0x07
3505 #define V_008DFC_SQ_V_MUL_F32 0x08
3506 #define V_008DFC_SQ_V_MUL_I32_I24 0x09
3507 #define V_008DFC_SQ_V_MUL_HI_I32_I24 0x0A
3508 #define V_008DFC_SQ_V_MUL_U32_U24 0x0B
3509 #define V_008DFC_SQ_V_MUL_HI_U32_U24 0x0C
3510 #define V_008DFC_SQ_V_MIN_LEGACY_F32 0x0D
3511 #define V_008DFC_SQ_V_MAX_LEGACY_F32 0x0E
3512 #define V_008DFC_SQ_V_MIN_F32 0x0F
3513 #define V_008DFC_SQ_V_MAX_F32 0x10
3514 #define V_008DFC_SQ_V_MIN_I32 0x11
3515 #define V_008DFC_SQ_V_MAX_I32 0x12
3516 #define V_008DFC_SQ_V_MIN_U32 0x13
3517 #define V_008DFC_SQ_V_MAX_U32 0x14
3518 #define V_008DFC_SQ_V_LSHR_B32 0x15
3519 #define V_008DFC_SQ_V_LSHRREV_B32 0x16
3520 #define V_008DFC_SQ_V_ASHR_I32 0x17
3521 #define V_008DFC_SQ_V_ASHRREV_I32 0x18
3522 #define V_008DFC_SQ_V_LSHL_B32 0x19
3523 #define V_008DFC_SQ_V_LSHLREV_B32 0x1A
3524 #define V_008DFC_SQ_V_AND_B32 0x1B
3525 #define V_008DFC_SQ_V_OR_B32 0x1C
3526 #define V_008DFC_SQ_V_XOR_B32 0x1D
3527 #define V_008DFC_SQ_V_BFM_B32 0x1E
3528 #define V_008DFC_SQ_V_MAC_F32 0x1F
3529 #define V_008DFC_SQ_V_MADMK_F32 0x20
3530 #define V_008DFC_SQ_V_MADAK_F32 0x21
3531 #define V_008DFC_SQ_V_BCNT_U32_B32 0x22
3532 #define V_008DFC_SQ_V_MBCNT_LO_U32_B32 0x23
3533 #define V_008DFC_SQ_V_MBCNT_HI_U32_B32 0x24
3534 #define V_008DFC_SQ_V_ADD_I32 0x25
3535 #define V_008DFC_SQ_V_SUB_I32 0x26
3536 #define V_008DFC_SQ_V_SUBREV_I32 0x27
3537 #define V_008DFC_SQ_V_ADDC_U32 0x28
3538 #define V_008DFC_SQ_V_SUBB_U32 0x29
3539 #define V_008DFC_SQ_V_SUBBREV_U32 0x2A
3540 #define V_008DFC_SQ_V_LDEXP_F32 0x2B
3541 #define V_008DFC_SQ_V_CVT_PKACCUM_U8_F32 0x2C
3542 #define V_008DFC_SQ_V_CVT_PKNORM_I16_F32 0x2D
3543 #define V_008DFC_SQ_V_CVT_PKNORM_U16_F32 0x2E
3544 #define V_008DFC_SQ_V_CVT_PKRTZ_F16_F32 0x2F
3545 #define V_008DFC_SQ_V_CVT_PK_U16_U32 0x30
3546 #define V_008DFC_SQ_V_CVT_PK_I16_I32 0x31
3547 #define S_008DFC_ENCODING(x) (((x) & 0x1) << 31)
3548 #define G_008DFC_ENCODING(x) (((x) >> 31) & 0x1)
3549 #define C_008DFC_ENCODING 0x7FFFFFFF
3550 #define R_008DFC_SQ_VOP3_0_SDST_ENC 0x008DFC
3551 #define S_008DFC_VDST(x) (((x) & 0xFF) << 0)
3552 #define G_008DFC_VDST(x) (((x) >> 0) & 0xFF)
3553 #define C_008DFC_VDST 0xFFFFFF00
3554 #define V_008DFC_SQ_VGPR 0x00
3555 #define S_008DFC_SDST(x) (((x) & 0x7F) << 8)
3556 #define G_008DFC_SDST(x) (((x) >> 8) & 0x7F)
3557 #define C_008DFC_SDST 0xFFFF80FF
3558 #define V_008DFC_SQ_SGPR 0x00
3559 /* CIK */
3560 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
3561 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
3562 /* */
3563 #define V_008DFC_SQ_VCC_LO 0x6A
3564 #define V_008DFC_SQ_VCC_HI 0x6B
3565 #define V_008DFC_SQ_TBA_LO 0x6C
3566 #define V_008DFC_SQ_TBA_HI 0x6D
3567 #define V_008DFC_SQ_TMA_LO 0x6E
3568 #define V_008DFC_SQ_TMA_HI 0x6F
3569 #define V_008DFC_SQ_TTMP0 0x70
3570 #define V_008DFC_SQ_TTMP1 0x71
3571 #define V_008DFC_SQ_TTMP2 0x72
3572 #define V_008DFC_SQ_TTMP3 0x73
3573 #define V_008DFC_SQ_TTMP4 0x74
3574 #define V_008DFC_SQ_TTMP5 0x75
3575 #define V_008DFC_SQ_TTMP6 0x76
3576 #define V_008DFC_SQ_TTMP7 0x77
3577 #define V_008DFC_SQ_TTMP8 0x78
3578 #define V_008DFC_SQ_TTMP9 0x79
3579 #define V_008DFC_SQ_TTMP10 0x7A
3580 #define V_008DFC_SQ_TTMP11 0x7B
3581 #define S_008DFC_OP(x) (((x) & 0x1FF) << 17)
3582 #define G_008DFC_OP(x) (((x) >> 17) & 0x1FF)
3583 #define C_008DFC_OP 0xFC01FFFF
3584 #define V_008DFC_SQ_V_OPC_OFFSET 0x00
3585 #define V_008DFC_SQ_V_OP2_OFFSET 0x100
3586 #define V_008DFC_SQ_V_MAD_LEGACY_F32 0x140
3587 #define V_008DFC_SQ_V_MAD_F32 0x141
3588 #define V_008DFC_SQ_V_MAD_I32_I24 0x142
3589 #define V_008DFC_SQ_V_MAD_U32_U24 0x143
3590 #define V_008DFC_SQ_V_CUBEID_F32 0x144
3591 #define V_008DFC_SQ_V_CUBESC_F32 0x145
3592 #define V_008DFC_SQ_V_CUBETC_F32 0x146
3593 #define V_008DFC_SQ_V_CUBEMA_F32 0x147
3594 #define V_008DFC_SQ_V_BFE_U32 0x148
3595 #define V_008DFC_SQ_V_BFE_I32 0x149
3596 #define V_008DFC_SQ_V_BFI_B32 0x14A
3597 #define V_008DFC_SQ_V_FMA_F32 0x14B
3598 #define V_008DFC_SQ_V_FMA_F64 0x14C
3599 #define V_008DFC_SQ_V_LERP_U8 0x14D
3600 #define V_008DFC_SQ_V_ALIGNBIT_B32 0x14E
3601 #define V_008DFC_SQ_V_ALIGNBYTE_B32 0x14F
3602 #define V_008DFC_SQ_V_MULLIT_F32 0x150
3603 #define V_008DFC_SQ_V_MIN3_F32 0x151
3604 #define V_008DFC_SQ_V_MIN3_I32 0x152
3605 #define V_008DFC_SQ_V_MIN3_U32 0x153
3606 #define V_008DFC_SQ_V_MAX3_F32 0x154
3607 #define V_008DFC_SQ_V_MAX3_I32 0x155
3608 #define V_008DFC_SQ_V_MAX3_U32 0x156
3609 #define V_008DFC_SQ_V_MED3_F32 0x157
3610 #define V_008DFC_SQ_V_MED3_I32 0x158
3611 #define V_008DFC_SQ_V_MED3_U32 0x159
3612 #define V_008DFC_SQ_V_SAD_U8 0x15A
3613 #define V_008DFC_SQ_V_SAD_HI_U8 0x15B
3614 #define V_008DFC_SQ_V_SAD_U16 0x15C
3615 #define V_008DFC_SQ_V_SAD_U32 0x15D
3616 #define V_008DFC_SQ_V_CVT_PK_U8_F32 0x15E
3617 #define V_008DFC_SQ_V_DIV_FIXUP_F32 0x15F
3618 #define V_008DFC_SQ_V_DIV_FIXUP_F64 0x160
3619 #define V_008DFC_SQ_V_LSHL_B64 0x161
3620 #define V_008DFC_SQ_V_LSHR_B64 0x162
3621 #define V_008DFC_SQ_V_ASHR_I64 0x163
3622 #define V_008DFC_SQ_V_ADD_F64 0x164
3623 #define V_008DFC_SQ_V_MUL_F64 0x165
3624 #define V_008DFC_SQ_V_MIN_F64 0x166
3625 #define V_008DFC_SQ_V_MAX_F64 0x167
3626 #define V_008DFC_SQ_V_LDEXP_F64 0x168
3627 #define V_008DFC_SQ_V_MUL_LO_U32 0x169
3628 #define V_008DFC_SQ_V_MUL_HI_U32 0x16A
3629 #define V_008DFC_SQ_V_MUL_LO_I32 0x16B
3630 #define V_008DFC_SQ_V_MUL_HI_I32 0x16C
3631 #define V_008DFC_SQ_V_DIV_SCALE_F32 0x16D
3632 #define V_008DFC_SQ_V_DIV_SCALE_F64 0x16E
3633 #define V_008DFC_SQ_V_DIV_FMAS_F32 0x16F
3634 #define V_008DFC_SQ_V_DIV_FMAS_F64 0x170
3635 #define V_008DFC_SQ_V_MSAD_U8 0x171
3636 #define V_008DFC_SQ_V_QSAD_U8 0x172
3637 #define V_008DFC_SQ_V_MQSAD_U8 0x173
3638 #define V_008DFC_SQ_V_TRIG_PREOP_F64 0x174
3639 /* CIK */
3640 #define V_008DFC_SQ_V_MQSAD_U32_U8 0x175
3641 #define V_008DFC_SQ_V_MAD_U64_U32 0x176
3642 #define V_008DFC_SQ_V_MAD_I64_I32 0x177
3643 /* */
3644 #define V_008DFC_SQ_V_OP1_OFFSET 0x180
3645 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
3646 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
3647 #define C_008DFC_ENCODING 0x03FFFFFF
3648 #define V_008DFC_SQ_ENC_VOP3_FIELD 0x34
3649 #define R_008DFC_SQ_MUBUF_0 0x008DFC
3650 #define S_008DFC_OFFSET(x) (((x) & 0xFFF) << 0)
3651 #define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFFF)
3652 #define C_008DFC_OFFSET 0xFFFFF000
3653 #define S_008DFC_OFFEN(x) (((x) & 0x1) << 12)
3654 #define G_008DFC_OFFEN(x) (((x) >> 12) & 0x1)
3655 #define C_008DFC_OFFEN 0xFFFFEFFF
3656 #define S_008DFC_IDXEN(x) (((x) & 0x1) << 13)
3657 #define G_008DFC_IDXEN(x) (((x) >> 13) & 0x1)
3658 #define C_008DFC_IDXEN 0xFFFFDFFF
3659 #define S_008DFC_GLC(x) (((x) & 0x1) << 14)
3660 #define G_008DFC_GLC(x) (((x) >> 14) & 0x1)
3661 #define C_008DFC_GLC 0xFFFFBFFF
3662 #define S_008DFC_ADDR64(x) (((x) & 0x1) << 15)
3663 #define G_008DFC_ADDR64(x) (((x) >> 15) & 0x1)
3664 #define C_008DFC_ADDR64 0xFFFF7FFF
3665 #define S_008DFC_LDS(x) (((x) & 0x1) << 16)
3666 #define G_008DFC_LDS(x) (((x) >> 16) & 0x1)
3667 #define C_008DFC_LDS 0xFFFEFFFF
3668 #define S_008DFC_OP(x) (((x) & 0x7F) << 18)
3669 #define G_008DFC_OP(x) (((x) >> 18) & 0x7F)
3670 #define C_008DFC_OP 0xFE03FFFF
3671 #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_X 0x00
3672 #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XY 0x01
3673 #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XYZ 0x02
3674 #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XYZW 0x03
3675 #define V_008DFC_SQ_BUFFER_STORE_FORMAT_X 0x04
3676 #define V_008DFC_SQ_BUFFER_STORE_FORMAT_XY 0x05
3677 #define V_008DFC_SQ_BUFFER_STORE_FORMAT_XYZ 0x06
3678 #define V_008DFC_SQ_BUFFER_STORE_FORMAT_XYZW 0x07
3679 #define V_008DFC_SQ_BUFFER_LOAD_UBYTE 0x08
3680 #define V_008DFC_SQ_BUFFER_LOAD_SBYTE 0x09
3681 #define V_008DFC_SQ_BUFFER_LOAD_USHORT 0x0A
3682 #define V_008DFC_SQ_BUFFER_LOAD_SSHORT 0x0B
3683 #define V_008DFC_SQ_BUFFER_LOAD_DWORD 0x0C
3684 #define V_008DFC_SQ_BUFFER_LOAD_DWORDX2 0x0D
3685 #define V_008DFC_SQ_BUFFER_LOAD_DWORDX4 0x0E
3686 /* CIK */
3687 #define V_008DFC_SQ_BUFFER_LOAD_DWORDX3 0x0F
3688 /* */
3689 #define V_008DFC_SQ_BUFFER_STORE_BYTE 0x18
3690 #define V_008DFC_SQ_BUFFER_STORE_SHORT 0x1A
3691 #define V_008DFC_SQ_BUFFER_STORE_DWORD 0x1C
3692 #define V_008DFC_SQ_BUFFER_STORE_DWORDX2 0x1D
3693 #define V_008DFC_SQ_BUFFER_STORE_DWORDX4 0x1E
3694 /* CIK */
3695 #define V_008DFC_SQ_BUFFER_STORE_DWORDX3 0x1F
3696 /* */
3697 #define V_008DFC_SQ_BUFFER_ATOMIC_SWAP 0x30
3698 #define V_008DFC_SQ_BUFFER_ATOMIC_CMPSWAP 0x31
3699 #define V_008DFC_SQ_BUFFER_ATOMIC_ADD 0x32
3700 #define V_008DFC_SQ_BUFFER_ATOMIC_SUB 0x33
3701 #define V_008DFC_SQ_BUFFER_ATOMIC_RSUB 0x34 /* not on CIK */
3702 #define V_008DFC_SQ_BUFFER_ATOMIC_SMIN 0x35
3703 #define V_008DFC_SQ_BUFFER_ATOMIC_UMIN 0x36
3704 #define V_008DFC_SQ_BUFFER_ATOMIC_SMAX 0x37
3705 #define V_008DFC_SQ_BUFFER_ATOMIC_UMAX 0x38
3706 #define V_008DFC_SQ_BUFFER_ATOMIC_AND 0x39
3707 #define V_008DFC_SQ_BUFFER_ATOMIC_OR 0x3A
3708 #define V_008DFC_SQ_BUFFER_ATOMIC_XOR 0x3B
3709 #define V_008DFC_SQ_BUFFER_ATOMIC_INC 0x3C
3710 #define V_008DFC_SQ_BUFFER_ATOMIC_DEC 0x3D
3711 #define V_008DFC_SQ_BUFFER_ATOMIC_FCMPSWAP 0x3E
3712 #define V_008DFC_SQ_BUFFER_ATOMIC_FMIN 0x3F
3713 #define V_008DFC_SQ_BUFFER_ATOMIC_FMAX 0x40
3714 #define V_008DFC_SQ_BUFFER_ATOMIC_SWAP_X2 0x50
3715 #define V_008DFC_SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x51
3716 #define V_008DFC_SQ_BUFFER_ATOMIC_ADD_X2 0x52
3717 #define V_008DFC_SQ_BUFFER_ATOMIC_SUB_X2 0x53
3718 #define V_008DFC_SQ_BUFFER_ATOMIC_RSUB_X2 0x54 /* not on CIK */
3719 #define V_008DFC_SQ_BUFFER_ATOMIC_SMIN_X2 0x55
3720 #define V_008DFC_SQ_BUFFER_ATOMIC_UMIN_X2 0x56
3721 #define V_008DFC_SQ_BUFFER_ATOMIC_SMAX_X2 0x57
3722 #define V_008DFC_SQ_BUFFER_ATOMIC_UMAX_X2 0x58
3723 #define V_008DFC_SQ_BUFFER_ATOMIC_AND_X2 0x59
3724 #define V_008DFC_SQ_BUFFER_ATOMIC_OR_X2 0x5A
3725 #define V_008DFC_SQ_BUFFER_ATOMIC_XOR_X2 0x5B
3726 #define V_008DFC_SQ_BUFFER_ATOMIC_INC_X2 0x5C
3727 #define V_008DFC_SQ_BUFFER_ATOMIC_DEC_X2 0x5D
3728 #define V_008DFC_SQ_BUFFER_ATOMIC_FCMPSWAP_X2 0x5E
3729 #define V_008DFC_SQ_BUFFER_ATOMIC_FMIN_X2 0x5F
3730 #define V_008DFC_SQ_BUFFER_ATOMIC_FMAX_X2 0x60
3731 #define V_008DFC_SQ_BUFFER_WBINVL1_SC 0x70
3732 /* CIK */
3733 #define V_008DFC_SQ_BUFFER_WBINVL1_VOL 0x70
3734 /* */
3735 #define V_008DFC_SQ_BUFFER_WBINVL1 0x71
3736 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
3737 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
3738 #define C_008DFC_ENCODING 0x03FFFFFF
3739 #define V_008DFC_SQ_ENC_MUBUF_FIELD 0x38
3740 #endif
3741 #define R_008F00_SQ_BUF_RSRC_WORD0 0x008F00
3742 #define R_008F04_SQ_BUF_RSRC_WORD1 0x008F04
3743 #define S_008F04_BASE_ADDRESS_HI(x) (((x) & 0xFFFF) << 0)
3744 #define G_008F04_BASE_ADDRESS_HI(x) (((x) >> 0) & 0xFFFF)
3745 #define C_008F04_BASE_ADDRESS_HI 0xFFFF0000
3746 #define S_008F04_STRIDE(x) (((x) & 0x3FFF) << 16)
3747 #define G_008F04_STRIDE(x) (((x) >> 16) & 0x3FFF)
3748 #define C_008F04_STRIDE 0xC000FFFF
3749 #define S_008F04_CACHE_SWIZZLE(x) (((x) & 0x1) << 30)
3750 #define G_008F04_CACHE_SWIZZLE(x) (((x) >> 30) & 0x1)
3751 #define C_008F04_CACHE_SWIZZLE 0xBFFFFFFF
3752 #define S_008F04_SWIZZLE_ENABLE(x) (((x) & 0x1) << 31)
3753 #define G_008F04_SWIZZLE_ENABLE(x) (((x) >> 31) & 0x1)
3754 #define C_008F04_SWIZZLE_ENABLE 0x7FFFFFFF
3755 #define R_008F08_SQ_BUF_RSRC_WORD2 0x008F08
3756 #define R_008F0C_SQ_BUF_RSRC_WORD3 0x008F0C
3757 #define S_008F0C_DST_SEL_X(x) (((x) & 0x07) << 0)
3758 #define G_008F0C_DST_SEL_X(x) (((x) >> 0) & 0x07)
3759 #define C_008F0C_DST_SEL_X 0xFFFFFFF8
3760 #define V_008F0C_SQ_SEL_0 0x00
3761 #define V_008F0C_SQ_SEL_1 0x01
3762 #define V_008F0C_SQ_SEL_RESERVED_0 0x02
3763 #define V_008F0C_SQ_SEL_RESERVED_1 0x03
3764 #define V_008F0C_SQ_SEL_X 0x04
3765 #define V_008F0C_SQ_SEL_Y 0x05
3766 #define V_008F0C_SQ_SEL_Z 0x06
3767 #define V_008F0C_SQ_SEL_W 0x07
3768 #define S_008F0C_DST_SEL_Y(x) (((x) & 0x07) << 3)
3769 #define G_008F0C_DST_SEL_Y(x) (((x) >> 3) & 0x07)
3770 #define C_008F0C_DST_SEL_Y 0xFFFFFFC7
3771 #define V_008F0C_SQ_SEL_0 0x00
3772 #define V_008F0C_SQ_SEL_1 0x01
3773 #define V_008F0C_SQ_SEL_RESERVED_0 0x02
3774 #define V_008F0C_SQ_SEL_RESERVED_1 0x03
3775 #define V_008F0C_SQ_SEL_X 0x04
3776 #define V_008F0C_SQ_SEL_Y 0x05
3777 #define V_008F0C_SQ_SEL_Z 0x06
3778 #define V_008F0C_SQ_SEL_W 0x07
3779 #define S_008F0C_DST_SEL_Z(x) (((x) & 0x07) << 6)
3780 #define G_008F0C_DST_SEL_Z(x) (((x) >> 6) & 0x07)
3781 #define C_008F0C_DST_SEL_Z 0xFFFFFE3F
3782 #define V_008F0C_SQ_SEL_0 0x00
3783 #define V_008F0C_SQ_SEL_1 0x01
3784 #define V_008F0C_SQ_SEL_RESERVED_0 0x02
3785 #define V_008F0C_SQ_SEL_RESERVED_1 0x03
3786 #define V_008F0C_SQ_SEL_X 0x04
3787 #define V_008F0C_SQ_SEL_Y 0x05
3788 #define V_008F0C_SQ_SEL_Z 0x06
3789 #define V_008F0C_SQ_SEL_W 0x07
3790 #define S_008F0C_DST_SEL_W(x) (((x) & 0x07) << 9)
3791 #define G_008F0C_DST_SEL_W(x) (((x) >> 9) & 0x07)
3792 #define C_008F0C_DST_SEL_W 0xFFFFF1FF
3793 #define V_008F0C_SQ_SEL_0 0x00
3794 #define V_008F0C_SQ_SEL_1 0x01
3795 #define V_008F0C_SQ_SEL_RESERVED_0 0x02
3796 #define V_008F0C_SQ_SEL_RESERVED_1 0x03
3797 #define V_008F0C_SQ_SEL_X 0x04
3798 #define V_008F0C_SQ_SEL_Y 0x05
3799 #define V_008F0C_SQ_SEL_Z 0x06
3800 #define V_008F0C_SQ_SEL_W 0x07
3801 #define S_008F0C_NUM_FORMAT(x) (((x) & 0x07) << 12)
3802 #define G_008F0C_NUM_FORMAT(x) (((x) >> 12) & 0x07)
3803 #define C_008F0C_NUM_FORMAT 0xFFFF8FFF
3804 #define V_008F0C_BUF_NUM_FORMAT_UNORM 0x00
3805 #define V_008F0C_BUF_NUM_FORMAT_SNORM 0x01
3806 #define V_008F0C_BUF_NUM_FORMAT_USCALED 0x02
3807 #define V_008F0C_BUF_NUM_FORMAT_SSCALED 0x03
3808 #define V_008F0C_BUF_NUM_FORMAT_UINT 0x04
3809 #define V_008F0C_BUF_NUM_FORMAT_SINT 0x05
3810 #define V_008F0C_BUF_NUM_FORMAT_SNORM_OGL 0x06
3811 #define V_008F0C_BUF_NUM_FORMAT_FLOAT 0x07
3812 #define S_008F0C_DATA_FORMAT(x) (((x) & 0x0F) << 15)
3813 #define G_008F0C_DATA_FORMAT(x) (((x) >> 15) & 0x0F)
3814 #define C_008F0C_DATA_FORMAT 0xFFF87FFF
3815 #define V_008F0C_BUF_DATA_FORMAT_INVALID 0x00
3816 #define V_008F0C_BUF_DATA_FORMAT_8 0x01
3817 #define V_008F0C_BUF_DATA_FORMAT_16 0x02
3818 #define V_008F0C_BUF_DATA_FORMAT_8_8 0x03
3819 #define V_008F0C_BUF_DATA_FORMAT_32 0x04
3820 #define V_008F0C_BUF_DATA_FORMAT_16_16 0x05
3821 #define V_008F0C_BUF_DATA_FORMAT_10_11_11 0x06
3822 #define V_008F0C_BUF_DATA_FORMAT_11_11_10 0x07
3823 #define V_008F0C_BUF_DATA_FORMAT_10_10_10_2 0x08
3824 #define V_008F0C_BUF_DATA_FORMAT_2_10_10_10 0x09
3825 #define V_008F0C_BUF_DATA_FORMAT_8_8_8_8 0x0A
3826 #define V_008F0C_BUF_DATA_FORMAT_32_32 0x0B
3827 #define V_008F0C_BUF_DATA_FORMAT_16_16_16_16 0x0C
3828 #define V_008F0C_BUF_DATA_FORMAT_32_32_32 0x0D
3829 #define V_008F0C_BUF_DATA_FORMAT_32_32_32_32 0x0E
3830 #define V_008F0C_BUF_DATA_FORMAT_RESERVED_15 0x0F
3831 #define S_008F0C_ELEMENT_SIZE(x) (((x) & 0x03) << 19)
3832 #define G_008F0C_ELEMENT_SIZE(x) (((x) >> 19) & 0x03)
3833 #define C_008F0C_ELEMENT_SIZE 0xFFE7FFFF
3834 #define S_008F0C_INDEX_STRIDE(x) (((x) & 0x03) << 21)
3835 #define G_008F0C_INDEX_STRIDE(x) (((x) >> 21) & 0x03)
3836 #define C_008F0C_INDEX_STRIDE 0xFF9FFFFF
3837 #define S_008F0C_ADD_TID_ENABLE(x) (((x) & 0x1) << 23)
3838 #define G_008F0C_ADD_TID_ENABLE(x) (((x) >> 23) & 0x1)
3839 #define C_008F0C_ADD_TID_ENABLE 0xFF7FFFFF
3840 /* CIK */
3841 #define S_008F0C_ATC(x) (((x) & 0x1) << 24)
3842 #define G_008F0C_ATC(x) (((x) >> 24) & 0x1)
3843 #define C_008F0C_ATC 0xFEFFFFFF
3844 /* */
3845 #define S_008F0C_HASH_ENABLE(x) (((x) & 0x1) << 25)
3846 #define G_008F0C_HASH_ENABLE(x) (((x) >> 25) & 0x1)
3847 #define C_008F0C_HASH_ENABLE 0xFDFFFFFF
3848 #define S_008F0C_HEAP(x) (((x) & 0x1) << 26)
3849 #define G_008F0C_HEAP(x) (((x) >> 26) & 0x1)
3850 #define C_008F0C_HEAP 0xFBFFFFFF
3851 /* CIK */
3852 #define S_008F0C_MTYPE(x) (((x) & 0x07) << 27)
3853 #define G_008F0C_MTYPE(x) (((x) >> 27) & 0x07)
3854 #define C_008F0C_MTYPE 0xC7FFFFFF
3855 /* */
3856 #define S_008F0C_TYPE(x) (((x) & 0x03) << 30)
3857 #define G_008F0C_TYPE(x) (((x) >> 30) & 0x03)
3858 #define C_008F0C_TYPE 0x3FFFFFFF
3859 #define V_008F0C_SQ_RSRC_BUF 0x00
3860 #define V_008F0C_SQ_RSRC_BUF_RSVD_1 0x01
3861 #define V_008F0C_SQ_RSRC_BUF_RSVD_2 0x02
3862 #define V_008F0C_SQ_RSRC_BUF_RSVD_3 0x03
3863 #define R_008F10_SQ_IMG_RSRC_WORD0 0x008F10
3864 #define R_008F14_SQ_IMG_RSRC_WORD1 0x008F14
3865 #define S_008F14_BASE_ADDRESS_HI(x) (((x) & 0xFF) << 0)
3866 #define G_008F14_BASE_ADDRESS_HI(x) (((x) >> 0) & 0xFF)
3867 #define C_008F14_BASE_ADDRESS_HI 0xFFFFFF00
3868 #define S_008F14_MIN_LOD(x) (((x) & 0xFFF) << 8)
3869 #define G_008F14_MIN_LOD(x) (((x) >> 8) & 0xFFF)
3870 #define C_008F14_MIN_LOD 0xFFF000FF
3871 #define S_008F14_DATA_FORMAT(x) (((x) & 0x3F) << 20)
3872 #define G_008F14_DATA_FORMAT(x) (((x) >> 20) & 0x3F)
3873 #define C_008F14_DATA_FORMAT 0xFC0FFFFF
3874 #define V_008F14_IMG_DATA_FORMAT_INVALID 0x00
3875 #define V_008F14_IMG_DATA_FORMAT_8 0x01
3876 #define V_008F14_IMG_DATA_FORMAT_16 0x02
3877 #define V_008F14_IMG_DATA_FORMAT_8_8 0x03
3878 #define V_008F14_IMG_DATA_FORMAT_32 0x04
3879 #define V_008F14_IMG_DATA_FORMAT_16_16 0x05
3880 #define V_008F14_IMG_DATA_FORMAT_10_11_11 0x06
3881 #define V_008F14_IMG_DATA_FORMAT_11_11_10 0x07
3882 #define V_008F14_IMG_DATA_FORMAT_10_10_10_2 0x08
3883 #define V_008F14_IMG_DATA_FORMAT_2_10_10_10 0x09
3884 #define V_008F14_IMG_DATA_FORMAT_8_8_8_8 0x0A
3885 #define V_008F14_IMG_DATA_FORMAT_32_32 0x0B
3886 #define V_008F14_IMG_DATA_FORMAT_16_16_16_16 0x0C
3887 #define V_008F14_IMG_DATA_FORMAT_32_32_32 0x0D
3888 #define V_008F14_IMG_DATA_FORMAT_32_32_32_32 0x0E
3889 #define V_008F14_IMG_DATA_FORMAT_RESERVED_15 0x0F
3890 #define V_008F14_IMG_DATA_FORMAT_5_6_5 0x10
3891 #define V_008F14_IMG_DATA_FORMAT_1_5_5_5 0x11
3892 #define V_008F14_IMG_DATA_FORMAT_5_5_5_1 0x12
3893 #define V_008F14_IMG_DATA_FORMAT_4_4_4_4 0x13
3894 #define V_008F14_IMG_DATA_FORMAT_8_24 0x14
3895 #define V_008F14_IMG_DATA_FORMAT_24_8 0x15
3896 #define V_008F14_IMG_DATA_FORMAT_X24_8_32 0x16
3897 #define V_008F14_IMG_DATA_FORMAT_RESERVED_23 0x17
3898 #define V_008F14_IMG_DATA_FORMAT_RESERVED_24 0x18
3899 #define V_008F14_IMG_DATA_FORMAT_RESERVED_25 0x19
3900 #define V_008F14_IMG_DATA_FORMAT_RESERVED_26 0x1A
3901 #define V_008F14_IMG_DATA_FORMAT_RESERVED_27 0x1B
3902 #define V_008F14_IMG_DATA_FORMAT_RESERVED_28 0x1C
3903 #define V_008F14_IMG_DATA_FORMAT_RESERVED_29 0x1D
3904 #define V_008F14_IMG_DATA_FORMAT_RESERVED_30 0x1E
3905 #define V_008F14_IMG_DATA_FORMAT_RESERVED_31 0x1F
3906 #define V_008F14_IMG_DATA_FORMAT_GB_GR 0x20
3907 #define V_008F14_IMG_DATA_FORMAT_BG_RG 0x21
3908 #define V_008F14_IMG_DATA_FORMAT_5_9_9_9 0x22
3909 #define V_008F14_IMG_DATA_FORMAT_BC1 0x23
3910 #define V_008F14_IMG_DATA_FORMAT_BC2 0x24
3911 #define V_008F14_IMG_DATA_FORMAT_BC3 0x25
3912 #define V_008F14_IMG_DATA_FORMAT_BC4 0x26
3913 #define V_008F14_IMG_DATA_FORMAT_BC5 0x27
3914 #define V_008F14_IMG_DATA_FORMAT_BC6 0x28
3915 #define V_008F14_IMG_DATA_FORMAT_BC7 0x29
3916 #define V_008F14_IMG_DATA_FORMAT_RESERVED_42 0x2A
3917 #define V_008F14_IMG_DATA_FORMAT_RESERVED_43 0x2B
3918 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1 0x2C
3919 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1 0x2D
3920 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1 0x2E
3921 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2 0x2F
3922 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2 0x30
3923 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4 0x31
3924 #define V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1 0x32
3925 #define V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2 0x33
3926 #define V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2 0x34
3927 #define V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4 0x35
3928 #define V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8 0x36
3929 #define V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4 0x37
3930 #define V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8 0x38
3931 #define V_008F14_IMG_DATA_FORMAT_4_4 0x39
3932 #define V_008F14_IMG_DATA_FORMAT_6_5_5 0x3A
3933 #define V_008F14_IMG_DATA_FORMAT_1 0x3B
3934 #define V_008F14_IMG_DATA_FORMAT_1_REVERSED 0x3C
3935 #define V_008F14_IMG_DATA_FORMAT_32_AS_8 0x3D
3936 #define V_008F14_IMG_DATA_FORMAT_32_AS_8_8 0x3E
3937 #define V_008F14_IMG_DATA_FORMAT_32_AS_32_32_32_32 0x3F
3938 #define S_008F14_NUM_FORMAT(x) (((x) & 0x0F) << 26)
3939 #define G_008F14_NUM_FORMAT(x) (((x) >> 26) & 0x0F)
3940 #define C_008F14_NUM_FORMAT 0xC3FFFFFF
3941 #define V_008F14_IMG_NUM_FORMAT_UNORM 0x00
3942 #define V_008F14_IMG_NUM_FORMAT_SNORM 0x01
3943 #define V_008F14_IMG_NUM_FORMAT_USCALED 0x02
3944 #define V_008F14_IMG_NUM_FORMAT_SSCALED 0x03
3945 #define V_008F14_IMG_NUM_FORMAT_UINT 0x04
3946 #define V_008F14_IMG_NUM_FORMAT_SINT 0x05
3947 #define V_008F14_IMG_NUM_FORMAT_SNORM_OGL 0x06
3948 #define V_008F14_IMG_NUM_FORMAT_FLOAT 0x07
3949 #define V_008F14_IMG_NUM_FORMAT_RESERVED_8 0x08
3950 #define V_008F14_IMG_NUM_FORMAT_SRGB 0x09
3951 #define V_008F14_IMG_NUM_FORMAT_UBNORM 0x0A
3952 #define V_008F14_IMG_NUM_FORMAT_UBNORM_OGL 0x0B
3953 #define V_008F14_IMG_NUM_FORMAT_UBINT 0x0C
3954 #define V_008F14_IMG_NUM_FORMAT_UBSCALED 0x0D
3955 #define V_008F14_IMG_NUM_FORMAT_RESERVED_14 0x0E
3956 #define V_008F14_IMG_NUM_FORMAT_RESERVED_15 0x0F
3957 /* CIK */
3958 #define S_008F14_MTYPE(x) (((x) & 0x03) << 30)
3959 #define G_008F14_MTYPE(x) (((x) >> 30) & 0x03)
3960 #define C_008F14_MTYPE 0x3FFFFFFF
3961 /* */
3962 #define R_008F18_SQ_IMG_RSRC_WORD2 0x008F18
3963 #define S_008F18_WIDTH(x) (((x) & 0x3FFF) << 0)
3964 #define G_008F18_WIDTH(x) (((x) >> 0) & 0x3FFF)
3965 #define C_008F18_WIDTH 0xFFFFC000
3966 #define S_008F18_HEIGHT(x) (((x) & 0x3FFF) << 14)
3967 #define G_008F18_HEIGHT(x) (((x) >> 14) & 0x3FFF)
3968 #define C_008F18_HEIGHT 0xF0003FFF
3969 #define S_008F18_PERF_MOD(x) (((x) & 0x07) << 28)
3970 #define G_008F18_PERF_MOD(x) (((x) >> 28) & 0x07)
3971 #define C_008F18_PERF_MOD 0x8FFFFFFF
3972 #define S_008F18_INTERLACED(x) (((x) & 0x1) << 31)
3973 #define G_008F18_INTERLACED(x) (((x) >> 31) & 0x1)
3974 #define C_008F18_INTERLACED 0x7FFFFFFF
3975 #define R_008F1C_SQ_IMG_RSRC_WORD3 0x008F1C
3976 #define S_008F1C_DST_SEL_X(x) (((x) & 0x07) << 0)
3977 #define G_008F1C_DST_SEL_X(x) (((x) >> 0) & 0x07)
3978 #define C_008F1C_DST_SEL_X 0xFFFFFFF8
3979 #define V_008F1C_SQ_SEL_0 0x00
3980 #define V_008F1C_SQ_SEL_1 0x01
3981 #define V_008F1C_SQ_SEL_RESERVED_0 0x02
3982 #define V_008F1C_SQ_SEL_RESERVED_1 0x03
3983 #define V_008F1C_SQ_SEL_X 0x04
3984 #define V_008F1C_SQ_SEL_Y 0x05
3985 #define V_008F1C_SQ_SEL_Z 0x06
3986 #define V_008F1C_SQ_SEL_W 0x07
3987 #define S_008F1C_DST_SEL_Y(x) (((x) & 0x07) << 3)
3988 #define G_008F1C_DST_SEL_Y(x) (((x) >> 3) & 0x07)
3989 #define C_008F1C_DST_SEL_Y 0xFFFFFFC7
3990 #define V_008F1C_SQ_SEL_0 0x00
3991 #define V_008F1C_SQ_SEL_1 0x01
3992 #define V_008F1C_SQ_SEL_RESERVED_0 0x02
3993 #define V_008F1C_SQ_SEL_RESERVED_1 0x03
3994 #define V_008F1C_SQ_SEL_X 0x04
3995 #define V_008F1C_SQ_SEL_Y 0x05
3996 #define V_008F1C_SQ_SEL_Z 0x06
3997 #define V_008F1C_SQ_SEL_W 0x07
3998 #define S_008F1C_DST_SEL_Z(x) (((x) & 0x07) << 6)
3999 #define G_008F1C_DST_SEL_Z(x) (((x) >> 6) & 0x07)
4000 #define C_008F1C_DST_SEL_Z 0xFFFFFE3F
4001 #define V_008F1C_SQ_SEL_0 0x00
4002 #define V_008F1C_SQ_SEL_1 0x01
4003 #define V_008F1C_SQ_SEL_RESERVED_0 0x02
4004 #define V_008F1C_SQ_SEL_RESERVED_1 0x03
4005 #define V_008F1C_SQ_SEL_X 0x04
4006 #define V_008F1C_SQ_SEL_Y 0x05
4007 #define V_008F1C_SQ_SEL_Z 0x06
4008 #define V_008F1C_SQ_SEL_W 0x07
4009 #define S_008F1C_DST_SEL_W(x) (((x) & 0x07) << 9)
4010 #define G_008F1C_DST_SEL_W(x) (((x) >> 9) & 0x07)
4011 #define C_008F1C_DST_SEL_W 0xFFFFF1FF
4012 #define V_008F1C_SQ_SEL_0 0x00
4013 #define V_008F1C_SQ_SEL_1 0x01
4014 #define V_008F1C_SQ_SEL_RESERVED_0 0x02
4015 #define V_008F1C_SQ_SEL_RESERVED_1 0x03
4016 #define V_008F1C_SQ_SEL_X 0x04
4017 #define V_008F1C_SQ_SEL_Y 0x05
4018 #define V_008F1C_SQ_SEL_Z 0x06
4019 #define V_008F1C_SQ_SEL_W 0x07
4020 #define S_008F1C_BASE_LEVEL(x) (((x) & 0x0F) << 12)
4021 #define G_008F1C_BASE_LEVEL(x) (((x) >> 12) & 0x0F)
4022 #define C_008F1C_BASE_LEVEL 0xFFFF0FFF
4023 #define S_008F1C_LAST_LEVEL(x) (((x) & 0x0F) << 16)
4024 #define G_008F1C_LAST_LEVEL(x) (((x) >> 16) & 0x0F)
4025 #define C_008F1C_LAST_LEVEL 0xFFF0FFFF
4026 #define S_008F1C_TILING_INDEX(x) (((x) & 0x1F) << 20)
4027 #define G_008F1C_TILING_INDEX(x) (((x) >> 20) & 0x1F)
4028 #define C_008F1C_TILING_INDEX 0xFE0FFFFF
4029 #define S_008F1C_POW2_PAD(x) (((x) & 0x1) << 25)
4030 #define G_008F1C_POW2_PAD(x) (((x) >> 25) & 0x1)
4031 #define C_008F1C_POW2_PAD 0xFDFFFFFF
4032 /* CIK */
4033 #define S_008F1C_MTYPE(x) (((x) & 0x1) << 26)
4034 #define G_008F1C_MTYPE(x) (((x) >> 26) & 0x1)
4035 #define C_008F1C_MTYPE 0xFBFFFFFF
4036 #define S_008F1C_ATC(x) (((x) & 0x1) << 27)
4037 #define G_008F1C_ATC(x) (((x) >> 27) & 0x1)
4038 #define C_008F1C_ATC 0xF7FFFFFF
4039 /* */
4040 #define S_008F1C_TYPE(x) (((x) & 0x0F) << 28)
4041 #define G_008F1C_TYPE(x) (((x) >> 28) & 0x0F)
4042 #define C_008F1C_TYPE 0x0FFFFFFF
4043 #define V_008F1C_SQ_RSRC_IMG_RSVD_0 0x00
4044 #define V_008F1C_SQ_RSRC_IMG_RSVD_1 0x01
4045 #define V_008F1C_SQ_RSRC_IMG_RSVD_2 0x02
4046 #define V_008F1C_SQ_RSRC_IMG_RSVD_3 0x03
4047 #define V_008F1C_SQ_RSRC_IMG_RSVD_4 0x04
4048 #define V_008F1C_SQ_RSRC_IMG_RSVD_5 0x05
4049 #define V_008F1C_SQ_RSRC_IMG_RSVD_6 0x06
4050 #define V_008F1C_SQ_RSRC_IMG_RSVD_7 0x07
4051 #define V_008F1C_SQ_RSRC_IMG_1D 0x08
4052 #define V_008F1C_SQ_RSRC_IMG_2D 0x09
4053 #define V_008F1C_SQ_RSRC_IMG_3D 0x0A
4054 #define V_008F1C_SQ_RSRC_IMG_CUBE 0x0B
4055 #define V_008F1C_SQ_RSRC_IMG_1D_ARRAY 0x0C
4056 #define V_008F1C_SQ_RSRC_IMG_2D_ARRAY 0x0D
4057 #define V_008F1C_SQ_RSRC_IMG_2D_MSAA 0x0E
4058 #define V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY 0x0F
4059 #define R_008F20_SQ_IMG_RSRC_WORD4 0x008F20
4060 #define S_008F20_DEPTH(x) (((x) & 0x1FFF) << 0)
4061 #define G_008F20_DEPTH(x) (((x) >> 0) & 0x1FFF)
4062 #define C_008F20_DEPTH 0xFFFFE000
4063 #define S_008F20_PITCH(x) (((x) & 0x3FFF) << 13)
4064 #define G_008F20_PITCH(x) (((x) >> 13) & 0x3FFF)
4065 #define C_008F20_PITCH 0xF8001FFF
4066 #define R_008F24_SQ_IMG_RSRC_WORD5 0x008F24
4067 #define S_008F24_BASE_ARRAY(x) (((x) & 0x1FFF) << 0)
4068 #define G_008F24_BASE_ARRAY(x) (((x) >> 0) & 0x1FFF)
4069 #define C_008F24_BASE_ARRAY 0xFFFFE000
4070 #define S_008F24_LAST_ARRAY(x) (((x) & 0x1FFF) << 13)
4071 #define G_008F24_LAST_ARRAY(x) (((x) >> 13) & 0x1FFF)
4072 #define C_008F24_LAST_ARRAY 0xFC001FFF
4073 #define R_008F28_SQ_IMG_RSRC_WORD6 0x008F28
4074 #define S_008F28_MIN_LOD_WARN(x) (((x) & 0xFFF) << 0)
4075 #define G_008F28_MIN_LOD_WARN(x) (((x) >> 0) & 0xFFF)
4076 #define C_008F28_MIN_LOD_WARN 0xFFFFF000
4077 /* CIK */
4078 #define S_008F28_COUNTER_BANK_ID(x) (((x) & 0xFF) << 12)
4079 #define G_008F28_COUNTER_BANK_ID(x) (((x) >> 12) & 0xFF)
4080 #define C_008F28_COUNTER_BANK_ID 0xFFF00FFF
4081 #define S_008F28_LOD_HDW_CNT_EN(x) (((x) & 0x1) << 20)
4082 #define G_008F28_LOD_HDW_CNT_EN(x) (((x) >> 20) & 0x1)
4083 #define C_008F28_LOD_HDW_CNT_EN 0xFFEFFFFF
4084 /* */
4085 #define R_008F2C_SQ_IMG_RSRC_WORD7 0x008F2C
4086 #define R_008F30_SQ_IMG_SAMP_WORD0 0x008F30
4087 #define S_008F30_CLAMP_X(x) (((x) & 0x07) << 0)
4088 #define G_008F30_CLAMP_X(x) (((x) >> 0) & 0x07)
4089 #define C_008F30_CLAMP_X 0xFFFFFFF8
4090 #define V_008F30_SQ_TEX_WRAP 0x00
4091 #define V_008F30_SQ_TEX_MIRROR 0x01
4092 #define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02
4093 #define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03
4094 #define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04
4095 #define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05
4096 #define V_008F30_SQ_TEX_CLAMP_BORDER 0x06
4097 #define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07
4098 #define S_008F30_CLAMP_Y(x) (((x) & 0x07) << 3)
4099 #define G_008F30_CLAMP_Y(x) (((x) >> 3) & 0x07)
4100 #define C_008F30_CLAMP_Y 0xFFFFFFC7
4101 #define V_008F30_SQ_TEX_WRAP 0x00
4102 #define V_008F30_SQ_TEX_MIRROR 0x01
4103 #define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02
4104 #define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03
4105 #define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04
4106 #define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05
4107 #define V_008F30_SQ_TEX_CLAMP_BORDER 0x06
4108 #define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07
4109 #define S_008F30_CLAMP_Z(x) (((x) & 0x07) << 6)
4110 #define G_008F30_CLAMP_Z(x) (((x) >> 6) & 0x07)
4111 #define C_008F30_CLAMP_Z 0xFFFFFE3F
4112 #define V_008F30_SQ_TEX_WRAP 0x00
4113 #define V_008F30_SQ_TEX_MIRROR 0x01
4114 #define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02
4115 #define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03
4116 #define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04
4117 #define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05
4118 #define V_008F30_SQ_TEX_CLAMP_BORDER 0x06
4119 #define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07
4120 #define S_008F30_DEPTH_COMPARE_FUNC(x) (((x) & 0x07) << 12)
4121 #define G_008F30_DEPTH_COMPARE_FUNC(x) (((x) >> 12) & 0x07)
4122 #define C_008F30_DEPTH_COMPARE_FUNC 0xFFFF8FFF
4123 #define V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER 0x00
4124 #define V_008F30_SQ_TEX_DEPTH_COMPARE_LESS 0x01
4125 #define V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL 0x02
4126 #define V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL 0x03
4127 #define V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER 0x04
4128 #define V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL 0x05
4129 #define V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL 0x06
4130 #define V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS 0x07
4131 #define S_008F30_FORCE_UNNORMALIZED(x) (((x) & 0x1) << 15)
4132 #define G_008F30_FORCE_UNNORMALIZED(x) (((x) >> 15) & 0x1)
4133 #define C_008F30_FORCE_UNNORMALIZED 0xFFFF7FFF
4134 #define S_008F30_MC_COORD_TRUNC(x) (((x) & 0x1) << 19)
4135 #define G_008F30_MC_COORD_TRUNC(x) (((x) >> 19) & 0x1)
4136 #define C_008F30_MC_COORD_TRUNC 0xFFF7FFFF
4137 #define S_008F30_FORCE_DEGAMMA(x) (((x) & 0x1) << 20)
4138 #define G_008F30_FORCE_DEGAMMA(x) (((x) >> 20) & 0x1)
4139 #define C_008F30_FORCE_DEGAMMA 0xFFEFFFFF
4140 #define S_008F30_TRUNC_COORD(x) (((x) & 0x1) << 27)
4141 #define G_008F30_TRUNC_COORD(x) (((x) >> 27) & 0x1)
4142 #define C_008F30_TRUNC_COORD 0xF7FFFFFF
4143 #define S_008F30_DISABLE_CUBE_WRAP(x) (((x) & 0x1) << 28)
4144 #define G_008F30_DISABLE_CUBE_WRAP(x) (((x) >> 28) & 0x1)
4145 #define C_008F30_DISABLE_CUBE_WRAP 0xEFFFFFFF
4146 #define S_008F30_FILTER_MODE(x) (((x) & 0x03) << 29)
4147 #define G_008F30_FILTER_MODE(x) (((x) >> 29) & 0x03)
4148 #define C_008F30_FILTER_MODE 0x9FFFFFFF
4149 #define R_008F34_SQ_IMG_SAMP_WORD1 0x008F34
4150 #define S_008F34_MIN_LOD(x) (((x) & 0xFFF) << 0)
4151 #define G_008F34_MIN_LOD(x) (((x) >> 0) & 0xFFF)
4152 #define C_008F34_MIN_LOD 0xFFFFF000
4153 #define S_008F34_MAX_LOD(x) (((x) & 0xFFF) << 12)
4154 #define G_008F34_MAX_LOD(x) (((x) >> 12) & 0xFFF)
4155 #define C_008F34_MAX_LOD 0xFF000FFF
4156 #define S_008F34_PERF_MIP(x) (((x) & 0x0F) << 24)
4157 #define G_008F34_PERF_MIP(x) (((x) >> 24) & 0x0F)
4158 #define C_008F34_PERF_MIP 0xF0FFFFFF
4159 #define S_008F34_PERF_Z(x) (((x) & 0x0F) << 28)
4160 #define G_008F34_PERF_Z(x) (((x) >> 28) & 0x0F)
4161 #define C_008F34_PERF_Z 0x0FFFFFFF
4162 #define R_008F38_SQ_IMG_SAMP_WORD2 0x008F38
4163 #define S_008F38_LOD_BIAS(x) (((x) & 0x3FFF) << 0)
4164 #define G_008F38_LOD_BIAS(x) (((x) >> 0) & 0x3FFF)
4165 #define C_008F38_LOD_BIAS 0xFFFFC000
4166 #define S_008F38_LOD_BIAS_SEC(x) (((x) & 0x3F) << 14)
4167 #define G_008F38_LOD_BIAS_SEC(x) (((x) >> 14) & 0x3F)
4168 #define C_008F38_LOD_BIAS_SEC 0xFFF03FFF
4169 #define S_008F38_XY_MAG_FILTER(x) (((x) & 0x03) << 20)
4170 #define G_008F38_XY_MAG_FILTER(x) (((x) >> 20) & 0x03)
4171 #define C_008F38_XY_MAG_FILTER 0xFFCFFFFF
4172 #define V_008F38_SQ_TEX_XY_FILTER_POINT 0x00
4173 #define V_008F38_SQ_TEX_XY_FILTER_BILINEAR 0x01
4174 #define S_008F38_XY_MIN_FILTER(x) (((x) & 0x03) << 22)
4175 #define G_008F38_XY_MIN_FILTER(x) (((x) >> 22) & 0x03)
4176 #define C_008F38_XY_MIN_FILTER 0xFF3FFFFF
4177 #define V_008F38_SQ_TEX_XY_FILTER_POINT 0x00
4178 #define V_008F38_SQ_TEX_XY_FILTER_BILINEAR 0x01
4179 #define S_008F38_Z_FILTER(x) (((x) & 0x03) << 24)
4180 #define G_008F38_Z_FILTER(x) (((x) >> 24) & 0x03)
4181 #define C_008F38_Z_FILTER 0xFCFFFFFF
4182 #define V_008F38_SQ_TEX_Z_FILTER_NONE 0x00
4183 #define V_008F38_SQ_TEX_Z_FILTER_POINT 0x01
4184 #define V_008F38_SQ_TEX_Z_FILTER_LINEAR 0x02
4185 #define S_008F38_MIP_FILTER(x) (((x) & 0x03) << 26)
4186 #define G_008F38_MIP_FILTER(x) (((x) >> 26) & 0x03)
4187 #define C_008F38_MIP_FILTER 0xF3FFFFFF
4188 #define V_008F38_SQ_TEX_Z_FILTER_NONE 0x00
4189 #define V_008F38_SQ_TEX_Z_FILTER_POINT 0x01
4190 #define V_008F38_SQ_TEX_Z_FILTER_LINEAR 0x02
4191 #define S_008F38_MIP_POINT_PRECLAMP(x) (((x) & 0x1) << 28)
4192 #define G_008F38_MIP_POINT_PRECLAMP(x) (((x) >> 28) & 0x1)
4193 #define C_008F38_MIP_POINT_PRECLAMP 0xEFFFFFFF
4194 #define S_008F38_DISABLE_LSB_CEIL(x) (((x) & 0x1) << 29)
4195 #define G_008F38_DISABLE_LSB_CEIL(x) (((x) >> 29) & 0x1)
4196 #define C_008F38_DISABLE_LSB_CEIL 0xDFFFFFFF
4197 #define S_008F38_FILTER_PREC_FIX(x) (((x) & 0x1) << 30)
4198 #define G_008F38_FILTER_PREC_FIX(x) (((x) >> 30) & 0x1)
4199 #define C_008F38_FILTER_PREC_FIX 0xBFFFFFFF
4200 #define R_008F3C_SQ_IMG_SAMP_WORD3 0x008F3C
4201 #define S_008F3C_BORDER_COLOR_PTR(x) (((x) & 0xFFF) << 0)
4202 #define G_008F3C_BORDER_COLOR_PTR(x) (((x) >> 0) & 0xFFF)
4203 #define C_008F3C_BORDER_COLOR_PTR 0xFFFFF000
4204 #define S_008F3C_BORDER_COLOR_TYPE(x) (((x) & 0x03) << 30)
4205 #define G_008F3C_BORDER_COLOR_TYPE(x) (((x) >> 30) & 0x03)
4206 #define C_008F3C_BORDER_COLOR_TYPE 0x3FFFFFFF
4207 #define V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK 0x00
4208 #define V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK 0x01
4209 #define V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE 0x02
4210 #define V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER 0x03
4211 #define R_0090DC_SPI_DYN_GPR_LOCK_EN 0x0090DC /* not on CIK */
4212 #define S_0090DC_VS_LOW_THRESHOLD(x) (((x) & 0x0F) << 0)
4213 #define G_0090DC_VS_LOW_THRESHOLD(x) (((x) >> 0) & 0x0F)
4214 #define C_0090DC_VS_LOW_THRESHOLD 0xFFFFFFF0
4215 #define S_0090DC_GS_LOW_THRESHOLD(x) (((x) & 0x0F) << 4)
4216 #define G_0090DC_GS_LOW_THRESHOLD(x) (((x) >> 4) & 0x0F)
4217 #define C_0090DC_GS_LOW_THRESHOLD 0xFFFFFF0F
4218 #define S_0090DC_ES_LOW_THRESHOLD(x) (((x) & 0x0F) << 8)
4219 #define G_0090DC_ES_LOW_THRESHOLD(x) (((x) >> 8) & 0x0F)
4220 #define C_0090DC_ES_LOW_THRESHOLD 0xFFFFF0FF
4221 #define S_0090DC_HS_LOW_THRESHOLD(x) (((x) & 0x0F) << 12)
4222 #define G_0090DC_HS_LOW_THRESHOLD(x) (((x) >> 12) & 0x0F)
4223 #define C_0090DC_HS_LOW_THRESHOLD 0xFFFF0FFF
4224 #define S_0090DC_LS_LOW_THRESHOLD(x) (((x) & 0x0F) << 16)
4225 #define G_0090DC_LS_LOW_THRESHOLD(x) (((x) >> 16) & 0x0F)
4226 #define C_0090DC_LS_LOW_THRESHOLD 0xFFF0FFFF
4227 #define R_0090E0_SPI_STATIC_THREAD_MGMT_1 0x0090E0 /* not on CIK */
4228 #define S_0090E0_PS_CU_EN(x) (((x) & 0xFFFF) << 0)
4229 #define G_0090E0_PS_CU_EN(x) (((x) >> 0) & 0xFFFF)
4230 #define C_0090E0_PS_CU_EN 0xFFFF0000
4231 #define S_0090E0_VS_CU_EN(x) (((x) & 0xFFFF) << 16)
4232 #define G_0090E0_VS_CU_EN(x) (((x) >> 16) & 0xFFFF)
4233 #define C_0090E0_VS_CU_EN 0x0000FFFF
4234 #define R_0090E4_SPI_STATIC_THREAD_MGMT_2 0x0090E4 /* not on CIK */
4235 #define S_0090E4_GS_CU_EN(x) (((x) & 0xFFFF) << 0)
4236 #define G_0090E4_GS_CU_EN(x) (((x) >> 0) & 0xFFFF)
4237 #define C_0090E4_GS_CU_EN 0xFFFF0000
4238 #define S_0090E4_ES_CU_EN(x) (((x) & 0xFFFF) << 16)
4239 #define G_0090E4_ES_CU_EN(x) (((x) >> 16) & 0xFFFF)
4240 #define C_0090E4_ES_CU_EN 0x0000FFFF
4241 #define R_0090E8_SPI_STATIC_THREAD_MGMT_3 0x0090E8 /* not on CIK */
4242 #define S_0090E8_LSHS_CU_EN(x) (((x) & 0xFFFF) << 0)
4243 #define G_0090E8_LSHS_CU_EN(x) (((x) >> 0) & 0xFFFF)
4244 #define C_0090E8_LSHS_CU_EN 0xFFFF0000
4245 #define R_0090EC_SPI_PS_MAX_WAVE_ID 0x0090EC
4246 #define S_0090EC_MAX_WAVE_ID(x) (((x) & 0xFFF) << 0)
4247 #define G_0090EC_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF)
4248 #define C_0090EC_MAX_WAVE_ID 0xFFFFF000
4249 /* CIK */
4250 #define R_0090E8_SPI_PS_MAX_WAVE_ID 0x0090E8
4251 #define S_0090E8_MAX_WAVE_ID(x) (((x) & 0xFFF) << 0)
4252 #define G_0090E8_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF)
4253 #define C_0090E8_MAX_WAVE_ID 0xFFFFF000
4254 /* */
4255 #define R_0090F0_SPI_ARB_PRIORITY 0x0090F0
4256 #define S_0090F0_RING_ORDER_TS0(x) (((x) & 0x07) << 0)
4257 #define G_0090F0_RING_ORDER_TS0(x) (((x) >> 0) & 0x07)
4258 #define C_0090F0_RING_ORDER_TS0 0xFFFFFFF8
4259 #define V_0090F0_X_R0 0x00
4260 #define S_0090F0_RING_ORDER_TS1(x) (((x) & 0x07) << 3)
4261 #define G_0090F0_RING_ORDER_TS1(x) (((x) >> 3) & 0x07)
4262 #define C_0090F0_RING_ORDER_TS1 0xFFFFFFC7
4263 #define S_0090F0_RING_ORDER_TS2(x) (((x) & 0x07) << 6)
4264 #define G_0090F0_RING_ORDER_TS2(x) (((x) >> 6) & 0x07)
4265 #define C_0090F0_RING_ORDER_TS2 0xFFFFFE3F
4266 /* CIK */
4267 #define R_00C700_SPI_ARB_PRIORITY 0x00C700
4268 #define S_00C700_PIPE_ORDER_TS0(x) (((x) & 0x07) << 0)
4269 #define G_00C700_PIPE_ORDER_TS0(x) (((x) >> 0) & 0x07)
4270 #define C_00C700_PIPE_ORDER_TS0 0xFFFFFFF8
4271 #define S_00C700_PIPE_ORDER_TS1(x) (((x) & 0x07) << 3)
4272 #define G_00C700_PIPE_ORDER_TS1(x) (((x) >> 3) & 0x07)
4273 #define C_00C700_PIPE_ORDER_TS1 0xFFFFFFC7
4274 #define S_00C700_PIPE_ORDER_TS2(x) (((x) & 0x07) << 6)
4275 #define G_00C700_PIPE_ORDER_TS2(x) (((x) >> 6) & 0x07)
4276 #define C_00C700_PIPE_ORDER_TS2 0xFFFFFE3F
4277 #define S_00C700_PIPE_ORDER_TS3(x) (((x) & 0x07) << 9)
4278 #define G_00C700_PIPE_ORDER_TS3(x) (((x) >> 9) & 0x07)
4279 #define C_00C700_PIPE_ORDER_TS3 0xFFFFF1FF
4280 #define S_00C700_TS0_DUR_MULT(x) (((x) & 0x03) << 12)
4281 #define G_00C700_TS0_DUR_MULT(x) (((x) >> 12) & 0x03)
4282 #define C_00C700_TS0_DUR_MULT 0xFFFFCFFF
4283 #define S_00C700_TS1_DUR_MULT(x) (((x) & 0x03) << 14)
4284 #define G_00C700_TS1_DUR_MULT(x) (((x) >> 14) & 0x03)
4285 #define C_00C700_TS1_DUR_MULT 0xFFFF3FFF
4286 #define S_00C700_TS2_DUR_MULT(x) (((x) & 0x03) << 16)
4287 #define G_00C700_TS2_DUR_MULT(x) (((x) >> 16) & 0x03)
4288 #define C_00C700_TS2_DUR_MULT 0xFFFCFFFF
4289 #define S_00C700_TS3_DUR_MULT(x) (((x) & 0x03) << 18)
4290 #define G_00C700_TS3_DUR_MULT(x) (((x) >> 18) & 0x03)
4291 #define C_00C700_TS3_DUR_MULT 0xFFF3FFFF
4292 /* */
4293 #define R_0090F4_SPI_ARB_CYCLES_0 0x0090F4 /* moved to 0xC704 on CIK */
4294 #define S_0090F4_TS0_DURATION(x) (((x) & 0xFFFF) << 0)
4295 #define G_0090F4_TS0_DURATION(x) (((x) >> 0) & 0xFFFF)
4296 #define C_0090F4_TS0_DURATION 0xFFFF0000
4297 #define S_0090F4_TS1_DURATION(x) (((x) & 0xFFFF) << 16)
4298 #define G_0090F4_TS1_DURATION(x) (((x) >> 16) & 0xFFFF)
4299 #define C_0090F4_TS1_DURATION 0x0000FFFF
4300 #define R_0090F8_SPI_ARB_CYCLES_1 0x0090F8 /* moved to 0xC708 on CIK */
4301 #define S_0090F8_TS2_DURATION(x) (((x) & 0xFFFF) << 0)
4302 #define G_0090F8_TS2_DURATION(x) (((x) >> 0) & 0xFFFF)
4303 #define C_0090F8_TS2_DURATION 0xFFFF0000
4304 /* CIK */
4305 #define R_008F40_SQ_FLAT_SCRATCH_WORD0 0x008F40
4306 #define S_008F40_SIZE(x) (((x) & 0x7FFFF) << 0)
4307 #define G_008F40_SIZE(x) (((x) >> 0) & 0x7FFFF)
4308 #define C_008F40_SIZE 0xFFF80000
4309 #define R_008F44_SQ_FLAT_SCRATCH_WORD1 0x008F44
4310 #define S_008F44_OFFSET(x) (((x) & 0xFFFFFF) << 0)
4311 #define G_008F44_OFFSET(x) (((x) >> 0) & 0xFFFFFF)
4312 #define C_008F44_OFFSET 0xFF000000
4313 /* */
4314 #define R_009100_SPI_CONFIG_CNTL 0x009100
4315 #define S_009100_GPR_WRITE_PRIORITY(x) (((x) & 0x1FFFFF) << 0)
4316 #define G_009100_GPR_WRITE_PRIORITY(x) (((x) >> 0) & 0x1FFFFF)
4317 #define C_009100_GPR_WRITE_PRIORITY 0xFFE00000
4318 #define S_009100_EXP_PRIORITY_ORDER(x) (((x) & 0x07) << 21)
4319 #define G_009100_EXP_PRIORITY_ORDER(x) (((x) >> 21) & 0x07)
4320 #define C_009100_EXP_PRIORITY_ORDER 0xFF1FFFFF
4321 #define S_009100_ENABLE_SQG_TOP_EVENTS(x) (((x) & 0x1) << 24)
4322 #define G_009100_ENABLE_SQG_TOP_EVENTS(x) (((x) >> 24) & 0x1)
4323 #define C_009100_ENABLE_SQG_TOP_EVENTS 0xFEFFFFFF
4324 #define S_009100_ENABLE_SQG_BOP_EVENTS(x) (((x) & 0x1) << 25)
4325 #define G_009100_ENABLE_SQG_BOP_EVENTS(x) (((x) >> 25) & 0x1)
4326 #define C_009100_ENABLE_SQG_BOP_EVENTS 0xFDFFFFFF
4327 #define S_009100_RSRC_MGMT_RESET(x) (((x) & 0x1) << 26)
4328 #define G_009100_RSRC_MGMT_RESET(x) (((x) >> 26) & 0x1)
4329 #define C_009100_RSRC_MGMT_RESET 0xFBFFFFFF
4330 #define R_00913C_SPI_CONFIG_CNTL_1 0x00913C
4331 #define S_00913C_VTX_DONE_DELAY(x) (((x) & 0x0F) << 0)
4332 #define G_00913C_VTX_DONE_DELAY(x) (((x) >> 0) & 0x0F)
4333 #define C_00913C_VTX_DONE_DELAY 0xFFFFFFF0
4334 #define V_00913C_X_DELAY_14_CLKS 0x00
4335 #define V_00913C_X_DELAY_16_CLKS 0x01
4336 #define V_00913C_X_DELAY_18_CLKS 0x02
4337 #define V_00913C_X_DELAY_20_CLKS 0x03
4338 #define V_00913C_X_DELAY_22_CLKS 0x04
4339 #define V_00913C_X_DELAY_24_CLKS 0x05
4340 #define V_00913C_X_DELAY_26_CLKS 0x06
4341 #define V_00913C_X_DELAY_28_CLKS 0x07
4342 #define V_00913C_X_DELAY_30_CLKS 0x08
4343 #define V_00913C_X_DELAY_32_CLKS 0x09
4344 #define V_00913C_X_DELAY_34_CLKS 0x0A
4345 #define V_00913C_X_DELAY_4_CLKS 0x0B
4346 #define V_00913C_X_DELAY_6_CLKS 0x0C
4347 #define V_00913C_X_DELAY_8_CLKS 0x0D
4348 #define V_00913C_X_DELAY_10_CLKS 0x0E
4349 #define V_00913C_X_DELAY_12_CLKS 0x0F
4350 #define S_00913C_INTERP_ONE_PRIM_PER_ROW(x) (((x) & 0x1) << 4)
4351 #define G_00913C_INTERP_ONE_PRIM_PER_ROW(x) (((x) >> 4) & 0x1)
4352 #define C_00913C_INTERP_ONE_PRIM_PER_ROW 0xFFFFFFEF
4353 #define S_00913C_PC_LIMIT_ENABLE(x) (((x) & 0x1) << 6)
4354 #define G_00913C_PC_LIMIT_ENABLE(x) (((x) >> 6) & 0x1)
4355 #define C_00913C_PC_LIMIT_ENABLE 0xFFFFFFBF
4356 #define S_00913C_PC_LIMIT_STRICT(x) (((x) & 0x1) << 7)
4357 #define G_00913C_PC_LIMIT_STRICT(x) (((x) >> 7) & 0x1)
4358 #define C_00913C_PC_LIMIT_STRICT 0xFFFFFF7F
4359 #define S_00913C_PC_LIMIT_SIZE(x) (((x) & 0xFFFF) << 16)
4360 #define G_00913C_PC_LIMIT_SIZE(x) (((x) >> 16) & 0xFFFF)
4361 #define C_00913C_PC_LIMIT_SIZE 0x0000FFFF
4362 #define R_00936C_SPI_RESOURCE_RESERVE_CU_AB_0 0x00936C
4363 #define S_00936C_TYPE_A(x) (((x) & 0x0F) << 0)
4364 #define G_00936C_TYPE_A(x) (((x) >> 0) & 0x0F)
4365 #define C_00936C_TYPE_A 0xFFFFFFF0
4366 #define S_00936C_VGPR_A(x) (((x) & 0x07) << 4)
4367 #define G_00936C_VGPR_A(x) (((x) >> 4) & 0x07)
4368 #define C_00936C_VGPR_A 0xFFFFFF8F
4369 #define S_00936C_SGPR_A(x) (((x) & 0x07) << 7)
4370 #define G_00936C_SGPR_A(x) (((x) >> 7) & 0x07)
4371 #define C_00936C_SGPR_A 0xFFFFFC7F
4372 #define S_00936C_LDS_A(x) (((x) & 0x07) << 10)
4373 #define G_00936C_LDS_A(x) (((x) >> 10) & 0x07)
4374 #define C_00936C_LDS_A 0xFFFFE3FF
4375 #define S_00936C_WAVES_A(x) (((x) & 0x03) << 13)
4376 #define G_00936C_WAVES_A(x) (((x) >> 13) & 0x03)
4377 #define C_00936C_WAVES_A 0xFFFF9FFF
4378 #define S_00936C_EN_A(x) (((x) & 0x1) << 15)
4379 #define G_00936C_EN_A(x) (((x) >> 15) & 0x1)
4380 #define C_00936C_EN_A 0xFFFF7FFF
4381 #define S_00936C_TYPE_B(x) (((x) & 0x0F) << 16)
4382 #define G_00936C_TYPE_B(x) (((x) >> 16) & 0x0F)
4383 #define C_00936C_TYPE_B 0xFFF0FFFF
4384 #define S_00936C_VGPR_B(x) (((x) & 0x07) << 20)
4385 #define G_00936C_VGPR_B(x) (((x) >> 20) & 0x07)
4386 #define C_00936C_VGPR_B 0xFF8FFFFF
4387 #define S_00936C_SGPR_B(x) (((x) & 0x07) << 23)
4388 #define G_00936C_SGPR_B(x) (((x) >> 23) & 0x07)
4389 #define C_00936C_SGPR_B 0xFC7FFFFF
4390 #define S_00936C_LDS_B(x) (((x) & 0x07) << 26)
4391 #define G_00936C_LDS_B(x) (((x) >> 26) & 0x07)
4392 #define C_00936C_LDS_B 0xE3FFFFFF
4393 #define S_00936C_WAVES_B(x) (((x) & 0x03) << 29)
4394 #define G_00936C_WAVES_B(x) (((x) >> 29) & 0x03)
4395 #define C_00936C_WAVES_B 0x9FFFFFFF
4396 #define S_00936C_EN_B(x) (((x) & 0x1) << 31)
4397 #define G_00936C_EN_B(x) (((x) >> 31) & 0x1)
4398 #define C_00936C_EN_B 0x7FFFFFFF
4399 #define R_00950C_TA_CS_BC_BASE_ADDR 0x00950C
4400 /* CIK */
4401 #define R_030E00_TA_CS_BC_BASE_ADDR 0x030E00
4402 #define R_030E04_TA_CS_BC_BASE_ADDR_HI 0x030E04
4403 #define S_030E04_ADDRESS(x) (((x) & 0xFF) << 0)
4404 #define G_030E04_ADDRESS(x) (((x) >> 0) & 0xFF)
4405 #define C_030E04_ADDRESS 0xFFFFFF00
4406 /* */
4407 #define R_009858_DB_SUBTILE_CONTROL 0x009858
4408 #define S_009858_MSAA1_X(x) (((x) & 0x03) << 0)
4409 #define G_009858_MSAA1_X(x) (((x) >> 0) & 0x03)
4410 #define C_009858_MSAA1_X 0xFFFFFFFC
4411 #define S_009858_MSAA1_Y(x) (((x) & 0x03) << 2)
4412 #define G_009858_MSAA1_Y(x) (((x) >> 2) & 0x03)
4413 #define C_009858_MSAA1_Y 0xFFFFFFF3
4414 #define S_009858_MSAA2_X(x) (((x) & 0x03) << 4)
4415 #define G_009858_MSAA2_X(x) (((x) >> 4) & 0x03)
4416 #define C_009858_MSAA2_X 0xFFFFFFCF
4417 #define S_009858_MSAA2_Y(x) (((x) & 0x03) << 6)
4418 #define G_009858_MSAA2_Y(x) (((x) >> 6) & 0x03)
4419 #define C_009858_MSAA2_Y 0xFFFFFF3F
4420 #define S_009858_MSAA4_X(x) (((x) & 0x03) << 8)
4421 #define G_009858_MSAA4_X(x) (((x) >> 8) & 0x03)
4422 #define C_009858_MSAA4_X 0xFFFFFCFF
4423 #define S_009858_MSAA4_Y(x) (((x) & 0x03) << 10)
4424 #define G_009858_MSAA4_Y(x) (((x) >> 10) & 0x03)
4425 #define C_009858_MSAA4_Y 0xFFFFF3FF
4426 #define S_009858_MSAA8_X(x) (((x) & 0x03) << 12)
4427 #define G_009858_MSAA8_X(x) (((x) >> 12) & 0x03)
4428 #define C_009858_MSAA8_X 0xFFFFCFFF
4429 #define S_009858_MSAA8_Y(x) (((x) & 0x03) << 14)
4430 #define G_009858_MSAA8_Y(x) (((x) >> 14) & 0x03)
4431 #define C_009858_MSAA8_Y 0xFFFF3FFF
4432 #define S_009858_MSAA16_X(x) (((x) & 0x03) << 16)
4433 #define G_009858_MSAA16_X(x) (((x) >> 16) & 0x03)
4434 #define C_009858_MSAA16_X 0xFFFCFFFF
4435 #define S_009858_MSAA16_Y(x) (((x) & 0x03) << 18)
4436 #define G_009858_MSAA16_Y(x) (((x) >> 18) & 0x03)
4437 #define C_009858_MSAA16_Y 0xFFF3FFFF
4438 #define R_009910_GB_TILE_MODE0 0x009910
4439 #define S_009910_MICRO_TILE_MODE(x) (((x) & 0x03) << 0)
4440 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
4441 #define C_009910_MICRO_TILE_MODE 0xFFFFFFFC
4442 #define V_009910_ADDR_SURF_DISPLAY_MICRO_TILING 0x00
4443 #define V_009910_ADDR_SURF_THIN_MICRO_TILING 0x01
4444 #define V_009910_ADDR_SURF_DEPTH_MICRO_TILING 0x02
4445 #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
4446 #define S_009910_ARRAY_MODE(x) (((x) & 0x0F) << 2)
4447 #define G_009910_ARRAY_MODE(x) (((x) >> 2) & 0x0F)
4448 #define C_009910_ARRAY_MODE 0xFFFFFFC3
4449 #define V_009910_ARRAY_LINEAR_GENERAL 0x00
4450 #define V_009910_ARRAY_LINEAR_ALIGNED 0x01
4451 #define V_009910_ARRAY_1D_TILED_THIN1 0x02
4452 #define V_009910_ARRAY_1D_TILED_THICK 0x03
4453 #define V_009910_ARRAY_2D_TILED_THIN1 0x04
4454 #define V_009910_ARRAY_2D_TILED_THICK 0x07
4455 #define V_009910_ARRAY_2D_TILED_XTHICK 0x08
4456 #define V_009910_ARRAY_3D_TILED_THIN1 0x0C
4457 #define V_009910_ARRAY_3D_TILED_THICK 0x0D
4458 #define V_009910_ARRAY_3D_TILED_XTHICK 0x0E
4459 #define V_009910_ARRAY_POWER_SAVE 0x0F
4460 #define S_009910_PIPE_CONFIG(x) (((x) & 0x1F) << 6)
4461 #define G_009910_PIPE_CONFIG(x) (((x) >> 6) & 0x1F)
4462 #define C_009910_PIPE_CONFIG 0xFFFFF83F
4463 #define V_009910_ADDR_SURF_P2 0x00
4464 #define V_009910_ADDR_SURF_P2_RESERVED0 0x01
4465 #define V_009910_ADDR_SURF_P2_RESERVED1 0x02
4466 #define V_009910_ADDR_SURF_P2_RESERVED2 0x03
4467 #define V_009910_X_ADDR_SURF_P4_8X16 0x04
4468 #define V_009910_X_ADDR_SURF_P4_16X16 0x05
4469 #define V_009910_X_ADDR_SURF_P4_16X32 0x06
4470 #define V_009910_X_ADDR_SURF_P4_32X32 0x07
4471 #define V_009910_X_ADDR_SURF_P8_16X16_8X16 0x08
4472 #define V_009910_X_ADDR_SURF_P8_16X32_8X16 0x09
4473 #define V_009910_X_ADDR_SURF_P8_32X32_8X16 0x0A
4474 #define V_009910_X_ADDR_SURF_P8_16X32_16X16 0x0B
4475 #define V_009910_X_ADDR_SURF_P8_32X32_16X16 0x0C
4476 #define V_009910_X_ADDR_SURF_P8_32X32_16X32 0x0D
4477 #define V_009910_X_ADDR_SURF_P8_32X64_32X32 0x0E
4478 #define S_009910_TILE_SPLIT(x) (((x) & 0x07) << 11)
4479 #define G_009910_TILE_SPLIT(x) (((x) >> 11) & 0x07)
4480 #define C_009910_TILE_SPLIT 0xFFFFC7FF
4481 #define V_009910_ADDR_SURF_TILE_SPLIT_64B 0x00
4482 #define V_009910_ADDR_SURF_TILE_SPLIT_128B 0x01
4483 #define V_009910_ADDR_SURF_TILE_SPLIT_256B 0x02
4484 #define V_009910_ADDR_SURF_TILE_SPLIT_512B 0x03
4485 #define V_009910_ADDR_SURF_TILE_SPLIT_1KB 0x04
4486 #define V_009910_ADDR_SURF_TILE_SPLIT_2KB 0x05
4487 #define V_009910_ADDR_SURF_TILE_SPLIT_4KB 0x06
4488 #define S_009910_BANK_WIDTH(x) (((x) & 0x03) << 14)
4489 #define G_009910_BANK_WIDTH(x) (((x) >> 14) & 0x03)
4490 #define C_009910_BANK_WIDTH 0xFFFF3FFF
4491 #define V_009910_ADDR_SURF_BANK_WIDTH_1 0x00
4492 #define V_009910_ADDR_SURF_BANK_WIDTH_2 0x01
4493 #define V_009910_ADDR_SURF_BANK_WIDTH_4 0x02
4494 #define V_009910_ADDR_SURF_BANK_WIDTH_8 0x03
4495 #define S_009910_BANK_HEIGHT(x) (((x) & 0x03) << 16)
4496 #define G_009910_BANK_HEIGHT(x) (((x) >> 16) & 0x03)
4497 #define C_009910_BANK_HEIGHT 0xFFFCFFFF
4498 #define V_009910_ADDR_SURF_BANK_HEIGHT_1 0x00
4499 #define V_009910_ADDR_SURF_BANK_HEIGHT_2 0x01
4500 #define V_009910_ADDR_SURF_BANK_HEIGHT_4 0x02
4501 #define V_009910_ADDR_SURF_BANK_HEIGHT_8 0x03
4502 #define S_009910_MACRO_TILE_ASPECT(x) (((x) & 0x03) << 18)
4503 #define G_009910_MACRO_TILE_ASPECT(x) (((x) >> 18) & 0x03)
4504 #define C_009910_MACRO_TILE_ASPECT 0xFFF3FFFF
4505 #define V_009910_ADDR_SURF_MACRO_ASPECT_1 0x00
4506 #define V_009910_ADDR_SURF_MACRO_ASPECT_2 0x01
4507 #define V_009910_ADDR_SURF_MACRO_ASPECT_4 0x02
4508 #define V_009910_ADDR_SURF_MACRO_ASPECT_8 0x03
4509 #define S_009910_NUM_BANKS(x) (((x) & 0x03) << 20)
4510 #define G_009910_NUM_BANKS(x) (((x) >> 20) & 0x03)
4511 #define C_009910_NUM_BANKS 0xFFCFFFFF
4512 #define V_009910_ADDR_SURF_2_BANK 0x00
4513 #define V_009910_ADDR_SURF_4_BANK 0x01
4514 #define V_009910_ADDR_SURF_8_BANK 0x02
4515 #define V_009910_ADDR_SURF_16_BANK 0x03
4516 /* CIK */
4517 #define R_00B01C_SPI_SHADER_PGM_RSRC3_PS 0x00B01C
4518 #define S_00B01C_CU_EN(x) (((x) & 0xFFFF) << 0)
4519 #define G_00B01C_CU_EN(x) (((x) >> 0) & 0xFFFF)
4520 #define C_00B01C_CU_EN 0xFFFF0000
4521 #define S_00B01C_WAVE_LIMIT(x) (((x) & 0x3F) << 16)
4522 #define G_00B01C_WAVE_LIMIT(x) (((x) >> 16) & 0x3F)
4523 #define C_00B01C_WAVE_LIMIT 0xFFC0FFFF
4524 #define S_00B01C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22)
4525 #define G_00B01C_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F)
4526 #define C_00B01C_LOCK_LOW_THRESHOLD 0xFC3FFFFF
4527 /* */
4528 #define R_00B020_SPI_SHADER_PGM_LO_PS 0x00B020
4529 #define R_00B024_SPI_SHADER_PGM_HI_PS 0x00B024
4530 #define S_00B024_MEM_BASE(x) (((x) & 0xFF) << 0)
4531 #define G_00B024_MEM_BASE(x) (((x) >> 0) & 0xFF)
4532 #define C_00B024_MEM_BASE 0xFFFFFF00
4533 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
4534 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
4535 #define G_00B028_VGPRS(x) (((x) >> 0) & 0x3F)
4536 #define C_00B028_VGPRS 0xFFFFFFC0
4537 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
4538 #define G_00B028_SGPRS(x) (((x) >> 6) & 0x0F)
4539 #define C_00B028_SGPRS 0xFFFFFC3F
4540 #define S_00B028_PRIORITY(x) (((x) & 0x03) << 10)
4541 #define G_00B028_PRIORITY(x) (((x) >> 10) & 0x03)
4542 #define C_00B028_PRIORITY 0xFFFFF3FF
4543 #define S_00B028_FLOAT_MODE(x) (((x) & 0xFF) << 12)
4544 #define G_00B028_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
4545 #define C_00B028_FLOAT_MODE 0xFFF00FFF
4546 #define S_00B028_PRIV(x) (((x) & 0x1) << 20)
4547 #define G_00B028_PRIV(x) (((x) >> 20) & 0x1)
4548 #define C_00B028_PRIV 0xFFEFFFFF
4549 #define S_00B028_DX10_CLAMP(x) (((x) & 0x1) << 21)
4550 #define G_00B028_DX10_CLAMP(x) (((x) >> 21) & 0x1)
4551 #define C_00B028_DX10_CLAMP 0xFFDFFFFF
4552 #define S_00B028_DEBUG_MODE(x) (((x) & 0x1) << 22)
4553 #define G_00B028_DEBUG_MODE(x) (((x) >> 22) & 0x1)
4554 #define C_00B028_DEBUG_MODE 0xFFBFFFFF
4555 #define S_00B028_IEEE_MODE(x) (((x) & 0x1) << 23)
4556 #define G_00B028_IEEE_MODE(x) (((x) >> 23) & 0x1)
4557 #define C_00B028_IEEE_MODE 0xFF7FFFFF
4558 #define S_00B028_CU_GROUP_DISABLE(x) (((x) & 0x1) << 24)
4559 #define G_00B028_CU_GROUP_DISABLE(x) (((x) >> 24) & 0x1)
4560 #define C_00B028_CU_GROUP_DISABLE 0xFEFFFFFF
4561 /* CIK */
4562 #define S_00B028_CACHE_CTL(x) (((x) & 0x07) << 25)
4563 #define G_00B028_CACHE_CTL(x) (((x) >> 25) & 0x07)
4564 #define C_00B028_CACHE_CTL 0xF1FFFFFF
4565 #define S_00B028_CDBG_USER(x) (((x) & 0x1) << 28)
4566 #define G_00B028_CDBG_USER(x) (((x) >> 28) & 0x1)
4567 #define C_00B028_CDBG_USER 0xEFFFFFFF
4568 /* */
4569 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
4570 #define S_00B02C_SCRATCH_EN(x) (((x) & 0x1) << 0)
4571 #define G_00B02C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
4572 #define C_00B02C_SCRATCH_EN 0xFFFFFFFE
4573 #define S_00B02C_USER_SGPR(x) (((x) & 0x1F) << 1)
4574 #define G_00B02C_USER_SGPR(x) (((x) >> 1) & 0x1F)
4575 #define C_00B02C_USER_SGPR 0xFFFFFFC1
4576 #define S_00B02C_WAVE_CNT_EN(x) (((x) & 0x1) << 7)
4577 #define G_00B02C_WAVE_CNT_EN(x) (((x) >> 7) & 0x1)
4578 #define C_00B02C_WAVE_CNT_EN 0xFFFFFF7F
4579 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
4580 #define G_00B02C_EXTRA_LDS_SIZE(x) (((x) >> 8) & 0xFF)
4581 #define C_00B02C_EXTRA_LDS_SIZE 0xFFFF00FF
4582 #define S_00B02C_EXCP_EN(x) (((x) & 0x7F) << 16) /* mask is 0x1FF on CIK */
4583 #define G_00B02C_EXCP_EN(x) (((x) >> 16) & 0x7F) /* mask is 0x1FF on CIK */
4584 #define C_00B02C_EXCP_EN 0xFF80FFFF /* mask is 0x1FF on CIK */
4585 #define R_00B030_SPI_SHADER_USER_DATA_PS_0 0x00B030
4586 #define R_00B034_SPI_SHADER_USER_DATA_PS_1 0x00B034
4587 #define R_00B038_SPI_SHADER_USER_DATA_PS_2 0x00B038
4588 #define R_00B03C_SPI_SHADER_USER_DATA_PS_3 0x00B03C
4589 #define R_00B040_SPI_SHADER_USER_DATA_PS_4 0x00B040
4590 #define R_00B044_SPI_SHADER_USER_DATA_PS_5 0x00B044
4591 #define R_00B048_SPI_SHADER_USER_DATA_PS_6 0x00B048
4592 #define R_00B04C_SPI_SHADER_USER_DATA_PS_7 0x00B04C
4593 #define R_00B050_SPI_SHADER_USER_DATA_PS_8 0x00B050
4594 #define R_00B054_SPI_SHADER_USER_DATA_PS_9 0x00B054
4595 #define R_00B058_SPI_SHADER_USER_DATA_PS_10 0x00B058
4596 #define R_00B05C_SPI_SHADER_USER_DATA_PS_11 0x00B05C
4597 #define R_00B060_SPI_SHADER_USER_DATA_PS_12 0x00B060
4598 #define R_00B064_SPI_SHADER_USER_DATA_PS_13 0x00B064
4599 #define R_00B068_SPI_SHADER_USER_DATA_PS_14 0x00B068
4600 #define R_00B06C_SPI_SHADER_USER_DATA_PS_15 0x00B06C
4601 /* CIK */
4602 #define R_00B118_SPI_SHADER_PGM_RSRC3_VS 0x00B118
4603 #define S_00B118_CU_EN(x) (((x) & 0xFFFF) << 0)
4604 #define G_00B118_CU_EN(x) (((x) >> 0) & 0xFFFF)
4605 #define C_00B118_CU_EN 0xFFFF0000
4606 #define S_00B118_WAVE_LIMIT(x) (((x) & 0x3F) << 16)
4607 #define G_00B118_WAVE_LIMIT(x) (((x) >> 16) & 0x3F)
4608 #define C_00B118_WAVE_LIMIT 0xFFC0FFFF
4609 #define S_00B118_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22)
4610 #define G_00B118_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F)
4611 #define C_00B118_LOCK_LOW_THRESHOLD 0xFC3FFFFF
4612 #define R_00B11C_SPI_SHADER_LATE_ALLOC_VS 0x00B11C
4613 #define S_00B11C_LIMIT(x) (((x) & 0x3F) << 0)
4614 #define G_00B11C_LIMIT(x) (((x) >> 0) & 0x3F)
4615 #define C_00B11C_LIMIT 0xFFFFFFC0
4616 /* */
4617 #define R_00B120_SPI_SHADER_PGM_LO_VS 0x00B120
4618 #define R_00B124_SPI_SHADER_PGM_HI_VS 0x00B124
4619 #define S_00B124_MEM_BASE(x) (((x) & 0xFF) << 0)
4620 #define G_00B124_MEM_BASE(x) (((x) >> 0) & 0xFF)
4621 #define C_00B124_MEM_BASE 0xFFFFFF00
4622 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
4623 #define S_00B128_VGPRS(x) (((x) & 0x3F) << 0)
4624 #define G_00B128_VGPRS(x) (((x) >> 0) & 0x3F)
4625 #define C_00B128_VGPRS 0xFFFFFFC0
4626 #define S_00B128_SGPRS(x) (((x) & 0x0F) << 6)
4627 #define G_00B128_SGPRS(x) (((x) >> 6) & 0x0F)
4628 #define C_00B128_SGPRS 0xFFFFFC3F
4629 #define S_00B128_PRIORITY(x) (((x) & 0x03) << 10)
4630 #define G_00B128_PRIORITY(x) (((x) >> 10) & 0x03)
4631 #define C_00B128_PRIORITY 0xFFFFF3FF
4632 #define S_00B128_FLOAT_MODE(x) (((x) & 0xFF) << 12)
4633 #define G_00B128_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
4634 #define C_00B128_FLOAT_MODE 0xFFF00FFF
4635 #define S_00B128_PRIV(x) (((x) & 0x1) << 20)
4636 #define G_00B128_PRIV(x) (((x) >> 20) & 0x1)
4637 #define C_00B128_PRIV 0xFFEFFFFF
4638 #define S_00B128_DX10_CLAMP(x) (((x) & 0x1) << 21)
4639 #define G_00B128_DX10_CLAMP(x) (((x) >> 21) & 0x1)
4640 #define C_00B128_DX10_CLAMP 0xFFDFFFFF
4641 #define S_00B128_DEBUG_MODE(x) (((x) & 0x1) << 22)
4642 #define G_00B128_DEBUG_MODE(x) (((x) >> 22) & 0x1)
4643 #define C_00B128_DEBUG_MODE 0xFFBFFFFF
4644 #define S_00B128_IEEE_MODE(x) (((x) & 0x1) << 23)
4645 #define G_00B128_IEEE_MODE(x) (((x) >> 23) & 0x1)
4646 #define C_00B128_IEEE_MODE 0xFF7FFFFF
4647 #define S_00B128_VGPR_COMP_CNT(x) (((x) & 0x03) << 24)
4648 #define G_00B128_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03)
4649 #define C_00B128_VGPR_COMP_CNT 0xFCFFFFFF
4650 #define S_00B128_CU_GROUP_ENABLE(x) (((x) & 0x1) << 26)
4651 #define G_00B128_CU_GROUP_ENABLE(x) (((x) >> 26) & 0x1)
4652 #define C_00B128_CU_GROUP_ENABLE 0xFBFFFFFF
4653 /* CIK */
4654 #define S_00B128_CACHE_CTL(x) (((x) & 0x07) << 27)
4655 #define G_00B128_CACHE_CTL(x) (((x) >> 27) & 0x07)
4656 #define C_00B128_CACHE_CTL 0xC7FFFFFF
4657 #define S_00B128_CDBG_USER(x) (((x) & 0x1) << 30)
4658 #define G_00B128_CDBG_USER(x) (((x) >> 30) & 0x1)
4659 #define C_00B128_CDBG_USER 0xBFFFFFFF
4660 /* */
4661 #define R_00B12C_SPI_SHADER_PGM_RSRC2_VS 0x00B12C
4662 #define S_00B12C_SCRATCH_EN(x) (((x) & 0x1) << 0)
4663 #define G_00B12C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
4664 #define C_00B12C_SCRATCH_EN 0xFFFFFFFE
4665 #define S_00B12C_USER_SGPR(x) (((x) & 0x1F) << 1)
4666 #define G_00B12C_USER_SGPR(x) (((x) >> 1) & 0x1F)
4667 #define C_00B12C_USER_SGPR 0xFFFFFFC1
4668 #define S_00B12C_OC_LDS_EN(x) (((x) & 0x1) << 7)
4669 #define G_00B12C_OC_LDS_EN(x) (((x) >> 7) & 0x1)
4670 #define C_00B12C_OC_LDS_EN 0xFFFFFF7F
4671 #define S_00B12C_SO_BASE0_EN(x) (((x) & 0x1) << 8)
4672 #define G_00B12C_SO_BASE0_EN(x) (((x) >> 8) & 0x1)
4673 #define C_00B12C_SO_BASE0_EN 0xFFFFFEFF
4674 #define S_00B12C_SO_BASE1_EN(x) (((x) & 0x1) << 9)
4675 #define G_00B12C_SO_BASE1_EN(x) (((x) >> 9) & 0x1)
4676 #define C_00B12C_SO_BASE1_EN 0xFFFFFDFF
4677 #define S_00B12C_SO_BASE2_EN(x) (((x) & 0x1) << 10)
4678 #define G_00B12C_SO_BASE2_EN(x) (((x) >> 10) & 0x1)
4679 #define C_00B12C_SO_BASE2_EN 0xFFFFFBFF
4680 #define S_00B12C_SO_BASE3_EN(x) (((x) & 0x1) << 11)
4681 #define G_00B12C_SO_BASE3_EN(x) (((x) >> 11) & 0x1)
4682 #define C_00B12C_SO_BASE3_EN 0xFFFFF7FF
4683 #define S_00B12C_SO_EN(x) (((x) & 0x1) << 12)
4684 #define G_00B12C_SO_EN(x) (((x) >> 12) & 0x1)
4685 #define C_00B12C_SO_EN 0xFFFFEFFF
4686 #define S_00B12C_EXCP_EN(x) (((x) & 0x7F) << 13) /* mask is 0x1FF on CIK */
4687 #define G_00B12C_EXCP_EN(x) (((x) >> 13) & 0x7F) /* mask is 0x1FF on CIK */
4688 #define C_00B12C_EXCP_EN 0xFFF01FFF /* mask is 0x1FF on CIK */
4689 #define R_00B130_SPI_SHADER_USER_DATA_VS_0 0x00B130
4690 #define R_00B134_SPI_SHADER_USER_DATA_VS_1 0x00B134
4691 #define R_00B138_SPI_SHADER_USER_DATA_VS_2 0x00B138
4692 #define R_00B13C_SPI_SHADER_USER_DATA_VS_3 0x00B13C
4693 #define R_00B140_SPI_SHADER_USER_DATA_VS_4 0x00B140
4694 #define R_00B144_SPI_SHADER_USER_DATA_VS_5 0x00B144
4695 #define R_00B148_SPI_SHADER_USER_DATA_VS_6 0x00B148
4696 #define R_00B14C_SPI_SHADER_USER_DATA_VS_7 0x00B14C
4697 #define R_00B150_SPI_SHADER_USER_DATA_VS_8 0x00B150
4698 #define R_00B154_SPI_SHADER_USER_DATA_VS_9 0x00B154
4699 #define R_00B158_SPI_SHADER_USER_DATA_VS_10 0x00B158
4700 #define R_00B15C_SPI_SHADER_USER_DATA_VS_11 0x00B15C
4701 #define R_00B160_SPI_SHADER_USER_DATA_VS_12 0x00B160
4702 #define R_00B164_SPI_SHADER_USER_DATA_VS_13 0x00B164
4703 #define R_00B168_SPI_SHADER_USER_DATA_VS_14 0x00B168
4704 #define R_00B16C_SPI_SHADER_USER_DATA_VS_15 0x00B16C
4705 /* CIK */
4706 #define R_00B21C_SPI_SHADER_PGM_RSRC3_GS 0x00B21C
4707 #define S_00B21C_CU_EN(x) (((x) & 0xFFFF) << 0)
4708 #define G_00B21C_CU_EN(x) (((x) >> 0) & 0xFFFF)
4709 #define C_00B21C_CU_EN 0xFFFF0000
4710 #define S_00B21C_WAVE_LIMIT(x) (((x) & 0x3F) << 16)
4711 #define G_00B21C_WAVE_LIMIT(x) (((x) >> 16) & 0x3F)
4712 #define C_00B21C_WAVE_LIMIT 0xFFC0FFFF
4713 #define S_00B21C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22)
4714 #define G_00B21C_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F)
4715 #define C_00B21C_LOCK_LOW_THRESHOLD 0xFC3FFFFF
4716 /* */
4717 #define R_00B220_SPI_SHADER_PGM_LO_GS 0x00B220
4718 #define R_00B224_SPI_SHADER_PGM_HI_GS 0x00B224
4719 #define S_00B224_MEM_BASE(x) (((x) & 0xFF) << 0)
4720 #define G_00B224_MEM_BASE(x) (((x) >> 0) & 0xFF)
4721 #define C_00B224_MEM_BASE 0xFFFFFF00
4722 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
4723 #define S_00B228_VGPRS(x) (((x) & 0x3F) << 0)
4724 #define G_00B228_VGPRS(x) (((x) >> 0) & 0x3F)
4725 #define C_00B228_VGPRS 0xFFFFFFC0
4726 #define S_00B228_SGPRS(x) (((x) & 0x0F) << 6)
4727 #define G_00B228_SGPRS(x) (((x) >> 6) & 0x0F)
4728 #define C_00B228_SGPRS 0xFFFFFC3F
4729 #define S_00B228_PRIORITY(x) (((x) & 0x03) << 10)
4730 #define G_00B228_PRIORITY(x) (((x) >> 10) & 0x03)
4731 #define C_00B228_PRIORITY 0xFFFFF3FF
4732 #define S_00B228_FLOAT_MODE(x) (((x) & 0xFF) << 12)
4733 #define G_00B228_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
4734 #define C_00B228_FLOAT_MODE 0xFFF00FFF
4735 #define S_00B228_PRIV(x) (((x) & 0x1) << 20)
4736 #define G_00B228_PRIV(x) (((x) >> 20) & 0x1)
4737 #define C_00B228_PRIV 0xFFEFFFFF
4738 #define S_00B228_DX10_CLAMP(x) (((x) & 0x1) << 21)
4739 #define G_00B228_DX10_CLAMP(x) (((x) >> 21) & 0x1)
4740 #define C_00B228_DX10_CLAMP 0xFFDFFFFF
4741 #define S_00B228_DEBUG_MODE(x) (((x) & 0x1) << 22)
4742 #define G_00B228_DEBUG_MODE(x) (((x) >> 22) & 0x1)
4743 #define C_00B228_DEBUG_MODE 0xFFBFFFFF
4744 #define S_00B228_IEEE_MODE(x) (((x) & 0x1) << 23)
4745 #define G_00B228_IEEE_MODE(x) (((x) >> 23) & 0x1)
4746 #define C_00B228_IEEE_MODE 0xFF7FFFFF
4747 #define S_00B228_CU_GROUP_ENABLE(x) (((x) & 0x1) << 24)
4748 #define G_00B228_CU_GROUP_ENABLE(x) (((x) >> 24) & 0x1)
4749 #define C_00B228_CU_GROUP_ENABLE 0xFEFFFFFF
4750 /* CIK */
4751 #define S_00B228_CACHE_CTL(x) (((x) & 0x07) << 25)
4752 #define G_00B228_CACHE_CTL(x) (((x) >> 25) & 0x07)
4753 #define C_00B228_CACHE_CTL 0xF1FFFFFF
4754 #define S_00B228_CDBG_USER(x) (((x) & 0x1) << 28)
4755 #define G_00B228_CDBG_USER(x) (((x) >> 28) & 0x1)
4756 #define C_00B228_CDBG_USER 0xEFFFFFFF
4757 /* */
4758 #define R_00B22C_SPI_SHADER_PGM_RSRC2_GS 0x00B22C
4759 #define S_00B22C_SCRATCH_EN(x) (((x) & 0x1) << 0)
4760 #define G_00B22C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
4761 #define C_00B22C_SCRATCH_EN 0xFFFFFFFE
4762 #define S_00B22C_USER_SGPR(x) (((x) & 0x1F) << 1)
4763 #define G_00B22C_USER_SGPR(x) (((x) >> 1) & 0x1F)
4764 #define C_00B22C_USER_SGPR 0xFFFFFFC1
4765 #define S_00B22C_EXCP_EN(x) (((x) & 0x7F) << 7) /* mask is 0x1FF on CIK */
4766 #define G_00B22C_EXCP_EN(x) (((x) >> 7) & 0x7F) /* mask is 0x1FF on CIK */
4767 #define C_00B22C_EXCP_EN 0xFFFFC07F /* mask is 0x1FF on CIK */
4768 #define R_00B230_SPI_SHADER_USER_DATA_GS_0 0x00B230
4769 /* CIK */
4770 #define R_00B31C_SPI_SHADER_PGM_RSRC3_ES 0x00B31C
4771 #define S_00B31C_CU_EN(x) (((x) & 0xFFFF) << 0)
4772 #define G_00B31C_CU_EN(x) (((x) >> 0) & 0xFFFF)
4773 #define C_00B31C_CU_EN 0xFFFF0000
4774 #define S_00B31C_WAVE_LIMIT(x) (((x) & 0x3F) << 16)
4775 #define G_00B31C_WAVE_LIMIT(x) (((x) >> 16) & 0x3F)
4776 #define C_00B31C_WAVE_LIMIT 0xFFC0FFFF
4777 #define S_00B31C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22)
4778 #define G_00B31C_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F)
4779 #define C_00B31C_LOCK_LOW_THRESHOLD 0xFC3FFFFF
4780 /* */
4781 #define R_00B320_SPI_SHADER_PGM_LO_ES 0x00B320
4782 #define R_00B324_SPI_SHADER_PGM_HI_ES 0x00B324
4783 #define S_00B324_MEM_BASE(x) (((x) & 0xFF) << 0)
4784 #define G_00B324_MEM_BASE(x) (((x) >> 0) & 0xFF)
4785 #define C_00B324_MEM_BASE 0xFFFFFF00
4786 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
4787 #define S_00B328_VGPRS(x) (((x) & 0x3F) << 0)
4788 #define G_00B328_VGPRS(x) (((x) >> 0) & 0x3F)
4789 #define C_00B328_VGPRS 0xFFFFFFC0
4790 #define S_00B328_SGPRS(x) (((x) & 0x0F) << 6)
4791 #define G_00B328_SGPRS(x) (((x) >> 6) & 0x0F)
4792 #define C_00B328_SGPRS 0xFFFFFC3F
4793 #define S_00B328_PRIORITY(x) (((x) & 0x03) << 10)
4794 #define G_00B328_PRIORITY(x) (((x) >> 10) & 0x03)
4795 #define C_00B328_PRIORITY 0xFFFFF3FF
4796 #define S_00B328_FLOAT_MODE(x) (((x) & 0xFF) << 12)
4797 #define G_00B328_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
4798 #define C_00B328_FLOAT_MODE 0xFFF00FFF
4799 #define S_00B328_PRIV(x) (((x) & 0x1) << 20)
4800 #define G_00B328_PRIV(x) (((x) >> 20) & 0x1)
4801 #define C_00B328_PRIV 0xFFEFFFFF
4802 #define S_00B328_DX10_CLAMP(x) (((x) & 0x1) << 21)
4803 #define G_00B328_DX10_CLAMP(x) (((x) >> 21) & 0x1)
4804 #define C_00B328_DX10_CLAMP 0xFFDFFFFF
4805 #define S_00B328_DEBUG_MODE(x) (((x) & 0x1) << 22)
4806 #define G_00B328_DEBUG_MODE(x) (((x) >> 22) & 0x1)
4807 #define C_00B328_DEBUG_MODE 0xFFBFFFFF
4808 #define S_00B328_IEEE_MODE(x) (((x) & 0x1) << 23)
4809 #define G_00B328_IEEE_MODE(x) (((x) >> 23) & 0x1)
4810 #define C_00B328_IEEE_MODE 0xFF7FFFFF
4811 #define S_00B328_VGPR_COMP_CNT(x) (((x) & 0x03) << 24)
4812 #define G_00B328_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03)
4813 #define C_00B328_VGPR_COMP_CNT 0xFCFFFFFF
4814 #define S_00B328_CU_GROUP_ENABLE(x) (((x) & 0x1) << 26)
4815 #define G_00B328_CU_GROUP_ENABLE(x) (((x) >> 26) & 0x1)
4816 #define C_00B328_CU_GROUP_ENABLE 0xFBFFFFFF
4817 /* CIK */
4818 #define S_00B328_CACHE_CTL(x) (((x) & 0x07) << 27)
4819 #define G_00B328_CACHE_CTL(x) (((x) >> 27) & 0x07)
4820 #define C_00B328_CACHE_CTL 0xC7FFFFFF
4821 #define S_00B328_CDBG_USER(x) (((x) & 0x1) << 30)
4822 #define G_00B328_CDBG_USER(x) (((x) >> 30) & 0x1)
4823 #define C_00B328_CDBG_USER 0xBFFFFFFF
4824 /* */
4825 #define R_00B32C_SPI_SHADER_PGM_RSRC2_ES 0x00B32C
4826 #define S_00B32C_SCRATCH_EN(x) (((x) & 0x1) << 0)
4827 #define G_00B32C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
4828 #define C_00B32C_SCRATCH_EN 0xFFFFFFFE
4829 #define S_00B32C_USER_SGPR(x) (((x) & 0x1F) << 1)
4830 #define G_00B32C_USER_SGPR(x) (((x) >> 1) & 0x1F)
4831 #define C_00B32C_USER_SGPR 0xFFFFFFC1
4832 #define S_00B32C_OC_LDS_EN(x) (((x) & 0x1) << 7)
4833 #define G_00B32C_OC_LDS_EN(x) (((x) >> 7) & 0x1)
4834 #define C_00B32C_OC_LDS_EN 0xFFFFFF7F
4835 #define S_00B32C_EXCP_EN(x) (((x) & 0x7F) << 8) /* mask is 0x1FF on CIK */
4836 #define G_00B32C_EXCP_EN(x) (((x) >> 8) & 0x7F) /* mask is 0x1FF on CIK */
4837 #define C_00B32C_EXCP_EN 0xFFFF80FF /* mask is 0x1FF on CIK */
4838 #define S_00B32C_LDS_SIZE(x) (((x) & 0x1FF) << 20) /* CIK, for on-chip GS */
4839 #define G_00B32C_LDS_SIZE(x) (((x) >> 20) & 0x1FF) /* CIK, for on-chip GS */
4840 #define C_00B32C_LDS_SIZE 0xE00FFFFF /* CIK, for on-chip GS */
4841 #define R_00B330_SPI_SHADER_USER_DATA_ES_0 0x00B330
4842 /* CIK */
4843 #define R_00B41C_SPI_SHADER_PGM_RSRC3_HS 0x00B41C
4844 #define S_00B41C_WAVE_LIMIT(x) (((x) & 0x3F) << 0)
4845 #define G_00B41C_WAVE_LIMIT(x) (((x) >> 0) & 0x3F)
4846 #define C_00B41C_WAVE_LIMIT 0xFFFFFFC0
4847 #define S_00B41C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 6)
4848 #define G_00B41C_LOCK_LOW_THRESHOLD(x) (((x) >> 6) & 0x0F)
4849 #define C_00B41C_LOCK_LOW_THRESHOLD 0xFFFFFC3F
4850 /* */
4851 #define R_00B420_SPI_SHADER_PGM_LO_HS 0x00B420
4852 #define R_00B424_SPI_SHADER_PGM_HI_HS 0x00B424
4853 #define S_00B424_MEM_BASE(x) (((x) & 0xFF) << 0)
4854 #define G_00B424_MEM_BASE(x) (((x) >> 0) & 0xFF)
4855 #define C_00B424_MEM_BASE 0xFFFFFF00
4856 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
4857 #define S_00B428_VGPRS(x) (((x) & 0x3F) << 0)
4858 #define G_00B428_VGPRS(x) (((x) >> 0) & 0x3F)
4859 #define C_00B428_VGPRS 0xFFFFFFC0
4860 #define S_00B428_SGPRS(x) (((x) & 0x0F) << 6)
4861 #define G_00B428_SGPRS(x) (((x) >> 6) & 0x0F)
4862 #define C_00B428_SGPRS 0xFFFFFC3F
4863 #define S_00B428_PRIORITY(x) (((x) & 0x03) << 10)
4864 #define G_00B428_PRIORITY(x) (((x) >> 10) & 0x03)
4865 #define C_00B428_PRIORITY 0xFFFFF3FF
4866 #define S_00B428_FLOAT_MODE(x) (((x) & 0xFF) << 12)
4867 #define G_00B428_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
4868 #define C_00B428_FLOAT_MODE 0xFFF00FFF
4869 #define S_00B428_PRIV(x) (((x) & 0x1) << 20)
4870 #define G_00B428_PRIV(x) (((x) >> 20) & 0x1)
4871 #define C_00B428_PRIV 0xFFEFFFFF
4872 #define S_00B428_DX10_CLAMP(x) (((x) & 0x1) << 21)
4873 #define G_00B428_DX10_CLAMP(x) (((x) >> 21) & 0x1)
4874 #define C_00B428_DX10_CLAMP 0xFFDFFFFF
4875 #define S_00B428_DEBUG_MODE(x) (((x) & 0x1) << 22)
4876 #define G_00B428_DEBUG_MODE(x) (((x) >> 22) & 0x1)
4877 #define C_00B428_DEBUG_MODE 0xFFBFFFFF
4878 #define S_00B428_IEEE_MODE(x) (((x) & 0x1) << 23)
4879 #define G_00B428_IEEE_MODE(x) (((x) >> 23) & 0x1)
4880 #define C_00B428_IEEE_MODE 0xFF7FFFFF
4881 /* CIK */
4882 #define S_00B428_CACHE_CTL(x) (((x) & 0x07) << 24)
4883 #define G_00B428_CACHE_CTL(x) (((x) >> 24) & 0x07)
4884 #define C_00B428_CACHE_CTL 0xF8FFFFFF
4885 #define S_00B428_CDBG_USER(x) (((x) & 0x1) << 27)
4886 #define G_00B428_CDBG_USER(x) (((x) >> 27) & 0x1)
4887 #define C_00B428_CDBG_USER 0xF7FFFFFF
4888 /* */
4889 #define R_00B42C_SPI_SHADER_PGM_RSRC2_HS 0x00B42C
4890 #define S_00B42C_SCRATCH_EN(x) (((x) & 0x1) << 0)
4891 #define G_00B42C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
4892 #define C_00B42C_SCRATCH_EN 0xFFFFFFFE
4893 #define S_00B42C_USER_SGPR(x) (((x) & 0x1F) << 1)
4894 #define G_00B42C_USER_SGPR(x) (((x) >> 1) & 0x1F)
4895 #define C_00B42C_USER_SGPR 0xFFFFFFC1
4896 #define S_00B42C_OC_LDS_EN(x) (((x) & 0x1) << 7)
4897 #define G_00B42C_OC_LDS_EN(x) (((x) >> 7) & 0x1)
4898 #define C_00B42C_OC_LDS_EN 0xFFFFFF7F
4899 #define S_00B42C_TG_SIZE_EN(x) (((x) & 0x1) << 8)
4900 #define G_00B42C_TG_SIZE_EN(x) (((x) >> 8) & 0x1)
4901 #define C_00B42C_TG_SIZE_EN 0xFFFFFEFF
4902 #define S_00B42C_EXCP_EN(x) (((x) & 0x7F) << 9) /* mask is 0x1FF on CIK */
4903 #define G_00B42C_EXCP_EN(x) (((x) >> 9) & 0x7F) /* mask is 0x1FF on CIK */
4904 #define C_00B42C_EXCP_EN 0xFFFF01FF /* mask is 0x1FF on CIK */
4905 #define R_00B430_SPI_SHADER_USER_DATA_HS_0 0x00B430
4906 /* CIK */
4907 #define R_00B51C_SPI_SHADER_PGM_RSRC3_LS 0x00B51C
4908 #define S_00B51C_CU_EN(x) (((x) & 0xFFFF) << 0)
4909 #define G_00B51C_CU_EN(x) (((x) >> 0) & 0xFFFF)
4910 #define C_00B51C_CU_EN 0xFFFF0000
4911 #define S_00B51C_WAVE_LIMIT(x) (((x) & 0x3F) << 16)
4912 #define G_00B51C_WAVE_LIMIT(x) (((x) >> 16) & 0x3F)
4913 #define C_00B51C_WAVE_LIMIT 0xFFC0FFFF
4914 #define S_00B51C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22)
4915 #define G_00B51C_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F)
4916 #define C_00B51C_LOCK_LOW_THRESHOLD 0xFC3FFFFF
4917 /* */
4918 #define R_00B520_SPI_SHADER_PGM_LO_LS 0x00B520
4919 #define R_00B524_SPI_SHADER_PGM_HI_LS 0x00B524
4920 #define S_00B524_MEM_BASE(x) (((x) & 0xFF) << 0)
4921 #define G_00B524_MEM_BASE(x) (((x) >> 0) & 0xFF)
4922 #define C_00B524_MEM_BASE 0xFFFFFF00
4923 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
4924 #define S_00B528_VGPRS(x) (((x) & 0x3F) << 0)
4925 #define G_00B528_VGPRS(x) (((x) >> 0) & 0x3F)
4926 #define C_00B528_VGPRS 0xFFFFFFC0
4927 #define S_00B528_SGPRS(x) (((x) & 0x0F) << 6)
4928 #define G_00B528_SGPRS(x) (((x) >> 6) & 0x0F)
4929 #define C_00B528_SGPRS 0xFFFFFC3F
4930 #define S_00B528_PRIORITY(x) (((x) & 0x03) << 10)
4931 #define G_00B528_PRIORITY(x) (((x) >> 10) & 0x03)
4932 #define C_00B528_PRIORITY 0xFFFFF3FF
4933 #define S_00B528_FLOAT_MODE(x) (((x) & 0xFF) << 12)
4934 #define G_00B528_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
4935 #define C_00B528_FLOAT_MODE 0xFFF00FFF
4936 #define S_00B528_PRIV(x) (((x) & 0x1) << 20)
4937 #define G_00B528_PRIV(x) (((x) >> 20) & 0x1)
4938 #define C_00B528_PRIV 0xFFEFFFFF
4939 #define S_00B528_DX10_CLAMP(x) (((x) & 0x1) << 21)
4940 #define G_00B528_DX10_CLAMP(x) (((x) >> 21) & 0x1)
4941 #define C_00B528_DX10_CLAMP 0xFFDFFFFF
4942 #define S_00B528_DEBUG_MODE(x) (((x) & 0x1) << 22)
4943 #define G_00B528_DEBUG_MODE(x) (((x) >> 22) & 0x1)
4944 #define C_00B528_DEBUG_MODE 0xFFBFFFFF
4945 #define S_00B528_IEEE_MODE(x) (((x) & 0x1) << 23)
4946 #define G_00B528_IEEE_MODE(x) (((x) >> 23) & 0x1)
4947 #define C_00B528_IEEE_MODE 0xFF7FFFFF
4948 #define S_00B528_VGPR_COMP_CNT(x) (((x) & 0x03) << 24)
4949 #define G_00B528_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03)
4950 #define C_00B528_VGPR_COMP_CNT 0xFCFFFFFF
4951 /* CIK */
4952 #define S_00B528_CACHE_CTL(x) (((x) & 0x07) << 26)
4953 #define G_00B528_CACHE_CTL(x) (((x) >> 26) & 0x07)
4954 #define C_00B528_CACHE_CTL 0xE3FFFFFF
4955 #define S_00B528_CDBG_USER(x) (((x) & 0x1) << 29)
4956 #define G_00B528_CDBG_USER(x) (((x) >> 29) & 0x1)
4957 #define C_00B528_CDBG_USER 0xDFFFFFFF
4958 /* */
4959 #define R_00B52C_SPI_SHADER_PGM_RSRC2_LS 0x00B52C
4960 #define S_00B52C_SCRATCH_EN(x) (((x) & 0x1) << 0)
4961 #define G_00B52C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
4962 #define C_00B52C_SCRATCH_EN 0xFFFFFFFE
4963 #define S_00B52C_USER_SGPR(x) (((x) & 0x1F) << 1)
4964 #define G_00B52C_USER_SGPR(x) (((x) >> 1) & 0x1F)
4965 #define C_00B52C_USER_SGPR 0xFFFFFFC1
4966 #define S_00B52C_LDS_SIZE(x) (((x) & 0x1FF) << 7)
4967 #define G_00B52C_LDS_SIZE(x) (((x) >> 7) & 0x1FF)
4968 #define C_00B52C_LDS_SIZE 0xFFFF007F
4969 #define S_00B52C_EXCP_EN(x) (((x) & 0x7F) << 16) /* mask is 0x1FF on CIK */
4970 #define G_00B52C_EXCP_EN(x) (((x) >> 16) & 0x7F) /* mask is 0x1FF on CIK */
4971 #define C_00B52C_EXCP_EN 0xFF80FFFF /* mask is 0x1FF on CIK */
4972 #define R_00B530_SPI_SHADER_USER_DATA_LS_0 0x00B530
4973 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
4974 #define S_00B800_COMPUTE_SHADER_EN(x) (((x) & 0x1) << 0)
4975 #define G_00B800_COMPUTE_SHADER_EN(x) (((x) >> 0) & 0x1)
4976 #define C_00B800_COMPUTE_SHADER_EN 0xFFFFFFFE
4977 #define S_00B800_PARTIAL_TG_EN(x) (((x) & 0x1) << 1)
4978 #define G_00B800_PARTIAL_TG_EN(x) (((x) >> 1) & 0x1)
4979 #define C_00B800_PARTIAL_TG_EN 0xFFFFFFFD
4980 #define S_00B800_FORCE_START_AT_000(x) (((x) & 0x1) << 2)
4981 #define G_00B800_FORCE_START_AT_000(x) (((x) >> 2) & 0x1)
4982 #define C_00B800_FORCE_START_AT_000 0xFFFFFFFB
4983 #define S_00B800_ORDERED_APPEND_ENBL(x) (((x) & 0x1) << 3)
4984 #define G_00B800_ORDERED_APPEND_ENBL(x) (((x) >> 3) & 0x1)
4985 #define C_00B800_ORDERED_APPEND_ENBL 0xFFFFFFF7
4986 /* CIK */
4987 #define S_00B800_ORDERED_APPEND_MODE(x) (((x) & 0x1) << 4)
4988 #define G_00B800_ORDERED_APPEND_MODE(x) (((x) >> 4) & 0x1)
4989 #define C_00B800_ORDERED_APPEND_MODE 0xFFFFFFEF
4990 #define S_00B800_USE_THREAD_DIMENSIONS(x) (((x) & 0x1) << 5)
4991 #define G_00B800_USE_THREAD_DIMENSIONS(x) (((x) >> 5) & 0x1)
4992 #define C_00B800_USE_THREAD_DIMENSIONS 0xFFFFFFDF
4993 #define S_00B800_ORDER_MODE(x) (((x) & 0x1) << 6)
4994 #define G_00B800_ORDER_MODE(x) (((x) >> 6) & 0x1)
4995 #define C_00B800_ORDER_MODE 0xFFFFFFBF
4996 #define S_00B800_DISPATCH_CACHE_CNTL(x) (((x) & 0x07) << 7)
4997 #define G_00B800_DISPATCH_CACHE_CNTL(x) (((x) >> 7) & 0x07)
4998 #define C_00B800_DISPATCH_CACHE_CNTL 0xFFFFFC7F
4999 #define S_00B800_SCALAR_L1_INV_VOL(x) (((x) & 0x1) << 10)
5000 #define G_00B800_SCALAR_L1_INV_VOL(x) (((x) >> 10) & 0x1)
5001 #define C_00B800_SCALAR_L1_INV_VOL 0xFFFFFBFF
5002 #define S_00B800_VECTOR_L1_INV_VOL(x) (((x) & 0x1) << 11)
5003 #define G_00B800_VECTOR_L1_INV_VOL(x) (((x) >> 11) & 0x1)
5004 #define C_00B800_VECTOR_L1_INV_VOL 0xFFFFF7FF
5005 #define S_00B800_DATA_ATC(x) (((x) & 0x1) << 12)
5006 #define G_00B800_DATA_ATC(x) (((x) >> 12) & 0x1)
5007 #define C_00B800_DATA_ATC 0xFFFFEFFF
5008 #define S_00B800_RESTORE(x) (((x) & 0x1) << 14)
5009 #define G_00B800_RESTORE(x) (((x) >> 14) & 0x1)
5010 #define C_00B800_RESTORE 0xFFFFBFFF
5011 /* */
5012 #define R_00B804_COMPUTE_DIM_X 0x00B804
5013 #define R_00B808_COMPUTE_DIM_Y 0x00B808
5014 #define R_00B80C_COMPUTE_DIM_Z 0x00B80C
5015 #define R_00B810_COMPUTE_START_X 0x00B810
5016 #define R_00B814_COMPUTE_START_Y 0x00B814
5017 #define R_00B818_COMPUTE_START_Z 0x00B818
5018 #define R_00B81C_COMPUTE_NUM_THREAD_X 0x00B81C
5019 #define S_00B81C_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0)
5020 #define G_00B81C_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF)
5021 #define C_00B81C_NUM_THREAD_FULL 0xFFFF0000
5022 #define S_00B81C_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16)
5023 #define G_00B81C_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF)
5024 #define C_00B81C_NUM_THREAD_PARTIAL 0x0000FFFF
5025 #define R_00B820_COMPUTE_NUM_THREAD_Y 0x00B820
5026 #define S_00B820_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0)
5027 #define G_00B820_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF)
5028 #define C_00B820_NUM_THREAD_FULL 0xFFFF0000
5029 #define S_00B820_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16)
5030 #define G_00B820_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF)
5031 #define C_00B820_NUM_THREAD_PARTIAL 0x0000FFFF
5032 #define R_00B824_COMPUTE_NUM_THREAD_Z 0x00B824
5033 #define S_00B824_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0)
5034 #define G_00B824_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF)
5035 #define C_00B824_NUM_THREAD_FULL 0xFFFF0000
5036 #define S_00B824_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16)
5037 #define G_00B824_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF)
5038 #define C_00B824_NUM_THREAD_PARTIAL 0x0000FFFF
5039 #define R_00B82C_COMPUTE_MAX_WAVE_ID 0x00B82C /* moved to 0xCD20 on CIK */
5040 #define S_00B82C_MAX_WAVE_ID(x) (((x) & 0xFFF) << 0)
5041 #define G_00B82C_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF)
5042 #define C_00B82C_MAX_WAVE_ID 0xFFFFF000
5043 #define R_00B830_COMPUTE_PGM_LO 0x00B830
5044 #define R_00B834_COMPUTE_PGM_HI 0x00B834
5045 #define S_00B834_DATA(x) (((x) & 0xFF) << 0)
5046 #define G_00B834_DATA(x) (((x) >> 0) & 0xFF)
5047 #define C_00B834_DATA 0xFFFFFF00
5048 /* CIK */
5049 #define S_00B834_INST_ATC(x) (((x) & 0x1) << 8)
5050 #define G_00B834_INST_ATC(x) (((x) >> 8) & 0x1)
5051 #define C_00B834_INST_ATC 0xFFFFFEFF
5052 /* */
5053 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
5054 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
5055 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
5056 #define C_00B848_VGPRS 0xFFFFFFC0
5057 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
5058 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
5059 #define C_00B848_SGPRS 0xFFFFFC3F
5060 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
5061 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
5062 #define C_00B848_PRIORITY 0xFFFFF3FF
5063 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
5064 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
5065 #define C_00B848_FLOAT_MODE 0xFFF00FFF
5066 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
5067 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
5068 #define C_00B848_PRIV 0xFFEFFFFF
5069 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
5070 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
5071 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
5072 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
5073 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
5074 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
5075 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
5076 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
5077 #define C_00B848_IEEE_MODE 0xFF7FFFFF
5078 /* CIK */
5079 #define S_00B848_BULKY(x) (((x) & 0x1) << 24)
5080 #define G_00B848_BULKY(x) (((x) >> 24) & 0x1)
5081 #define C_00B848_BULKY 0xFEFFFFFF
5082 #define S_00B848_CDBG_USER(x) (((x) & 0x1) << 25)
5083 #define G_00B848_CDBG_USER(x) (((x) >> 25) & 0x1)
5084 #define C_00B848_CDBG_USER 0xFDFFFFFF
5085 /* */
5086 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
5087 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
5088 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
5089 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
5090 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
5091 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
5092 #define C_00B84C_USER_SGPR 0xFFFFFFC1
5093 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
5094 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
5095 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
5096 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
5097 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
5098 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
5099 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
5100 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
5101 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
5102 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
5103 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
5104 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
5105 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
5106 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
5107 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
5108 /* CIK */
5109 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
5110 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
5111 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
5112 /* */
5113 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
5114 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
5115 #define C_00B84C_LDS_SIZE 0xFF007FFF
5116 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
5117 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
5118 #define C_00B84C_EXCP_EN 0x80FFFFFF
5119 #define R_00B854_COMPUTE_RESOURCE_LIMITS 0x00B854
5120 #define S_00B854_WAVES_PER_SH(x) (((x) & 0x3F) << 0) /* mask is 0x3FF on CIK */
5121 #define G_00B854_WAVES_PER_SH(x) (((x) >> 0) & 0x3F) /* mask is 0x3FF on CIK */
5122 #define C_00B854_WAVES_PER_SH 0xFFFFFFC0 /* mask is 0x3FF on CIK */
5123 #define S_00B854_TG_PER_CU(x) (((x) & 0x0F) << 12)
5124 #define G_00B854_TG_PER_CU(x) (((x) >> 12) & 0x0F)
5125 #define C_00B854_TG_PER_CU 0xFFFF0FFF
5126 #define S_00B854_LOCK_THRESHOLD(x) (((x) & 0x3F) << 16)
5127 #define G_00B854_LOCK_THRESHOLD(x) (((x) >> 16) & 0x3F)
5128 #define C_00B854_LOCK_THRESHOLD 0xFFC0FFFF
5129 #define S_00B854_SIMD_DEST_CNTL(x) (((x) & 0x1) << 22)
5130 #define G_00B854_SIMD_DEST_CNTL(x) (((x) >> 22) & 0x1)
5131 #define C_00B854_SIMD_DEST_CNTL 0xFFBFFFFF
5132 /* CIK */
5133 #define S_00B854_FORCE_SIMD_DIST(x) (((x) & 0x1) << 23)
5134 #define G_00B854_FORCE_SIMD_DIST(x) (((x) >> 23) & 0x1)
5135 #define C_00B854_FORCE_SIMD_DIST 0xFF7FFFFF
5136 #define S_00B854_CU_GROUP_COUNT(x) (((x) & 0x07) << 24)
5137 #define G_00B854_CU_GROUP_COUNT(x) (((x) >> 24) & 0x07)
5138 #define C_00B854_CU_GROUP_COUNT 0xF8FFFFFF
5139 /* */
5140 #define R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 0x00B858
5141 #define S_00B858_SH0_CU_EN(x) (((x) & 0xFFFF) << 0)
5142 #define G_00B858_SH0_CU_EN(x) (((x) >> 0) & 0xFFFF)
5143 #define C_00B858_SH0_CU_EN 0xFFFF0000
5144 #define S_00B858_SH1_CU_EN(x) (((x) & 0xFFFF) << 16)
5145 #define G_00B858_SH1_CU_EN(x) (((x) >> 16) & 0xFFFF)
5146 #define C_00B858_SH1_CU_EN 0x0000FFFF
5147 #define R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1 0x00B85C
5148 #define S_00B85C_SH0_CU_EN(x) (((x) & 0xFFFF) << 0)
5149 #define G_00B85C_SH0_CU_EN(x) (((x) >> 0) & 0xFFFF)
5150 #define C_00B85C_SH0_CU_EN 0xFFFF0000
5151 #define S_00B85C_SH1_CU_EN(x) (((x) & 0xFFFF) << 16)
5152 #define G_00B85C_SH1_CU_EN(x) (((x) >> 16) & 0xFFFF)
5153 #define C_00B85C_SH1_CU_EN 0x0000FFFF
5154 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
5155 #define S_00B860_WAVES(x) (((x) & 0xFFF) << 0)
5156 #define G_00B860_WAVES(x) (((x) >> 0) & 0xFFF)
5157 #define C_00B860_WAVES 0xFFFFF000
5158 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
5159 #define G_00B860_WAVESIZE(x) (((x) >> 12) & 0x1FFF)
5160 #define C_00B860_WAVESIZE 0xFE000FFF
5161 #define R_00B900_COMPUTE_USER_DATA_0 0x00B900
5162 #define R_028000_DB_RENDER_CONTROL 0x028000
5163 #define S_028000_DEPTH_CLEAR_ENABLE(x) (((x) & 0x1) << 0)
5164 #define G_028000_DEPTH_CLEAR_ENABLE(x) (((x) >> 0) & 0x1)
5165 #define C_028000_DEPTH_CLEAR_ENABLE 0xFFFFFFFE
5166 #define S_028000_STENCIL_CLEAR_ENABLE(x) (((x) & 0x1) << 1)
5167 #define G_028000_STENCIL_CLEAR_ENABLE(x) (((x) >> 1) & 0x1)
5168 #define C_028000_STENCIL_CLEAR_ENABLE 0xFFFFFFFD
5169 #define S_028000_DEPTH_COPY(x) (((x) & 0x1) << 2)
5170 #define G_028000_DEPTH_COPY(x) (((x) >> 2) & 0x1)
5171 #define C_028000_DEPTH_COPY 0xFFFFFFFB
5172 #define S_028000_STENCIL_COPY(x) (((x) & 0x1) << 3)
5173 #define G_028000_STENCIL_COPY(x) (((x) >> 3) & 0x1)
5174 #define C_028000_STENCIL_COPY 0xFFFFFFF7
5175 #define S_028000_RESUMMARIZE_ENABLE(x) (((x) & 0x1) << 4)
5176 #define G_028000_RESUMMARIZE_ENABLE(x) (((x) >> 4) & 0x1)
5177 #define C_028000_RESUMMARIZE_ENABLE 0xFFFFFFEF
5178 #define S_028000_STENCIL_COMPRESS_DISABLE(x) (((x) & 0x1) << 5)
5179 #define G_028000_STENCIL_COMPRESS_DISABLE(x) (((x) >> 5) & 0x1)
5180 #define C_028000_STENCIL_COMPRESS_DISABLE 0xFFFFFFDF
5181 #define S_028000_DEPTH_COMPRESS_DISABLE(x) (((x) & 0x1) << 6)
5182 #define G_028000_DEPTH_COMPRESS_DISABLE(x) (((x) >> 6) & 0x1)
5183 #define C_028000_DEPTH_COMPRESS_DISABLE 0xFFFFFFBF
5184 #define S_028000_COPY_CENTROID(x) (((x) & 0x1) << 7)
5185 #define G_028000_COPY_CENTROID(x) (((x) >> 7) & 0x1)
5186 #define C_028000_COPY_CENTROID 0xFFFFFF7F
5187 #define S_028000_COPY_SAMPLE(x) (((x) & 0x0F) << 8)
5188 #define G_028000_COPY_SAMPLE(x) (((x) >> 8) & 0x0F)
5189 #define C_028000_COPY_SAMPLE 0xFFFFF0FF
5190 #define R_028004_DB_COUNT_CONTROL 0x028004
5191 #define S_028004_ZPASS_INCREMENT_DISABLE(x) (((x) & 0x1) << 0)
5192 #define G_028004_ZPASS_INCREMENT_DISABLE(x) (((x) >> 0) & 0x1)
5193 #define C_028004_ZPASS_INCREMENT_DISABLE 0xFFFFFFFE
5194 #define S_028004_PERFECT_ZPASS_COUNTS(x) (((x) & 0x1) << 1)
5195 #define G_028004_PERFECT_ZPASS_COUNTS(x) (((x) >> 1) & 0x1)
5196 #define C_028004_PERFECT_ZPASS_COUNTS 0xFFFFFFFD
5197 #define S_028004_SAMPLE_RATE(x) (((x) & 0x07) << 4)
5198 #define G_028004_SAMPLE_RATE(x) (((x) >> 4) & 0x07)
5199 #define C_028004_SAMPLE_RATE 0xFFFFFF8F
5200 /* CIK */
5201 #define S_028004_ZPASS_ENABLE(x) (((x) & 0x0F) << 8)
5202 #define G_028004_ZPASS_ENABLE(x) (((x) >> 8) & 0x0F)
5203 #define C_028004_ZPASS_ENABLE 0xFFFFF0FF
5204 #define S_028004_ZFAIL_ENABLE(x) (((x) & 0x0F) << 12)
5205 #define G_028004_ZFAIL_ENABLE(x) (((x) >> 12) & 0x0F)
5206 #define C_028004_ZFAIL_ENABLE 0xFFFF0FFF
5207 #define S_028004_SFAIL_ENABLE(x) (((x) & 0x0F) << 16)
5208 #define G_028004_SFAIL_ENABLE(x) (((x) >> 16) & 0x0F)
5209 #define C_028004_SFAIL_ENABLE 0xFFF0FFFF
5210 #define S_028004_DBFAIL_ENABLE(x) (((x) & 0x0F) << 20)
5211 #define G_028004_DBFAIL_ENABLE(x) (((x) >> 20) & 0x0F)
5212 #define C_028004_DBFAIL_ENABLE 0xFF0FFFFF
5213 #define S_028004_SLICE_EVEN_ENABLE(x) (((x) & 0x0F) << 24)
5214 #define G_028004_SLICE_EVEN_ENABLE(x) (((x) >> 24) & 0x0F)
5215 #define C_028004_SLICE_EVEN_ENABLE 0xF0FFFFFF
5216 #define S_028004_SLICE_ODD_ENABLE(x) (((x) & 0x0F) << 28)
5217 #define G_028004_SLICE_ODD_ENABLE(x) (((x) >> 28) & 0x0F)
5218 #define C_028004_SLICE_ODD_ENABLE 0x0FFFFFFF
5219 /* */
5220 #define R_028008_DB_DEPTH_VIEW 0x028008
5221 #define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0)
5222 #define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF)
5223 #define C_028008_SLICE_START 0xFFFFF800
5224 #define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13)
5225 #define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
5226 #define C_028008_SLICE_MAX 0xFF001FFF
5227 #define S_028008_Z_READ_ONLY(x) (((x) & 0x1) << 24)
5228 #define G_028008_Z_READ_ONLY(x) (((x) >> 24) & 0x1)
5229 #define C_028008_Z_READ_ONLY 0xFEFFFFFF
5230 #define S_028008_STENCIL_READ_ONLY(x) (((x) & 0x1) << 25)
5231 #define G_028008_STENCIL_READ_ONLY(x) (((x) >> 25) & 0x1)
5232 #define C_028008_STENCIL_READ_ONLY 0xFDFFFFFF
5233 #define R_02800C_DB_RENDER_OVERRIDE 0x02800C
5234 #define S_02800C_FORCE_HIZ_ENABLE(x) (((x) & 0x03) << 0)
5235 #define G_02800C_FORCE_HIZ_ENABLE(x) (((x) >> 0) & 0x03)
5236 #define C_02800C_FORCE_HIZ_ENABLE 0xFFFFFFFC
5237 #define V_02800C_FORCE_OFF 0x00
5238 #define V_02800C_FORCE_ENABLE 0x01
5239 #define V_02800C_FORCE_DISABLE 0x02
5240 #define V_02800C_FORCE_RESERVED 0x03
5241 #define S_02800C_FORCE_HIS_ENABLE0(x) (((x) & 0x03) << 2)
5242 #define G_02800C_FORCE_HIS_ENABLE0(x) (((x) >> 2) & 0x03)
5243 #define C_02800C_FORCE_HIS_ENABLE0 0xFFFFFFF3
5244 #define V_02800C_FORCE_OFF 0x00
5245 #define V_02800C_FORCE_ENABLE 0x01
5246 #define V_02800C_FORCE_DISABLE 0x02
5247 #define V_02800C_FORCE_RESERVED 0x03
5248 #define S_02800C_FORCE_HIS_ENABLE1(x) (((x) & 0x03) << 4)
5249 #define G_02800C_FORCE_HIS_ENABLE1(x) (((x) >> 4) & 0x03)
5250 #define C_02800C_FORCE_HIS_ENABLE1 0xFFFFFFCF
5251 #define V_02800C_FORCE_OFF 0x00
5252 #define V_02800C_FORCE_ENABLE 0x01
5253 #define V_02800C_FORCE_DISABLE 0x02
5254 #define V_02800C_FORCE_RESERVED 0x03
5255 #define S_02800C_FORCE_SHADER_Z_ORDER(x) (((x) & 0x1) << 6)
5256 #define G_02800C_FORCE_SHADER_Z_ORDER(x) (((x) >> 6) & 0x1)
5257 #define C_02800C_FORCE_SHADER_Z_ORDER 0xFFFFFFBF
5258 #define S_02800C_FAST_Z_DISABLE(x) (((x) & 0x1) << 7)
5259 #define G_02800C_FAST_Z_DISABLE(x) (((x) >> 7) & 0x1)
5260 #define C_02800C_FAST_Z_DISABLE 0xFFFFFF7F
5261 #define S_02800C_FAST_STENCIL_DISABLE(x) (((x) & 0x1) << 8)
5262 #define G_02800C_FAST_STENCIL_DISABLE(x) (((x) >> 8) & 0x1)
5263 #define C_02800C_FAST_STENCIL_DISABLE 0xFFFFFEFF
5264 #define S_02800C_NOOP_CULL_DISABLE(x) (((x) & 0x1) << 9)
5265 #define G_02800C_NOOP_CULL_DISABLE(x) (((x) >> 9) & 0x1)
5266 #define C_02800C_NOOP_CULL_DISABLE 0xFFFFFDFF
5267 #define S_02800C_FORCE_COLOR_KILL(x) (((x) & 0x1) << 10)
5268 #define G_02800C_FORCE_COLOR_KILL(x) (((x) >> 10) & 0x1)
5269 #define C_02800C_FORCE_COLOR_KILL 0xFFFFFBFF
5270 #define S_02800C_FORCE_Z_READ(x) (((x) & 0x1) << 11)
5271 #define G_02800C_FORCE_Z_READ(x) (((x) >> 11) & 0x1)
5272 #define C_02800C_FORCE_Z_READ 0xFFFFF7FF
5273 #define S_02800C_FORCE_STENCIL_READ(x) (((x) & 0x1) << 12)
5274 #define G_02800C_FORCE_STENCIL_READ(x) (((x) >> 12) & 0x1)
5275 #define C_02800C_FORCE_STENCIL_READ 0xFFFFEFFF
5276 #define S_02800C_FORCE_FULL_Z_RANGE(x) (((x) & 0x03) << 13)
5277 #define G_02800C_FORCE_FULL_Z_RANGE(x) (((x) >> 13) & 0x03)
5278 #define C_02800C_FORCE_FULL_Z_RANGE 0xFFFF9FFF
5279 #define V_02800C_FORCE_OFF 0x00
5280 #define V_02800C_FORCE_ENABLE 0x01
5281 #define V_02800C_FORCE_DISABLE 0x02
5282 #define V_02800C_FORCE_RESERVED 0x03
5283 #define S_02800C_FORCE_QC_SMASK_CONFLICT(x) (((x) & 0x1) << 15)
5284 #define G_02800C_FORCE_QC_SMASK_CONFLICT(x) (((x) >> 15) & 0x1)
5285 #define C_02800C_FORCE_QC_SMASK_CONFLICT 0xFFFF7FFF
5286 #define S_02800C_DISABLE_VIEWPORT_CLAMP(x) (((x) & 0x1) << 16)
5287 #define G_02800C_DISABLE_VIEWPORT_CLAMP(x) (((x) >> 16) & 0x1)
5288 #define C_02800C_DISABLE_VIEWPORT_CLAMP 0xFFFEFFFF
5289 #define S_02800C_IGNORE_SC_ZRANGE(x) (((x) & 0x1) << 17)
5290 #define G_02800C_IGNORE_SC_ZRANGE(x) (((x) >> 17) & 0x1)
5291 #define C_02800C_IGNORE_SC_ZRANGE 0xFFFDFFFF
5292 #define S_02800C_DISABLE_FULLY_COVERED(x) (((x) & 0x1) << 18)
5293 #define G_02800C_DISABLE_FULLY_COVERED(x) (((x) >> 18) & 0x1)
5294 #define C_02800C_DISABLE_FULLY_COVERED 0xFFFBFFFF
5295 #define S_02800C_FORCE_Z_LIMIT_SUMM(x) (((x) & 0x03) << 19)
5296 #define G_02800C_FORCE_Z_LIMIT_SUMM(x) (((x) >> 19) & 0x03)
5297 #define C_02800C_FORCE_Z_LIMIT_SUMM 0xFFE7FFFF
5298 #define V_02800C_FORCE_SUMM_OFF 0x00
5299 #define V_02800C_FORCE_SUMM_MINZ 0x01
5300 #define V_02800C_FORCE_SUMM_MAXZ 0x02
5301 #define V_02800C_FORCE_SUMM_BOTH 0x03
5302 #define S_02800C_MAX_TILES_IN_DTT(x) (((x) & 0x1F) << 21)
5303 #define G_02800C_MAX_TILES_IN_DTT(x) (((x) >> 21) & 0x1F)
5304 #define C_02800C_MAX_TILES_IN_DTT 0xFC1FFFFF
5305 #define S_02800C_DISABLE_TILE_RATE_TILES(x) (((x) & 0x1) << 26)
5306 #define G_02800C_DISABLE_TILE_RATE_TILES(x) (((x) >> 26) & 0x1)
5307 #define C_02800C_DISABLE_TILE_RATE_TILES 0xFBFFFFFF
5308 #define S_02800C_FORCE_Z_DIRTY(x) (((x) & 0x1) << 27)
5309 #define G_02800C_FORCE_Z_DIRTY(x) (((x) >> 27) & 0x1)
5310 #define C_02800C_FORCE_Z_DIRTY 0xF7FFFFFF
5311 #define S_02800C_FORCE_STENCIL_DIRTY(x) (((x) & 0x1) << 28)
5312 #define G_02800C_FORCE_STENCIL_DIRTY(x) (((x) >> 28) & 0x1)
5313 #define C_02800C_FORCE_STENCIL_DIRTY 0xEFFFFFFF
5314 #define S_02800C_FORCE_Z_VALID(x) (((x) & 0x1) << 29)
5315 #define G_02800C_FORCE_Z_VALID(x) (((x) >> 29) & 0x1)
5316 #define C_02800C_FORCE_Z_VALID 0xDFFFFFFF
5317 #define S_02800C_FORCE_STENCIL_VALID(x) (((x) & 0x1) << 30)
5318 #define G_02800C_FORCE_STENCIL_VALID(x) (((x) >> 30) & 0x1)
5319 #define C_02800C_FORCE_STENCIL_VALID 0xBFFFFFFF
5320 #define S_02800C_PRESERVE_COMPRESSION(x) (((x) & 0x1) << 31)
5321 #define G_02800C_PRESERVE_COMPRESSION(x) (((x) >> 31) & 0x1)
5322 #define C_02800C_PRESERVE_COMPRESSION 0x7FFFFFFF
5323 #define R_028010_DB_RENDER_OVERRIDE2 0x028010
5324 #define S_028010_PARTIAL_SQUAD_LAUNCH_CONTROL(x) (((x) & 0x03) << 0)
5325 #define G_028010_PARTIAL_SQUAD_LAUNCH_CONTROL(x) (((x) >> 0) & 0x03)
5326 #define C_028010_PARTIAL_SQUAD_LAUNCH_CONTROL 0xFFFFFFFC
5327 #define V_028010_PSLC_AUTO 0x00
5328 #define V_028010_PSLC_ON_HANG_ONLY 0x01
5329 #define V_028010_PSLC_ASAP 0x02
5330 #define V_028010_PSLC_COUNTDOWN 0x03
5331 #define S_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN(x) (((x) & 0x07) << 2)
5332 #define G_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN(x) (((x) >> 2) & 0x07)
5333 #define C_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN 0xFFFFFFE3
5334 #define S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(x) (((x) & 0x1) << 5)
5335 #define G_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(x) (((x) >> 5) & 0x1)
5336 #define C_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION 0xFFFFFFDF
5337 #define S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(x) (((x) & 0x1) << 6)
5338 #define G_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(x) (((x) >> 6) & 0x1)
5339 #define C_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION 0xFFFFFFBF
5340 #define S_028010_DISABLE_COLOR_ON_VALIDATION(x) (((x) & 0x1) << 7)
5341 #define G_028010_DISABLE_COLOR_ON_VALIDATION(x) (((x) >> 7) & 0x1)
5342 #define C_028010_DISABLE_COLOR_ON_VALIDATION 0xFFFFFF7F
5343 #define S_028010_DECOMPRESS_Z_ON_FLUSH(x) (((x) & 0x1) << 8)
5344 #define G_028010_DECOMPRESS_Z_ON_FLUSH(x) (((x) >> 8) & 0x1)
5345 #define C_028010_DECOMPRESS_Z_ON_FLUSH 0xFFFFFEFF
5346 #define S_028010_DISABLE_REG_SNOOP(x) (((x) & 0x1) << 9)
5347 #define G_028010_DISABLE_REG_SNOOP(x) (((x) >> 9) & 0x1)
5348 #define C_028010_DISABLE_REG_SNOOP 0xFFFFFDFF
5349 #define S_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE(x) (((x) & 0x1) << 10)
5350 #define G_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE(x) (((x) >> 10) & 0x1)
5351 #define C_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE 0xFFFFFBFF
5352 /* CIK */
5353 #define S_028010_SEPARATE_HIZS_FUNC_ENABLE(x) (((x) & 0x1) << 11)
5354 #define G_028010_SEPARATE_HIZS_FUNC_ENABLE(x) (((x) >> 11) & 0x1)
5355 #define C_028010_SEPARATE_HIZS_FUNC_ENABLE 0xFFFFF7FF
5356 #define S_028010_HIZ_ZFUNC(x) (((x) & 0x07) << 12)
5357 #define G_028010_HIZ_ZFUNC(x) (((x) >> 12) & 0x07)
5358 #define C_028010_HIZ_ZFUNC 0xFFFF8FFF
5359 #define S_028010_HIS_SFUNC_FF(x) (((x) & 0x07) << 15)
5360 #define G_028010_HIS_SFUNC_FF(x) (((x) >> 15) & 0x07)
5361 #define C_028010_HIS_SFUNC_FF 0xFFFC7FFF
5362 #define S_028010_HIS_SFUNC_BF(x) (((x) & 0x07) << 18)
5363 #define G_028010_HIS_SFUNC_BF(x) (((x) >> 18) & 0x07)
5364 #define C_028010_HIS_SFUNC_BF 0xFFE3FFFF
5365 #define S_028010_PRESERVE_ZRANGE(x) (((x) & 0x1) << 21)
5366 #define G_028010_PRESERVE_ZRANGE(x) (((x) >> 21) & 0x1)
5367 #define C_028010_PRESERVE_ZRANGE 0xFFDFFFFF
5368 #define S_028010_PRESERVE_SRESULTS(x) (((x) & 0x1) << 22)
5369 #define G_028010_PRESERVE_SRESULTS(x) (((x) >> 22) & 0x1)
5370 #define C_028010_PRESERVE_SRESULTS 0xFFBFFFFF
5371 #define S_028010_DISABLE_FAST_PASS(x) (((x) & 0x1) << 23)
5372 #define G_028010_DISABLE_FAST_PASS(x) (((x) >> 23) & 0x1)
5373 #define C_028010_DISABLE_FAST_PASS 0xFF7FFFFF
5374 /* */
5375 #define R_028014_DB_HTILE_DATA_BASE 0x028014
5376 #define R_028020_DB_DEPTH_BOUNDS_MIN 0x028020
5377 #define R_028024_DB_DEPTH_BOUNDS_MAX 0x028024
5378 #define R_028028_DB_STENCIL_CLEAR 0x028028
5379 #define S_028028_CLEAR(x) (((x) & 0xFF) << 0)
5380 #define G_028028_CLEAR(x) (((x) >> 0) & 0xFF)
5381 #define C_028028_CLEAR 0xFFFFFF00
5382 #define R_02802C_DB_DEPTH_CLEAR 0x02802C
5383 #define R_028030_PA_SC_SCREEN_SCISSOR_TL 0x028030
5384 #define S_028030_TL_X(x) (((x) & 0xFFFF) << 0)
5385 #define G_028030_TL_X(x) (((x) >> 0) & 0xFFFF)
5386 #define C_028030_TL_X 0xFFFF0000
5387 #define S_028030_TL_Y(x) (((x) & 0xFFFF) << 16)
5388 #define G_028030_TL_Y(x) (((x) >> 16) & 0xFFFF)
5389 #define C_028030_TL_Y 0x0000FFFF
5390 #define R_028034_PA_SC_SCREEN_SCISSOR_BR 0x028034
5391 #define S_028034_BR_X(x) (((x) & 0xFFFF) << 0)
5392 #define G_028034_BR_X(x) (((x) >> 0) & 0xFFFF)
5393 #define C_028034_BR_X 0xFFFF0000
5394 #define S_028034_BR_Y(x) (((x) & 0xFFFF) << 16)
5395 #define G_028034_BR_Y(x) (((x) >> 16) & 0xFFFF)
5396 #define C_028034_BR_Y 0x0000FFFF
5397 #define R_02803C_DB_DEPTH_INFO 0x02803C
5398 #define S_02803C_ADDR5_SWIZZLE_MASK(x) (((x) & 0x0F) << 0)
5399 #define G_02803C_ADDR5_SWIZZLE_MASK(x) (((x) >> 0) & 0x0F)
5400 #define C_02803C_ADDR5_SWIZZLE_MASK 0xFFFFFFF0
5401 /* CIK */
5402 #define S_02803C_ARRAY_MODE(x) (((x) & 0x0F) << 4)
5403 #define G_02803C_ARRAY_MODE(x) (((x) >> 4) & 0x0F)
5404 #define C_02803C_ARRAY_MODE 0xFFFFFF0F
5405 #define V_02803C_ARRAY_LINEAR_GENERAL 0x00
5406 #define V_02803C_ARRAY_LINEAR_ALIGNED 0x01
5407 #define V_02803C_ARRAY_1D_TILED_THIN1 0x02
5408 #define V_02803C_ARRAY_2D_TILED_THIN1 0x04
5409 #define V_02803C_ARRAY_PRT_TILED_THIN1 0x05
5410 #define V_02803C_ARRAY_PRT_2D_TILED_THIN1 0x06
5411 #define S_02803C_PIPE_CONFIG(x) (((x) & 0x1F) << 8)
5412 #define G_02803C_PIPE_CONFIG(x) (((x) >> 8) & 0x1F)
5413 #define C_02803C_PIPE_CONFIG 0xFFFFE0FF
5414 #define V_02803C_ADDR_SURF_P2 0x00
5415 #define V_02803C_X_ADDR_SURF_P4_8X16 0x04
5416 #define V_02803C_X_ADDR_SURF_P4_16X16 0x05
5417 #define V_02803C_X_ADDR_SURF_P4_16X32 0x06
5418 #define V_02803C_X_ADDR_SURF_P4_32X32 0x07
5419 #define V_02803C_X_ADDR_SURF_P8_16X16_8X16 0x08
5420 #define V_02803C_X_ADDR_SURF_P8_16X32_8X16 0x09
5421 #define V_02803C_X_ADDR_SURF_P8_32X32_8X16 0x0A
5422 #define V_02803C_X_ADDR_SURF_P8_16X32_16X16 0x0B
5423 #define V_02803C_X_ADDR_SURF_P8_32X32_16X16 0x0C
5424 #define V_02803C_X_ADDR_SURF_P8_32X32_16X32 0x0D
5425 #define V_02803C_X_ADDR_SURF_P8_32X64_32X32 0x0E
5426 #define V_02803C_X_ADDR_SURF_P16_32X32_8X16 0x10
5427 #define V_02803C_X_ADDR_SURF_P16_32X32_16X16 0x11
5428 #define S_02803C_BANK_WIDTH(x) (((x) & 0x03) << 13)
5429 #define G_02803C_BANK_WIDTH(x) (((x) >> 13) & 0x03)
5430 #define C_02803C_BANK_WIDTH 0xFFFF9FFF
5431 #define V_02803C_ADDR_SURF_BANK_WIDTH_1 0x00
5432 #define V_02803C_ADDR_SURF_BANK_WIDTH_2 0x01
5433 #define V_02803C_ADDR_SURF_BANK_WIDTH_4 0x02
5434 #define V_02803C_ADDR_SURF_BANK_WIDTH_8 0x03
5435 #define S_02803C_BANK_HEIGHT(x) (((x) & 0x03) << 15)
5436 #define G_02803C_BANK_HEIGHT(x) (((x) >> 15) & 0x03)
5437 #define C_02803C_BANK_HEIGHT 0xFFFE7FFF
5438 #define V_02803C_ADDR_SURF_BANK_HEIGHT_1 0x00
5439 #define V_02803C_ADDR_SURF_BANK_HEIGHT_2 0x01
5440 #define V_02803C_ADDR_SURF_BANK_HEIGHT_4 0x02
5441 #define V_02803C_ADDR_SURF_BANK_HEIGHT_8 0x03
5442 #define S_02803C_MACRO_TILE_ASPECT(x) (((x) & 0x03) << 17)
5443 #define G_02803C_MACRO_TILE_ASPECT(x) (((x) >> 17) & 0x03)
5444 #define C_02803C_MACRO_TILE_ASPECT 0xFFF9FFFF
5445 #define V_02803C_ADDR_SURF_MACRO_ASPECT_1 0x00
5446 #define V_02803C_ADDR_SURF_MACRO_ASPECT_2 0x01
5447 #define V_02803C_ADDR_SURF_MACRO_ASPECT_4 0x02
5448 #define V_02803C_ADDR_SURF_MACRO_ASPECT_8 0x03
5449 #define S_02803C_NUM_BANKS(x) (((x) & 0x03) << 19)
5450 #define G_02803C_NUM_BANKS(x) (((x) >> 19) & 0x03)
5451 #define C_02803C_NUM_BANKS 0xFFE7FFFF
5452 #define V_02803C_ADDR_SURF_2_BANK 0x00
5453 #define V_02803C_ADDR_SURF_4_BANK 0x01
5454 #define V_02803C_ADDR_SURF_8_BANK 0x02
5455 #define V_02803C_ADDR_SURF_16_BANK 0x03
5456 /* */
5457 #define R_028040_DB_Z_INFO 0x028040
5458 #define S_028040_FORMAT(x) (((x) & 0x03) << 0)
5459 #define G_028040_FORMAT(x) (((x) >> 0) & 0x03)
5460 #define C_028040_FORMAT 0xFFFFFFFC
5461 #define V_028040_Z_INVALID 0x00
5462 #define V_028040_Z_16 0x01
5463 #define V_028040_Z_24 0x02 /* deprecated */
5464 #define V_028040_Z_32_FLOAT 0x03
5465 #define S_028040_NUM_SAMPLES(x) (((x) & 0x03) << 2)
5466 #define G_028040_NUM_SAMPLES(x) (((x) >> 2) & 0x03)
5467 #define C_028040_NUM_SAMPLES 0xFFFFFFF3
5468 #define S_028040_TILE_MODE_INDEX(x) (((x) & 0x07) << 20) /* not on CIK */
5469 #define G_028040_TILE_MODE_INDEX(x) (((x) >> 20) & 0x07) /* not on CIK */
5470 #define C_028040_TILE_MODE_INDEX 0xFF8FFFFF /* not on CIK */
5471 /* CIK */
5472 #define S_028040_TILE_SPLIT(x) (((x) & 0x07) << 13)
5473 #define G_028040_TILE_SPLIT(x) (((x) >> 13) & 0x07)
5474 #define C_028040_TILE_SPLIT 0xFFFF1FFF
5475 #define V_028040_ADDR_SURF_TILE_SPLIT_64B 0x00
5476 #define V_028040_ADDR_SURF_TILE_SPLIT_128B 0x01
5477 #define V_028040_ADDR_SURF_TILE_SPLIT_256B 0x02
5478 #define V_028040_ADDR_SURF_TILE_SPLIT_512B 0x03
5479 #define V_028040_ADDR_SURF_TILE_SPLIT_1KB 0x04
5480 #define V_028040_ADDR_SURF_TILE_SPLIT_2KB 0x05
5481 #define V_028040_ADDR_SURF_TILE_SPLIT_4KB 0x06
5482 /* */
5483 #define S_028040_ALLOW_EXPCLEAR(x) (((x) & 0x1) << 27)
5484 #define G_028040_ALLOW_EXPCLEAR(x) (((x) >> 27) & 0x1)
5485 #define C_028040_ALLOW_EXPCLEAR 0xF7FFFFFF
5486 #define S_028040_READ_SIZE(x) (((x) & 0x1) << 28)
5487 #define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1)
5488 #define C_028040_READ_SIZE 0xEFFFFFFF
5489 #define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29)
5490 #define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1)
5491 #define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF
5492 #define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
5493 #define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
5494 #define C_028040_ZRANGE_PRECISION 0x7FFFFFFF
5495 #define R_028044_DB_STENCIL_INFO 0x028044
5496 #define S_028044_FORMAT(x) (((x) & 0x1) << 0)
5497 #define G_028044_FORMAT(x) (((x) >> 0) & 0x1)
5498 #define C_028044_FORMAT 0xFFFFFFFE
5499 #define V_028044_STENCIL_INVALID 0x00
5500 #define V_028044_STENCIL_8 0x01
5501 #define S_028044_TILE_MODE_INDEX(x) (((x) & 0x07) << 20) /* not on CIK */
5502 #define G_028044_TILE_MODE_INDEX(x) (((x) >> 20) & 0x07) /* not on CIK */
5503 #define C_028044_TILE_MODE_INDEX 0xFF8FFFFF /* not on CIK */
5504 /* CIK */
5505 #define S_028044_TILE_SPLIT(x) (((x) & 0x07) << 13)
5506 #define G_028044_TILE_SPLIT(x) (((x) >> 13) & 0x07)
5507 #define C_028044_TILE_SPLIT 0xFFFF1FFF
5508 #define V_028044_ADDR_SURF_TILE_SPLIT_64B 0x00
5509 #define V_028044_ADDR_SURF_TILE_SPLIT_128B 0x01
5510 #define V_028044_ADDR_SURF_TILE_SPLIT_256B 0x02
5511 #define V_028044_ADDR_SURF_TILE_SPLIT_512B 0x03
5512 #define V_028044_ADDR_SURF_TILE_SPLIT_1KB 0x04
5513 #define V_028044_ADDR_SURF_TILE_SPLIT_2KB 0x05
5514 #define V_028044_ADDR_SURF_TILE_SPLIT_4KB 0x06
5515 /* */
5516 #define S_028044_ALLOW_EXPCLEAR(x) (((x) & 0x1) << 27)
5517 #define G_028044_ALLOW_EXPCLEAR(x) (((x) >> 27) & 0x1)
5518 #define C_028044_ALLOW_EXPCLEAR 0xF7FFFFFF
5519 #define S_028044_TILE_STENCIL_DISABLE(x) (((x) & 0x1) << 29)
5520 #define G_028044_TILE_STENCIL_DISABLE(x) (((x) >> 29) & 0x1)
5521 #define C_028044_TILE_STENCIL_DISABLE 0xDFFFFFFF
5522 #define R_028048_DB_Z_READ_BASE 0x028048
5523 #define R_02804C_DB_STENCIL_READ_BASE 0x02804C
5524 #define R_028050_DB_Z_WRITE_BASE 0x028050
5525 #define R_028054_DB_STENCIL_WRITE_BASE 0x028054
5526 #define R_028058_DB_DEPTH_SIZE 0x028058
5527 #define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0)
5528 #define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF)
5529 #define C_028058_PITCH_TILE_MAX 0xFFFFF800
5530 #define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11)
5531 #define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF)
5532 #define C_028058_HEIGHT_TILE_MAX 0xFFC007FF
5533 #define R_02805C_DB_DEPTH_SLICE 0x02805C
5534 #define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0)
5535 #define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF)
5536 #define C_02805C_SLICE_TILE_MAX 0xFFC00000
5537 #define R_028080_TA_BC_BASE_ADDR 0x028080
5538 /* CIK */
5539 #define R_028084_TA_BC_BASE_ADDR_HI 0x028084
5540 #define S_028084_ADDRESS(x) (((x) & 0xFF) << 0)
5541 #define G_028084_ADDRESS(x) (((x) >> 0) & 0xFF)
5542 #define C_028084_ADDRESS 0xFFFFFF00
5543 /* */
5544 #define R_028200_PA_SC_WINDOW_OFFSET 0x028200
5545 #define S_028200_WINDOW_X_OFFSET(x) (((x) & 0xFFFF) << 0)
5546 #define G_028200_WINDOW_X_OFFSET(x) (((x) >> 0) & 0xFFFF)
5547 #define C_028200_WINDOW_X_OFFSET 0xFFFF0000
5548 #define S_028200_WINDOW_Y_OFFSET(x) (((x) & 0xFFFF) << 16)
5549 #define G_028200_WINDOW_Y_OFFSET(x) (((x) >> 16) & 0xFFFF)
5550 #define C_028200_WINDOW_Y_OFFSET 0x0000FFFF
5551 #define R_028204_PA_SC_WINDOW_SCISSOR_TL 0x028204
5552 #define S_028204_TL_X(x) (((x) & 0x7FFF) << 0)
5553 #define G_028204_TL_X(x) (((x) >> 0) & 0x7FFF)
5554 #define C_028204_TL_X 0xFFFF8000
5555 #define S_028204_TL_Y(x) (((x) & 0x7FFF) << 16)
5556 #define G_028204_TL_Y(x) (((x) >> 16) & 0x7FFF)
5557 #define C_028204_TL_Y 0x8000FFFF
5558 #define S_028204_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31)
5559 #define G_028204_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1)
5560 #define C_028204_WINDOW_OFFSET_DISABLE 0x7FFFFFFF
5561 #define R_028208_PA_SC_WINDOW_SCISSOR_BR 0x028208
5562 #define S_028208_BR_X(x) (((x) & 0x7FFF) << 0)
5563 #define G_028208_BR_X(x) (((x) >> 0) & 0x7FFF)
5564 #define C_028208_BR_X 0xFFFF8000
5565 #define S_028208_BR_Y(x) (((x) & 0x7FFF) << 16)
5566 #define G_028208_BR_Y(x) (((x) >> 16) & 0x7FFF)
5567 #define C_028208_BR_Y 0x8000FFFF
5568 #define R_02820C_PA_SC_CLIPRECT_RULE 0x02820C
5569 #define S_02820C_CLIP_RULE(x) (((x) & 0xFFFF) << 0)
5570 #define G_02820C_CLIP_RULE(x) (((x) >> 0) & 0xFFFF)
5571 #define C_02820C_CLIP_RULE 0xFFFF0000
5572 #define R_028210_PA_SC_CLIPRECT_0_TL 0x028210
5573 #define S_028210_TL_X(x) (((x) & 0x7FFF) << 0)
5574 #define G_028210_TL_X(x) (((x) >> 0) & 0x7FFF)
5575 #define C_028210_TL_X 0xFFFF8000
5576 #define S_028210_TL_Y(x) (((x) & 0x7FFF) << 16)
5577 #define G_028210_TL_Y(x) (((x) >> 16) & 0x7FFF)
5578 #define C_028210_TL_Y 0x8000FFFF
5579 #define R_028214_PA_SC_CLIPRECT_0_BR 0x028214
5580 #define S_028214_BR_X(x) (((x) & 0x7FFF) << 0)
5581 #define G_028214_BR_X(x) (((x) >> 0) & 0x7FFF)
5582 #define C_028214_BR_X 0xFFFF8000
5583 #define S_028214_BR_Y(x) (((x) & 0x7FFF) << 16)
5584 #define G_028214_BR_Y(x) (((x) >> 16) & 0x7FFF)
5585 #define C_028214_BR_Y 0x8000FFFF
5586 #define R_028218_PA_SC_CLIPRECT_1_TL 0x028218
5587 #define R_02821C_PA_SC_CLIPRECT_1_BR 0x02821C
5588 #define R_028220_PA_SC_CLIPRECT_2_TL 0x028220
5589 #define R_028224_PA_SC_CLIPRECT_2_BR 0x028224
5590 #define R_028228_PA_SC_CLIPRECT_3_TL 0x028228
5591 #define R_02822C_PA_SC_CLIPRECT_3_BR 0x02822C
5592 #define R_028230_PA_SC_EDGERULE 0x028230
5593 #define S_028230_ER_TRI(x) (((x) & 0x0F) << 0)
5594 #define G_028230_ER_TRI(x) (((x) >> 0) & 0x0F)
5595 #define C_028230_ER_TRI 0xFFFFFFF0
5596 #define S_028230_ER_POINT(x) (((x) & 0x0F) << 4)
5597 #define G_028230_ER_POINT(x) (((x) >> 4) & 0x0F)
5598 #define C_028230_ER_POINT 0xFFFFFF0F
5599 #define S_028230_ER_RECT(x) (((x) & 0x0F) << 8)
5600 #define G_028230_ER_RECT(x) (((x) >> 8) & 0x0F)
5601 #define C_028230_ER_RECT 0xFFFFF0FF
5602 #define S_028230_ER_LINE_LR(x) (((x) & 0x3F) << 12)
5603 #define G_028230_ER_LINE_LR(x) (((x) >> 12) & 0x3F)
5604 #define C_028230_ER_LINE_LR 0xFFFC0FFF
5605 #define S_028230_ER_LINE_RL(x) (((x) & 0x3F) << 18)
5606 #define G_028230_ER_LINE_RL(x) (((x) >> 18) & 0x3F)
5607 #define C_028230_ER_LINE_RL 0xFF03FFFF
5608 #define S_028230_ER_LINE_TB(x) (((x) & 0x0F) << 24)
5609 #define G_028230_ER_LINE_TB(x) (((x) >> 24) & 0x0F)
5610 #define C_028230_ER_LINE_TB 0xF0FFFFFF
5611 #define S_028230_ER_LINE_BT(x) (((x) & 0x0F) << 28)
5612 #define G_028230_ER_LINE_BT(x) (((x) >> 28) & 0x0F)
5613 #define C_028230_ER_LINE_BT 0x0FFFFFFF
5614 #define R_028234_PA_SU_HARDWARE_SCREEN_OFFSET 0x028234
5615 #define S_028234_HW_SCREEN_OFFSET_X(x) (((x) & 0x1FF) << 0)
5616 #define G_028234_HW_SCREEN_OFFSET_X(x) (((x) >> 0) & 0x1FF)
5617 #define C_028234_HW_SCREEN_OFFSET_X 0xFFFFFE00
5618 #define S_028234_HW_SCREEN_OFFSET_Y(x) (((x) & 0x1FF) << 16)
5619 #define G_028234_HW_SCREEN_OFFSET_Y(x) (((x) >> 16) & 0x1FF)
5620 #define C_028234_HW_SCREEN_OFFSET_Y 0xFE00FFFF
5621 #define R_028238_CB_TARGET_MASK 0x028238
5622 #define S_028238_TARGET0_ENABLE(x) (((x) & 0x0F) << 0)
5623 #define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0x0F)
5624 #define C_028238_TARGET0_ENABLE 0xFFFFFFF0
5625 #define S_028238_TARGET1_ENABLE(x) (((x) & 0x0F) << 4)
5626 #define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0x0F)
5627 #define C_028238_TARGET1_ENABLE 0xFFFFFF0F
5628 #define S_028238_TARGET2_ENABLE(x) (((x) & 0x0F) << 8)
5629 #define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0x0F)
5630 #define C_028238_TARGET2_ENABLE 0xFFFFF0FF
5631 #define S_028238_TARGET3_ENABLE(x) (((x) & 0x0F) << 12)
5632 #define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0x0F)
5633 #define C_028238_TARGET3_ENABLE 0xFFFF0FFF
5634 #define S_028238_TARGET4_ENABLE(x) (((x) & 0x0F) << 16)
5635 #define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0x0F)
5636 #define C_028238_TARGET4_ENABLE 0xFFF0FFFF
5637 #define S_028238_TARGET5_ENABLE(x) (((x) & 0x0F) << 20)
5638 #define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0x0F)
5639 #define C_028238_TARGET5_ENABLE 0xFF0FFFFF
5640 #define S_028238_TARGET6_ENABLE(x) (((x) & 0x0F) << 24)
5641 #define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0x0F)
5642 #define C_028238_TARGET6_ENABLE 0xF0FFFFFF
5643 #define S_028238_TARGET7_ENABLE(x) (((x) & 0x0F) << 28)
5644 #define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0x0F)
5645 #define C_028238_TARGET7_ENABLE 0x0FFFFFFF
5646 #define R_02823C_CB_SHADER_MASK 0x02823C
5647 #define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0x0F) << 0)
5648 #define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0x0F)
5649 #define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0
5650 #define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0x0F) << 4)
5651 #define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0x0F)
5652 #define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F
5653 #define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0x0F) << 8)
5654 #define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0x0F)
5655 #define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF
5656 #define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0x0F) << 12)
5657 #define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0x0F)
5658 #define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF
5659 #define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0x0F) << 16)
5660 #define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0x0F)
5661 #define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF
5662 #define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0x0F) << 20)
5663 #define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0x0F)
5664 #define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF
5665 #define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0x0F) << 24)
5666 #define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0x0F)
5667 #define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF
5668 #define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0x0F) << 28)
5669 #define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0x0F)
5670 #define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF
5671 #define R_028240_PA_SC_GENERIC_SCISSOR_TL 0x028240
5672 #define S_028240_TL_X(x) (((x) & 0x7FFF) << 0)
5673 #define G_028240_TL_X(x) (((x) >> 0) & 0x7FFF)
5674 #define C_028240_TL_X 0xFFFF8000
5675 #define S_028240_TL_Y(x) (((x) & 0x7FFF) << 16)
5676 #define G_028240_TL_Y(x) (((x) >> 16) & 0x7FFF)
5677 #define C_028240_TL_Y 0x8000FFFF
5678 #define S_028240_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31)
5679 #define G_028240_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1)
5680 #define C_028240_WINDOW_OFFSET_DISABLE 0x7FFFFFFF
5681 #define R_028244_PA_SC_GENERIC_SCISSOR_BR 0x028244
5682 #define S_028244_BR_X(x) (((x) & 0x7FFF) << 0)
5683 #define G_028244_BR_X(x) (((x) >> 0) & 0x7FFF)
5684 #define C_028244_BR_X 0xFFFF8000
5685 #define S_028244_BR_Y(x) (((x) & 0x7FFF) << 16)
5686 #define G_028244_BR_Y(x) (((x) >> 16) & 0x7FFF)
5687 #define C_028244_BR_Y 0x8000FFFF
5688 #define R_028250_PA_SC_VPORT_SCISSOR_0_TL 0x028250
5689 #define S_028250_TL_X(x) (((x) & 0x7FFF) << 0)
5690 #define G_028250_TL_X(x) (((x) >> 0) & 0x7FFF)
5691 #define C_028250_TL_X 0xFFFF8000
5692 #define S_028250_TL_Y(x) (((x) & 0x7FFF) << 16)
5693 #define G_028250_TL_Y(x) (((x) >> 16) & 0x7FFF)
5694 #define C_028250_TL_Y 0x8000FFFF
5695 #define S_028250_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31)
5696 #define G_028250_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1)
5697 #define C_028250_WINDOW_OFFSET_DISABLE 0x7FFFFFFF
5698 #define R_028254_PA_SC_VPORT_SCISSOR_0_BR 0x028254
5699 #define S_028254_BR_X(x) (((x) & 0x7FFF) << 0)
5700 #define G_028254_BR_X(x) (((x) >> 0) & 0x7FFF)
5701 #define C_028254_BR_X 0xFFFF8000
5702 #define S_028254_BR_Y(x) (((x) & 0x7FFF) << 16)
5703 #define G_028254_BR_Y(x) (((x) >> 16) & 0x7FFF)
5704 #define C_028254_BR_Y 0x8000FFFF
5705 #define R_0282D0_PA_SC_VPORT_ZMIN_0 0x0282D0
5706 #define R_0282D4_PA_SC_VPORT_ZMAX_0 0x0282D4
5707 #define R_028350_PA_SC_RASTER_CONFIG 0x028350
5708 #define S_028350_RB_MAP_PKR0(x) (((x) & 0x03) << 0)
5709 #define G_028350_RB_MAP_PKR0(x) (((x) >> 0) & 0x03)
5710 #define C_028350_RB_MAP_PKR0 0xFFFFFFFC
5711 #define V_028350_RASTER_CONFIG_RB_MAP_0 0x00
5712 #define V_028350_RASTER_CONFIG_RB_MAP_1 0x01
5713 #define V_028350_RASTER_CONFIG_RB_MAP_2 0x02
5714 #define V_028350_RASTER_CONFIG_RB_MAP_3 0x03
5715 #define S_028350_RB_MAP_PKR1(x) (((x) & 0x03) << 2)
5716 #define G_028350_RB_MAP_PKR1(x) (((x) >> 2) & 0x03)
5717 #define C_028350_RB_MAP_PKR1 0xFFFFFFF3
5718 #define V_028350_RASTER_CONFIG_RB_MAP_0 0x00
5719 #define V_028350_RASTER_CONFIG_RB_MAP_1 0x01
5720 #define V_028350_RASTER_CONFIG_RB_MAP_2 0x02
5721 #define V_028350_RASTER_CONFIG_RB_MAP_3 0x03
5722 #define S_028350_RB_XSEL2(x) (((x) & 0x03) << 4)
5723 #define G_028350_RB_XSEL2(x) (((x) >> 4) & 0x03)
5724 #define C_028350_RB_XSEL2 0xFFFFFFCF
5725 #define V_028350_RASTER_CONFIG_RB_XSEL2_0 0x00
5726 #define V_028350_RASTER_CONFIG_RB_XSEL2_1 0x01
5727 #define V_028350_RASTER_CONFIG_RB_XSEL2_2 0x02
5728 #define V_028350_RASTER_CONFIG_RB_XSEL2_3 0x03
5729 #define S_028350_RB_XSEL(x) (((x) & 0x1) << 6)
5730 #define G_028350_RB_XSEL(x) (((x) >> 6) & 0x1)
5731 #define C_028350_RB_XSEL 0xFFFFFFBF
5732 #define S_028350_RB_YSEL(x) (((x) & 0x1) << 7)
5733 #define G_028350_RB_YSEL(x) (((x) >> 7) & 0x1)
5734 #define C_028350_RB_YSEL 0xFFFFFF7F
5735 #define S_028350_PKR_MAP(x) (((x) & 0x03) << 8)
5736 #define G_028350_PKR_MAP(x) (((x) >> 8) & 0x03)
5737 #define C_028350_PKR_MAP 0xFFFFFCFF
5738 #define V_028350_RASTER_CONFIG_PKR_MAP_0 0x00
5739 #define V_028350_RASTER_CONFIG_PKR_MAP_1 0x01
5740 #define V_028350_RASTER_CONFIG_PKR_MAP_2 0x02
5741 #define V_028350_RASTER_CONFIG_PKR_MAP_3 0x03
5742 #define S_028350_PKR_XSEL(x) (((x) & 0x03) << 10)
5743 #define G_028350_PKR_XSEL(x) (((x) >> 10) & 0x03)
5744 #define C_028350_PKR_XSEL 0xFFFFF3FF
5745 #define V_028350_RASTER_CONFIG_PKR_XSEL_0 0x00
5746 #define V_028350_RASTER_CONFIG_PKR_XSEL_1 0x01
5747 #define V_028350_RASTER_CONFIG_PKR_XSEL_2 0x02
5748 #define V_028350_RASTER_CONFIG_PKR_XSEL_3 0x03
5749 #define S_028350_PKR_YSEL(x) (((x) & 0x03) << 12)
5750 #define G_028350_PKR_YSEL(x) (((x) >> 12) & 0x03)
5751 #define C_028350_PKR_YSEL 0xFFFFCFFF
5752 #define V_028350_RASTER_CONFIG_PKR_YSEL_0 0x00
5753 #define V_028350_RASTER_CONFIG_PKR_YSEL_1 0x01
5754 #define V_028350_RASTER_CONFIG_PKR_YSEL_2 0x02
5755 #define V_028350_RASTER_CONFIG_PKR_YSEL_3 0x03
5756 #define S_028350_PKR_XSEL2(x) (((x) & 0x03) << 14)
5757 #define G_028350_PKR_XSEL2(x) (((x) >> 14) & 0x03)
5758 #define C_028350_PKR_XSEL2 0xFFFF3FFF
5759 #define V_028350_RASTER_CONFIG_PKR_XSEL2_0 0x00
5760 #define V_028350_RASTER_CONFIG_PKR_XSEL2_1 0x01
5761 #define V_028350_RASTER_CONFIG_PKR_XSEL2_2 0x02
5762 #define V_028350_RASTER_CONFIG_PKR_XSEL2_3 0x03
5763 #define S_028350_SC_MAP(x) (((x) & 0x03) << 16)
5764 #define G_028350_SC_MAP(x) (((x) >> 16) & 0x03)
5765 #define C_028350_SC_MAP 0xFFFCFFFF
5766 #define V_028350_RASTER_CONFIG_SC_MAP_0 0x00
5767 #define V_028350_RASTER_CONFIG_SC_MAP_1 0x01
5768 #define V_028350_RASTER_CONFIG_SC_MAP_2 0x02
5769 #define V_028350_RASTER_CONFIG_SC_MAP_3 0x03
5770 #define S_028350_SC_XSEL(x) (((x) & 0x03) << 18)
5771 #define G_028350_SC_XSEL(x) (((x) >> 18) & 0x03)
5772 #define C_028350_SC_XSEL 0xFFF3FFFF
5773 #define V_028350_RASTER_CONFIG_SC_XSEL_8_WIDE_TILE 0x00
5774 #define V_028350_RASTER_CONFIG_SC_XSEL_16_WIDE_TILE 0x01
5775 #define V_028350_RASTER_CONFIG_SC_XSEL_32_WIDE_TILE 0x02
5776 #define V_028350_RASTER_CONFIG_SC_XSEL_64_WIDE_TILE 0x03
5777 #define S_028350_SC_YSEL(x) (((x) & 0x03) << 20)
5778 #define G_028350_SC_YSEL(x) (((x) >> 20) & 0x03)
5779 #define C_028350_SC_YSEL 0xFFCFFFFF
5780 #define V_028350_RASTER_CONFIG_SC_YSEL_8_WIDE_TILE 0x00
5781 #define V_028350_RASTER_CONFIG_SC_YSEL_16_WIDE_TILE 0x01
5782 #define V_028350_RASTER_CONFIG_SC_YSEL_32_WIDE_TILE 0x02
5783 #define V_028350_RASTER_CONFIG_SC_YSEL_64_WIDE_TILE 0x03
5784 #define S_028350_SE_MAP(x) (((x) & 0x03) << 24)
5785 #define G_028350_SE_MAP(x) (((x) >> 24) & 0x03)
5786 #define C_028350_SE_MAP 0xFCFFFFFF
5787 #define V_028350_RASTER_CONFIG_SE_MAP_0 0x00
5788 #define V_028350_RASTER_CONFIG_SE_MAP_1 0x01
5789 #define V_028350_RASTER_CONFIG_SE_MAP_2 0x02
5790 #define V_028350_RASTER_CONFIG_SE_MAP_3 0x03
5791 #define S_028350_SE_XSEL(x) (((x) & 0x03) << 26)
5792 #define G_028350_SE_XSEL(x) (((x) >> 26) & 0x03)
5793 #define C_028350_SE_XSEL 0xF3FFFFFF
5794 #define V_028350_RASTER_CONFIG_SE_XSEL_8_WIDE_TILE 0x00
5795 #define V_028350_RASTER_CONFIG_SE_XSEL_16_WIDE_TILE 0x01
5796 #define V_028350_RASTER_CONFIG_SE_XSEL_32_WIDE_TILE 0x02
5797 #define V_028350_RASTER_CONFIG_SE_XSEL_64_WIDE_TILE 0x03
5798 #define S_028350_SE_YSEL(x) (((x) & 0x03) << 28)
5799 #define G_028350_SE_YSEL(x) (((x) >> 28) & 0x03)
5800 #define C_028350_SE_YSEL 0xCFFFFFFF
5801 #define V_028350_RASTER_CONFIG_SE_YSEL_8_WIDE_TILE 0x00
5802 #define V_028350_RASTER_CONFIG_SE_YSEL_16_WIDE_TILE 0x01
5803 #define V_028350_RASTER_CONFIG_SE_YSEL_32_WIDE_TILE 0x02
5804 #define V_028350_RASTER_CONFIG_SE_YSEL_64_WIDE_TILE 0x03
5805 /* CIK */
5806 #define R_028354_PA_SC_RASTER_CONFIG_1 0x028354
5807 #define S_028354_SE_PAIR_MAP(x) (((x) & 0x03) << 0)
5808 #define G_028354_SE_PAIR_MAP(x) (((x) >> 0) & 0x03)
5809 #define C_028354_SE_PAIR_MAP 0xFFFFFFFC
5810 #define V_028354_RASTER_CONFIG_SE_PAIR_MAP_0 0x00
5811 #define V_028354_RASTER_CONFIG_SE_PAIR_MAP_1 0x01
5812 #define V_028354_RASTER_CONFIG_SE_PAIR_MAP_2 0x02
5813 #define V_028354_RASTER_CONFIG_SE_PAIR_MAP_3 0x03
5814 #define S_028354_SE_PAIR_XSEL(x) (((x) & 0x03) << 2)
5815 #define G_028354_SE_PAIR_XSEL(x) (((x) >> 2) & 0x03)
5816 #define C_028354_SE_PAIR_XSEL 0xFFFFFFF3
5817 #define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE 0x00
5818 #define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE 0x01
5819 #define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE 0x02
5820 #define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE 0x03
5821 #define S_028354_SE_PAIR_YSEL(x) (((x) & 0x03) << 4)
5822 #define G_028354_SE_PAIR_YSEL(x) (((x) >> 4) & 0x03)
5823 #define C_028354_SE_PAIR_YSEL 0xFFFFFFCF
5824 #define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE 0x00
5825 #define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE 0x01
5826 #define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE 0x02
5827 #define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE 0x03
5828 /* */
5829 #define R_028400_VGT_MAX_VTX_INDX 0x028400
5830 #define R_028404_VGT_MIN_VTX_INDX 0x028404
5831 #define R_028408_VGT_INDX_OFFSET 0x028408
5832 #define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX 0x02840C
5833 #define R_028414_CB_BLEND_RED 0x028414
5834 #define R_028418_CB_BLEND_GREEN 0x028418
5835 #define R_02841C_CB_BLEND_BLUE 0x02841C
5836 #define R_028420_CB_BLEND_ALPHA 0x028420
5837 #define R_02842C_DB_STENCIL_CONTROL 0x02842C
5838 #define S_02842C_STENCILFAIL(x) (((x) & 0x0F) << 0)
5839 #define G_02842C_STENCILFAIL(x) (((x) >> 0) & 0x0F)
5840 #define C_02842C_STENCILFAIL 0xFFFFFFF0
5841 #define V_02842C_STENCIL_KEEP 0x00
5842 #define V_02842C_STENCIL_ZERO 0x01
5843 #define V_02842C_STENCIL_ONES 0x02
5844 #define V_02842C_STENCIL_REPLACE_TEST 0x03
5845 #define V_02842C_STENCIL_REPLACE_OP 0x04
5846 #define V_02842C_STENCIL_ADD_CLAMP 0x05
5847 #define V_02842C_STENCIL_SUB_CLAMP 0x06
5848 #define V_02842C_STENCIL_INVERT 0x07
5849 #define V_02842C_STENCIL_ADD_WRAP 0x08
5850 #define V_02842C_STENCIL_SUB_WRAP 0x09
5851 #define V_02842C_STENCIL_AND 0x0A
5852 #define V_02842C_STENCIL_OR 0x0B
5853 #define V_02842C_STENCIL_XOR 0x0C
5854 #define V_02842C_STENCIL_NAND 0x0D
5855 #define V_02842C_STENCIL_NOR 0x0E
5856 #define V_02842C_STENCIL_XNOR 0x0F
5857 #define S_02842C_STENCILZPASS(x) (((x) & 0x0F) << 4)
5858 #define G_02842C_STENCILZPASS(x) (((x) >> 4) & 0x0F)
5859 #define C_02842C_STENCILZPASS 0xFFFFFF0F
5860 #define V_02842C_STENCIL_KEEP 0x00
5861 #define V_02842C_STENCIL_ZERO 0x01
5862 #define V_02842C_STENCIL_ONES 0x02
5863 #define V_02842C_STENCIL_REPLACE_TEST 0x03
5864 #define V_02842C_STENCIL_REPLACE_OP 0x04
5865 #define V_02842C_STENCIL_ADD_CLAMP 0x05
5866 #define V_02842C_STENCIL_SUB_CLAMP 0x06
5867 #define V_02842C_STENCIL_INVERT 0x07
5868 #define V_02842C_STENCIL_ADD_WRAP 0x08
5869 #define V_02842C_STENCIL_SUB_WRAP 0x09
5870 #define V_02842C_STENCIL_AND 0x0A
5871 #define V_02842C_STENCIL_OR 0x0B
5872 #define V_02842C_STENCIL_XOR 0x0C
5873 #define V_02842C_STENCIL_NAND 0x0D
5874 #define V_02842C_STENCIL_NOR 0x0E
5875 #define V_02842C_STENCIL_XNOR 0x0F
5876 #define S_02842C_STENCILZFAIL(x) (((x) & 0x0F) << 8)
5877 #define G_02842C_STENCILZFAIL(x) (((x) >> 8) & 0x0F)
5878 #define C_02842C_STENCILZFAIL 0xFFFFF0FF
5879 #define V_02842C_STENCIL_KEEP 0x00
5880 #define V_02842C_STENCIL_ZERO 0x01
5881 #define V_02842C_STENCIL_ONES 0x02
5882 #define V_02842C_STENCIL_REPLACE_TEST 0x03
5883 #define V_02842C_STENCIL_REPLACE_OP 0x04
5884 #define V_02842C_STENCIL_ADD_CLAMP 0x05
5885 #define V_02842C_STENCIL_SUB_CLAMP 0x06
5886 #define V_02842C_STENCIL_INVERT 0x07
5887 #define V_02842C_STENCIL_ADD_WRAP 0x08
5888 #define V_02842C_STENCIL_SUB_WRAP 0x09
5889 #define V_02842C_STENCIL_AND 0x0A
5890 #define V_02842C_STENCIL_OR 0x0B
5891 #define V_02842C_STENCIL_XOR 0x0C
5892 #define V_02842C_STENCIL_NAND 0x0D
5893 #define V_02842C_STENCIL_NOR 0x0E
5894 #define V_02842C_STENCIL_XNOR 0x0F
5895 #define S_02842C_STENCILFAIL_BF(x) (((x) & 0x0F) << 12)
5896 #define G_02842C_STENCILFAIL_BF(x) (((x) >> 12) & 0x0F)
5897 #define C_02842C_STENCILFAIL_BF 0xFFFF0FFF
5898 #define V_02842C_STENCIL_KEEP 0x00
5899 #define V_02842C_STENCIL_ZERO 0x01
5900 #define V_02842C_STENCIL_ONES 0x02
5901 #define V_02842C_STENCIL_REPLACE_TEST 0x03
5902 #define V_02842C_STENCIL_REPLACE_OP 0x04
5903 #define V_02842C_STENCIL_ADD_CLAMP 0x05
5904 #define V_02842C_STENCIL_SUB_CLAMP 0x06
5905 #define V_02842C_STENCIL_INVERT 0x07
5906 #define V_02842C_STENCIL_ADD_WRAP 0x08
5907 #define V_02842C_STENCIL_SUB_WRAP 0x09
5908 #define V_02842C_STENCIL_AND 0x0A
5909 #define V_02842C_STENCIL_OR 0x0B
5910 #define V_02842C_STENCIL_XOR 0x0C
5911 #define V_02842C_STENCIL_NAND 0x0D
5912 #define V_02842C_STENCIL_NOR 0x0E
5913 #define V_02842C_STENCIL_XNOR 0x0F
5914 #define S_02842C_STENCILZPASS_BF(x) (((x) & 0x0F) << 16)
5915 #define G_02842C_STENCILZPASS_BF(x) (((x) >> 16) & 0x0F)
5916 #define C_02842C_STENCILZPASS_BF 0xFFF0FFFF
5917 #define V_02842C_STENCIL_KEEP 0x00
5918 #define V_02842C_STENCIL_ZERO 0x01
5919 #define V_02842C_STENCIL_ONES 0x02
5920 #define V_02842C_STENCIL_REPLACE_TEST 0x03
5921 #define V_02842C_STENCIL_REPLACE_OP 0x04
5922 #define V_02842C_STENCIL_ADD_CLAMP 0x05
5923 #define V_02842C_STENCIL_SUB_CLAMP 0x06
5924 #define V_02842C_STENCIL_INVERT 0x07
5925 #define V_02842C_STENCIL_ADD_WRAP 0x08
5926 #define V_02842C_STENCIL_SUB_WRAP 0x09
5927 #define V_02842C_STENCIL_AND 0x0A
5928 #define V_02842C_STENCIL_OR 0x0B
5929 #define V_02842C_STENCIL_XOR 0x0C
5930 #define V_02842C_STENCIL_NAND 0x0D
5931 #define V_02842C_STENCIL_NOR 0x0E
5932 #define V_02842C_STENCIL_XNOR 0x0F
5933 #define S_02842C_STENCILZFAIL_BF(x) (((x) & 0x0F) << 20)
5934 #define G_02842C_STENCILZFAIL_BF(x) (((x) >> 20) & 0x0F)
5935 #define C_02842C_STENCILZFAIL_BF 0xFF0FFFFF
5936 #define V_02842C_STENCIL_KEEP 0x00
5937 #define V_02842C_STENCIL_ZERO 0x01
5938 #define V_02842C_STENCIL_ONES 0x02
5939 #define V_02842C_STENCIL_REPLACE_TEST 0x03
5940 #define V_02842C_STENCIL_REPLACE_OP 0x04
5941 #define V_02842C_STENCIL_ADD_CLAMP 0x05
5942 #define V_02842C_STENCIL_SUB_CLAMP 0x06
5943 #define V_02842C_STENCIL_INVERT 0x07
5944 #define V_02842C_STENCIL_ADD_WRAP 0x08
5945 #define V_02842C_STENCIL_SUB_WRAP 0x09
5946 #define V_02842C_STENCIL_AND 0x0A
5947 #define V_02842C_STENCIL_OR 0x0B
5948 #define V_02842C_STENCIL_XOR 0x0C
5949 #define V_02842C_STENCIL_NAND 0x0D
5950 #define V_02842C_STENCIL_NOR 0x0E
5951 #define V_02842C_STENCIL_XNOR 0x0F
5952 #define R_028430_DB_STENCILREFMASK 0x028430
5953 #define S_028430_STENCILTESTVAL(x) (((x) & 0xFF) << 0)
5954 #define G_028430_STENCILTESTVAL(x) (((x) >> 0) & 0xFF)
5955 #define C_028430_STENCILTESTVAL 0xFFFFFF00
5956 #define S_028430_STENCILMASK(x) (((x) & 0xFF) << 8)
5957 #define G_028430_STENCILMASK(x) (((x) >> 8) & 0xFF)
5958 #define C_028430_STENCILMASK 0xFFFF00FF
5959 #define S_028430_STENCILWRITEMASK(x) (((x) & 0xFF) << 16)
5960 #define G_028430_STENCILWRITEMASK(x) (((x) >> 16) & 0xFF)
5961 #define C_028430_STENCILWRITEMASK 0xFF00FFFF
5962 #define S_028430_STENCILOPVAL(x) (((x) & 0xFF) << 24)
5963 #define G_028430_STENCILOPVAL(x) (((x) >> 24) & 0xFF)
5964 #define C_028430_STENCILOPVAL 0x00FFFFFF
5965 #define R_028434_DB_STENCILREFMASK_BF 0x028434
5966 #define S_028434_STENCILTESTVAL_BF(x) (((x) & 0xFF) << 0)
5967 #define G_028434_STENCILTESTVAL_BF(x) (((x) >> 0) & 0xFF)
5968 #define C_028434_STENCILTESTVAL_BF 0xFFFFFF00
5969 #define S_028434_STENCILMASK_BF(x) (((x) & 0xFF) << 8)
5970 #define G_028434_STENCILMASK_BF(x) (((x) >> 8) & 0xFF)
5971 #define C_028434_STENCILMASK_BF 0xFFFF00FF
5972 #define S_028434_STENCILWRITEMASK_BF(x) (((x) & 0xFF) << 16)
5973 #define G_028434_STENCILWRITEMASK_BF(x) (((x) >> 16) & 0xFF)
5974 #define C_028434_STENCILWRITEMASK_BF 0xFF00FFFF
5975 #define S_028434_STENCILOPVAL_BF(x) (((x) & 0xFF) << 24)
5976 #define G_028434_STENCILOPVAL_BF(x) (((x) >> 24) & 0xFF)
5977 #define C_028434_STENCILOPVAL_BF 0x00FFFFFF
5978 #define R_02843C_PA_CL_VPORT_XSCALE_0 0x02843C
5979 #define R_028440_PA_CL_VPORT_XOFFSET_0 0x028440
5980 #define R_028444_PA_CL_VPORT_YSCALE_0 0x028444
5981 #define R_028448_PA_CL_VPORT_YOFFSET_0 0x028448
5982 #define R_02844C_PA_CL_VPORT_ZSCALE_0 0x02844C
5983 #define R_028450_PA_CL_VPORT_ZOFFSET_0 0x028450
5984 #define R_0285BC_PA_CL_UCP_0_X 0x0285BC
5985 #define R_0285C0_PA_CL_UCP_0_Y 0x0285C0
5986 #define R_0285C4_PA_CL_UCP_0_Z 0x0285C4
5987 #define R_0285C8_PA_CL_UCP_0_W 0x0285C8
5988 #define R_0285CC_PA_CL_UCP_1_X 0x0285CC
5989 #define R_0285D0_PA_CL_UCP_1_Y 0x0285D0
5990 #define R_0285D4_PA_CL_UCP_1_Z 0x0285D4
5991 #define R_0285D8_PA_CL_UCP_1_W 0x0285D8
5992 #define R_0285DC_PA_CL_UCP_2_X 0x0285DC
5993 #define R_0285E0_PA_CL_UCP_2_Y 0x0285E0
5994 #define R_0285E4_PA_CL_UCP_2_Z 0x0285E4
5995 #define R_0285E8_PA_CL_UCP_2_W 0x0285E8
5996 #define R_0285EC_PA_CL_UCP_3_X 0x0285EC
5997 #define R_0285F0_PA_CL_UCP_3_Y 0x0285F0
5998 #define R_0285F4_PA_CL_UCP_3_Z 0x0285F4
5999 #define R_0285F8_PA_CL_UCP_3_W 0x0285F8
6000 #define R_0285FC_PA_CL_UCP_4_X 0x0285FC
6001 #define R_028600_PA_CL_UCP_4_Y 0x028600
6002 #define R_028604_PA_CL_UCP_4_Z 0x028604
6003 #define R_028608_PA_CL_UCP_4_W 0x028608
6004 #define R_02860C_PA_CL_UCP_5_X 0x02860C
6005 #define R_028610_PA_CL_UCP_5_Y 0x028610
6006 #define R_028614_PA_CL_UCP_5_Z 0x028614
6007 #define R_028618_PA_CL_UCP_5_W 0x028618
6008 #define R_028644_SPI_PS_INPUT_CNTL_0 0x028644
6009 #define S_028644_OFFSET(x) (((x) & 0x3F) << 0)
6010 #define G_028644_OFFSET(x) (((x) >> 0) & 0x3F)
6011 #define C_028644_OFFSET 0xFFFFFFC0
6012 #define S_028644_DEFAULT_VAL(x) (((x) & 0x03) << 8)
6013 #define G_028644_DEFAULT_VAL(x) (((x) >> 8) & 0x03)
6014 #define C_028644_DEFAULT_VAL 0xFFFFFCFF
6015 #define V_028644_X_0_0F 0x00
6016 #define S_028644_FLAT_SHADE(x) (((x) & 0x1) << 10)
6017 #define G_028644_FLAT_SHADE(x) (((x) >> 10) & 0x1)
6018 #define C_028644_FLAT_SHADE 0xFFFFFBFF
6019 #define S_028644_CYL_WRAP(x) (((x) & 0x0F) << 13)
6020 #define G_028644_CYL_WRAP(x) (((x) >> 13) & 0x0F)
6021 #define C_028644_CYL_WRAP 0xFFFE1FFF
6022 #define S_028644_PT_SPRITE_TEX(x) (((x) & 0x1) << 17)
6023 #define G_028644_PT_SPRITE_TEX(x) (((x) >> 17) & 0x1)
6024 #define C_028644_PT_SPRITE_TEX 0xFFFDFFFF
6025 /* CIK */
6026 #define S_028644_DUP(x) (((x) & 0x1) << 18)
6027 #define G_028644_DUP(x) (((x) >> 18) & 0x1)
6028 #define C_028644_DUP 0xFFFBFFFF
6029 /* */
6030 #define R_028648_SPI_PS_INPUT_CNTL_1 0x028648
6031 #define R_02864C_SPI_PS_INPUT_CNTL_2 0x02864C
6032 #define R_028650_SPI_PS_INPUT_CNTL_3 0x028650
6033 #define R_028654_SPI_PS_INPUT_CNTL_4 0x028654
6034 #define R_028658_SPI_PS_INPUT_CNTL_5 0x028658
6035 #define R_02865C_SPI_PS_INPUT_CNTL_6 0x02865C
6036 #define R_028660_SPI_PS_INPUT_CNTL_7 0x028660
6037 #define R_028664_SPI_PS_INPUT_CNTL_8 0x028664
6038 #define R_028668_SPI_PS_INPUT_CNTL_9 0x028668
6039 #define R_02866C_SPI_PS_INPUT_CNTL_10 0x02866C
6040 #define R_028670_SPI_PS_INPUT_CNTL_11 0x028670
6041 #define R_028674_SPI_PS_INPUT_CNTL_12 0x028674
6042 #define R_028678_SPI_PS_INPUT_CNTL_13 0x028678
6043 #define R_02867C_SPI_PS_INPUT_CNTL_14 0x02867C
6044 #define R_028680_SPI_PS_INPUT_CNTL_15 0x028680
6045 #define R_028684_SPI_PS_INPUT_CNTL_16 0x028684
6046 #define R_028688_SPI_PS_INPUT_CNTL_17 0x028688
6047 #define R_02868C_SPI_PS_INPUT_CNTL_18 0x02868C
6048 #define R_028690_SPI_PS_INPUT_CNTL_19 0x028690
6049 #define R_028694_SPI_PS_INPUT_CNTL_20 0x028694
6050 #define R_028698_SPI_PS_INPUT_CNTL_21 0x028698
6051 #define R_02869C_SPI_PS_INPUT_CNTL_22 0x02869C
6052 #define R_0286A0_SPI_PS_INPUT_CNTL_23 0x0286A0
6053 #define R_0286A4_SPI_PS_INPUT_CNTL_24 0x0286A4
6054 #define R_0286A8_SPI_PS_INPUT_CNTL_25 0x0286A8
6055 #define R_0286AC_SPI_PS_INPUT_CNTL_26 0x0286AC
6056 #define R_0286B0_SPI_PS_INPUT_CNTL_27 0x0286B0
6057 #define R_0286B4_SPI_PS_INPUT_CNTL_28 0x0286B4
6058 #define R_0286B8_SPI_PS_INPUT_CNTL_29 0x0286B8
6059 #define R_0286BC_SPI_PS_INPUT_CNTL_30 0x0286BC
6060 #define R_0286C0_SPI_PS_INPUT_CNTL_31 0x0286C0
6061 #define R_0286C4_SPI_VS_OUT_CONFIG 0x0286C4
6062 #define S_0286C4_VS_EXPORT_COUNT(x) (((x) & 0x1F) << 1)
6063 #define G_0286C4_VS_EXPORT_COUNT(x) (((x) >> 1) & 0x1F)
6064 #define C_0286C4_VS_EXPORT_COUNT 0xFFFFFFC1
6065 #define S_0286C4_VS_HALF_PACK(x) (((x) & 0x1) << 6)
6066 #define G_0286C4_VS_HALF_PACK(x) (((x) >> 6) & 0x1)
6067 #define C_0286C4_VS_HALF_PACK 0xFFFFFFBF
6068 #define S_0286C4_VS_EXPORTS_FOG(x) (((x) & 0x1) << 7) /* not on CIK */
6069 #define G_0286C4_VS_EXPORTS_FOG(x) (((x) >> 7) & 0x1) /* not on CIK */
6070 #define C_0286C4_VS_EXPORTS_FOG 0xFFFFFF7F /* not on CIK */
6071 #define S_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) & 0x1F) << 8) /* not on CIK */
6072 #define G_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) >> 8) & 0x1F) /* not on CIK */
6073 #define C_0286C4_VS_OUT_FOG_VEC_ADDR 0xFFFFE0FF /* not on CIK */
6074 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
6075 #define S_0286CC_PERSP_SAMPLE_ENA(x) (((x) & 0x1) << 0)
6076 #define G_0286CC_PERSP_SAMPLE_ENA(x) (((x) >> 0) & 0x1)
6077 #define C_0286CC_PERSP_SAMPLE_ENA 0xFFFFFFFE
6078 #define S_0286CC_PERSP_CENTER_ENA(x) (((x) & 0x1) << 1)
6079 #define G_0286CC_PERSP_CENTER_ENA(x) (((x) >> 1) & 0x1)
6080 #define C_0286CC_PERSP_CENTER_ENA 0xFFFFFFFD
6081 #define S_0286CC_PERSP_CENTROID_ENA(x) (((x) & 0x1) << 2)
6082 #define G_0286CC_PERSP_CENTROID_ENA(x) (((x) >> 2) & 0x1)
6083 #define C_0286CC_PERSP_CENTROID_ENA 0xFFFFFFFB
6084 #define S_0286CC_PERSP_PULL_MODEL_ENA(x) (((x) & 0x1) << 3)
6085 #define G_0286CC_PERSP_PULL_MODEL_ENA(x) (((x) >> 3) & 0x1)
6086 #define C_0286CC_PERSP_PULL_MODEL_ENA 0xFFFFFFF7
6087 #define S_0286CC_LINEAR_SAMPLE_ENA(x) (((x) & 0x1) << 4)
6088 #define G_0286CC_LINEAR_SAMPLE_ENA(x) (((x) >> 4) & 0x1)
6089 #define C_0286CC_LINEAR_SAMPLE_ENA 0xFFFFFFEF
6090 #define S_0286CC_LINEAR_CENTER_ENA(x) (((x) & 0x1) << 5)
6091 #define G_0286CC_LINEAR_CENTER_ENA(x) (((x) >> 5) & 0x1)
6092 #define C_0286CC_LINEAR_CENTER_ENA 0xFFFFFFDF
6093 #define S_0286CC_LINEAR_CENTROID_ENA(x) (((x) & 0x1) << 6)
6094 #define G_0286CC_LINEAR_CENTROID_ENA(x) (((x) >> 6) & 0x1)
6095 #define C_0286CC_LINEAR_CENTROID_ENA 0xFFFFFFBF
6096 #define S_0286CC_LINE_STIPPLE_TEX_ENA(x) (((x) & 0x1) << 7)
6097 #define G_0286CC_LINE_STIPPLE_TEX_ENA(x) (((x) >> 7) & 0x1)
6098 #define C_0286CC_LINE_STIPPLE_TEX_ENA 0xFFFFFF7F
6099 #define S_0286CC_POS_X_FLOAT_ENA(x) (((x) & 0x1) << 8)
6100 #define G_0286CC_POS_X_FLOAT_ENA(x) (((x) >> 8) & 0x1)
6101 #define C_0286CC_POS_X_FLOAT_ENA 0xFFFFFEFF
6102 #define S_0286CC_POS_Y_FLOAT_ENA(x) (((x) & 0x1) << 9)
6103 #define G_0286CC_POS_Y_FLOAT_ENA(x) (((x) >> 9) & 0x1)
6104 #define C_0286CC_POS_Y_FLOAT_ENA 0xFFFFFDFF
6105 #define S_0286CC_POS_Z_FLOAT_ENA(x) (((x) & 0x1) << 10)
6106 #define G_0286CC_POS_Z_FLOAT_ENA(x) (((x) >> 10) & 0x1)
6107 #define C_0286CC_POS_Z_FLOAT_ENA 0xFFFFFBFF
6108 #define S_0286CC_POS_W_FLOAT_ENA(x) (((x) & 0x1) << 11)
6109 #define G_0286CC_POS_W_FLOAT_ENA(x) (((x) >> 11) & 0x1)
6110 #define C_0286CC_POS_W_FLOAT_ENA 0xFFFFF7FF
6111 #define S_0286CC_FRONT_FACE_ENA(x) (((x) & 0x1) << 12)
6112 #define G_0286CC_FRONT_FACE_ENA(x) (((x) >> 12) & 0x1)
6113 #define C_0286CC_FRONT_FACE_ENA 0xFFFFEFFF
6114 #define S_0286CC_ANCILLARY_ENA(x) (((x) & 0x1) << 13)
6115 #define G_0286CC_ANCILLARY_ENA(x) (((x) >> 13) & 0x1)
6116 #define C_0286CC_ANCILLARY_ENA 0xFFFFDFFF
6117 #define S_0286CC_SAMPLE_COVERAGE_ENA(x) (((x) & 0x1) << 14)
6118 #define G_0286CC_SAMPLE_COVERAGE_ENA(x) (((x) >> 14) & 0x1)
6119 #define C_0286CC_SAMPLE_COVERAGE_ENA 0xFFFFBFFF
6120 #define S_0286CC_POS_FIXED_PT_ENA(x) (((x) & 0x1) << 15)
6121 #define G_0286CC_POS_FIXED_PT_ENA(x) (((x) >> 15) & 0x1)
6122 #define C_0286CC_POS_FIXED_PT_ENA 0xFFFF7FFF
6123 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
6124 #define S_0286D0_PERSP_SAMPLE_ENA(x) (((x) & 0x1) << 0)
6125 #define G_0286D0_PERSP_SAMPLE_ENA(x) (((x) >> 0) & 0x1)
6126 #define C_0286D0_PERSP_SAMPLE_ENA 0xFFFFFFFE
6127 #define S_0286D0_PERSP_CENTER_ENA(x) (((x) & 0x1) << 1)
6128 #define G_0286D0_PERSP_CENTER_ENA(x) (((x) >> 1) & 0x1)
6129 #define C_0286D0_PERSP_CENTER_ENA 0xFFFFFFFD
6130 #define S_0286D0_PERSP_CENTROID_ENA(x) (((x) & 0x1) << 2)
6131 #define G_0286D0_PERSP_CENTROID_ENA(x) (((x) >> 2) & 0x1)
6132 #define C_0286D0_PERSP_CENTROID_ENA 0xFFFFFFFB
6133 #define S_0286D0_PERSP_PULL_MODEL_ENA(x) (((x) & 0x1) << 3)
6134 #define G_0286D0_PERSP_PULL_MODEL_ENA(x) (((x) >> 3) & 0x1)
6135 #define C_0286D0_PERSP_PULL_MODEL_ENA 0xFFFFFFF7
6136 #define S_0286D0_LINEAR_SAMPLE_ENA(x) (((x) & 0x1) << 4)
6137 #define G_0286D0_LINEAR_SAMPLE_ENA(x) (((x) >> 4) & 0x1)
6138 #define C_0286D0_LINEAR_SAMPLE_ENA 0xFFFFFFEF
6139 #define S_0286D0_LINEAR_CENTER_ENA(x) (((x) & 0x1) << 5)
6140 #define G_0286D0_LINEAR_CENTER_ENA(x) (((x) >> 5) & 0x1)
6141 #define C_0286D0_LINEAR_CENTER_ENA 0xFFFFFFDF
6142 #define S_0286D0_LINEAR_CENTROID_ENA(x) (((x) & 0x1) << 6)
6143 #define G_0286D0_LINEAR_CENTROID_ENA(x) (((x) >> 6) & 0x1)
6144 #define C_0286D0_LINEAR_CENTROID_ENA 0xFFFFFFBF
6145 #define S_0286D0_LINE_STIPPLE_TEX_ENA(x) (((x) & 0x1) << 7)
6146 #define G_0286D0_LINE_STIPPLE_TEX_ENA(x) (((x) >> 7) & 0x1)
6147 #define C_0286D0_LINE_STIPPLE_TEX_ENA 0xFFFFFF7F
6148 #define S_0286D0_POS_X_FLOAT_ENA(x) (((x) & 0x1) << 8)
6149 #define G_0286D0_POS_X_FLOAT_ENA(x) (((x) >> 8) & 0x1)
6150 #define C_0286D0_POS_X_FLOAT_ENA 0xFFFFFEFF
6151 #define S_0286D0_POS_Y_FLOAT_ENA(x) (((x) & 0x1) << 9)
6152 #define G_0286D0_POS_Y_FLOAT_ENA(x) (((x) >> 9) & 0x1)
6153 #define C_0286D0_POS_Y_FLOAT_ENA 0xFFFFFDFF
6154 #define S_0286D0_POS_Z_FLOAT_ENA(x) (((x) & 0x1) << 10)
6155 #define G_0286D0_POS_Z_FLOAT_ENA(x) (((x) >> 10) & 0x1)
6156 #define C_0286D0_POS_Z_FLOAT_ENA 0xFFFFFBFF
6157 #define S_0286D0_POS_W_FLOAT_ENA(x) (((x) & 0x1) << 11)
6158 #define G_0286D0_POS_W_FLOAT_ENA(x) (((x) >> 11) & 0x1)
6159 #define C_0286D0_POS_W_FLOAT_ENA 0xFFFFF7FF
6160 #define S_0286D0_FRONT_FACE_ENA(x) (((x) & 0x1) << 12)
6161 #define G_0286D0_FRONT_FACE_ENA(x) (((x) >> 12) & 0x1)
6162 #define C_0286D0_FRONT_FACE_ENA 0xFFFFEFFF
6163 #define S_0286D0_ANCILLARY_ENA(x) (((x) & 0x1) << 13)
6164 #define G_0286D0_ANCILLARY_ENA(x) (((x) >> 13) & 0x1)
6165 #define C_0286D0_ANCILLARY_ENA 0xFFFFDFFF
6166 #define S_0286D0_SAMPLE_COVERAGE_ENA(x) (((x) & 0x1) << 14)
6167 #define G_0286D0_SAMPLE_COVERAGE_ENA(x) (((x) >> 14) & 0x1)
6168 #define C_0286D0_SAMPLE_COVERAGE_ENA 0xFFFFBFFF
6169 #define S_0286D0_POS_FIXED_PT_ENA(x) (((x) & 0x1) << 15)
6170 #define G_0286D0_POS_FIXED_PT_ENA(x) (((x) >> 15) & 0x1)
6171 #define C_0286D0_POS_FIXED_PT_ENA 0xFFFF7FFF
6172 #define R_0286D4_SPI_INTERP_CONTROL_0 0x0286D4
6173 #define S_0286D4_FLAT_SHADE_ENA(x) (((x) & 0x1) << 0)
6174 #define G_0286D4_FLAT_SHADE_ENA(x) (((x) >> 0) & 0x1)
6175 #define C_0286D4_FLAT_SHADE_ENA 0xFFFFFFFE
6176 #define S_0286D4_PNT_SPRITE_ENA(x) (((x) & 0x1) << 1)
6177 #define G_0286D4_PNT_SPRITE_ENA(x) (((x) >> 1) & 0x1)
6178 #define C_0286D4_PNT_SPRITE_ENA 0xFFFFFFFD
6179 #define S_0286D4_PNT_SPRITE_OVRD_X(x) (((x) & 0x07) << 2)
6180 #define G_0286D4_PNT_SPRITE_OVRD_X(x) (((x) >> 2) & 0x07)
6181 #define C_0286D4_PNT_SPRITE_OVRD_X 0xFFFFFFE3
6182 #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00
6183 #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01
6184 #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02
6185 #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03
6186 #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04
6187 #define S_0286D4_PNT_SPRITE_OVRD_Y(x) (((x) & 0x07) << 5)
6188 #define G_0286D4_PNT_SPRITE_OVRD_Y(x) (((x) >> 5) & 0x07)
6189 #define C_0286D4_PNT_SPRITE_OVRD_Y 0xFFFFFF1F
6190 #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00
6191 #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01
6192 #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02
6193 #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03
6194 #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04
6195 #define S_0286D4_PNT_SPRITE_OVRD_Z(x) (((x) & 0x07) << 8)
6196 #define G_0286D4_PNT_SPRITE_OVRD_Z(x) (((x) >> 8) & 0x07)
6197 #define C_0286D4_PNT_SPRITE_OVRD_Z 0xFFFFF8FF
6198 #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00
6199 #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01
6200 #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02
6201 #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03
6202 #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04
6203 #define S_0286D4_PNT_SPRITE_OVRD_W(x) (((x) & 0x07) << 11)
6204 #define G_0286D4_PNT_SPRITE_OVRD_W(x) (((x) >> 11) & 0x07)
6205 #define C_0286D4_PNT_SPRITE_OVRD_W 0xFFFFC7FF
6206 #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00
6207 #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01
6208 #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02
6209 #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03
6210 #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04
6211 #define S_0286D4_PNT_SPRITE_TOP_1(x) (((x) & 0x1) << 14)
6212 #define G_0286D4_PNT_SPRITE_TOP_1(x) (((x) >> 14) & 0x1)
6213 #define C_0286D4_PNT_SPRITE_TOP_1 0xFFFFBFFF
6214 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
6215 #define S_0286D8_NUM_INTERP(x) (((x) & 0x3F) << 0)
6216 #define G_0286D8_NUM_INTERP(x) (((x) >> 0) & 0x3F)
6217 #define C_0286D8_NUM_INTERP 0xFFFFFFC0
6218 #define S_0286D8_PARAM_GEN(x) (((x) & 0x1) << 6)
6219 #define G_0286D8_PARAM_GEN(x) (((x) >> 6) & 0x1)
6220 #define C_0286D8_PARAM_GEN 0xFFFFFFBF
6221 #define S_0286D8_FOG_ADDR(x) (((x) & 0x7F) << 7) /* not on CIK */
6222 #define G_0286D8_FOG_ADDR(x) (((x) >> 7) & 0x7F) /* not on CIK */
6223 #define C_0286D8_FOG_ADDR 0xFFFFC07F /* not on CIK */
6224 #define S_0286D8_BC_OPTIMIZE_DISABLE(x) (((x) & 0x1) << 14)
6225 #define G_0286D8_BC_OPTIMIZE_DISABLE(x) (((x) >> 14) & 0x1)
6226 #define C_0286D8_BC_OPTIMIZE_DISABLE 0xFFFFBFFF
6227 #define S_0286D8_PASS_FOG_THROUGH_PS(x) (((x) & 0x1) << 15) /* not on CIK */
6228 #define G_0286D8_PASS_FOG_THROUGH_PS(x) (((x) >> 15) & 0x1) /* not on CIK */
6229 #define C_0286D8_PASS_FOG_THROUGH_PS 0xFFFF7FFF /* not on CIK */
6230 #define R_0286E0_SPI_BARYC_CNTL 0x0286E0
6231 #define S_0286E0_PERSP_CENTER_CNTL(x) (((x) & 0x1) << 0)
6232 #define G_0286E0_PERSP_CENTER_CNTL(x) (((x) >> 0) & 0x1)
6233 #define C_0286E0_PERSP_CENTER_CNTL 0xFFFFFFFE
6234 #define S_0286E0_PERSP_CENTROID_CNTL(x) (((x) & 0x1) << 4)
6235 #define G_0286E0_PERSP_CENTROID_CNTL(x) (((x) >> 4) & 0x1)
6236 #define C_0286E0_PERSP_CENTROID_CNTL 0xFFFFFFEF
6237 #define S_0286E0_LINEAR_CENTER_CNTL(x) (((x) & 0x1) << 8)
6238 #define G_0286E0_LINEAR_CENTER_CNTL(x) (((x) >> 8) & 0x1)
6239 #define C_0286E0_LINEAR_CENTER_CNTL 0xFFFFFEFF
6240 #define S_0286E0_LINEAR_CENTROID_CNTL(x) (((x) & 0x1) << 12)
6241 #define G_0286E0_LINEAR_CENTROID_CNTL(x) (((x) >> 12) & 0x1)
6242 #define C_0286E0_LINEAR_CENTROID_CNTL 0xFFFFEFFF
6243 #define S_0286E0_POS_FLOAT_LOCATION(x) (((x) & 0x03) << 16)
6244 #define G_0286E0_POS_FLOAT_LOCATION(x) (((x) >> 16) & 0x03)
6245 #define C_0286E0_POS_FLOAT_LOCATION 0xFFFCFFFF
6246 #define V_0286E0_X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT 0x00
6247 #define S_0286E0_POS_FLOAT_ULC(x) (((x) & 0x1) << 20)
6248 #define G_0286E0_POS_FLOAT_ULC(x) (((x) >> 20) & 0x1)
6249 #define C_0286E0_POS_FLOAT_ULC 0xFFEFFFFF
6250 #define S_0286E0_FRONT_FACE_ALL_BITS(x) (((x) & 0x1) << 24)
6251 #define G_0286E0_FRONT_FACE_ALL_BITS(x) (((x) >> 24) & 0x1)
6252 #define C_0286E0_FRONT_FACE_ALL_BITS 0xFEFFFFFF
6253 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
6254 #define S_0286E8_WAVES(x) (((x) & 0xFFF) << 0)
6255 #define G_0286E8_WAVES(x) (((x) >> 0) & 0xFFF)
6256 #define C_0286E8_WAVES 0xFFFFF000
6257 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
6258 #define G_0286E8_WAVESIZE(x) (((x) >> 12) & 0x1FFF)
6259 #define C_0286E8_WAVESIZE 0xFE000FFF
6260 #define R_028704_SPI_WAVE_MGMT_1 0x028704 /* not on CIK */
6261 #define S_028704_NUM_PS_WAVES(x) (((x) & 0x3F) << 0)
6262 #define G_028704_NUM_PS_WAVES(x) (((x) >> 0) & 0x3F)
6263 #define C_028704_NUM_PS_WAVES 0xFFFFFFC0
6264 #define S_028704_NUM_VS_WAVES(x) (((x) & 0x3F) << 6)
6265 #define G_028704_NUM_VS_WAVES(x) (((x) >> 6) & 0x3F)
6266 #define C_028704_NUM_VS_WAVES 0xFFFFF03F
6267 #define S_028704_NUM_GS_WAVES(x) (((x) & 0x3F) << 12)
6268 #define G_028704_NUM_GS_WAVES(x) (((x) >> 12) & 0x3F)
6269 #define C_028704_NUM_GS_WAVES 0xFFFC0FFF
6270 #define S_028704_NUM_ES_WAVES(x) (((x) & 0x3F) << 18)
6271 #define G_028704_NUM_ES_WAVES(x) (((x) >> 18) & 0x3F)
6272 #define C_028704_NUM_ES_WAVES 0xFF03FFFF
6273 #define S_028704_NUM_HS_WAVES(x) (((x) & 0x3F) << 24)
6274 #define G_028704_NUM_HS_WAVES(x) (((x) >> 24) & 0x3F)
6275 #define C_028704_NUM_HS_WAVES 0xC0FFFFFF
6276 #define R_028708_SPI_WAVE_MGMT_2 0x028708 /* not on CIK */
6277 #define S_028708_NUM_LS_WAVES(x) (((x) & 0x3F) << 0)
6278 #define G_028708_NUM_LS_WAVES(x) (((x) >> 0) & 0x3F)
6279 #define C_028708_NUM_LS_WAVES 0xFFFFFFC0
6280 #define R_02870C_SPI_SHADER_POS_FORMAT 0x02870C
6281 #define S_02870C_POS0_EXPORT_FORMAT(x) (((x) & 0x0F) << 0)
6282 #define G_02870C_POS0_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F)
6283 #define C_02870C_POS0_EXPORT_FORMAT 0xFFFFFFF0
6284 #define V_02870C_SPI_SHADER_NONE 0x00
6285 #define V_02870C_SPI_SHADER_1COMP 0x01
6286 #define V_02870C_SPI_SHADER_2COMP 0x02
6287 #define V_02870C_SPI_SHADER_4COMPRESS 0x03
6288 #define V_02870C_SPI_SHADER_4COMP 0x04
6289 #define S_02870C_POS1_EXPORT_FORMAT(x) (((x) & 0x0F) << 4)
6290 #define G_02870C_POS1_EXPORT_FORMAT(x) (((x) >> 4) & 0x0F)
6291 #define C_02870C_POS1_EXPORT_FORMAT 0xFFFFFF0F
6292 #define V_02870C_SPI_SHADER_NONE 0x00
6293 #define V_02870C_SPI_SHADER_1COMP 0x01
6294 #define V_02870C_SPI_SHADER_2COMP 0x02
6295 #define V_02870C_SPI_SHADER_4COMPRESS 0x03
6296 #define V_02870C_SPI_SHADER_4COMP 0x04
6297 #define S_02870C_POS2_EXPORT_FORMAT(x) (((x) & 0x0F) << 8)
6298 #define G_02870C_POS2_EXPORT_FORMAT(x) (((x) >> 8) & 0x0F)
6299 #define C_02870C_POS2_EXPORT_FORMAT 0xFFFFF0FF
6300 #define V_02870C_SPI_SHADER_NONE 0x00
6301 #define V_02870C_SPI_SHADER_1COMP 0x01
6302 #define V_02870C_SPI_SHADER_2COMP 0x02
6303 #define V_02870C_SPI_SHADER_4COMPRESS 0x03
6304 #define V_02870C_SPI_SHADER_4COMP 0x04
6305 #define S_02870C_POS3_EXPORT_FORMAT(x) (((x) & 0x0F) << 12)
6306 #define G_02870C_POS3_EXPORT_FORMAT(x) (((x) >> 12) & 0x0F)
6307 #define C_02870C_POS3_EXPORT_FORMAT 0xFFFF0FFF
6308 #define V_02870C_SPI_SHADER_NONE 0x00
6309 #define V_02870C_SPI_SHADER_1COMP 0x01
6310 #define V_02870C_SPI_SHADER_2COMP 0x02
6311 #define V_02870C_SPI_SHADER_4COMPRESS 0x03
6312 #define V_02870C_SPI_SHADER_4COMP 0x04
6313 #define R_028710_SPI_SHADER_Z_FORMAT 0x028710
6314 #define S_028710_Z_EXPORT_FORMAT(x) (((x) & 0x0F) << 0)
6315 #define G_028710_Z_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F)
6316 #define C_028710_Z_EXPORT_FORMAT 0xFFFFFFF0
6317 #define V_028710_SPI_SHADER_ZERO 0x00
6318 #define V_028710_SPI_SHADER_32_R 0x01
6319 #define V_028710_SPI_SHADER_32_GR 0x02
6320 #define V_028710_SPI_SHADER_32_AR 0x03
6321 #define V_028710_SPI_SHADER_FP16_ABGR 0x04
6322 #define V_028710_SPI_SHADER_UNORM16_ABGR 0x05
6323 #define V_028710_SPI_SHADER_SNORM16_ABGR 0x06
6324 #define V_028710_SPI_SHADER_UINT16_ABGR 0x07
6325 #define V_028710_SPI_SHADER_SINT16_ABGR 0x08
6326 #define V_028710_SPI_SHADER_32_ABGR 0x09
6327 #define R_028714_SPI_SHADER_COL_FORMAT 0x028714
6328 #define S_028714_COL0_EXPORT_FORMAT(x) (((x) & 0x0F) << 0)
6329 #define G_028714_COL0_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F)
6330 #define C_028714_COL0_EXPORT_FORMAT 0xFFFFFFF0
6331 #define V_028714_SPI_SHADER_ZERO 0x00
6332 #define V_028714_SPI_SHADER_32_R 0x01
6333 #define V_028714_SPI_SHADER_32_GR 0x02
6334 #define V_028714_SPI_SHADER_32_AR 0x03
6335 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
6336 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
6337 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
6338 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
6339 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
6340 #define V_028714_SPI_SHADER_32_ABGR 0x09
6341 #define S_028714_COL1_EXPORT_FORMAT(x) (((x) & 0x0F) << 4)
6342 #define G_028714_COL1_EXPORT_FORMAT(x) (((x) >> 4) & 0x0F)
6343 #define C_028714_COL1_EXPORT_FORMAT 0xFFFFFF0F
6344 #define V_028714_SPI_SHADER_ZERO 0x00
6345 #define V_028714_SPI_SHADER_32_R 0x01
6346 #define V_028714_SPI_SHADER_32_GR 0x02
6347 #define V_028714_SPI_SHADER_32_AR 0x03
6348 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
6349 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
6350 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
6351 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
6352 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
6353 #define V_028714_SPI_SHADER_32_ABGR 0x09
6354 #define S_028714_COL2_EXPORT_FORMAT(x) (((x) & 0x0F) << 8)
6355 #define G_028714_COL2_EXPORT_FORMAT(x) (((x) >> 8) & 0x0F)
6356 #define C_028714_COL2_EXPORT_FORMAT 0xFFFFF0FF
6357 #define V_028714_SPI_SHADER_ZERO 0x00
6358 #define V_028714_SPI_SHADER_32_R 0x01
6359 #define V_028714_SPI_SHADER_32_GR 0x02
6360 #define V_028714_SPI_SHADER_32_AR 0x03
6361 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
6362 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
6363 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
6364 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
6365 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
6366 #define V_028714_SPI_SHADER_32_ABGR 0x09
6367 #define S_028714_COL3_EXPORT_FORMAT(x) (((x) & 0x0F) << 12)
6368 #define G_028714_COL3_EXPORT_FORMAT(x) (((x) >> 12) & 0x0F)
6369 #define C_028714_COL3_EXPORT_FORMAT 0xFFFF0FFF
6370 #define V_028714_SPI_SHADER_ZERO 0x00
6371 #define V_028714_SPI_SHADER_32_R 0x01
6372 #define V_028714_SPI_SHADER_32_GR 0x02
6373 #define V_028714_SPI_SHADER_32_AR 0x03
6374 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
6375 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
6376 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
6377 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
6378 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
6379 #define V_028714_SPI_SHADER_32_ABGR 0x09
6380 #define S_028714_COL4_EXPORT_FORMAT(x) (((x) & 0x0F) << 16)
6381 #define G_028714_COL4_EXPORT_FORMAT(x) (((x) >> 16) & 0x0F)
6382 #define C_028714_COL4_EXPORT_FORMAT 0xFFF0FFFF
6383 #define V_028714_SPI_SHADER_ZERO 0x00
6384 #define V_028714_SPI_SHADER_32_R 0x01
6385 #define V_028714_SPI_SHADER_32_GR 0x02
6386 #define V_028714_SPI_SHADER_32_AR 0x03
6387 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
6388 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
6389 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
6390 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
6391 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
6392 #define V_028714_SPI_SHADER_32_ABGR 0x09
6393 #define S_028714_COL5_EXPORT_FORMAT(x) (((x) & 0x0F) << 20)
6394 #define G_028714_COL5_EXPORT_FORMAT(x) (((x) >> 20) & 0x0F)
6395 #define C_028714_COL5_EXPORT_FORMAT 0xFF0FFFFF
6396 #define V_028714_SPI_SHADER_ZERO 0x00
6397 #define V_028714_SPI_SHADER_32_R 0x01
6398 #define V_028714_SPI_SHADER_32_GR 0x02
6399 #define V_028714_SPI_SHADER_32_AR 0x03
6400 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
6401 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
6402 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
6403 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
6404 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
6405 #define V_028714_SPI_SHADER_32_ABGR 0x09
6406 #define S_028714_COL6_EXPORT_FORMAT(x) (((x) & 0x0F) << 24)
6407 #define G_028714_COL6_EXPORT_FORMAT(x) (((x) >> 24) & 0x0F)
6408 #define C_028714_COL6_EXPORT_FORMAT 0xF0FFFFFF
6409 #define V_028714_SPI_SHADER_ZERO 0x00
6410 #define V_028714_SPI_SHADER_32_R 0x01
6411 #define V_028714_SPI_SHADER_32_GR 0x02
6412 #define V_028714_SPI_SHADER_32_AR 0x03
6413 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
6414 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
6415 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
6416 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
6417 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
6418 #define V_028714_SPI_SHADER_32_ABGR 0x09
6419 #define S_028714_COL7_EXPORT_FORMAT(x) (((x) & 0x0F) << 28)
6420 #define G_028714_COL7_EXPORT_FORMAT(x) (((x) >> 28) & 0x0F)
6421 #define C_028714_COL7_EXPORT_FORMAT 0x0FFFFFFF
6422 #define V_028714_SPI_SHADER_ZERO 0x00
6423 #define V_028714_SPI_SHADER_32_R 0x01
6424 #define V_028714_SPI_SHADER_32_GR 0x02
6425 #define V_028714_SPI_SHADER_32_AR 0x03
6426 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
6427 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
6428 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
6429 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
6430 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
6431 #define V_028714_SPI_SHADER_32_ABGR 0x09
6432 #define R_028780_CB_BLEND0_CONTROL 0x028780
6433 #define S_028780_COLOR_SRCBLEND(x) (((x) & 0x1F) << 0)
6434 #define G_028780_COLOR_SRCBLEND(x) (((x) >> 0) & 0x1F)
6435 #define C_028780_COLOR_SRCBLEND 0xFFFFFFE0
6436 #define V_028780_BLEND_ZERO 0x00
6437 #define V_028780_BLEND_ONE 0x01
6438 #define V_028780_BLEND_SRC_COLOR 0x02
6439 #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03
6440 #define V_028780_BLEND_SRC_ALPHA 0x04
6441 #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05
6442 #define V_028780_BLEND_DST_ALPHA 0x06
6443 #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07
6444 #define V_028780_BLEND_DST_COLOR 0x08
6445 #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09
6446 #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A
6447 #define V_028780_BLEND_CONSTANT_COLOR 0x0D
6448 #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E
6449 #define V_028780_BLEND_SRC1_COLOR 0x0F
6450 #define V_028780_BLEND_INV_SRC1_COLOR 0x10
6451 #define V_028780_BLEND_SRC1_ALPHA 0x11
6452 #define V_028780_BLEND_INV_SRC1_ALPHA 0x12
6453 #define V_028780_BLEND_CONSTANT_ALPHA 0x13
6454 #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
6455 #define S_028780_COLOR_COMB_FCN(x) (((x) & 0x07) << 5)
6456 #define G_028780_COLOR_COMB_FCN(x) (((x) >> 5) & 0x07)
6457 #define C_028780_COLOR_COMB_FCN 0xFFFFFF1F
6458 #define V_028780_COMB_DST_PLUS_SRC 0x00
6459 #define V_028780_COMB_SRC_MINUS_DST 0x01
6460 #define V_028780_COMB_MIN_DST_SRC 0x02
6461 #define V_028780_COMB_MAX_DST_SRC 0x03
6462 #define V_028780_COMB_DST_MINUS_SRC 0x04
6463 #define S_028780_COLOR_DESTBLEND(x) (((x) & 0x1F) << 8)
6464 #define G_028780_COLOR_DESTBLEND(x) (((x) >> 8) & 0x1F)
6465 #define C_028780_COLOR_DESTBLEND 0xFFFFE0FF
6466 #define V_028780_BLEND_ZERO 0x00
6467 #define V_028780_BLEND_ONE 0x01
6468 #define V_028780_BLEND_SRC_COLOR 0x02
6469 #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03
6470 #define V_028780_BLEND_SRC_ALPHA 0x04
6471 #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05
6472 #define V_028780_BLEND_DST_ALPHA 0x06
6473 #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07
6474 #define V_028780_BLEND_DST_COLOR 0x08
6475 #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09
6476 #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A
6477 #define V_028780_BLEND_CONSTANT_COLOR 0x0D
6478 #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E
6479 #define V_028780_BLEND_SRC1_COLOR 0x0F
6480 #define V_028780_BLEND_INV_SRC1_COLOR 0x10
6481 #define V_028780_BLEND_SRC1_ALPHA 0x11
6482 #define V_028780_BLEND_INV_SRC1_ALPHA 0x12
6483 #define V_028780_BLEND_CONSTANT_ALPHA 0x13
6484 #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
6485 #define S_028780_ALPHA_SRCBLEND(x) (((x) & 0x1F) << 16)
6486 #define G_028780_ALPHA_SRCBLEND(x) (((x) >> 16) & 0x1F)
6487 #define C_028780_ALPHA_SRCBLEND 0xFFE0FFFF
6488 #define V_028780_BLEND_ZERO 0x00
6489 #define V_028780_BLEND_ONE 0x01
6490 #define V_028780_BLEND_SRC_COLOR 0x02
6491 #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03
6492 #define V_028780_BLEND_SRC_ALPHA 0x04
6493 #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05
6494 #define V_028780_BLEND_DST_ALPHA 0x06
6495 #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07
6496 #define V_028780_BLEND_DST_COLOR 0x08
6497 #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09
6498 #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A
6499 #define V_028780_BLEND_CONSTANT_COLOR 0x0D
6500 #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E
6501 #define V_028780_BLEND_SRC1_COLOR 0x0F
6502 #define V_028780_BLEND_INV_SRC1_COLOR 0x10
6503 #define V_028780_BLEND_SRC1_ALPHA 0x11
6504 #define V_028780_BLEND_INV_SRC1_ALPHA 0x12
6505 #define V_028780_BLEND_CONSTANT_ALPHA 0x13
6506 #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
6507 #define S_028780_ALPHA_COMB_FCN(x) (((x) & 0x07) << 21)
6508 #define G_028780_ALPHA_COMB_FCN(x) (((x) >> 21) & 0x07)
6509 #define C_028780_ALPHA_COMB_FCN 0xFF1FFFFF
6510 #define V_028780_COMB_DST_PLUS_SRC 0x00
6511 #define V_028780_COMB_SRC_MINUS_DST 0x01
6512 #define V_028780_COMB_MIN_DST_SRC 0x02
6513 #define V_028780_COMB_MAX_DST_SRC 0x03
6514 #define V_028780_COMB_DST_MINUS_SRC 0x04
6515 #define S_028780_ALPHA_DESTBLEND(x) (((x) & 0x1F) << 24)
6516 #define G_028780_ALPHA_DESTBLEND(x) (((x) >> 24) & 0x1F)
6517 #define C_028780_ALPHA_DESTBLEND 0xE0FFFFFF
6518 #define V_028780_BLEND_ZERO 0x00
6519 #define V_028780_BLEND_ONE 0x01
6520 #define V_028780_BLEND_SRC_COLOR 0x02
6521 #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03
6522 #define V_028780_BLEND_SRC_ALPHA 0x04
6523 #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05
6524 #define V_028780_BLEND_DST_ALPHA 0x06
6525 #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07
6526 #define V_028780_BLEND_DST_COLOR 0x08
6527 #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09
6528 #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A
6529 #define V_028780_BLEND_CONSTANT_COLOR 0x0D
6530 #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E
6531 #define V_028780_BLEND_SRC1_COLOR 0x0F
6532 #define V_028780_BLEND_INV_SRC1_COLOR 0x10
6533 #define V_028780_BLEND_SRC1_ALPHA 0x11
6534 #define V_028780_BLEND_INV_SRC1_ALPHA 0x12
6535 #define V_028780_BLEND_CONSTANT_ALPHA 0x13
6536 #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
6537 #define S_028780_SEPARATE_ALPHA_BLEND(x) (((x) & 0x1) << 29)
6538 #define G_028780_SEPARATE_ALPHA_BLEND(x) (((x) >> 29) & 0x1)
6539 #define C_028780_SEPARATE_ALPHA_BLEND 0xDFFFFFFF
6540 #define S_028780_ENABLE(x) (((x) & 0x1) << 30)
6541 #define G_028780_ENABLE(x) (((x) >> 30) & 0x1)
6542 #define C_028780_ENABLE 0xBFFFFFFF
6543 #define S_028780_DISABLE_ROP3(x) (((x) & 0x1) << 31)
6544 #define G_028780_DISABLE_ROP3(x) (((x) >> 31) & 0x1)
6545 #define C_028780_DISABLE_ROP3 0x7FFFFFFF
6546 #define R_028784_CB_BLEND1_CONTROL 0x028784
6547 #define R_028788_CB_BLEND2_CONTROL 0x028788
6548 #define R_02878C_CB_BLEND3_CONTROL 0x02878C
6549 #define R_028790_CB_BLEND4_CONTROL 0x028790
6550 #define R_028794_CB_BLEND5_CONTROL 0x028794
6551 #define R_028798_CB_BLEND6_CONTROL 0x028798
6552 #define R_02879C_CB_BLEND7_CONTROL 0x02879C
6553 #define R_0287D4_PA_CL_POINT_X_RAD 0x0287D4
6554 #define R_0287D8_PA_CL_POINT_Y_RAD 0x0287D8
6555 #define R_0287DC_PA_CL_POINT_SIZE 0x0287DC
6556 #define R_0287E0_PA_CL_POINT_CULL_RAD 0x0287E0
6557 #define R_0287E4_VGT_DMA_BASE_HI 0x0287E4
6558 #define S_0287E4_BASE_ADDR(x) (((x) & 0xFF) << 0)
6559 #define G_0287E4_BASE_ADDR(x) (((x) >> 0) & 0xFF)
6560 #define C_0287E4_BASE_ADDR 0xFFFFFF00
6561 #define R_0287E8_VGT_DMA_BASE 0x0287E8
6562 #define R_0287F0_VGT_DRAW_INITIATOR 0x0287F0
6563 #define S_0287F0_SOURCE_SELECT(x) (((x) & 0x03) << 0)
6564 #define G_0287F0_SOURCE_SELECT(x) (((x) >> 0) & 0x03)
6565 #define C_0287F0_SOURCE_SELECT 0xFFFFFFFC
6566 #define V_0287F0_DI_SRC_SEL_DMA 0x00
6567 #define V_0287F0_DI_SRC_SEL_IMMEDIATE 0x01 /* not on CIK */
6568 #define V_0287F0_DI_SRC_SEL_AUTO_INDEX 0x02
6569 #define V_0287F0_DI_SRC_SEL_RESERVED 0x03
6570 #define S_0287F0_MAJOR_MODE(x) (((x) & 0x03) << 2)
6571 #define G_0287F0_MAJOR_MODE(x) (((x) >> 2) & 0x03)
6572 #define C_0287F0_MAJOR_MODE 0xFFFFFFF3
6573 #define V_0287F0_DI_MAJOR_MODE_0 0x00
6574 #define V_0287F0_DI_MAJOR_MODE_1 0x01
6575 #define S_0287F0_NOT_EOP(x) (((x) & 0x1) << 5)
6576 #define G_0287F0_NOT_EOP(x) (((x) >> 5) & 0x1)
6577 #define C_0287F0_NOT_EOP 0xFFFFFFDF
6578 #define S_0287F0_USE_OPAQUE(x) (((x) & 0x1) << 6)
6579 #define G_0287F0_USE_OPAQUE(x) (((x) >> 6) & 0x1)
6580 #define C_0287F0_USE_OPAQUE 0xFFFFFFBF
6581 #define R_0287F4_VGT_IMMED_DATA 0x0287F4 /* not on CIK */
6582 #define R_028800_DB_DEPTH_CONTROL 0x028800
6583 #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)
6584 #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)
6585 #define C_028800_STENCIL_ENABLE 0xFFFFFFFE
6586 #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)
6587 #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)
6588 #define C_028800_Z_ENABLE 0xFFFFFFFD
6589 #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)
6590 #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)
6591 #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB
6592 #define S_028800_DEPTH_BOUNDS_ENABLE(x) (((x) & 0x1) << 3)
6593 #define G_028800_DEPTH_BOUNDS_ENABLE(x) (((x) >> 3) & 0x1)
6594 #define C_028800_DEPTH_BOUNDS_ENABLE 0xFFFFFFF7
6595 #define S_028800_ZFUNC(x) (((x) & 0x07) << 4)
6596 #define G_028800_ZFUNC(x) (((x) >> 4) & 0x07)
6597 #define C_028800_ZFUNC 0xFFFFFF8F
6598 #define V_028800_FRAG_NEVER 0x00
6599 #define V_028800_FRAG_LESS 0x01
6600 #define V_028800_FRAG_EQUAL 0x02
6601 #define V_028800_FRAG_LEQUAL 0x03
6602 #define V_028800_FRAG_GREATER 0x04
6603 #define V_028800_FRAG_NOTEQUAL 0x05
6604 #define V_028800_FRAG_GEQUAL 0x06
6605 #define V_028800_FRAG_ALWAYS 0x07
6606 #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)
6607 #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)
6608 #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F
6609 #define S_028800_STENCILFUNC(x) (((x) & 0x07) << 8)
6610 #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x07)
6611 #define C_028800_STENCILFUNC 0xFFFFF8FF
6612 #define V_028800_REF_NEVER 0x00
6613 #define V_028800_REF_LESS 0x01
6614 #define V_028800_REF_EQUAL 0x02
6615 #define V_028800_REF_LEQUAL 0x03
6616 #define V_028800_REF_GREATER 0x04
6617 #define V_028800_REF_NOTEQUAL 0x05
6618 #define V_028800_REF_GEQUAL 0x06
6619 #define V_028800_REF_ALWAYS 0x07
6620 #define S_028800_STENCILFUNC_BF(x) (((x) & 0x07) << 20)
6621 #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x07)
6622 #define C_028800_STENCILFUNC_BF 0xFF8FFFFF
6623 #define V_028800_REF_NEVER 0x00
6624 #define V_028800_REF_LESS 0x01
6625 #define V_028800_REF_EQUAL 0x02
6626 #define V_028800_REF_LEQUAL 0x03
6627 #define V_028800_REF_GREATER 0x04
6628 #define V_028800_REF_NOTEQUAL 0x05
6629 #define V_028800_REF_GEQUAL 0x06
6630 #define V_028800_REF_ALWAYS 0x07
6631 #define S_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL(x) (((x) & 0x1) << 30)
6632 #define G_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL(x) (((x) >> 30) & 0x1)
6633 #define C_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL 0xBFFFFFFF
6634 #define S_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS(x) (((x) & 0x1) << 31)
6635 #define G_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS(x) (((x) >> 31) & 0x1)
6636 #define C_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS 0x7FFFFFFF
6637 #define R_028804_DB_EQAA 0x028804
6638 #define S_028804_MAX_ANCHOR_SAMPLES(x) (((x) & 0x7) << 0)
6639 #define G_028804_MAX_ANCHOR_SAMPLES(x) (((x) >> 0) & 0x7)
6640 #define C_028804_MAX_ANCHOR_SAMPLES (~(((~0) & 0x7) << 0))
6641 #define S_028804_PS_ITER_SAMPLES(x) (((x) & 0x7) << 4)
6642 #define G_028804_PS_ITER_SAMPLES(x) (((x) >> 4) & 0x7)
6643 #define C_028804_PS_ITER_SAMPLES (~(((~0) & 0x7) << 4))
6644 #define S_028804_MASK_EXPORT_NUM_SAMPLES(x) (((x) & 0x7) << 8)
6645 #define G_028804_MASK_EXPORT_NUM_SAMPLES(x) (((x) >> 8) & 0x7)
6646 #define C_028804_MASK_EXPORT_NUM_SAMPLES (~(((~0) & 0x7) << 8))
6647 #define S_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((x) & 0x7) << 12)
6648 #define G_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((x) >> 12) & 0x7)
6649 #define C_028804_ALPHA_TO_MASK_NUM_SAMPLES (~(((~0) & 0x7) << 12))
6650 #define S_028804_HIGH_QUALITY_INTERSECTIONS(x) (((x) & 0x1) << 16)
6651 #define G_028804_HIGH_QUALITY_INTERSECTIONS(x) (((x) >> 16) & 0x1)
6652 #define C_028804_HIGH_QUALITY_INTERSECTIONS (~(((~0) & 0x1) << 16))
6653 #define S_028804_INCOHERENT_EQAA_READS(x) (((x) & 0x1) << 17)
6654 #define G_028804_INCOHERENT_EQAA_READS(x) (((x) >> 17) & 0x1)
6655 #define C_028804_INCOHERENT_EQAA_READS (~(((~0) & 0x1) << 17))
6656 #define S_028804_INTERPOLATE_COMP_Z(x) (((x) & 0x1) << 18)
6657 #define G_028804_INTERPOLATE_COMP_Z(x) (((x) >> 18) & 0x1)
6658 #define C_028804_INTERPOLATE_COMP_Z (~(((~0) >> 18) & 0x1))
6659 #define S_028804_INTERPOLATE_SRC_Z(x) (((x) & 0x1) << 19)
6660 #define G_028804_INTERPOLATE_SRC_Z(x) (((x) >> 19) & 0x1)
6661 #define C_028804_INTERPOLATE_SRC_Z (~(((~0) & 0x1) << 19))
6662 #define S_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((x) & 0x1) << 20)
6663 #define G_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((x) >> 20) & 0x1)
6664 #define C_028804_STATIC_ANCHOR_ASSOCIATIONS (~(((~0) & 0x1) << 20))
6665 #define S_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((x) & 0x1) << 21)
6666 #define G_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((x) >> 21) & 0x1)
6667 #define C_028804_ALPHA_TO_MASK_EQAA_DISABLE (~(((~0) & 0x1) << 21))
6668 #define R_028808_CB_COLOR_CONTROL 0x028808
6669 #define S_028808_DEGAMMA_ENABLE(x) (((x) & 0x1) << 3)
6670 #define G_028808_DEGAMMA_ENABLE(x) (((x) >> 3) & 0x1)
6671 #define C_028808_DEGAMMA_ENABLE 0xFFFFFFF7
6672 #define S_028808_MODE(x) (((x) & 0x07) << 4)
6673 #define G_028808_MODE(x) (((x) >> 4) & 0x07)
6674 #define C_028808_MODE 0xFFFFFF8F
6675 #define V_028808_CB_DISABLE 0x00
6676 #define V_028808_CB_NORMAL 0x01
6677 #define V_028808_CB_ELIMINATE_FAST_CLEAR 0x02
6678 #define V_028808_CB_RESOLVE 0x03
6679 #define V_028808_CB_FMASK_DECOMPRESS 0x05
6680 #define S_028808_ROP3(x) (((x) & 0xFF) << 16)
6681 #define G_028808_ROP3(x) (((x) >> 16) & 0xFF)
6682 #define C_028808_ROP3 0xFF00FFFF
6683 #define V_028808_X_0X00 0x00
6684 #define V_028808_X_0X05 0x05
6685 #define V_028808_X_0X0A 0x0A
6686 #define V_028808_X_0X0F 0x0F
6687 #define V_028808_X_0X11 0x11
6688 #define V_028808_X_0X22 0x22
6689 #define V_028808_X_0X33 0x33
6690 #define V_028808_X_0X44 0x44
6691 #define V_028808_X_0X50 0x50
6692 #define V_028808_X_0X55 0x55
6693 #define V_028808_X_0X5A 0x5A
6694 #define V_028808_X_0X5F 0x5F
6695 #define V_028808_X_0X66 0x66
6696 #define V_028808_X_0X77 0x77
6697 #define V_028808_X_0X88 0x88
6698 #define V_028808_X_0X99 0x99
6699 #define V_028808_X_0XA0 0xA0
6700 #define V_028808_X_0XA5 0xA5
6701 #define V_028808_X_0XAA 0xAA
6702 #define V_028808_X_0XAF 0xAF
6703 #define V_028808_X_0XBB 0xBB
6704 #define V_028808_X_0XCC 0xCC
6705 #define V_028808_X_0XDD 0xDD
6706 #define V_028808_X_0XEE 0xEE
6707 #define V_028808_X_0XF0 0xF0
6708 #define V_028808_X_0XF5 0xF5
6709 #define V_028808_X_0XFA 0xFA
6710 #define V_028808_X_0XFF 0xFF
6711 #define R_02880C_DB_SHADER_CONTROL 0x02880C
6712 #define S_02880C_Z_EXPORT_ENABLE(x) (((x) & 0x1) << 0)
6713 #define G_02880C_Z_EXPORT_ENABLE(x) (((x) >> 0) & 0x1)
6714 #define C_02880C_Z_EXPORT_ENABLE 0xFFFFFFFE
6715 #define S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(x) (((x) & 0x1) << 1)
6716 #define G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(x) (((x) >> 1) & 0x1)
6717 #define C_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE 0xFFFFFFFD
6718 #define S_02880C_STENCIL_OP_VAL_EXPORT_ENABLE(x) (((x) & 0x1) << 2)
6719 #define G_02880C_STENCIL_OP_VAL_EXPORT_ENABLE(x) (((x) >> 2) & 0x1)
6720 #define C_02880C_STENCIL_OP_VAL_EXPORT_ENABLE 0xFFFFFFFB
6721 #define S_02880C_Z_ORDER(x) (((x) & 0x03) << 4)
6722 #define G_02880C_Z_ORDER(x) (((x) >> 4) & 0x03)
6723 #define C_02880C_Z_ORDER 0xFFFFFFCF
6724 #define V_02880C_LATE_Z 0x00
6725 #define V_02880C_EARLY_Z_THEN_LATE_Z 0x01
6726 #define V_02880C_RE_Z 0x02
6727 #define V_02880C_EARLY_Z_THEN_RE_Z 0x03
6728 #define S_02880C_KILL_ENABLE(x) (((x) & 0x1) << 6)
6729 #define G_02880C_KILL_ENABLE(x) (((x) >> 6) & 0x1)
6730 #define C_02880C_KILL_ENABLE 0xFFFFFFBF
6731 #define S_02880C_COVERAGE_TO_MASK_ENABLE(x) (((x) & 0x1) << 7)
6732 #define G_02880C_COVERAGE_TO_MASK_ENABLE(x) (((x) >> 7) & 0x1)
6733 #define C_02880C_COVERAGE_TO_MASK_ENABLE 0xFFFFFF7F
6734 #define S_02880C_MASK_EXPORT_ENABLE(x) (((x) & 0x1) << 8)
6735 #define G_02880C_MASK_EXPORT_ENABLE(x) (((x) >> 8) & 0x1)
6736 #define C_02880C_MASK_EXPORT_ENABLE 0xFFFFFEFF
6737 #define S_02880C_EXEC_ON_HIER_FAIL(x) (((x) & 0x1) << 9)
6738 #define G_02880C_EXEC_ON_HIER_FAIL(x) (((x) >> 9) & 0x1)
6739 #define C_02880C_EXEC_ON_HIER_FAIL 0xFFFFFDFF
6740 #define S_02880C_EXEC_ON_NOOP(x) (((x) & 0x1) << 10)
6741 #define G_02880C_EXEC_ON_NOOP(x) (((x) >> 10) & 0x1)
6742 #define C_02880C_EXEC_ON_NOOP 0xFFFFFBFF
6743 #define S_02880C_ALPHA_TO_MASK_DISABLE(x) (((x) & 0x1) << 11)
6744 #define G_02880C_ALPHA_TO_MASK_DISABLE(x) (((x) >> 11) & 0x1)
6745 #define C_02880C_ALPHA_TO_MASK_DISABLE 0xFFFFF7FF
6746 #define S_02880C_DEPTH_BEFORE_SHADER(x) (((x) & 0x1) << 12)
6747 #define G_02880C_DEPTH_BEFORE_SHADER(x) (((x) >> 12) & 0x1)
6748 #define C_02880C_DEPTH_BEFORE_SHADER 0xFFFFEFFF
6749 /* CIK */
6750 #define S_02880C_CONSERVATIVE_Z_EXPORT(x) (((x) & 0x03) << 13)
6751 #define G_02880C_CONSERVATIVE_Z_EXPORT(x) (((x) >> 13) & 0x03)
6752 #define C_02880C_CONSERVATIVE_Z_EXPORT 0xFFFF9FFF
6753 #define V_02880C_EXPORT_ANY_Z 0
6754 #define V_02880C_EXPORT_LESS_THAN_Z 1
6755 #define V_02880C_EXPORT_GREATER_THAN_Z 2
6756 #define V_02880C_EXPORT_RESERVED 3
6757 /* */
6758 #define R_028810_PA_CL_CLIP_CNTL 0x028810
6759 #define S_028810_UCP_ENA_0(x) (((x) & 0x1) << 0)
6760 #define G_028810_UCP_ENA_0(x) (((x) >> 0) & 0x1)
6761 #define C_028810_UCP_ENA_0 0xFFFFFFFE
6762 #define S_028810_UCP_ENA_1(x) (((x) & 0x1) << 1)
6763 #define G_028810_UCP_ENA_1(x) (((x) >> 1) & 0x1)
6764 #define C_028810_UCP_ENA_1 0xFFFFFFFD
6765 #define S_028810_UCP_ENA_2(x) (((x) & 0x1) << 2)
6766 #define G_028810_UCP_ENA_2(x) (((x) >> 2) & 0x1)
6767 #define C_028810_UCP_ENA_2 0xFFFFFFFB
6768 #define S_028810_UCP_ENA_3(x) (((x) & 0x1) << 3)
6769 #define G_028810_UCP_ENA_3(x) (((x) >> 3) & 0x1)
6770 #define C_028810_UCP_ENA_3 0xFFFFFFF7
6771 #define S_028810_UCP_ENA_4(x) (((x) & 0x1) << 4)
6772 #define G_028810_UCP_ENA_4(x) (((x) >> 4) & 0x1)
6773 #define C_028810_UCP_ENA_4 0xFFFFFFEF
6774 #define S_028810_UCP_ENA_5(x) (((x) & 0x1) << 5)
6775 #define G_028810_UCP_ENA_5(x) (((x) >> 5) & 0x1)
6776 #define C_028810_UCP_ENA_5 0xFFFFFFDF
6777 #define S_028810_PS_UCP_Y_SCALE_NEG(x) (((x) & 0x1) << 13)
6778 #define G_028810_PS_UCP_Y_SCALE_NEG(x) (((x) >> 13) & 0x1)
6779 #define C_028810_PS_UCP_Y_SCALE_NEG 0xFFFFDFFF
6780 #define S_028810_PS_UCP_MODE(x) (((x) & 0x03) << 14)
6781 #define G_028810_PS_UCP_MODE(x) (((x) >> 14) & 0x03)
6782 #define C_028810_PS_UCP_MODE 0xFFFF3FFF
6783 #define S_028810_CLIP_DISABLE(x) (((x) & 0x1) << 16)
6784 #define G_028810_CLIP_DISABLE(x) (((x) >> 16) & 0x1)
6785 #define C_028810_CLIP_DISABLE 0xFFFEFFFF
6786 #define S_028810_UCP_CULL_ONLY_ENA(x) (((x) & 0x1) << 17)
6787 #define G_028810_UCP_CULL_ONLY_ENA(x) (((x) >> 17) & 0x1)
6788 #define C_028810_UCP_CULL_ONLY_ENA 0xFFFDFFFF
6789 #define S_028810_BOUNDARY_EDGE_FLAG_ENA(x) (((x) & 0x1) << 18)
6790 #define G_028810_BOUNDARY_EDGE_FLAG_ENA(x) (((x) >> 18) & 0x1)
6791 #define C_028810_BOUNDARY_EDGE_FLAG_ENA 0xFFFBFFFF
6792 #define S_028810_DX_CLIP_SPACE_DEF(x) (((x) & 0x1) << 19)
6793 #define G_028810_DX_CLIP_SPACE_DEF(x) (((x) >> 19) & 0x1)
6794 #define C_028810_DX_CLIP_SPACE_DEF 0xFFF7FFFF
6795 #define S_028810_DIS_CLIP_ERR_DETECT(x) (((x) & 0x1) << 20)
6796 #define G_028810_DIS_CLIP_ERR_DETECT(x) (((x) >> 20) & 0x1)
6797 #define C_028810_DIS_CLIP_ERR_DETECT 0xFFEFFFFF
6798 #define S_028810_VTX_KILL_OR(x) (((x) & 0x1) << 21)
6799 #define G_028810_VTX_KILL_OR(x) (((x) >> 21) & 0x1)
6800 #define C_028810_VTX_KILL_OR 0xFFDFFFFF
6801 #define S_028810_DX_RASTERIZATION_KILL(x) (((x) & 0x1) << 22)
6802 #define G_028810_DX_RASTERIZATION_KILL(x) (((x) >> 22) & 0x1)
6803 #define C_028810_DX_RASTERIZATION_KILL 0xFFBFFFFF
6804 #define S_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) & 0x1) << 24)
6805 #define G_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) >> 24) & 0x1)
6806 #define C_028810_DX_LINEAR_ATTR_CLIP_ENA 0xFEFFFFFF
6807 #define S_028810_VTE_VPORT_PROVOKE_DISABLE(x) (((x) & 0x1) << 25)
6808 #define G_028810_VTE_VPORT_PROVOKE_DISABLE(x) (((x) >> 25) & 0x1)
6809 #define C_028810_VTE_VPORT_PROVOKE_DISABLE 0xFDFFFFFF
6810 #define S_028810_ZCLIP_NEAR_DISABLE(x) (((x) & 0x1) << 26)
6811 #define G_028810_ZCLIP_NEAR_DISABLE(x) (((x) >> 26) & 0x1)
6812 #define C_028810_ZCLIP_NEAR_DISABLE 0xFBFFFFFF
6813 #define S_028810_ZCLIP_FAR_DISABLE(x) (((x) & 0x1) << 27)
6814 #define G_028810_ZCLIP_FAR_DISABLE(x) (((x) >> 27) & 0x1)
6815 #define C_028810_ZCLIP_FAR_DISABLE 0xF7FFFFFF
6816 #define R_028814_PA_SU_SC_MODE_CNTL 0x028814
6817 #define S_028814_CULL_FRONT(x) (((x) & 0x1) << 0)
6818 #define G_028814_CULL_FRONT(x) (((x) >> 0) & 0x1)
6819 #define C_028814_CULL_FRONT 0xFFFFFFFE
6820 #define S_028814_CULL_BACK(x) (((x) & 0x1) << 1)
6821 #define G_028814_CULL_BACK(x) (((x) >> 1) & 0x1)
6822 #define C_028814_CULL_BACK 0xFFFFFFFD
6823 #define S_028814_FACE(x) (((x) & 0x1) << 2)
6824 #define G_028814_FACE(x) (((x) >> 2) & 0x1)
6825 #define C_028814_FACE 0xFFFFFFFB
6826 #define S_028814_POLY_MODE(x) (((x) & 0x03) << 3)
6827 #define G_028814_POLY_MODE(x) (((x) >> 3) & 0x03)
6828 #define C_028814_POLY_MODE 0xFFFFFFE7
6829 #define V_028814_X_DISABLE_POLY_MODE 0x00
6830 #define V_028814_X_DUAL_MODE 0x01
6831 #define S_028814_POLYMODE_FRONT_PTYPE(x) (((x) & 0x07) << 5)
6832 #define G_028814_POLYMODE_FRONT_PTYPE(x) (((x) >> 5) & 0x07)
6833 #define C_028814_POLYMODE_FRONT_PTYPE 0xFFFFFF1F
6834 #define V_028814_X_DRAW_POINTS 0x00
6835 #define V_028814_X_DRAW_LINES 0x01
6836 #define V_028814_X_DRAW_TRIANGLES 0x02
6837 #define S_028814_POLYMODE_BACK_PTYPE(x) (((x) & 0x07) << 8)
6838 #define G_028814_POLYMODE_BACK_PTYPE(x) (((x) >> 8) & 0x07)
6839 #define C_028814_POLYMODE_BACK_PTYPE 0xFFFFF8FF
6840 #define V_028814_X_DRAW_POINTS 0x00
6841 #define V_028814_X_DRAW_LINES 0x01
6842 #define V_028814_X_DRAW_TRIANGLES 0x02
6843 #define S_028814_POLY_OFFSET_FRONT_ENABLE(x) (((x) & 0x1) << 11)
6844 #define G_028814_POLY_OFFSET_FRONT_ENABLE(x) (((x) >> 11) & 0x1)
6845 #define C_028814_POLY_OFFSET_FRONT_ENABLE 0xFFFFF7FF
6846 #define S_028814_POLY_OFFSET_BACK_ENABLE(x) (((x) & 0x1) << 12)
6847 #define G_028814_POLY_OFFSET_BACK_ENABLE(x) (((x) >> 12) & 0x1)
6848 #define C_028814_POLY_OFFSET_BACK_ENABLE 0xFFFFEFFF
6849 #define S_028814_POLY_OFFSET_PARA_ENABLE(x) (((x) & 0x1) << 13)
6850 #define G_028814_POLY_OFFSET_PARA_ENABLE(x) (((x) >> 13) & 0x1)
6851 #define C_028814_POLY_OFFSET_PARA_ENABLE 0xFFFFDFFF
6852 #define S_028814_VTX_WINDOW_OFFSET_ENABLE(x) (((x) & 0x1) << 16)
6853 #define G_028814_VTX_WINDOW_OFFSET_ENABLE(x) (((x) >> 16) & 0x1)
6854 #define C_028814_VTX_WINDOW_OFFSET_ENABLE 0xFFFEFFFF
6855 #define S_028814_PROVOKING_VTX_LAST(x) (((x) & 0x1) << 19)
6856 #define G_028814_PROVOKING_VTX_LAST(x) (((x) >> 19) & 0x1)
6857 #define C_028814_PROVOKING_VTX_LAST 0xFFF7FFFF
6858 #define S_028814_PERSP_CORR_DIS(x) (((x) & 0x1) << 20)
6859 #define G_028814_PERSP_CORR_DIS(x) (((x) >> 20) & 0x1)
6860 #define C_028814_PERSP_CORR_DIS 0xFFEFFFFF
6861 #define S_028814_MULTI_PRIM_IB_ENA(x) (((x) & 0x1) << 21)
6862 #define G_028814_MULTI_PRIM_IB_ENA(x) (((x) >> 21) & 0x1)
6863 #define C_028814_MULTI_PRIM_IB_ENA 0xFFDFFFFF
6864 #define R_028818_PA_CL_VTE_CNTL 0x028818
6865 #define S_028818_VPORT_X_SCALE_ENA(x) (((x) & 0x1) << 0)
6866 #define G_028818_VPORT_X_SCALE_ENA(x) (((x) >> 0) & 0x1)
6867 #define C_028818_VPORT_X_SCALE_ENA 0xFFFFFFFE
6868 #define S_028818_VPORT_X_OFFSET_ENA(x) (((x) & 0x1) << 1)
6869 #define G_028818_VPORT_X_OFFSET_ENA(x) (((x) >> 1) & 0x1)
6870 #define C_028818_VPORT_X_OFFSET_ENA 0xFFFFFFFD
6871 #define S_028818_VPORT_Y_SCALE_ENA(x) (((x) & 0x1) << 2)
6872 #define G_028818_VPORT_Y_SCALE_ENA(x) (((x) >> 2) & 0x1)
6873 #define C_028818_VPORT_Y_SCALE_ENA 0xFFFFFFFB
6874 #define S_028818_VPORT_Y_OFFSET_ENA(x) (((x) & 0x1) << 3)
6875 #define G_028818_VPORT_Y_OFFSET_ENA(x) (((x) >> 3) & 0x1)
6876 #define C_028818_VPORT_Y_OFFSET_ENA 0xFFFFFFF7
6877 #define S_028818_VPORT_Z_SCALE_ENA(x) (((x) & 0x1) << 4)
6878 #define G_028818_VPORT_Z_SCALE_ENA(x) (((x) >> 4) & 0x1)
6879 #define C_028818_VPORT_Z_SCALE_ENA 0xFFFFFFEF
6880 #define S_028818_VPORT_Z_OFFSET_ENA(x) (((x) & 0x1) << 5)
6881 #define G_028818_VPORT_Z_OFFSET_ENA(x) (((x) >> 5) & 0x1)
6882 #define C_028818_VPORT_Z_OFFSET_ENA 0xFFFFFFDF
6883 #define S_028818_VTX_XY_FMT(x) (((x) & 0x1) << 8)
6884 #define G_028818_VTX_XY_FMT(x) (((x) >> 8) & 0x1)
6885 #define C_028818_VTX_XY_FMT 0xFFFFFEFF
6886 #define S_028818_VTX_Z_FMT(x) (((x) & 0x1) << 9)
6887 #define G_028818_VTX_Z_FMT(x) (((x) >> 9) & 0x1)
6888 #define C_028818_VTX_Z_FMT 0xFFFFFDFF
6889 #define S_028818_VTX_W0_FMT(x) (((x) & 0x1) << 10)
6890 #define G_028818_VTX_W0_FMT(x) (((x) >> 10) & 0x1)
6891 #define C_028818_VTX_W0_FMT 0xFFFFFBFF
6892 #define R_02881C_PA_CL_VS_OUT_CNTL 0x02881C
6893 #define S_02881C_CLIP_DIST_ENA_0(x) (((x) & 0x1) << 0)
6894 #define G_02881C_CLIP_DIST_ENA_0(x) (((x) >> 0) & 0x1)
6895 #define C_02881C_CLIP_DIST_ENA_0 0xFFFFFFFE
6896 #define S_02881C_CLIP_DIST_ENA_1(x) (((x) & 0x1) << 1)
6897 #define G_02881C_CLIP_DIST_ENA_1(x) (((x) >> 1) & 0x1)
6898 #define C_02881C_CLIP_DIST_ENA_1 0xFFFFFFFD
6899 #define S_02881C_CLIP_DIST_ENA_2(x) (((x) & 0x1) << 2)
6900 #define G_02881C_CLIP_DIST_ENA_2(x) (((x) >> 2) & 0x1)
6901 #define C_02881C_CLIP_DIST_ENA_2 0xFFFFFFFB
6902 #define S_02881C_CLIP_DIST_ENA_3(x) (((x) & 0x1) << 3)
6903 #define G_02881C_CLIP_DIST_ENA_3(x) (((x) >> 3) & 0x1)
6904 #define C_02881C_CLIP_DIST_ENA_3 0xFFFFFFF7
6905 #define S_02881C_CLIP_DIST_ENA_4(x) (((x) & 0x1) << 4)
6906 #define G_02881C_CLIP_DIST_ENA_4(x) (((x) >> 4) & 0x1)
6907 #define C_02881C_CLIP_DIST_ENA_4 0xFFFFFFEF
6908 #define S_02881C_CLIP_DIST_ENA_5(x) (((x) & 0x1) << 5)
6909 #define G_02881C_CLIP_DIST_ENA_5(x) (((x) >> 5) & 0x1)
6910 #define C_02881C_CLIP_DIST_ENA_5 0xFFFFFFDF
6911 #define S_02881C_CLIP_DIST_ENA_6(x) (((x) & 0x1) << 6)
6912 #define G_02881C_CLIP_DIST_ENA_6(x) (((x) >> 6) & 0x1)
6913 #define C_02881C_CLIP_DIST_ENA_6 0xFFFFFFBF
6914 #define S_02881C_CLIP_DIST_ENA_7(x) (((x) & 0x1) << 7)
6915 #define G_02881C_CLIP_DIST_ENA_7(x) (((x) >> 7) & 0x1)
6916 #define C_02881C_CLIP_DIST_ENA_7 0xFFFFFF7F
6917 #define S_02881C_CULL_DIST_ENA_0(x) (((x) & 0x1) << 8)
6918 #define G_02881C_CULL_DIST_ENA_0(x) (((x) >> 8) & 0x1)
6919 #define C_02881C_CULL_DIST_ENA_0 0xFFFFFEFF
6920 #define S_02881C_CULL_DIST_ENA_1(x) (((x) & 0x1) << 9)
6921 #define G_02881C_CULL_DIST_ENA_1(x) (((x) >> 9) & 0x1)
6922 #define C_02881C_CULL_DIST_ENA_1 0xFFFFFDFF
6923 #define S_02881C_CULL_DIST_ENA_2(x) (((x) & 0x1) << 10)
6924 #define G_02881C_CULL_DIST_ENA_2(x) (((x) >> 10) & 0x1)
6925 #define C_02881C_CULL_DIST_ENA_2 0xFFFFFBFF
6926 #define S_02881C_CULL_DIST_ENA_3(x) (((x) & 0x1) << 11)
6927 #define G_02881C_CULL_DIST_ENA_3(x) (((x) >> 11) & 0x1)
6928 #define C_02881C_CULL_DIST_ENA_3 0xFFFFF7FF
6929 #define S_02881C_CULL_DIST_ENA_4(x) (((x) & 0x1) << 12)
6930 #define G_02881C_CULL_DIST_ENA_4(x) (((x) >> 12) & 0x1)
6931 #define C_02881C_CULL_DIST_ENA_4 0xFFFFEFFF
6932 #define S_02881C_CULL_DIST_ENA_5(x) (((x) & 0x1) << 13)
6933 #define G_02881C_CULL_DIST_ENA_5(x) (((x) >> 13) & 0x1)
6934 #define C_02881C_CULL_DIST_ENA_5 0xFFFFDFFF
6935 #define S_02881C_CULL_DIST_ENA_6(x) (((x) & 0x1) << 14)
6936 #define G_02881C_CULL_DIST_ENA_6(x) (((x) >> 14) & 0x1)
6937 #define C_02881C_CULL_DIST_ENA_6 0xFFFFBFFF
6938 #define S_02881C_CULL_DIST_ENA_7(x) (((x) & 0x1) << 15)
6939 #define G_02881C_CULL_DIST_ENA_7(x) (((x) >> 15) & 0x1)
6940 #define C_02881C_CULL_DIST_ENA_7 0xFFFF7FFF
6941 #define S_02881C_USE_VTX_POINT_SIZE(x) (((x) & 0x1) << 16)
6942 #define G_02881C_USE_VTX_POINT_SIZE(x) (((x) >> 16) & 0x1)
6943 #define C_02881C_USE_VTX_POINT_SIZE 0xFFFEFFFF
6944 #define S_02881C_USE_VTX_EDGE_FLAG(x) (((x) & 0x1) << 17)
6945 #define G_02881C_USE_VTX_EDGE_FLAG(x) (((x) >> 17) & 0x1)
6946 #define C_02881C_USE_VTX_EDGE_FLAG 0xFFFDFFFF
6947 #define S_02881C_USE_VTX_RENDER_TARGET_INDX(x) (((x) & 0x1) << 18)
6948 #define G_02881C_USE_VTX_RENDER_TARGET_INDX(x) (((x) >> 18) & 0x1)
6949 #define C_02881C_USE_VTX_RENDER_TARGET_INDX 0xFFFBFFFF
6950 #define S_02881C_USE_VTX_VIEWPORT_INDX(x) (((x) & 0x1) << 19)
6951 #define G_02881C_USE_VTX_VIEWPORT_INDX(x) (((x) >> 19) & 0x1)
6952 #define C_02881C_USE_VTX_VIEWPORT_INDX 0xFFF7FFFF
6953 #define S_02881C_USE_VTX_KILL_FLAG(x) (((x) & 0x1) << 20)
6954 #define G_02881C_USE_VTX_KILL_FLAG(x) (((x) >> 20) & 0x1)
6955 #define C_02881C_USE_VTX_KILL_FLAG 0xFFEFFFFF
6956 #define S_02881C_VS_OUT_MISC_VEC_ENA(x) (((x) & 0x1) << 21)
6957 #define G_02881C_VS_OUT_MISC_VEC_ENA(x) (((x) >> 21) & 0x1)
6958 #define C_02881C_VS_OUT_MISC_VEC_ENA 0xFFDFFFFF
6959 #define S_02881C_VS_OUT_CCDIST0_VEC_ENA(x) (((x) & 0x1) << 22)
6960 #define G_02881C_VS_OUT_CCDIST0_VEC_ENA(x) (((x) >> 22) & 0x1)
6961 #define C_02881C_VS_OUT_CCDIST0_VEC_ENA 0xFFBFFFFF
6962 #define S_02881C_VS_OUT_CCDIST1_VEC_ENA(x) (((x) & 0x1) << 23)
6963 #define G_02881C_VS_OUT_CCDIST1_VEC_ENA(x) (((x) >> 23) & 0x1)
6964 #define C_02881C_VS_OUT_CCDIST1_VEC_ENA 0xFF7FFFFF
6965 #define S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(x) (((x) & 0x1) << 24)
6966 #define G_02881C_VS_OUT_MISC_SIDE_BUS_ENA(x) (((x) >> 24) & 0x1)
6967 #define C_02881C_VS_OUT_MISC_SIDE_BUS_ENA 0xFEFFFFFF
6968 #define S_02881C_USE_VTX_GS_CUT_FLAG(x) (((x) & 0x1) << 25)
6969 #define G_02881C_USE_VTX_GS_CUT_FLAG(x) (((x) >> 25) & 0x1)
6970 #define C_02881C_USE_VTX_GS_CUT_FLAG 0xFDFFFFFF
6971 #define R_028820_PA_CL_NANINF_CNTL 0x028820
6972 #define S_028820_VTE_XY_INF_DISCARD(x) (((x) & 0x1) << 0)
6973 #define G_028820_VTE_XY_INF_DISCARD(x) (((x) >> 0) & 0x1)
6974 #define C_028820_VTE_XY_INF_DISCARD 0xFFFFFFFE
6975 #define S_028820_VTE_Z_INF_DISCARD(x) (((x) & 0x1) << 1)
6976 #define G_028820_VTE_Z_INF_DISCARD(x) (((x) >> 1) & 0x1)
6977 #define C_028820_VTE_Z_INF_DISCARD 0xFFFFFFFD
6978 #define S_028820_VTE_W_INF_DISCARD(x) (((x) & 0x1) << 2)
6979 #define G_028820_VTE_W_INF_DISCARD(x) (((x) >> 2) & 0x1)
6980 #define C_028820_VTE_W_INF_DISCARD 0xFFFFFFFB
6981 #define S_028820_VTE_0XNANINF_IS_0(x) (((x) & 0x1) << 3)
6982 #define G_028820_VTE_0XNANINF_IS_0(x) (((x) >> 3) & 0x1)
6983 #define C_028820_VTE_0XNANINF_IS_0 0xFFFFFFF7
6984 #define S_028820_VTE_XY_NAN_RETAIN(x) (((x) & 0x1) << 4)
6985 #define G_028820_VTE_XY_NAN_RETAIN(x) (((x) >> 4) & 0x1)
6986 #define C_028820_VTE_XY_NAN_RETAIN 0xFFFFFFEF
6987 #define S_028820_VTE_Z_NAN_RETAIN(x) (((x) & 0x1) << 5)
6988 #define G_028820_VTE_Z_NAN_RETAIN(x) (((x) >> 5) & 0x1)
6989 #define C_028820_VTE_Z_NAN_RETAIN 0xFFFFFFDF
6990 #define S_028820_VTE_W_NAN_RETAIN(x) (((x) & 0x1) << 6)
6991 #define G_028820_VTE_W_NAN_RETAIN(x) (((x) >> 6) & 0x1)
6992 #define C_028820_VTE_W_NAN_RETAIN 0xFFFFFFBF
6993 #define S_028820_VTE_W_RECIP_NAN_IS_0(x) (((x) & 0x1) << 7)
6994 #define G_028820_VTE_W_RECIP_NAN_IS_0(x) (((x) >> 7) & 0x1)
6995 #define C_028820_VTE_W_RECIP_NAN_IS_0 0xFFFFFF7F
6996 #define S_028820_VS_XY_NAN_TO_INF(x) (((x) & 0x1) << 8)
6997 #define G_028820_VS_XY_NAN_TO_INF(x) (((x) >> 8) & 0x1)
6998 #define C_028820_VS_XY_NAN_TO_INF 0xFFFFFEFF
6999 #define S_028820_VS_XY_INF_RETAIN(x) (((x) & 0x1) << 9)
7000 #define G_028820_VS_XY_INF_RETAIN(x) (((x) >> 9) & 0x1)
7001 #define C_028820_VS_XY_INF_RETAIN 0xFFFFFDFF
7002 #define S_028820_VS_Z_NAN_TO_INF(x) (((x) & 0x1) << 10)
7003 #define G_028820_VS_Z_NAN_TO_INF(x) (((x) >> 10) & 0x1)
7004 #define C_028820_VS_Z_NAN_TO_INF 0xFFFFFBFF
7005 #define S_028820_VS_Z_INF_RETAIN(x) (((x) & 0x1) << 11)
7006 #define G_028820_VS_Z_INF_RETAIN(x) (((x) >> 11) & 0x1)
7007 #define C_028820_VS_Z_INF_RETAIN 0xFFFFF7FF
7008 #define S_028820_VS_W_NAN_TO_INF(x) (((x) & 0x1) << 12)
7009 #define G_028820_VS_W_NAN_TO_INF(x) (((x) >> 12) & 0x1)
7010 #define C_028820_VS_W_NAN_TO_INF 0xFFFFEFFF
7011 #define S_028820_VS_W_INF_RETAIN(x) (((x) & 0x1) << 13)
7012 #define G_028820_VS_W_INF_RETAIN(x) (((x) >> 13) & 0x1)
7013 #define C_028820_VS_W_INF_RETAIN 0xFFFFDFFF
7014 #define S_028820_VS_CLIP_DIST_INF_DISCARD(x) (((x) & 0x1) << 14)
7015 #define G_028820_VS_CLIP_DIST_INF_DISCARD(x) (((x) >> 14) & 0x1)
7016 #define C_028820_VS_CLIP_DIST_INF_DISCARD 0xFFFFBFFF
7017 #define S_028820_VTE_NO_OUTPUT_NEG_0(x) (((x) & 0x1) << 20)
7018 #define G_028820_VTE_NO_OUTPUT_NEG_0(x) (((x) >> 20) & 0x1)
7019 #define C_028820_VTE_NO_OUTPUT_NEG_0 0xFFEFFFFF
7020 #define R_028824_PA_SU_LINE_STIPPLE_CNTL 0x028824
7021 #define S_028824_LINE_STIPPLE_RESET(x) (((x) & 0x03) << 0)
7022 #define G_028824_LINE_STIPPLE_RESET(x) (((x) >> 0) & 0x03)
7023 #define C_028824_LINE_STIPPLE_RESET 0xFFFFFFFC
7024 #define S_028824_EXPAND_FULL_LENGTH(x) (((x) & 0x1) << 2)
7025 #define G_028824_EXPAND_FULL_LENGTH(x) (((x) >> 2) & 0x1)
7026 #define C_028824_EXPAND_FULL_LENGTH 0xFFFFFFFB
7027 #define S_028824_FRACTIONAL_ACCUM(x) (((x) & 0x1) << 3)
7028 #define G_028824_FRACTIONAL_ACCUM(x) (((x) >> 3) & 0x1)
7029 #define C_028824_FRACTIONAL_ACCUM 0xFFFFFFF7
7030 #define S_028824_DIAMOND_ADJUST(x) (((x) & 0x1) << 4)
7031 #define G_028824_DIAMOND_ADJUST(x) (((x) >> 4) & 0x1)
7032 #define C_028824_DIAMOND_ADJUST 0xFFFFFFEF
7033 #define R_028828_PA_SU_LINE_STIPPLE_SCALE 0x028828
7034 #define R_02882C_PA_SU_PRIM_FILTER_CNTL 0x02882C
7035 #define S_02882C_TRIANGLE_FILTER_DISABLE(x) (((x) & 0x1) << 0)
7036 #define G_02882C_TRIANGLE_FILTER_DISABLE(x) (((x) >> 0) & 0x1)
7037 #define C_02882C_TRIANGLE_FILTER_DISABLE 0xFFFFFFFE
7038 #define S_02882C_LINE_FILTER_DISABLE(x) (((x) & 0x1) << 1)
7039 #define G_02882C_LINE_FILTER_DISABLE(x) (((x) >> 1) & 0x1)
7040 #define C_02882C_LINE_FILTER_DISABLE 0xFFFFFFFD
7041 #define S_02882C_POINT_FILTER_DISABLE(x) (((x) & 0x1) << 2)
7042 #define G_02882C_POINT_FILTER_DISABLE(x) (((x) >> 2) & 0x1)
7043 #define C_02882C_POINT_FILTER_DISABLE 0xFFFFFFFB
7044 #define S_02882C_RECTANGLE_FILTER_DISABLE(x) (((x) & 0x1) << 3)
7045 #define G_02882C_RECTANGLE_FILTER_DISABLE(x) (((x) >> 3) & 0x1)
7046 #define C_02882C_RECTANGLE_FILTER_DISABLE 0xFFFFFFF7
7047 #define S_02882C_TRIANGLE_EXPAND_ENA(x) (((x) & 0x1) << 4)
7048 #define G_02882C_TRIANGLE_EXPAND_ENA(x) (((x) >> 4) & 0x1)
7049 #define C_02882C_TRIANGLE_EXPAND_ENA 0xFFFFFFEF
7050 #define S_02882C_LINE_EXPAND_ENA(x) (((x) & 0x1) << 5)
7051 #define G_02882C_LINE_EXPAND_ENA(x) (((x) >> 5) & 0x1)
7052 #define C_02882C_LINE_EXPAND_ENA 0xFFFFFFDF
7053 #define S_02882C_POINT_EXPAND_ENA(x) (((x) & 0x1) << 6)
7054 #define G_02882C_POINT_EXPAND_ENA(x) (((x) >> 6) & 0x1)
7055 #define C_02882C_POINT_EXPAND_ENA 0xFFFFFFBF
7056 #define S_02882C_RECTANGLE_EXPAND_ENA(x) (((x) & 0x1) << 7)
7057 #define G_02882C_RECTANGLE_EXPAND_ENA(x) (((x) >> 7) & 0x1)
7058 #define C_02882C_RECTANGLE_EXPAND_ENA 0xFFFFFF7F
7059 #define S_02882C_PRIM_EXPAND_CONSTANT(x) (((x) & 0xFF) << 8)
7060 #define G_02882C_PRIM_EXPAND_CONSTANT(x) (((x) >> 8) & 0xFF)
7061 #define C_02882C_PRIM_EXPAND_CONSTANT 0xFFFF00FF
7062 /* CIK */
7063 #define S_02882C_XMAX_RIGHT_EXCLUSION(x) (((x) & 0x1) << 30)
7064 #define G_02882C_XMAX_RIGHT_EXCLUSION(x) (((x) >> 30) & 0x1)
7065 #define C_02882C_XMAX_RIGHT_EXCLUSION 0xBFFFFFFF
7066 #define S_02882C_YMAX_BOTTOM_EXCLUSION(x) (((x) & 0x1) << 31)
7067 #define G_02882C_YMAX_BOTTOM_EXCLUSION(x) (((x) >> 31) & 0x1)
7068 #define C_02882C_YMAX_BOTTOM_EXCLUSION 0x7FFFFFFF
7069 /* */
7070 #define R_028A00_PA_SU_POINT_SIZE 0x028A00
7071 #define S_028A00_HEIGHT(x) (((x) & 0xFFFF) << 0)
7072 #define G_028A00_HEIGHT(x) (((x) >> 0) & 0xFFFF)
7073 #define C_028A00_HEIGHT 0xFFFF0000
7074 #define S_028A00_WIDTH(x) (((x) & 0xFFFF) << 16)
7075 #define G_028A00_WIDTH(x) (((x) >> 16) & 0xFFFF)
7076 #define C_028A00_WIDTH 0x0000FFFF
7077 #define R_028A04_PA_SU_POINT_MINMAX 0x028A04
7078 #define S_028A04_MIN_SIZE(x) (((x) & 0xFFFF) << 0)
7079 #define G_028A04_MIN_SIZE(x) (((x) >> 0) & 0xFFFF)
7080 #define C_028A04_MIN_SIZE 0xFFFF0000
7081 #define S_028A04_MAX_SIZE(x) (((x) & 0xFFFF) << 16)
7082 #define G_028A04_MAX_SIZE(x) (((x) >> 16) & 0xFFFF)
7083 #define C_028A04_MAX_SIZE 0x0000FFFF
7084 #define R_028A08_PA_SU_LINE_CNTL 0x028A08
7085 #define S_028A08_WIDTH(x) (((x) & 0xFFFF) << 0)
7086 #define G_028A08_WIDTH(x) (((x) >> 0) & 0xFFFF)
7087 #define C_028A08_WIDTH 0xFFFF0000
7088 #define R_028A0C_PA_SC_LINE_STIPPLE 0x028A0C
7089 #define S_028A0C_LINE_PATTERN(x) (((x) & 0xFFFF) << 0)
7090 #define G_028A0C_LINE_PATTERN(x) (((x) >> 0) & 0xFFFF)
7091 #define C_028A0C_LINE_PATTERN 0xFFFF0000
7092 #define S_028A0C_REPEAT_COUNT(x) (((x) & 0xFF) << 16)
7093 #define G_028A0C_REPEAT_COUNT(x) (((x) >> 16) & 0xFF)
7094 #define C_028A0C_REPEAT_COUNT 0xFF00FFFF
7095 #define S_028A0C_PATTERN_BIT_ORDER(x) (((x) & 0x1) << 28)
7096 #define G_028A0C_PATTERN_BIT_ORDER(x) (((x) >> 28) & 0x1)
7097 #define C_028A0C_PATTERN_BIT_ORDER 0xEFFFFFFF
7098 #define S_028A0C_AUTO_RESET_CNTL(x) (((x) & 0x03) << 29)
7099 #define G_028A0C_AUTO_RESET_CNTL(x) (((x) >> 29) & 0x03)
7100 #define C_028A0C_AUTO_RESET_CNTL 0x9FFFFFFF
7101 #define R_028A10_VGT_OUTPUT_PATH_CNTL 0x028A10
7102 #define S_028A10_PATH_SELECT(x) (((x) & 0x07) << 0)
7103 #define G_028A10_PATH_SELECT(x) (((x) >> 0) & 0x07)
7104 #define C_028A10_PATH_SELECT 0xFFFFFFF8
7105 #define V_028A10_VGT_OUTPATH_VTX_REUSE 0x00
7106 #define V_028A10_VGT_OUTPATH_TESS_EN 0x01
7107 #define V_028A10_VGT_OUTPATH_PASSTHRU 0x02
7108 #define V_028A10_VGT_OUTPATH_GS_BLOCK 0x03
7109 #define V_028A10_VGT_OUTPATH_HS_BLOCK 0x04
7110 #define R_028A14_VGT_HOS_CNTL 0x028A14
7111 #define S_028A14_TESS_MODE(x) (((x) & 0x03) << 0)
7112 #define G_028A14_TESS_MODE(x) (((x) >> 0) & 0x03)
7113 #define C_028A14_TESS_MODE 0xFFFFFFFC
7114 #define R_028A18_VGT_HOS_MAX_TESS_LEVEL 0x028A18
7115 #define R_028A1C_VGT_HOS_MIN_TESS_LEVEL 0x028A1C
7116 #define R_028A20_VGT_HOS_REUSE_DEPTH 0x028A20
7117 #define S_028A20_REUSE_DEPTH(x) (((x) & 0xFF) << 0)
7118 #define G_028A20_REUSE_DEPTH(x) (((x) >> 0) & 0xFF)
7119 #define C_028A20_REUSE_DEPTH 0xFFFFFF00
7120 #define R_028A24_VGT_GROUP_PRIM_TYPE 0x028A24
7121 #define S_028A24_PRIM_TYPE(x) (((x) & 0x1F) << 0)
7122 #define G_028A24_PRIM_TYPE(x) (((x) >> 0) & 0x1F)
7123 #define C_028A24_PRIM_TYPE 0xFFFFFFE0
7124 #define V_028A24_VGT_GRP_3D_POINT 0x00
7125 #define V_028A24_VGT_GRP_3D_LINE 0x01
7126 #define V_028A24_VGT_GRP_3D_TRI 0x02
7127 #define V_028A24_VGT_GRP_3D_RECT 0x03
7128 #define V_028A24_VGT_GRP_3D_QUAD 0x04
7129 #define V_028A24_VGT_GRP_2D_COPY_RECT_V0 0x05
7130 #define V_028A24_VGT_GRP_2D_COPY_RECT_V1 0x06
7131 #define V_028A24_VGT_GRP_2D_COPY_RECT_V2 0x07
7132 #define V_028A24_VGT_GRP_2D_COPY_RECT_V3 0x08
7133 #define V_028A24_VGT_GRP_2D_FILL_RECT 0x09
7134 #define V_028A24_VGT_GRP_2D_LINE 0x0A
7135 #define V_028A24_VGT_GRP_2D_TRI 0x0B
7136 #define V_028A24_VGT_GRP_PRIM_INDEX_LINE 0x0C
7137 #define V_028A24_VGT_GRP_PRIM_INDEX_TRI 0x0D
7138 #define V_028A24_VGT_GRP_PRIM_INDEX_QUAD 0x0E
7139 #define V_028A24_VGT_GRP_3D_LINE_ADJ 0x0F
7140 #define V_028A24_VGT_GRP_3D_TRI_ADJ 0x10
7141 #define V_028A24_VGT_GRP_3D_PATCH 0x11
7142 #define S_028A24_RETAIN_ORDER(x) (((x) & 0x1) << 14)
7143 #define G_028A24_RETAIN_ORDER(x) (((x) >> 14) & 0x1)
7144 #define C_028A24_RETAIN_ORDER 0xFFFFBFFF
7145 #define S_028A24_RETAIN_QUADS(x) (((x) & 0x1) << 15)
7146 #define G_028A24_RETAIN_QUADS(x) (((x) >> 15) & 0x1)
7147 #define C_028A24_RETAIN_QUADS 0xFFFF7FFF
7148 #define S_028A24_PRIM_ORDER(x) (((x) & 0x07) << 16)
7149 #define G_028A24_PRIM_ORDER(x) (((x) >> 16) & 0x07)
7150 #define C_028A24_PRIM_ORDER 0xFFF8FFFF
7151 #define V_028A24_VGT_GRP_LIST 0x00
7152 #define V_028A24_VGT_GRP_STRIP 0x01
7153 #define V_028A24_VGT_GRP_FAN 0x02
7154 #define V_028A24_VGT_GRP_LOOP 0x03
7155 #define V_028A24_VGT_GRP_POLYGON 0x04
7156 #define R_028A28_VGT_GROUP_FIRST_DECR 0x028A28
7157 #define S_028A28_FIRST_DECR(x) (((x) & 0x0F) << 0)
7158 #define G_028A28_FIRST_DECR(x) (((x) >> 0) & 0x0F)
7159 #define C_028A28_FIRST_DECR 0xFFFFFFF0
7160 #define R_028A2C_VGT_GROUP_DECR 0x028A2C
7161 #define S_028A2C_DECR(x) (((x) & 0x0F) << 0)
7162 #define G_028A2C_DECR(x) (((x) >> 0) & 0x0F)
7163 #define C_028A2C_DECR 0xFFFFFFF0
7164 #define R_028A30_VGT_GROUP_VECT_0_CNTL 0x028A30
7165 #define S_028A30_COMP_X_EN(x) (((x) & 0x1) << 0)
7166 #define G_028A30_COMP_X_EN(x) (((x) >> 0) & 0x1)
7167 #define C_028A30_COMP_X_EN 0xFFFFFFFE
7168 #define S_028A30_COMP_Y_EN(x) (((x) & 0x1) << 1)
7169 #define G_028A30_COMP_Y_EN(x) (((x) >> 1) & 0x1)
7170 #define C_028A30_COMP_Y_EN 0xFFFFFFFD
7171 #define S_028A30_COMP_Z_EN(x) (((x) & 0x1) << 2)
7172 #define G_028A30_COMP_Z_EN(x) (((x) >> 2) & 0x1)
7173 #define C_028A30_COMP_Z_EN 0xFFFFFFFB
7174 #define S_028A30_COMP_W_EN(x) (((x) & 0x1) << 3)
7175 #define G_028A30_COMP_W_EN(x) (((x) >> 3) & 0x1)
7176 #define C_028A30_COMP_W_EN 0xFFFFFFF7
7177 #define S_028A30_STRIDE(x) (((x) & 0xFF) << 8)
7178 #define G_028A30_STRIDE(x) (((x) >> 8) & 0xFF)
7179 #define C_028A30_STRIDE 0xFFFF00FF
7180 #define S_028A30_SHIFT(x) (((x) & 0xFF) << 16)
7181 #define G_028A30_SHIFT(x) (((x) >> 16) & 0xFF)
7182 #define C_028A30_SHIFT 0xFF00FFFF
7183 #define R_028A34_VGT_GROUP_VECT_1_CNTL 0x028A34
7184 #define S_028A34_COMP_X_EN(x) (((x) & 0x1) << 0)
7185 #define G_028A34_COMP_X_EN(x) (((x) >> 0) & 0x1)
7186 #define C_028A34_COMP_X_EN 0xFFFFFFFE
7187 #define S_028A34_COMP_Y_EN(x) (((x) & 0x1) << 1)
7188 #define G_028A34_COMP_Y_EN(x) (((x) >> 1) & 0x1)
7189 #define C_028A34_COMP_Y_EN 0xFFFFFFFD
7190 #define S_028A34_COMP_Z_EN(x) (((x) & 0x1) << 2)
7191 #define G_028A34_COMP_Z_EN(x) (((x) >> 2) & 0x1)
7192 #define C_028A34_COMP_Z_EN 0xFFFFFFFB
7193 #define S_028A34_COMP_W_EN(x) (((x) & 0x1) << 3)
7194 #define G_028A34_COMP_W_EN(x) (((x) >> 3) & 0x1)
7195 #define C_028A34_COMP_W_EN 0xFFFFFFF7
7196 #define S_028A34_STRIDE(x) (((x) & 0xFF) << 8)
7197 #define G_028A34_STRIDE(x) (((x) >> 8) & 0xFF)
7198 #define C_028A34_STRIDE 0xFFFF00FF
7199 #define S_028A34_SHIFT(x) (((x) & 0xFF) << 16)
7200 #define G_028A34_SHIFT(x) (((x) >> 16) & 0xFF)
7201 #define C_028A34_SHIFT 0xFF00FFFF
7202 #define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL 0x028A38
7203 #define S_028A38_X_CONV(x) (((x) & 0x0F) << 0)
7204 #define G_028A38_X_CONV(x) (((x) >> 0) & 0x0F)
7205 #define C_028A38_X_CONV 0xFFFFFFF0
7206 #define V_028A38_VGT_GRP_INDEX_16 0x00
7207 #define V_028A38_VGT_GRP_INDEX_32 0x01
7208 #define V_028A38_VGT_GRP_UINT_16 0x02
7209 #define V_028A38_VGT_GRP_UINT_32 0x03
7210 #define V_028A38_VGT_GRP_SINT_16 0x04
7211 #define V_028A38_VGT_GRP_SINT_32 0x05
7212 #define V_028A38_VGT_GRP_FLOAT_32 0x06
7213 #define V_028A38_VGT_GRP_AUTO_PRIM 0x07
7214 #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
7215 #define S_028A38_X_OFFSET(x) (((x) & 0x0F) << 4)
7216 #define G_028A38_X_OFFSET(x) (((x) >> 4) & 0x0F)
7217 #define C_028A38_X_OFFSET 0xFFFFFF0F
7218 #define S_028A38_Y_CONV(x) (((x) & 0x0F) << 8)
7219 #define G_028A38_Y_CONV(x) (((x) >> 8) & 0x0F)
7220 #define C_028A38_Y_CONV 0xFFFFF0FF
7221 #define V_028A38_VGT_GRP_INDEX_16 0x00
7222 #define V_028A38_VGT_GRP_INDEX_32 0x01
7223 #define V_028A38_VGT_GRP_UINT_16 0x02
7224 #define V_028A38_VGT_GRP_UINT_32 0x03
7225 #define V_028A38_VGT_GRP_SINT_16 0x04
7226 #define V_028A38_VGT_GRP_SINT_32 0x05
7227 #define V_028A38_VGT_GRP_FLOAT_32 0x06
7228 #define V_028A38_VGT_GRP_AUTO_PRIM 0x07
7229 #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
7230 #define S_028A38_Y_OFFSET(x) (((x) & 0x0F) << 12)
7231 #define G_028A38_Y_OFFSET(x) (((x) >> 12) & 0x0F)
7232 #define C_028A38_Y_OFFSET 0xFFFF0FFF
7233 #define S_028A38_Z_CONV(x) (((x) & 0x0F) << 16)
7234 #define G_028A38_Z_CONV(x) (((x) >> 16) & 0x0F)
7235 #define C_028A38_Z_CONV 0xFFF0FFFF
7236 #define V_028A38_VGT_GRP_INDEX_16 0x00
7237 #define V_028A38_VGT_GRP_INDEX_32 0x01
7238 #define V_028A38_VGT_GRP_UINT_16 0x02
7239 #define V_028A38_VGT_GRP_UINT_32 0x03
7240 #define V_028A38_VGT_GRP_SINT_16 0x04
7241 #define V_028A38_VGT_GRP_SINT_32 0x05
7242 #define V_028A38_VGT_GRP_FLOAT_32 0x06
7243 #define V_028A38_VGT_GRP_AUTO_PRIM 0x07
7244 #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
7245 #define S_028A38_Z_OFFSET(x) (((x) & 0x0F) << 20)
7246 #define G_028A38_Z_OFFSET(x) (((x) >> 20) & 0x0F)
7247 #define C_028A38_Z_OFFSET 0xFF0FFFFF
7248 #define S_028A38_W_CONV(x) (((x) & 0x0F) << 24)
7249 #define G_028A38_W_CONV(x) (((x) >> 24) & 0x0F)
7250 #define C_028A38_W_CONV 0xF0FFFFFF
7251 #define V_028A38_VGT_GRP_INDEX_16 0x00
7252 #define V_028A38_VGT_GRP_INDEX_32 0x01
7253 #define V_028A38_VGT_GRP_UINT_16 0x02
7254 #define V_028A38_VGT_GRP_UINT_32 0x03
7255 #define V_028A38_VGT_GRP_SINT_16 0x04
7256 #define V_028A38_VGT_GRP_SINT_32 0x05
7257 #define V_028A38_VGT_GRP_FLOAT_32 0x06
7258 #define V_028A38_VGT_GRP_AUTO_PRIM 0x07
7259 #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
7260 #define S_028A38_W_OFFSET(x) (((x) & 0x0F) << 28)
7261 #define G_028A38_W_OFFSET(x) (((x) >> 28) & 0x0F)
7262 #define C_028A38_W_OFFSET 0x0FFFFFFF
7263 #define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL 0x028A3C
7264 #define S_028A3C_X_CONV(x) (((x) & 0x0F) << 0)
7265 #define G_028A3C_X_CONV(x) (((x) >> 0) & 0x0F)
7266 #define C_028A3C_X_CONV 0xFFFFFFF0
7267 #define V_028A3C_VGT_GRP_INDEX_16 0x00
7268 #define V_028A3C_VGT_GRP_INDEX_32 0x01
7269 #define V_028A3C_VGT_GRP_UINT_16 0x02
7270 #define V_028A3C_VGT_GRP_UINT_32 0x03
7271 #define V_028A3C_VGT_GRP_SINT_16 0x04
7272 #define V_028A3C_VGT_GRP_SINT_32 0x05
7273 #define V_028A3C_VGT_GRP_FLOAT_32 0x06
7274 #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07
7275 #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
7276 #define S_028A3C_X_OFFSET(x) (((x) & 0x0F) << 4)
7277 #define G_028A3C_X_OFFSET(x) (((x) >> 4) & 0x0F)
7278 #define C_028A3C_X_OFFSET 0xFFFFFF0F
7279 #define S_028A3C_Y_CONV(x) (((x) & 0x0F) << 8)
7280 #define G_028A3C_Y_CONV(x) (((x) >> 8) & 0x0F)
7281 #define C_028A3C_Y_CONV 0xFFFFF0FF
7282 #define V_028A3C_VGT_GRP_INDEX_16 0x00
7283 #define V_028A3C_VGT_GRP_INDEX_32 0x01
7284 #define V_028A3C_VGT_GRP_UINT_16 0x02
7285 #define V_028A3C_VGT_GRP_UINT_32 0x03
7286 #define V_028A3C_VGT_GRP_SINT_16 0x04
7287 #define V_028A3C_VGT_GRP_SINT_32 0x05
7288 #define V_028A3C_VGT_GRP_FLOAT_32 0x06
7289 #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07
7290 #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
7291 #define S_028A3C_Y_OFFSET(x) (((x) & 0x0F) << 12)
7292 #define G_028A3C_Y_OFFSET(x) (((x) >> 12) & 0x0F)
7293 #define C_028A3C_Y_OFFSET 0xFFFF0FFF
7294 #define S_028A3C_Z_CONV(x) (((x) & 0x0F) << 16)
7295 #define G_028A3C_Z_CONV(x) (((x) >> 16) & 0x0F)
7296 #define C_028A3C_Z_CONV 0xFFF0FFFF
7297 #define V_028A3C_VGT_GRP_INDEX_16 0x00
7298 #define V_028A3C_VGT_GRP_INDEX_32 0x01
7299 #define V_028A3C_VGT_GRP_UINT_16 0x02
7300 #define V_028A3C_VGT_GRP_UINT_32 0x03
7301 #define V_028A3C_VGT_GRP_SINT_16 0x04
7302 #define V_028A3C_VGT_GRP_SINT_32 0x05
7303 #define V_028A3C_VGT_GRP_FLOAT_32 0x06
7304 #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07
7305 #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
7306 #define S_028A3C_Z_OFFSET(x) (((x) & 0x0F) << 20)
7307 #define G_028A3C_Z_OFFSET(x) (((x) >> 20) & 0x0F)
7308 #define C_028A3C_Z_OFFSET 0xFF0FFFFF
7309 #define S_028A3C_W_CONV(x) (((x) & 0x0F) << 24)
7310 #define G_028A3C_W_CONV(x) (((x) >> 24) & 0x0F)
7311 #define C_028A3C_W_CONV 0xF0FFFFFF
7312 #define V_028A3C_VGT_GRP_INDEX_16 0x00
7313 #define V_028A3C_VGT_GRP_INDEX_32 0x01
7314 #define V_028A3C_VGT_GRP_UINT_16 0x02
7315 #define V_028A3C_VGT_GRP_UINT_32 0x03
7316 #define V_028A3C_VGT_GRP_SINT_16 0x04
7317 #define V_028A3C_VGT_GRP_SINT_32 0x05
7318 #define V_028A3C_VGT_GRP_FLOAT_32 0x06
7319 #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07
7320 #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
7321 #define S_028A3C_W_OFFSET(x) (((x) & 0x0F) << 28)
7322 #define G_028A3C_W_OFFSET(x) (((x) >> 28) & 0x0F)
7323 #define C_028A3C_W_OFFSET 0x0FFFFFFF
7324 #define R_028A40_VGT_GS_MODE 0x028A40
7325 #define S_028A40_MODE(x) (((x) & 0x07) << 0)
7326 #define G_028A40_MODE(x) (((x) >> 0) & 0x07)
7327 #define C_028A40_MODE 0xFFFFFFF8
7328 #define V_028A40_GS_OFF 0x00
7329 #define V_028A40_GS_SCENARIO_A 0x01
7330 #define V_028A40_GS_SCENARIO_B 0x02
7331 #define V_028A40_GS_SCENARIO_G 0x03
7332 #define V_028A40_GS_SCENARIO_C 0x04
7333 #define V_028A40_SPRITE_EN 0x05
7334 #define S_028A40_CUT_MODE(x) (((x) & 0x03) << 4)
7335 #define G_028A40_CUT_MODE(x) (((x) >> 4) & 0x03)
7336 #define C_028A40_CUT_MODE 0xFFFFFFCF
7337 #define V_028A40_GS_CUT_1024 0x00
7338 #define V_028A40_GS_CUT_512 0x01
7339 #define V_028A40_GS_CUT_256 0x02
7340 #define V_028A40_GS_CUT_128 0x03
7341 #define S_028A40_GS_C_PACK_EN(x) (((x) & 0x1) << 11)
7342 #define G_028A40_GS_C_PACK_EN(x) (((x) >> 11) & 0x1)
7343 #define C_028A40_GS_C_PACK_EN 0xFFFFF7FF
7344 #define S_028A40_ES_PASSTHRU(x) (((x) & 0x1) << 13)
7345 #define G_028A40_ES_PASSTHRU(x) (((x) >> 13) & 0x1)
7346 #define C_028A40_ES_PASSTHRU 0xFFFFDFFF
7347 #define S_028A40_COMPUTE_MODE(x) (((x) & 0x1) << 14)
7348 #define G_028A40_COMPUTE_MODE(x) (((x) >> 14) & 0x1)
7349 #define C_028A40_COMPUTE_MODE 0xFFFFBFFF
7350 #define S_028A40_FAST_COMPUTE_MODE(x) (((x) & 0x1) << 15)
7351 #define G_028A40_FAST_COMPUTE_MODE(x) (((x) >> 15) & 0x1)
7352 #define C_028A40_FAST_COMPUTE_MODE 0xFFFF7FFF
7353 #define S_028A40_ELEMENT_INFO_EN(x) (((x) & 0x1) << 16)
7354 #define G_028A40_ELEMENT_INFO_EN(x) (((x) >> 16) & 0x1)
7355 #define C_028A40_ELEMENT_INFO_EN 0xFFFEFFFF
7356 #define S_028A40_PARTIAL_THD_AT_EOI(x) (((x) & 0x1) << 17)
7357 #define G_028A40_PARTIAL_THD_AT_EOI(x) (((x) >> 17) & 0x1)
7358 #define C_028A40_PARTIAL_THD_AT_EOI 0xFFFDFFFF
7359 #define S_028A40_SUPPRESS_CUTS(x) (((x) & 0x1) << 18)
7360 #define G_028A40_SUPPRESS_CUTS(x) (((x) >> 18) & 0x1)
7361 #define C_028A40_SUPPRESS_CUTS 0xFFFBFFFF
7362 #define S_028A40_ES_WRITE_OPTIMIZE(x) (((x) & 0x1) << 19)
7363 #define G_028A40_ES_WRITE_OPTIMIZE(x) (((x) >> 19) & 0x1)
7364 #define C_028A40_ES_WRITE_OPTIMIZE 0xFFF7FFFF
7365 #define S_028A40_GS_WRITE_OPTIMIZE(x) (((x) & 0x1) << 20)
7366 #define G_028A40_GS_WRITE_OPTIMIZE(x) (((x) >> 20) & 0x1)
7367 #define C_028A40_GS_WRITE_OPTIMIZE 0xFFEFFFFF
7368 /* CIK */
7369 #define S_028A40_ONCHIP(x) (((x) & 0x03) << 21)
7370 #define G_028A40_ONCHIP(x) (((x) >> 21) & 0x03)
7371 #define C_028A40_ONCHIP 0xFF9FFFFF
7372 #define V_028A40_X_0_OFFCHIP_GS 0x00
7373 #define V_028A40_X_3_ES_AND_GS_ARE_ONCHIP 0x03
7374 #define R_028A44_VGT_GS_ONCHIP_CNTL 0x028A44
7375 #define S_028A44_ES_VERTS_PER_SUBGRP(x) (((x) & 0x7FF) << 0)
7376 #define G_028A44_ES_VERTS_PER_SUBGRP(x) (((x) >> 0) & 0x7FF)
7377 #define C_028A44_ES_VERTS_PER_SUBGRP 0xFFFFF800
7378 #define S_028A44_GS_PRIMS_PER_SUBGRP(x) (((x) & 0x7FF) << 11)
7379 #define G_028A44_GS_PRIMS_PER_SUBGRP(x) (((x) >> 11) & 0x7FF)
7380 #define C_028A44_GS_PRIMS_PER_SUBGRP 0xFFC007FF
7381 /* */
7382 #define R_028A48_PA_SC_MODE_CNTL_0 0x028A48
7383 #define S_028A48_MSAA_ENABLE(x) (((x) & 0x1) << 0)
7384 #define G_028A48_MSAA_ENABLE(x) (((x) >> 0) & 0x1)
7385 #define C_028A48_MSAA_ENABLE 0xFFFFFFFE
7386 #define S_028A48_VPORT_SCISSOR_ENABLE(x) (((x) & 0x1) << 1)
7387 #define G_028A48_VPORT_SCISSOR_ENABLE(x) (((x) >> 1) & 0x1)
7388 #define C_028A48_VPORT_SCISSOR_ENABLE 0xFFFFFFFD
7389 #define S_028A48_LINE_STIPPLE_ENABLE(x) (((x) & 0x1) << 2)
7390 #define G_028A48_LINE_STIPPLE_ENABLE(x) (((x) >> 2) & 0x1)
7391 #define C_028A48_LINE_STIPPLE_ENABLE 0xFFFFFFFB
7392 #define S_028A48_SEND_UNLIT_STILES_TO_PKR(x) (((x) & 0x1) << 3)
7393 #define G_028A48_SEND_UNLIT_STILES_TO_PKR(x) (((x) >> 3) & 0x1)
7394 #define C_028A48_SEND_UNLIT_STILES_TO_PKR 0xFFFFFFF7
7395 #define R_028A4C_PA_SC_MODE_CNTL_1 0x028A4C
7396 #define S_028A4C_WALK_SIZE(x) (((x) & 0x1) << 0)
7397 #define G_028A4C_WALK_SIZE(x) (((x) >> 0) & 0x1)
7398 #define C_028A4C_WALK_SIZE 0xFFFFFFFE
7399 #define S_028A4C_WALK_ALIGNMENT(x) (((x) & 0x1) << 1)
7400 #define G_028A4C_WALK_ALIGNMENT(x) (((x) >> 1) & 0x1)
7401 #define C_028A4C_WALK_ALIGNMENT 0xFFFFFFFD
7402 #define S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) & 0x1) << 2)
7403 #define G_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) >> 2) & 0x1)
7404 #define C_028A4C_WALK_ALIGN8_PRIM_FITS_ST 0xFFFFFFFB
7405 #define S_028A4C_WALK_FENCE_ENABLE(x) (((x) & 0x1) << 3)
7406 #define G_028A4C_WALK_FENCE_ENABLE(x) (((x) >> 3) & 0x1)
7407 #define C_028A4C_WALK_FENCE_ENABLE 0xFFFFFFF7
7408 #define S_028A4C_WALK_FENCE_SIZE(x) (((x) & 0x07) << 4)
7409 #define G_028A4C_WALK_FENCE_SIZE(x) (((x) >> 4) & 0x07)
7410 #define C_028A4C_WALK_FENCE_SIZE 0xFFFFFF8F
7411 #define S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(x) (((x) & 0x1) << 7)
7412 #define G_028A4C_SUPERTILE_WALK_ORDER_ENABLE(x) (((x) >> 7) & 0x1)
7413 #define C_028A4C_SUPERTILE_WALK_ORDER_ENABLE 0xFFFFFF7F
7414 #define S_028A4C_TILE_WALK_ORDER_ENABLE(x) (((x) & 0x1) << 8)
7415 #define G_028A4C_TILE_WALK_ORDER_ENABLE(x) (((x) >> 8) & 0x1)
7416 #define C_028A4C_TILE_WALK_ORDER_ENABLE 0xFFFFFEFF
7417 #define S_028A4C_TILE_COVER_DISABLE(x) (((x) & 0x1) << 9)
7418 #define G_028A4C_TILE_COVER_DISABLE(x) (((x) >> 9) & 0x1)
7419 #define C_028A4C_TILE_COVER_DISABLE 0xFFFFFDFF
7420 #define S_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) & 0x1) << 10)
7421 #define G_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) >> 10) & 0x1)
7422 #define C_028A4C_TILE_COVER_NO_SCISSOR 0xFFFFFBFF
7423 #define S_028A4C_ZMM_LINE_EXTENT(x) (((x) & 0x1) << 11)
7424 #define G_028A4C_ZMM_LINE_EXTENT(x) (((x) >> 11) & 0x1)
7425 #define C_028A4C_ZMM_LINE_EXTENT 0xFFFFF7FF
7426 #define S_028A4C_ZMM_LINE_OFFSET(x) (((x) & 0x1) << 12)
7427 #define G_028A4C_ZMM_LINE_OFFSET(x) (((x) >> 12) & 0x1)
7428 #define C_028A4C_ZMM_LINE_OFFSET 0xFFFFEFFF
7429 #define S_028A4C_ZMM_RECT_EXTENT(x) (((x) & 0x1) << 13)
7430 #define G_028A4C_ZMM_RECT_EXTENT(x) (((x) >> 13) & 0x1)
7431 #define C_028A4C_ZMM_RECT_EXTENT 0xFFFFDFFF
7432 #define S_028A4C_KILL_PIX_POST_HI_Z(x) (((x) & 0x1) << 14)
7433 #define G_028A4C_KILL_PIX_POST_HI_Z(x) (((x) >> 14) & 0x1)
7434 #define C_028A4C_KILL_PIX_POST_HI_Z 0xFFFFBFFF
7435 #define S_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) & 0x1) << 15)
7436 #define G_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) >> 15) & 0x1)
7437 #define C_028A4C_KILL_PIX_POST_DETAIL_MASK 0xFFFF7FFF
7438 #define S_028A4C_PS_ITER_SAMPLE(x) (((x) & 0x1) << 16)
7439 #define G_028A4C_PS_ITER_SAMPLE(x) (((x) >> 16) & 0x1)
7440 #define C_028A4C_PS_ITER_SAMPLE 0xFFFEFFFF
7441 #define S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC(x) (((x) & 0x1) << 17)
7442 #define G_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC(x) (((x) >> 17) & 0x1)
7443 #define C_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC 0xFFFDFFFF
7444 #define S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) & 0x1) << 25)
7445 #define G_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) >> 25) & 0x1)
7446 #define C_028A4C_FORCE_EOV_CNTDWN_ENABLE 0xFDFFFFFF
7447 #define S_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) & 0x1) << 26)
7448 #define G_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) >> 26) & 0x1)
7449 #define C_028A4C_FORCE_EOV_REZ_ENABLE 0xFBFFFFFF
7450 #define S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(x) (((x) & 0x1) << 27)
7451 #define G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(x) (((x) >> 27) & 0x1)
7452 #define C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE 0xF7FFFFFF
7453 #define S_028A4C_OUT_OF_ORDER_WATER_MARK(x) (((x) & 0x07) << 28)
7454 #define G_028A4C_OUT_OF_ORDER_WATER_MARK(x) (((x) >> 28) & 0x07)
7455 #define C_028A4C_OUT_OF_ORDER_WATER_MARK 0x8FFFFFFF
7456 #define R_028A50_VGT_ENHANCE 0x028A50
7457 #define R_028A54_VGT_GS_PER_ES 0x028A54
7458 #define S_028A54_GS_PER_ES(x) (((x) & 0x7FF) << 0)
7459 #define G_028A54_GS_PER_ES(x) (((x) >> 0) & 0x7FF)
7460 #define C_028A54_GS_PER_ES 0xFFFFF800
7461 #define R_028A58_VGT_ES_PER_GS 0x028A58
7462 #define S_028A58_ES_PER_GS(x) (((x) & 0x7FF) << 0)
7463 #define G_028A58_ES_PER_GS(x) (((x) >> 0) & 0x7FF)
7464 #define C_028A58_ES_PER_GS 0xFFFFF800
7465 #define R_028A5C_VGT_GS_PER_VS 0x028A5C
7466 #define S_028A5C_GS_PER_VS(x) (((x) & 0x0F) << 0)
7467 #define G_028A5C_GS_PER_VS(x) (((x) >> 0) & 0x0F)
7468 #define C_028A5C_GS_PER_VS 0xFFFFFFF0
7469 #define R_028A60_VGT_GSVS_RING_OFFSET_1 0x028A60
7470 #define S_028A60_OFFSET(x) (((x) & 0x7FFF) << 0)
7471 #define G_028A60_OFFSET(x) (((x) >> 0) & 0x7FFF)
7472 #define C_028A60_OFFSET 0xFFFF8000
7473 #define R_028A64_VGT_GSVS_RING_OFFSET_2 0x028A64
7474 #define S_028A64_OFFSET(x) (((x) & 0x7FFF) << 0)
7475 #define G_028A64_OFFSET(x) (((x) >> 0) & 0x7FFF)
7476 #define C_028A64_OFFSET 0xFFFF8000
7477 #define R_028A68_VGT_GSVS_RING_OFFSET_3 0x028A68
7478 #define S_028A68_OFFSET(x) (((x) & 0x7FFF) << 0)
7479 #define G_028A68_OFFSET(x) (((x) >> 0) & 0x7FFF)
7480 #define C_028A68_OFFSET 0xFFFF8000
7481 #define R_028A6C_VGT_GS_OUT_PRIM_TYPE 0x028A6C
7482 #define S_028A6C_OUTPRIM_TYPE(x) (((x) & 0x3F) << 0)
7483 #define G_028A6C_OUTPRIM_TYPE(x) (((x) >> 0) & 0x3F)
7484 #define C_028A6C_OUTPRIM_TYPE 0xFFFFFFC0
7485 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
7486 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
7487 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
7488 #define S_028A6C_OUTPRIM_TYPE_1(x) (((x) & 0x3F) << 8)
7489 #define G_028A6C_OUTPRIM_TYPE_1(x) (((x) >> 8) & 0x3F)
7490 #define C_028A6C_OUTPRIM_TYPE_1 0xFFFFC0FF
7491 #define S_028A6C_OUTPRIM_TYPE_2(x) (((x) & 0x3F) << 16)
7492 #define G_028A6C_OUTPRIM_TYPE_2(x) (((x) >> 16) & 0x3F)
7493 #define C_028A6C_OUTPRIM_TYPE_2 0xFFC0FFFF
7494 #define S_028A6C_OUTPRIM_TYPE_3(x) (((x) & 0x3F) << 22)
7495 #define G_028A6C_OUTPRIM_TYPE_3(x) (((x) >> 22) & 0x3F)
7496 #define C_028A6C_OUTPRIM_TYPE_3 0xF03FFFFF
7497 #define S_028A6C_UNIQUE_TYPE_PER_STREAM(x) (((x) & 0x1) << 31)
7498 #define G_028A6C_UNIQUE_TYPE_PER_STREAM(x) (((x) >> 31) & 0x1)
7499 #define C_028A6C_UNIQUE_TYPE_PER_STREAM 0x7FFFFFFF
7500 #define R_028A70_IA_ENHANCE 0x028A70
7501 #define R_028A74_VGT_DMA_SIZE 0x028A74
7502 #define R_028A78_VGT_DMA_MAX_SIZE 0x028A78
7503 #define R_028A7C_VGT_DMA_INDEX_TYPE 0x028A7C
7504 #define S_028A7C_INDEX_TYPE(x) (((x) & 0x03) << 0)
7505 #define G_028A7C_INDEX_TYPE(x) (((x) >> 0) & 0x03)
7506 #define C_028A7C_INDEX_TYPE 0xFFFFFFFC
7507 #define V_028A7C_VGT_INDEX_16 0x00
7508 #define V_028A7C_VGT_INDEX_32 0x01
7509 #define S_028A7C_SWAP_MODE(x) (((x) & 0x03) << 2)
7510 #define G_028A7C_SWAP_MODE(x) (((x) >> 2) & 0x03)
7511 #define C_028A7C_SWAP_MODE 0xFFFFFFF3
7512 #define V_028A7C_VGT_DMA_SWAP_NONE 0x00
7513 #define V_028A7C_VGT_DMA_SWAP_16_BIT 0x01
7514 #define V_028A7C_VGT_DMA_SWAP_32_BIT 0x02
7515 #define V_028A7C_VGT_DMA_SWAP_WORD 0x03
7516 /* CIK */
7517 #define S_028A7C_BUF_TYPE(x) (((x) & 0x03) << 4)
7518 #define G_028A7C_BUF_TYPE(x) (((x) >> 4) & 0x03)
7519 #define C_028A7C_BUF_TYPE 0xFFFFFFCF
7520 #define V_028A7C_VGT_DMA_BUF_MEM 0x00
7521 #define V_028A7C_VGT_DMA_BUF_RING 0x01
7522 #define V_028A7C_VGT_DMA_BUF_SETUP 0x02
7523 #define S_028A7C_RDREQ_POLICY(x) (((x) & 0x03) << 6)
7524 #define G_028A7C_RDREQ_POLICY(x) (((x) >> 6) & 0x03)
7525 #define C_028A7C_RDREQ_POLICY 0xFFFFFF3F
7526 #define V_028A7C_VGT_POLICY_LRU 0x00
7527 #define V_028A7C_VGT_POLICY_STREAM 0x01
7528 #define S_028A7C_ATC(x) (((x) & 0x1) << 8)
7529 #define G_028A7C_ATC(x) (((x) >> 8) & 0x1)
7530 #define C_028A7C_ATC 0xFFFFFEFF
7531 #define S_028A7C_NOT_EOP(x) (((x) & 0x1) << 9)
7532 #define G_028A7C_NOT_EOP(x) (((x) >> 9) & 0x1)
7533 #define C_028A7C_NOT_EOP 0xFFFFFDFF
7534 #define S_028A7C_REQ_PATH(x) (((x) & 0x1) << 10)
7535 #define G_028A7C_REQ_PATH(x) (((x) >> 10) & 0x1)
7536 #define C_028A7C_REQ_PATH 0xFFFFFBFF
7537 /* */
7538 #define R_028A84_VGT_PRIMITIVEID_EN 0x028A84
7539 #define S_028A84_PRIMITIVEID_EN(x) (((x) & 0x1) << 0)
7540 #define G_028A84_PRIMITIVEID_EN(x) (((x) >> 0) & 0x1)
7541 #define C_028A84_PRIMITIVEID_EN 0xFFFFFFFE
7542 #define S_028A84_DISABLE_RESET_ON_EOI(x) (((x) & 0x1) << 1) /* not on CIK */
7543 #define G_028A84_DISABLE_RESET_ON_EOI(x) (((x) >> 1) & 0x1) /* not on CIK */
7544 #define C_028A84_DISABLE_RESET_ON_EOI 0xFFFFFFFD /* not on CIK */
7545 #define R_028A88_VGT_DMA_NUM_INSTANCES 0x028A88
7546 #define R_028A8C_VGT_PRIMITIVEID_RESET 0x028A8C
7547 #define R_028A90_VGT_EVENT_INITIATOR 0x028A90
7548 #define S_028A90_EVENT_TYPE(x) (((x) & 0x3F) << 0)
7549 #define G_028A90_EVENT_TYPE(x) (((x) >> 0) & 0x3F)
7550 #define C_028A90_EVENT_TYPE 0xFFFFFFC0
7551 #define V_028A90_SAMPLE_STREAMOUTSTATS1 0x01
7552 #define V_028A90_SAMPLE_STREAMOUTSTATS2 0x02
7553 #define V_028A90_SAMPLE_STREAMOUTSTATS3 0x03
7554 #define V_028A90_CACHE_FLUSH_TS 0x04
7555 #define V_028A90_CONTEXT_DONE 0x05
7556 #define V_028A90_CACHE_FLUSH 0x06
7557 #define V_028A90_CS_PARTIAL_FLUSH 0x07
7558 #define V_028A90_VGT_STREAMOUT_SYNC 0x08
7559 #define V_028A90_VGT_STREAMOUT_RESET 0x0A
7560 #define V_028A90_END_OF_PIPE_INCR_DE 0x0B
7561 #define V_028A90_END_OF_PIPE_IB_END 0x0C
7562 #define V_028A90_RST_PIX_CNT 0x0D
7563 #define V_028A90_VS_PARTIAL_FLUSH 0x0F
7564 #define V_028A90_PS_PARTIAL_FLUSH 0x10
7565 #define V_028A90_FLUSH_HS_OUTPUT 0x11
7566 #define V_028A90_FLUSH_LS_OUTPUT 0x12
7567 #define V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT 0x14
7568 #define V_028A90_ZPASS_DONE 0x15 /* not on CIK */
7569 #define V_028A90_CACHE_FLUSH_AND_INV_EVENT 0x16
7570 #define V_028A90_PERFCOUNTER_START 0x17
7571 #define V_028A90_PERFCOUNTER_STOP 0x18
7572 #define V_028A90_PIPELINESTAT_START 0x19
7573 #define V_028A90_PIPELINESTAT_STOP 0x1A
7574 #define V_028A90_PERFCOUNTER_SAMPLE 0x1B
7575 #define V_028A90_FLUSH_ES_OUTPUT 0x1C
7576 #define V_028A90_FLUSH_GS_OUTPUT 0x1D
7577 #define V_028A90_SAMPLE_PIPELINESTAT 0x1E
7578 #define V_028A90_SO_VGTSTREAMOUT_FLUSH 0x1F
7579 #define V_028A90_SAMPLE_STREAMOUTSTATS 0x20
7580 #define V_028A90_RESET_VTX_CNT 0x21
7581 #define V_028A90_BLOCK_CONTEXT_DONE 0x22
7582 #define V_028A90_CS_CONTEXT_DONE 0x23
7583 #define V_028A90_VGT_FLUSH 0x24
7584 #define V_028A90_SC_SEND_DB_VPZ 0x27
7585 #define V_028A90_BOTTOM_OF_PIPE_TS 0x28
7586 #define V_028A90_DB_CACHE_FLUSH_AND_INV 0x2A
7587 #define V_028A90_FLUSH_AND_INV_DB_DATA_TS 0x2B
7588 #define V_028A90_FLUSH_AND_INV_DB_META 0x2C
7589 #define V_028A90_FLUSH_AND_INV_CB_DATA_TS 0x2D
7590 #define V_028A90_FLUSH_AND_INV_CB_META 0x2E
7591 #define V_028A90_CS_DONE 0x2F
7592 #define V_028A90_PS_DONE 0x30
7593 #define V_028A90_FLUSH_AND_INV_CB_PIXEL_DATA 0x31
7594 #define V_028A90_THREAD_TRACE_START 0x33
7595 #define V_028A90_THREAD_TRACE_STOP 0x34
7596 #define V_028A90_THREAD_TRACE_MARKER 0x35
7597 #define V_028A90_THREAD_TRACE_FLUSH 0x36
7598 #define V_028A90_THREAD_TRACE_FINISH 0x37
7599 /* CIK */
7600 #define V_028A90_PIXEL_PIPE_STAT_CONTROL 0x38
7601 #define V_028A90_PIXEL_PIPE_STAT_DUMP 0x39
7602 #define V_028A90_PIXEL_PIPE_STAT_RESET 0x40
7603 /* */
7604 #define S_028A90_ADDRESS_HI(x) (((x) & 0x1FF) << 18)
7605 #define G_028A90_ADDRESS_HI(x) (((x) >> 18) & 0x1FF)
7606 #define C_028A90_ADDRESS_HI 0xF803FFFF
7607 #define S_028A90_EXTENDED_EVENT(x) (((x) & 0x1) << 27)
7608 #define G_028A90_EXTENDED_EVENT(x) (((x) >> 27) & 0x1)
7609 #define C_028A90_EXTENDED_EVENT 0xF7FFFFFF
7610 #define R_028A94_VGT_MULTI_PRIM_IB_RESET_EN 0x028A94
7611 #define S_028A94_RESET_EN(x) (((x) & 0x1) << 0)
7612 #define G_028A94_RESET_EN(x) (((x) >> 0) & 0x1)
7613 #define C_028A94_RESET_EN 0xFFFFFFFE
7614 #define R_028AA0_VGT_INSTANCE_STEP_RATE_0 0x028AA0
7615 #define R_028AA4_VGT_INSTANCE_STEP_RATE_1 0x028AA4
7616 #define R_028AA8_IA_MULTI_VGT_PARAM 0x028AA8
7617 #define S_028AA8_PRIMGROUP_SIZE(x) (((x) & 0xFFFF) << 0)
7618 #define G_028AA8_PRIMGROUP_SIZE(x) (((x) >> 0) & 0xFFFF)
7619 #define C_028AA8_PRIMGROUP_SIZE 0xFFFF0000
7620 #define S_028AA8_PARTIAL_VS_WAVE_ON(x) (((x) & 0x1) << 16)
7621 #define G_028AA8_PARTIAL_VS_WAVE_ON(x) (((x) >> 16) & 0x1)
7622 #define C_028AA8_PARTIAL_VS_WAVE_ON 0xFFFEFFFF
7623 #define S_028AA8_SWITCH_ON_EOP(x) (((x) & 0x1) << 17)
7624 #define G_028AA8_SWITCH_ON_EOP(x) (((x) >> 17) & 0x1)
7625 #define C_028AA8_SWITCH_ON_EOP 0xFFFDFFFF
7626 #define S_028AA8_PARTIAL_ES_WAVE_ON(x) (((x) & 0x1) << 18)
7627 #define G_028AA8_PARTIAL_ES_WAVE_ON(x) (((x) >> 18) & 0x1)
7628 #define C_028AA8_PARTIAL_ES_WAVE_ON 0xFFFBFFFF
7629 #define S_028AA8_SWITCH_ON_EOI(x) (((x) & 0x1) << 19)
7630 #define G_028AA8_SWITCH_ON_EOI(x) (((x) >> 19) & 0x1)
7631 #define C_028AA8_SWITCH_ON_EOI 0xFFF7FFFF
7632 /* CIK */
7633 #define S_028AA8_WD_SWITCH_ON_EOP(x) (((x) & 0x1) << 20)
7634 #define G_028AA8_WD_SWITCH_ON_EOP(x) (((x) >> 20) & 0x1)
7635 #define C_028AA8_WD_SWITCH_ON_EOP 0xFFEFFFFF
7636 /* */
7637 #define R_028AAC_VGT_ESGS_RING_ITEMSIZE 0x028AAC
7638 #define S_028AAC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
7639 #define G_028AAC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
7640 #define C_028AAC_ITEMSIZE 0xFFFF8000
7641 #define R_028AB0_VGT_GSVS_RING_ITEMSIZE 0x028AB0
7642 #define S_028AB0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
7643 #define G_028AB0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
7644 #define C_028AB0_ITEMSIZE 0xFFFF8000
7645 #define R_028AB4_VGT_REUSE_OFF 0x028AB4
7646 #define S_028AB4_REUSE_OFF(x) (((x) & 0x1) << 0)
7647 #define G_028AB4_REUSE_OFF(x) (((x) >> 0) & 0x1)
7648 #define C_028AB4_REUSE_OFF 0xFFFFFFFE
7649 #define R_028AB8_VGT_VTX_CNT_EN 0x028AB8
7650 #define S_028AB8_VTX_CNT_EN(x) (((x) & 0x1) << 0)
7651 #define G_028AB8_VTX_CNT_EN(x) (((x) >> 0) & 0x1)
7652 #define C_028AB8_VTX_CNT_EN 0xFFFFFFFE
7653 #define R_028ABC_DB_HTILE_SURFACE 0x028ABC
7654 #define S_028ABC_LINEAR(x) (((x) & 0x1) << 0)
7655 #define G_028ABC_LINEAR(x) (((x) >> 0) & 0x1)
7656 #define C_028ABC_LINEAR 0xFFFFFFFE
7657 #define S_028ABC_FULL_CACHE(x) (((x) & 0x1) << 1)
7658 #define G_028ABC_FULL_CACHE(x) (((x) >> 1) & 0x1)
7659 #define C_028ABC_FULL_CACHE 0xFFFFFFFD
7660 #define S_028ABC_HTILE_USES_PRELOAD_WIN(x) (((x) & 0x1) << 2)
7661 #define G_028ABC_HTILE_USES_PRELOAD_WIN(x) (((x) >> 2) & 0x1)
7662 #define C_028ABC_HTILE_USES_PRELOAD_WIN 0xFFFFFFFB
7663 #define S_028ABC_PRELOAD(x) (((x) & 0x1) << 3)
7664 #define G_028ABC_PRELOAD(x) (((x) >> 3) & 0x1)
7665 #define C_028ABC_PRELOAD 0xFFFFFFF7
7666 #define S_028ABC_PREFETCH_WIDTH(x) (((x) & 0x3F) << 4)
7667 #define G_028ABC_PREFETCH_WIDTH(x) (((x) >> 4) & 0x3F)
7668 #define C_028ABC_PREFETCH_WIDTH 0xFFFFFC0F
7669 #define S_028ABC_PREFETCH_HEIGHT(x) (((x) & 0x3F) << 10)
7670 #define G_028ABC_PREFETCH_HEIGHT(x) (((x) >> 10) & 0x3F)
7671 #define C_028ABC_PREFETCH_HEIGHT 0xFFFF03FF
7672 #define S_028ABC_DST_OUTSIDE_ZERO_TO_ONE(x) (((x) & 0x1) << 16)
7673 #define G_028ABC_DST_OUTSIDE_ZERO_TO_ONE(x) (((x) >> 16) & 0x1)
7674 #define C_028ABC_DST_OUTSIDE_ZERO_TO_ONE 0xFFFEFFFF
7675 #define R_028AC0_DB_SRESULTS_COMPARE_STATE0 0x028AC0
7676 #define S_028AC0_COMPAREFUNC0(x) (((x) & 0x07) << 0)
7677 #define G_028AC0_COMPAREFUNC0(x) (((x) >> 0) & 0x07)
7678 #define C_028AC0_COMPAREFUNC0 0xFFFFFFF8
7679 #define V_028AC0_REF_NEVER 0x00
7680 #define V_028AC0_REF_LESS 0x01
7681 #define V_028AC0_REF_EQUAL 0x02
7682 #define V_028AC0_REF_LEQUAL 0x03
7683 #define V_028AC0_REF_GREATER 0x04
7684 #define V_028AC0_REF_NOTEQUAL 0x05
7685 #define V_028AC0_REF_GEQUAL 0x06
7686 #define V_028AC0_REF_ALWAYS 0x07
7687 #define S_028AC0_COMPAREVALUE0(x) (((x) & 0xFF) << 4)
7688 #define G_028AC0_COMPAREVALUE0(x) (((x) >> 4) & 0xFF)
7689 #define C_028AC0_COMPAREVALUE0 0xFFFFF00F
7690 #define S_028AC0_COMPAREMASK0(x) (((x) & 0xFF) << 12)
7691 #define G_028AC0_COMPAREMASK0(x) (((x) >> 12) & 0xFF)
7692 #define C_028AC0_COMPAREMASK0 0xFFF00FFF
7693 #define S_028AC0_ENABLE0(x) (((x) & 0x1) << 24)
7694 #define G_028AC0_ENABLE0(x) (((x) >> 24) & 0x1)
7695 #define C_028AC0_ENABLE0 0xFEFFFFFF
7696 #define R_028AC4_DB_SRESULTS_COMPARE_STATE1 0x028AC4
7697 #define S_028AC4_COMPAREFUNC1(x) (((x) & 0x07) << 0)
7698 #define G_028AC4_COMPAREFUNC1(x) (((x) >> 0) & 0x07)
7699 #define C_028AC4_COMPAREFUNC1 0xFFFFFFF8
7700 #define V_028AC4_REF_NEVER 0x00
7701 #define V_028AC4_REF_LESS 0x01
7702 #define V_028AC4_REF_EQUAL 0x02
7703 #define V_028AC4_REF_LEQUAL 0x03
7704 #define V_028AC4_REF_GREATER 0x04
7705 #define V_028AC4_REF_NOTEQUAL 0x05
7706 #define V_028AC4_REF_GEQUAL 0x06
7707 #define V_028AC4_REF_ALWAYS 0x07
7708 #define S_028AC4_COMPAREVALUE1(x) (((x) & 0xFF) << 4)
7709 #define G_028AC4_COMPAREVALUE1(x) (((x) >> 4) & 0xFF)
7710 #define C_028AC4_COMPAREVALUE1 0xFFFFF00F
7711 #define S_028AC4_COMPAREMASK1(x) (((x) & 0xFF) << 12)
7712 #define G_028AC4_COMPAREMASK1(x) (((x) >> 12) & 0xFF)
7713 #define C_028AC4_COMPAREMASK1 0xFFF00FFF
7714 #define S_028AC4_ENABLE1(x) (((x) & 0x1) << 24)
7715 #define G_028AC4_ENABLE1(x) (((x) >> 24) & 0x1)
7716 #define C_028AC4_ENABLE1 0xFEFFFFFF
7717 #define R_028AC8_DB_PRELOAD_CONTROL 0x028AC8
7718 #define S_028AC8_START_X(x) (((x) & 0xFF) << 0)
7719 #define G_028AC8_START_X(x) (((x) >> 0) & 0xFF)
7720 #define C_028AC8_START_X 0xFFFFFF00
7721 #define S_028AC8_START_Y(x) (((x) & 0xFF) << 8)
7722 #define G_028AC8_START_Y(x) (((x) >> 8) & 0xFF)
7723 #define C_028AC8_START_Y 0xFFFF00FF
7724 #define S_028AC8_MAX_X(x) (((x) & 0xFF) << 16)
7725 #define G_028AC8_MAX_X(x) (((x) >> 16) & 0xFF)
7726 #define C_028AC8_MAX_X 0xFF00FFFF
7727 #define S_028AC8_MAX_Y(x) (((x) & 0xFF) << 24)
7728 #define G_028AC8_MAX_Y(x) (((x) >> 24) & 0xFF)
7729 #define C_028AC8_MAX_Y 0x00FFFFFF
7730 #define R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 0x028AD0
7731 #define R_028AD4_VGT_STRMOUT_VTX_STRIDE_0 0x028AD4
7732 #define S_028AD4_STRIDE(x) (((x) & 0x3FF) << 0)
7733 #define G_028AD4_STRIDE(x) (((x) >> 0) & 0x3FF)
7734 #define C_028AD4_STRIDE 0xFFFFFC00
7735 #define R_028ADC_VGT_STRMOUT_BUFFER_OFFSET_0 0x028ADC
7736 #define R_028AE0_VGT_STRMOUT_BUFFER_SIZE_1 0x028AE0
7737 #define R_028AE4_VGT_STRMOUT_VTX_STRIDE_1 0x028AE4
7738 #define S_028AE4_STRIDE(x) (((x) & 0x3FF) << 0)
7739 #define G_028AE4_STRIDE(x) (((x) >> 0) & 0x3FF)
7740 #define C_028AE4_STRIDE 0xFFFFFC00
7741 #define R_028AEC_VGT_STRMOUT_BUFFER_OFFSET_1 0x028AEC
7742 #define R_028AF0_VGT_STRMOUT_BUFFER_SIZE_2 0x028AF0
7743 #define R_028AF4_VGT_STRMOUT_VTX_STRIDE_2 0x028AF4
7744 #define S_028AF4_STRIDE(x) (((x) & 0x3FF) << 0)
7745 #define G_028AF4_STRIDE(x) (((x) >> 0) & 0x3FF)
7746 #define C_028AF4_STRIDE 0xFFFFFC00
7747 #define R_028AFC_VGT_STRMOUT_BUFFER_OFFSET_2 0x028AFC
7748 #define R_028B00_VGT_STRMOUT_BUFFER_SIZE_3 0x028B00
7749 #define R_028B04_VGT_STRMOUT_VTX_STRIDE_3 0x028B04
7750 #define S_028B04_STRIDE(x) (((x) & 0x3FF) << 0)
7751 #define G_028B04_STRIDE(x) (((x) >> 0) & 0x3FF)
7752 #define C_028B04_STRIDE 0xFFFFFC00
7753 #define R_028B0C_VGT_STRMOUT_BUFFER_OFFSET_3 0x028B0C
7754 #define R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x028B28
7755 #define R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x028B2C
7756 #define R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x028B30
7757 #define S_028B30_VERTEX_STRIDE(x) (((x) & 0x1FF) << 0)
7758 #define G_028B30_VERTEX_STRIDE(x) (((x) >> 0) & 0x1FF)
7759 #define C_028B30_VERTEX_STRIDE 0xFFFFFE00
7760 #define R_028B38_VGT_GS_MAX_VERT_OUT 0x028B38
7761 #define S_028B38_MAX_VERT_OUT(x) (((x) & 0x7FF) << 0)
7762 #define G_028B38_MAX_VERT_OUT(x) (((x) >> 0) & 0x7FF)
7763 #define C_028B38_MAX_VERT_OUT 0xFFFFF800
7764 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
7765 #define S_028B54_LS_EN(x) (((x) & 0x03) << 0)
7766 #define G_028B54_LS_EN(x) (((x) >> 0) & 0x03)
7767 #define C_028B54_LS_EN 0xFFFFFFFC
7768 #define V_028B54_LS_STAGE_OFF 0x00
7769 #define V_028B54_LS_STAGE_ON 0x01
7770 #define V_028B54_CS_STAGE_ON 0x02
7771 #define S_028B54_HS_EN(x) (((x) & 0x1) << 2)
7772 #define G_028B54_HS_EN(x) (((x) >> 2) & 0x1)
7773 #define C_028B54_HS_EN 0xFFFFFFFB
7774 #define S_028B54_ES_EN(x) (((x) & 0x03) << 3)
7775 #define G_028B54_ES_EN(x) (((x) >> 3) & 0x03)
7776 #define C_028B54_ES_EN 0xFFFFFFE7
7777 #define V_028B54_ES_STAGE_OFF 0x00
7778 #define V_028B54_ES_STAGE_DS 0x01
7779 #define V_028B54_ES_STAGE_REAL 0x02
7780 #define S_028B54_GS_EN(x) (((x) & 0x1) << 5)
7781 #define G_028B54_GS_EN(x) (((x) >> 5) & 0x1)
7782 #define C_028B54_GS_EN 0xFFFFFFDF
7783 #define S_028B54_VS_EN(x) (((x) & 0x03) << 6)
7784 #define G_028B54_VS_EN(x) (((x) >> 6) & 0x03)
7785 #define C_028B54_VS_EN 0xFFFFFF3F
7786 #define V_028B54_VS_STAGE_REAL 0x00
7787 #define V_028B54_VS_STAGE_DS 0x01
7788 #define V_028B54_VS_STAGE_COPY_SHADER 0x02
7789 #define S_028B54_DYNAMIC_HS(x) (((x) & 0x1) << 8)
7790 #define G_028B54_DYNAMIC_HS(x) (((x) >> 8) & 0x1)
7791 #define C_028B54_DYNAMIC_HS 0xFFFFFEFF
7792 #define R_028B58_VGT_LS_HS_CONFIG 0x028B58
7793 #define S_028B58_NUM_PATCHES(x) (((x) & 0xFF) << 0)
7794 #define G_028B58_NUM_PATCHES(x) (((x) >> 0) & 0xFF)
7795 #define C_028B58_NUM_PATCHES 0xFFFFFF00
7796 #define S_028B58_HS_NUM_INPUT_CP(x) (((x) & 0x3F) << 8)
7797 #define G_028B58_HS_NUM_INPUT_CP(x) (((x) >> 8) & 0x3F)
7798 #define C_028B58_HS_NUM_INPUT_CP 0xFFFFC0FF
7799 #define S_028B58_HS_NUM_OUTPUT_CP(x) (((x) & 0x3F) << 14)
7800 #define G_028B58_HS_NUM_OUTPUT_CP(x) (((x) >> 14) & 0x3F)
7801 #define C_028B58_HS_NUM_OUTPUT_CP 0xFFF03FFF
7802 #define R_028B5C_VGT_GS_VERT_ITEMSIZE 0x028B5C
7803 #define S_028B5C_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
7804 #define G_028B5C_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
7805 #define C_028B5C_ITEMSIZE 0xFFFF8000
7806 #define R_028B60_VGT_GS_VERT_ITEMSIZE_1 0x028B60
7807 #define S_028B60_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
7808 #define G_028B60_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
7809 #define C_028B60_ITEMSIZE 0xFFFF8000
7810 #define R_028B64_VGT_GS_VERT_ITEMSIZE_2 0x028B64
7811 #define S_028B64_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
7812 #define G_028B64_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
7813 #define C_028B64_ITEMSIZE 0xFFFF8000
7814 #define R_028B68_VGT_GS_VERT_ITEMSIZE_3 0x028B68
7815 #define S_028B68_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
7816 #define G_028B68_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
7817 #define C_028B68_ITEMSIZE 0xFFFF8000
7818 #define R_028B6C_VGT_TF_PARAM 0x028B6C
7819 #define S_028B6C_TYPE(x) (((x) & 0x03) << 0)
7820 #define G_028B6C_TYPE(x) (((x) >> 0) & 0x03)
7821 #define C_028B6C_TYPE 0xFFFFFFFC
7822 #define V_028B6C_TESS_ISOLINE 0x00
7823 #define V_028B6C_TESS_TRIANGLE 0x01
7824 #define V_028B6C_TESS_QUAD 0x02
7825 #define S_028B6C_PARTITIONING(x) (((x) & 0x07) << 2)
7826 #define G_028B6C_PARTITIONING(x) (((x) >> 2) & 0x07)
7827 #define C_028B6C_PARTITIONING 0xFFFFFFE3
7828 #define V_028B6C_PART_INTEGER 0x00
7829 #define V_028B6C_PART_POW2 0x01
7830 #define V_028B6C_PART_FRAC_ODD 0x02
7831 #define V_028B6C_PART_FRAC_EVEN 0x03
7832 #define S_028B6C_TOPOLOGY(x) (((x) & 0x07) << 5)
7833 #define G_028B6C_TOPOLOGY(x) (((x) >> 5) & 0x07)
7834 #define C_028B6C_TOPOLOGY 0xFFFFFF1F
7835 #define V_028B6C_OUTPUT_POINT 0x00
7836 #define V_028B6C_OUTPUT_LINE 0x01
7837 #define V_028B6C_OUTPUT_TRIANGLE_CW 0x02
7838 #define V_028B6C_OUTPUT_TRIANGLE_CCW 0x03
7839 #define S_028B6C_RESERVED_REDUC_AXIS(x) (((x) & 0x1) << 8) /* not on CIK */
7840 #define G_028B6C_RESERVED_REDUC_AXIS(x) (((x) >> 8) & 0x1) /* not on CIK */
7841 #define C_028B6C_RESERVED_REDUC_AXIS 0xFFFFFEFF /* not on CIK */
7842 #define S_028B6C_NUM_DS_WAVES_PER_SIMD(x) (((x) & 0x0F) << 10)
7843 #define G_028B6C_NUM_DS_WAVES_PER_SIMD(x) (((x) >> 10) & 0x0F)
7844 #define C_028B6C_NUM_DS_WAVES_PER_SIMD 0xFFFFC3FF
7845 #define S_028B6C_DISABLE_DONUTS(x) (((x) & 0x1) << 14)
7846 #define G_028B6C_DISABLE_DONUTS(x) (((x) >> 14) & 0x1)
7847 #define C_028B6C_DISABLE_DONUTS 0xFFFFBFFF
7848 /* CIK */
7849 #define S_028B6C_RDREQ_POLICY(x) (((x) & 0x03) << 15)
7850 #define G_028B6C_RDREQ_POLICY(x) (((x) >> 15) & 0x03)
7851 #define C_028B6C_RDREQ_POLICY 0xFFFE7FFF
7852 #define V_028B6C_VGT_POLICY_LRU 0x00
7853 #define V_028B6C_VGT_POLICY_STREAM 0x01
7854 #define V_028B6C_VGT_POLICY_BYPASS 0x02
7855 /* */
7856 #define R_028B70_DB_ALPHA_TO_MASK 0x028B70
7857 #define S_028B70_ALPHA_TO_MASK_ENABLE(x) (((x) & 0x1) << 0)
7858 #define G_028B70_ALPHA_TO_MASK_ENABLE(x) (((x) >> 0) & 0x1)
7859 #define C_028B70_ALPHA_TO_MASK_ENABLE 0xFFFFFFFE
7860 #define S_028B70_ALPHA_TO_MASK_OFFSET0(x) (((x) & 0x03) << 8)
7861 #define G_028B70_ALPHA_TO_MASK_OFFSET0(x) (((x) >> 8) & 0x03)
7862 #define C_028B70_ALPHA_TO_MASK_OFFSET0 0xFFFFFCFF
7863 #define S_028B70_ALPHA_TO_MASK_OFFSET1(x) (((x) & 0x03) << 10)
7864 #define G_028B70_ALPHA_TO_MASK_OFFSET1(x) (((x) >> 10) & 0x03)
7865 #define C_028B70_ALPHA_TO_MASK_OFFSET1 0xFFFFF3FF
7866 #define S_028B70_ALPHA_TO_MASK_OFFSET2(x) (((x) & 0x03) << 12)
7867 #define G_028B70_ALPHA_TO_MASK_OFFSET2(x) (((x) >> 12) & 0x03)
7868 #define C_028B70_ALPHA_TO_MASK_OFFSET2 0xFFFFCFFF
7869 #define S_028B70_ALPHA_TO_MASK_OFFSET3(x) (((x) & 0x03) << 14)
7870 #define G_028B70_ALPHA_TO_MASK_OFFSET3(x) (((x) >> 14) & 0x03)
7871 #define C_028B70_ALPHA_TO_MASK_OFFSET3 0xFFFF3FFF
7872 #define S_028B70_OFFSET_ROUND(x) (((x) & 0x1) << 16)
7873 #define G_028B70_OFFSET_ROUND(x) (((x) >> 16) & 0x1)
7874 #define C_028B70_OFFSET_ROUND 0xFFFEFFFF
7875 /* CIK */
7876 #define R_028B74_VGT_DISPATCH_DRAW_INDEX 0x028B74
7877 /* */
7878 #define R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL 0x028B78
7879 #define S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) & 0xFF) << 0)
7880 #define G_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) >> 0) & 0xFF)
7881 #define C_028B78_POLY_OFFSET_NEG_NUM_DB_BITS 0xFFFFFF00
7882 #define S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x) (((x) & 0x1) << 8)
7883 #define G_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x) (((x) >> 8) & 0x1)
7884 #define C_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT 0xFFFFFEFF
7885 #define R_028B7C_PA_SU_POLY_OFFSET_CLAMP 0x028B7C
7886 #define R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE 0x028B80
7887 #define R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x028B84
7888 #define R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE 0x028B88
7889 #define R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET 0x028B8C
7890 #define R_028B90_VGT_GS_INSTANCE_CNT 0x028B90
7891 #define S_028B90_ENABLE(x) (((x) & 0x1) << 0)
7892 #define G_028B90_ENABLE(x) (((x) >> 0) & 0x1)
7893 #define C_028B90_ENABLE 0xFFFFFFFE
7894 #define S_028B90_CNT(x) (((x) & 0x7F) << 2)
7895 #define G_028B90_CNT(x) (((x) >> 2) & 0x7F)
7896 #define C_028B90_CNT 0xFFFFFE03
7897 #define R_028B94_VGT_STRMOUT_CONFIG 0x028B94
7898 #define S_028B94_STREAMOUT_0_EN(x) (((x) & 0x1) << 0)
7899 #define G_028B94_STREAMOUT_0_EN(x) (((x) >> 0) & 0x1)
7900 #define C_028B94_STREAMOUT_0_EN 0xFFFFFFFE
7901 #define S_028B94_STREAMOUT_1_EN(x) (((x) & 0x1) << 1)
7902 #define G_028B94_STREAMOUT_1_EN(x) (((x) >> 1) & 0x1)
7903 #define C_028B94_STREAMOUT_1_EN 0xFFFFFFFD
7904 #define S_028B94_STREAMOUT_2_EN(x) (((x) & 0x1) << 2)
7905 #define G_028B94_STREAMOUT_2_EN(x) (((x) >> 2) & 0x1)
7906 #define C_028B94_STREAMOUT_2_EN 0xFFFFFFFB
7907 #define S_028B94_STREAMOUT_3_EN(x) (((x) & 0x1) << 3)
7908 #define G_028B94_STREAMOUT_3_EN(x) (((x) >> 3) & 0x1)
7909 #define C_028B94_STREAMOUT_3_EN 0xFFFFFFF7
7910 #define S_028B94_RAST_STREAM(x) (((x) & 0x07) << 4)
7911 #define G_028B94_RAST_STREAM(x) (((x) >> 4) & 0x07)
7912 #define C_028B94_RAST_STREAM 0xFFFFFF8F
7913 #define S_028B94_RAST_STREAM_MASK(x) (((x) & 0x0F) << 8)
7914 #define G_028B94_RAST_STREAM_MASK(x) (((x) >> 8) & 0x0F)
7915 #define C_028B94_RAST_STREAM_MASK 0xFFFFF0FF
7916 #define S_028B94_USE_RAST_STREAM_MASK(x) (((x) & 0x1) << 31)
7917 #define G_028B94_USE_RAST_STREAM_MASK(x) (((x) >> 31) & 0x1)
7918 #define C_028B94_USE_RAST_STREAM_MASK 0x7FFFFFFF
7919 #define R_028B98_VGT_STRMOUT_BUFFER_CONFIG 0x028B98
7920 #define S_028B98_STREAM_0_BUFFER_EN(x) (((x) & 0x0F) << 0)
7921 #define G_028B98_STREAM_0_BUFFER_EN(x) (((x) >> 0) & 0x0F)
7922 #define C_028B98_STREAM_0_BUFFER_EN 0xFFFFFFF0
7923 #define S_028B98_STREAM_1_BUFFER_EN(x) (((x) & 0x0F) << 4)
7924 #define G_028B98_STREAM_1_BUFFER_EN(x) (((x) >> 4) & 0x0F)
7925 #define C_028B98_STREAM_1_BUFFER_EN 0xFFFFFF0F
7926 #define S_028B98_STREAM_2_BUFFER_EN(x) (((x) & 0x0F) << 8)
7927 #define G_028B98_STREAM_2_BUFFER_EN(x) (((x) >> 8) & 0x0F)
7928 #define C_028B98_STREAM_2_BUFFER_EN 0xFFFFF0FF
7929 #define S_028B98_STREAM_3_BUFFER_EN(x) (((x) & 0x0F) << 12)
7930 #define G_028B98_STREAM_3_BUFFER_EN(x) (((x) >> 12) & 0x0F)
7931 #define C_028B98_STREAM_3_BUFFER_EN 0xFFFF0FFF
7932 #define R_028BD4_PA_SC_CENTROID_PRIORITY_0 0x028BD4
7933 #define S_028BD4_DISTANCE_0(x) (((x) & 0x0F) << 0)
7934 #define G_028BD4_DISTANCE_0(x) (((x) >> 0) & 0x0F)
7935 #define C_028BD4_DISTANCE_0 0xFFFFFFF0
7936 #define S_028BD4_DISTANCE_1(x) (((x) & 0x0F) << 4)
7937 #define G_028BD4_DISTANCE_1(x) (((x) >> 4) & 0x0F)
7938 #define C_028BD4_DISTANCE_1 0xFFFFFF0F
7939 #define S_028BD4_DISTANCE_2(x) (((x) & 0x0F) << 8)
7940 #define G_028BD4_DISTANCE_2(x) (((x) >> 8) & 0x0F)
7941 #define C_028BD4_DISTANCE_2 0xFFFFF0FF
7942 #define S_028BD4_DISTANCE_3(x) (((x) & 0x0F) << 12)
7943 #define G_028BD4_DISTANCE_3(x) (((x) >> 12) & 0x0F)
7944 #define C_028BD4_DISTANCE_3 0xFFFF0FFF
7945 #define S_028BD4_DISTANCE_4(x) (((x) & 0x0F) << 16)
7946 #define G_028BD4_DISTANCE_4(x) (((x) >> 16) & 0x0F)
7947 #define C_028BD4_DISTANCE_4 0xFFF0FFFF
7948 #define S_028BD4_DISTANCE_5(x) (((x) & 0x0F) << 20)
7949 #define G_028BD4_DISTANCE_5(x) (((x) >> 20) & 0x0F)
7950 #define C_028BD4_DISTANCE_5 0xFF0FFFFF
7951 #define S_028BD4_DISTANCE_6(x) (((x) & 0x0F) << 24)
7952 #define G_028BD4_DISTANCE_6(x) (((x) >> 24) & 0x0F)
7953 #define C_028BD4_DISTANCE_6 0xF0FFFFFF
7954 #define S_028BD4_DISTANCE_7(x) (((x) & 0x0F) << 28)
7955 #define G_028BD4_DISTANCE_7(x) (((x) >> 28) & 0x0F)
7956 #define C_028BD4_DISTANCE_7 0x0FFFFFFF
7957 #define R_028BD8_PA_SC_CENTROID_PRIORITY_1 0x028BD8
7958 #define S_028BD8_DISTANCE_8(x) (((x) & 0x0F) << 0)
7959 #define G_028BD8_DISTANCE_8(x) (((x) >> 0) & 0x0F)
7960 #define C_028BD8_DISTANCE_8 0xFFFFFFF0
7961 #define S_028BD8_DISTANCE_9(x) (((x) & 0x0F) << 4)
7962 #define G_028BD8_DISTANCE_9(x) (((x) >> 4) & 0x0F)
7963 #define C_028BD8_DISTANCE_9 0xFFFFFF0F
7964 #define S_028BD8_DISTANCE_10(x) (((x) & 0x0F) << 8)
7965 #define G_028BD8_DISTANCE_10(x) (((x) >> 8) & 0x0F)
7966 #define C_028BD8_DISTANCE_10 0xFFFFF0FF
7967 #define S_028BD8_DISTANCE_11(x) (((x) & 0x0F) << 12)
7968 #define G_028BD8_DISTANCE_11(x) (((x) >> 12) & 0x0F)
7969 #define C_028BD8_DISTANCE_11 0xFFFF0FFF
7970 #define S_028BD8_DISTANCE_12(x) (((x) & 0x0F) << 16)
7971 #define G_028BD8_DISTANCE_12(x) (((x) >> 16) & 0x0F)
7972 #define C_028BD8_DISTANCE_12 0xFFF0FFFF
7973 #define S_028BD8_DISTANCE_13(x) (((x) & 0x0F) << 20)
7974 #define G_028BD8_DISTANCE_13(x) (((x) >> 20) & 0x0F)
7975 #define C_028BD8_DISTANCE_13 0xFF0FFFFF
7976 #define S_028BD8_DISTANCE_14(x) (((x) & 0x0F) << 24)
7977 #define G_028BD8_DISTANCE_14(x) (((x) >> 24) & 0x0F)
7978 #define C_028BD8_DISTANCE_14 0xF0FFFFFF
7979 #define S_028BD8_DISTANCE_15(x) (((x) & 0x0F) << 28)
7980 #define G_028BD8_DISTANCE_15(x) (((x) >> 28) & 0x0F)
7981 #define C_028BD8_DISTANCE_15 0x0FFFFFFF
7982 #define R_028BDC_PA_SC_LINE_CNTL 0x028BDC
7983 #define S_028BDC_EXPAND_LINE_WIDTH(x) (((x) & 0x1) << 9)
7984 #define G_028BDC_EXPAND_LINE_WIDTH(x) (((x) >> 9) & 0x1)
7985 #define C_028BDC_EXPAND_LINE_WIDTH 0xFFFFFDFF
7986 #define S_028BDC_LAST_PIXEL(x) (((x) & 0x1) << 10)
7987 #define G_028BDC_LAST_PIXEL(x) (((x) >> 10) & 0x1)
7988 #define C_028BDC_LAST_PIXEL 0xFFFFFBFF
7989 #define S_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) & 0x1) << 11)
7990 #define G_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) >> 11) & 0x1)
7991 #define C_028BDC_PERPENDICULAR_ENDCAP_ENA 0xFFFFF7FF
7992 #define S_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) & 0x1) << 12)
7993 #define G_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) >> 12) & 0x1)
7994 #define C_028BDC_DX10_DIAMOND_TEST_ENA 0xFFFFEFFF
7995 #define R_028BE4_PA_SU_VTX_CNTL 0x028BE4
7996 #define S_028BE4_PIX_CENTER(x) (((x) & 0x1) << 0)
7997 #define G_028BE4_PIX_CENTER(x) (((x) >> 0) & 0x1)
7998 #define C_028BE4_PIX_CENTER 0xFFFFFFFE
7999 #define S_028BE4_ROUND_MODE(x) (((x) & 0x03) << 1)
8000 #define G_028BE4_ROUND_MODE(x) (((x) >> 1) & 0x03)
8001 #define C_028BE4_ROUND_MODE 0xFFFFFFF9
8002 #define V_028BE4_X_TRUNCATE 0x00
8003 #define V_028BE4_X_ROUND 0x01
8004 #define V_028BE4_X_ROUND_TO_EVEN 0x02
8005 #define V_028BE4_X_ROUND_TO_ODD 0x03
8006 #define S_028BE4_QUANT_MODE(x) (((x) & 0x07) << 3)
8007 #define G_028BE4_QUANT_MODE(x) (((x) >> 3) & 0x07)
8008 #define C_028BE4_QUANT_MODE 0xFFFFFFC7
8009 #define V_028BE4_X_16_8_FIXED_POINT_1_16TH 0x00
8010 #define V_028BE4_X_16_8_FIXED_POINT_1_8TH 0x01
8011 #define V_028BE4_X_16_8_FIXED_POINT_1_4TH 0x02
8012 #define V_028BE4_X_16_8_FIXED_POINT_1_2 0x03
8013 #define V_028BE4_X_16_8_FIXED_POINT_1 0x04
8014 #define V_028BE4_X_16_8_FIXED_POINT_1_256TH 0x05
8015 #define V_028BE4_X_14_10_FIXED_POINT_1_1024TH 0x06
8016 #define V_028BE4_X_12_12_FIXED_POINT_1_4096TH 0x07
8017 #define R_028BE8_PA_CL_GB_VERT_CLIP_ADJ 0x028BE8
8018 #define R_028BEC_PA_CL_GB_VERT_DISC_ADJ 0x028BEC
8019 #define R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ 0x028BF0
8020 #define R_028BF4_PA_CL_GB_HORZ_DISC_ADJ 0x028BF4
8021 #define R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x028BF8
8022 #define S_028BF8_S0_X(x) (((x) & 0x0F) << 0)
8023 #define G_028BF8_S0_X(x) (((x) >> 0) & 0x0F)
8024 #define C_028BF8_S0_X 0xFFFFFFF0
8025 #define S_028BF8_S0_Y(x) (((x) & 0x0F) << 4)
8026 #define G_028BF8_S0_Y(x) (((x) >> 4) & 0x0F)
8027 #define C_028BF8_S0_Y 0xFFFFFF0F
8028 #define S_028BF8_S1_X(x) (((x) & 0x0F) << 8)
8029 #define G_028BF8_S1_X(x) (((x) >> 8) & 0x0F)
8030 #define C_028BF8_S1_X 0xFFFFF0FF
8031 #define S_028BF8_S1_Y(x) (((x) & 0x0F) << 12)
8032 #define G_028BF8_S1_Y(x) (((x) >> 12) & 0x0F)
8033 #define C_028BF8_S1_Y 0xFFFF0FFF
8034 #define S_028BF8_S2_X(x) (((x) & 0x0F) << 16)
8035 #define G_028BF8_S2_X(x) (((x) >> 16) & 0x0F)
8036 #define C_028BF8_S2_X 0xFFF0FFFF
8037 #define S_028BF8_S2_Y(x) (((x) & 0x0F) << 20)
8038 #define G_028BF8_S2_Y(x) (((x) >> 20) & 0x0F)
8039 #define C_028BF8_S2_Y 0xFF0FFFFF
8040 #define S_028BF8_S3_X(x) (((x) & 0x0F) << 24)
8041 #define G_028BF8_S3_X(x) (((x) >> 24) & 0x0F)
8042 #define C_028BF8_S3_X 0xF0FFFFFF
8043 #define S_028BF8_S3_Y(x) (((x) & 0x0F) << 28)
8044 #define G_028BF8_S3_Y(x) (((x) >> 28) & 0x0F)
8045 #define C_028BF8_S3_Y 0x0FFFFFFF
8046 #define R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x028BFC
8047 #define S_028BFC_S4_X(x) (((x) & 0x0F) << 0)
8048 #define G_028BFC_S4_X(x) (((x) >> 0) & 0x0F)
8049 #define C_028BFC_S4_X 0xFFFFFFF0
8050 #define S_028BFC_S4_Y(x) (((x) & 0x0F) << 4)
8051 #define G_028BFC_S4_Y(x) (((x) >> 4) & 0x0F)
8052 #define C_028BFC_S4_Y 0xFFFFFF0F
8053 #define S_028BFC_S5_X(x) (((x) & 0x0F) << 8)
8054 #define G_028BFC_S5_X(x) (((x) >> 8) & 0x0F)
8055 #define C_028BFC_S5_X 0xFFFFF0FF
8056 #define S_028BFC_S5_Y(x) (((x) & 0x0F) << 12)
8057 #define G_028BFC_S5_Y(x) (((x) >> 12) & 0x0F)
8058 #define C_028BFC_S5_Y 0xFFFF0FFF
8059 #define S_028BFC_S6_X(x) (((x) & 0x0F) << 16)
8060 #define G_028BFC_S6_X(x) (((x) >> 16) & 0x0F)
8061 #define C_028BFC_S6_X 0xFFF0FFFF
8062 #define S_028BFC_S6_Y(x) (((x) & 0x0F) << 20)
8063 #define G_028BFC_S6_Y(x) (((x) >> 20) & 0x0F)
8064 #define C_028BFC_S6_Y 0xFF0FFFFF
8065 #define S_028BFC_S7_X(x) (((x) & 0x0F) << 24)
8066 #define G_028BFC_S7_X(x) (((x) >> 24) & 0x0F)
8067 #define C_028BFC_S7_X 0xF0FFFFFF
8068 #define S_028BFC_S7_Y(x) (((x) & 0x0F) << 28)
8069 #define G_028BFC_S7_Y(x) (((x) >> 28) & 0x0F)
8070 #define C_028BFC_S7_Y 0x0FFFFFFF
8071 #define R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x028C00
8072 #define S_028C00_S8_X(x) (((x) & 0x0F) << 0)
8073 #define G_028C00_S8_X(x) (((x) >> 0) & 0x0F)
8074 #define C_028C00_S8_X 0xFFFFFFF0
8075 #define S_028C00_S8_Y(x) (((x) & 0x0F) << 4)
8076 #define G_028C00_S8_Y(x) (((x) >> 4) & 0x0F)
8077 #define C_028C00_S8_Y 0xFFFFFF0F
8078 #define S_028C00_S9_X(x) (((x) & 0x0F) << 8)
8079 #define G_028C00_S9_X(x) (((x) >> 8) & 0x0F)
8080 #define C_028C00_S9_X 0xFFFFF0FF
8081 #define S_028C00_S9_Y(x) (((x) & 0x0F) << 12)
8082 #define G_028C00_S9_Y(x) (((x) >> 12) & 0x0F)
8083 #define C_028C00_S9_Y 0xFFFF0FFF
8084 #define S_028C00_S10_X(x) (((x) & 0x0F) << 16)
8085 #define G_028C00_S10_X(x) (((x) >> 16) & 0x0F)
8086 #define C_028C00_S10_X 0xFFF0FFFF
8087 #define S_028C00_S10_Y(x) (((x) & 0x0F) << 20)
8088 #define G_028C00_S10_Y(x) (((x) >> 20) & 0x0F)
8089 #define C_028C00_S10_Y 0xFF0FFFFF
8090 #define S_028C00_S11_X(x) (((x) & 0x0F) << 24)
8091 #define G_028C00_S11_X(x) (((x) >> 24) & 0x0F)
8092 #define C_028C00_S11_X 0xF0FFFFFF
8093 #define S_028C00_S11_Y(x) (((x) & 0x0F) << 28)
8094 #define G_028C00_S11_Y(x) (((x) >> 28) & 0x0F)
8095 #define C_028C00_S11_Y 0x0FFFFFFF
8096 #define R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x028C04
8097 #define S_028C04_S12_X(x) (((x) & 0x0F) << 0)
8098 #define G_028C04_S12_X(x) (((x) >> 0) & 0x0F)
8099 #define C_028C04_S12_X 0xFFFFFFF0
8100 #define S_028C04_S12_Y(x) (((x) & 0x0F) << 4)
8101 #define G_028C04_S12_Y(x) (((x) >> 4) & 0x0F)
8102 #define C_028C04_S12_Y 0xFFFFFF0F
8103 #define S_028C04_S13_X(x) (((x) & 0x0F) << 8)
8104 #define G_028C04_S13_X(x) (((x) >> 8) & 0x0F)
8105 #define C_028C04_S13_X 0xFFFFF0FF
8106 #define S_028C04_S13_Y(x) (((x) & 0x0F) << 12)
8107 #define G_028C04_S13_Y(x) (((x) >> 12) & 0x0F)
8108 #define C_028C04_S13_Y 0xFFFF0FFF
8109 #define S_028C04_S14_X(x) (((x) & 0x0F) << 16)
8110 #define G_028C04_S14_X(x) (((x) >> 16) & 0x0F)
8111 #define C_028C04_S14_X 0xFFF0FFFF
8112 #define S_028C04_S14_Y(x) (((x) & 0x0F) << 20)
8113 #define G_028C04_S14_Y(x) (((x) >> 20) & 0x0F)
8114 #define C_028C04_S14_Y 0xFF0FFFFF
8115 #define S_028C04_S15_X(x) (((x) & 0x0F) << 24)
8116 #define G_028C04_S15_X(x) (((x) >> 24) & 0x0F)
8117 #define C_028C04_S15_X 0xF0FFFFFF
8118 #define S_028C04_S15_Y(x) (((x) & 0x0F) << 28)
8119 #define G_028C04_S15_Y(x) (((x) >> 28) & 0x0F)
8120 #define C_028C04_S15_Y 0x0FFFFFFF
8121 #define R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x028C08
8122 #define S_028C08_S0_X(x) (((x) & 0x0F) << 0)
8123 #define G_028C08_S0_X(x) (((x) >> 0) & 0x0F)
8124 #define C_028C08_S0_X 0xFFFFFFF0
8125 #define S_028C08_S0_Y(x) (((x) & 0x0F) << 4)
8126 #define G_028C08_S0_Y(x) (((x) >> 4) & 0x0F)
8127 #define C_028C08_S0_Y 0xFFFFFF0F
8128 #define S_028C08_S1_X(x) (((x) & 0x0F) << 8)
8129 #define G_028C08_S1_X(x) (((x) >> 8) & 0x0F)
8130 #define C_028C08_S1_X 0xFFFFF0FF
8131 #define S_028C08_S1_Y(x) (((x) & 0x0F) << 12)
8132 #define G_028C08_S1_Y(x) (((x) >> 12) & 0x0F)
8133 #define C_028C08_S1_Y 0xFFFF0FFF
8134 #define S_028C08_S2_X(x) (((x) & 0x0F) << 16)
8135 #define G_028C08_S2_X(x) (((x) >> 16) & 0x0F)
8136 #define C_028C08_S2_X 0xFFF0FFFF
8137 #define S_028C08_S2_Y(x) (((x) & 0x0F) << 20)
8138 #define G_028C08_S2_Y(x) (((x) >> 20) & 0x0F)
8139 #define C_028C08_S2_Y 0xFF0FFFFF
8140 #define S_028C08_S3_X(x) (((x) & 0x0F) << 24)
8141 #define G_028C08_S3_X(x) (((x) >> 24) & 0x0F)
8142 #define C_028C08_S3_X 0xF0FFFFFF
8143 #define S_028C08_S3_Y(x) (((x) & 0x0F) << 28)
8144 #define G_028C08_S3_Y(x) (((x) >> 28) & 0x0F)
8145 #define C_028C08_S3_Y 0x0FFFFFFF
8146 #define R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x028C0C
8147 #define S_028C0C_S4_X(x) (((x) & 0x0F) << 0)
8148 #define G_028C0C_S4_X(x) (((x) >> 0) & 0x0F)
8149 #define C_028C0C_S4_X 0xFFFFFFF0
8150 #define S_028C0C_S4_Y(x) (((x) & 0x0F) << 4)
8151 #define G_028C0C_S4_Y(x) (((x) >> 4) & 0x0F)
8152 #define C_028C0C_S4_Y 0xFFFFFF0F
8153 #define S_028C0C_S5_X(x) (((x) & 0x0F) << 8)
8154 #define G_028C0C_S5_X(x) (((x) >> 8) & 0x0F)
8155 #define C_028C0C_S5_X 0xFFFFF0FF
8156 #define S_028C0C_S5_Y(x) (((x) & 0x0F) << 12)
8157 #define G_028C0C_S5_Y(x) (((x) >> 12) & 0x0F)
8158 #define C_028C0C_S5_Y 0xFFFF0FFF
8159 #define S_028C0C_S6_X(x) (((x) & 0x0F) << 16)
8160 #define G_028C0C_S6_X(x) (((x) >> 16) & 0x0F)
8161 #define C_028C0C_S6_X 0xFFF0FFFF
8162 #define S_028C0C_S6_Y(x) (((x) & 0x0F) << 20)
8163 #define G_028C0C_S6_Y(x) (((x) >> 20) & 0x0F)
8164 #define C_028C0C_S6_Y 0xFF0FFFFF
8165 #define S_028C0C_S7_X(x) (((x) & 0x0F) << 24)
8166 #define G_028C0C_S7_X(x) (((x) >> 24) & 0x0F)
8167 #define C_028C0C_S7_X 0xF0FFFFFF
8168 #define S_028C0C_S7_Y(x) (((x) & 0x0F) << 28)
8169 #define G_028C0C_S7_Y(x) (((x) >> 28) & 0x0F)
8170 #define C_028C0C_S7_Y 0x0FFFFFFF
8171 #define R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x028C10
8172 #define S_028C10_S8_X(x) (((x) & 0x0F) << 0)
8173 #define G_028C10_S8_X(x) (((x) >> 0) & 0x0F)
8174 #define C_028C10_S8_X 0xFFFFFFF0
8175 #define S_028C10_S8_Y(x) (((x) & 0x0F) << 4)
8176 #define G_028C10_S8_Y(x) (((x) >> 4) & 0x0F)
8177 #define C_028C10_S8_Y 0xFFFFFF0F
8178 #define S_028C10_S9_X(x) (((x) & 0x0F) << 8)
8179 #define G_028C10_S9_X(x) (((x) >> 8) & 0x0F)
8180 #define C_028C10_S9_X 0xFFFFF0FF
8181 #define S_028C10_S9_Y(x) (((x) & 0x0F) << 12)
8182 #define G_028C10_S9_Y(x) (((x) >> 12) & 0x0F)
8183 #define C_028C10_S9_Y 0xFFFF0FFF
8184 #define S_028C10_S10_X(x) (((x) & 0x0F) << 16)
8185 #define G_028C10_S10_X(x) (((x) >> 16) & 0x0F)
8186 #define C_028C10_S10_X 0xFFF0FFFF
8187 #define S_028C10_S10_Y(x) (((x) & 0x0F) << 20)
8188 #define G_028C10_S10_Y(x) (((x) >> 20) & 0x0F)
8189 #define C_028C10_S10_Y 0xFF0FFFFF
8190 #define S_028C10_S11_X(x) (((x) & 0x0F) << 24)
8191 #define G_028C10_S11_X(x) (((x) >> 24) & 0x0F)
8192 #define C_028C10_S11_X 0xF0FFFFFF
8193 #define S_028C10_S11_Y(x) (((x) & 0x0F) << 28)
8194 #define G_028C10_S11_Y(x) (((x) >> 28) & 0x0F)
8195 #define C_028C10_S11_Y 0x0FFFFFFF
8196 #define R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x028C14
8197 #define S_028C14_S12_X(x) (((x) & 0x0F) << 0)
8198 #define G_028C14_S12_X(x) (((x) >> 0) & 0x0F)
8199 #define C_028C14_S12_X 0xFFFFFFF0
8200 #define S_028C14_S12_Y(x) (((x) & 0x0F) << 4)
8201 #define G_028C14_S12_Y(x) (((x) >> 4) & 0x0F)
8202 #define C_028C14_S12_Y 0xFFFFFF0F
8203 #define S_028C14_S13_X(x) (((x) & 0x0F) << 8)
8204 #define G_028C14_S13_X(x) (((x) >> 8) & 0x0F)
8205 #define C_028C14_S13_X 0xFFFFF0FF
8206 #define S_028C14_S13_Y(x) (((x) & 0x0F) << 12)
8207 #define G_028C14_S13_Y(x) (((x) >> 12) & 0x0F)
8208 #define C_028C14_S13_Y 0xFFFF0FFF
8209 #define S_028C14_S14_X(x) (((x) & 0x0F) << 16)
8210 #define G_028C14_S14_X(x) (((x) >> 16) & 0x0F)
8211 #define C_028C14_S14_X 0xFFF0FFFF
8212 #define S_028C14_S14_Y(x) (((x) & 0x0F) << 20)
8213 #define G_028C14_S14_Y(x) (((x) >> 20) & 0x0F)
8214 #define C_028C14_S14_Y 0xFF0FFFFF
8215 #define S_028C14_S15_X(x) (((x) & 0x0F) << 24)
8216 #define G_028C14_S15_X(x) (((x) >> 24) & 0x0F)
8217 #define C_028C14_S15_X 0xF0FFFFFF
8218 #define S_028C14_S15_Y(x) (((x) & 0x0F) << 28)
8219 #define G_028C14_S15_Y(x) (((x) >> 28) & 0x0F)
8220 #define C_028C14_S15_Y 0x0FFFFFFF
8221 #define R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x028C18
8222 #define S_028C18_S0_X(x) (((x) & 0x0F) << 0)
8223 #define G_028C18_S0_X(x) (((x) >> 0) & 0x0F)
8224 #define C_028C18_S0_X 0xFFFFFFF0
8225 #define S_028C18_S0_Y(x) (((x) & 0x0F) << 4)
8226 #define G_028C18_S0_Y(x) (((x) >> 4) & 0x0F)
8227 #define C_028C18_S0_Y 0xFFFFFF0F
8228 #define S_028C18_S1_X(x) (((x) & 0x0F) << 8)
8229 #define G_028C18_S1_X(x) (((x) >> 8) & 0x0F)
8230 #define C_028C18_S1_X 0xFFFFF0FF
8231 #define S_028C18_S1_Y(x) (((x) & 0x0F) << 12)
8232 #define G_028C18_S1_Y(x) (((x) >> 12) & 0x0F)
8233 #define C_028C18_S1_Y 0xFFFF0FFF
8234 #define S_028C18_S2_X(x) (((x) & 0x0F) << 16)
8235 #define G_028C18_S2_X(x) (((x) >> 16) & 0x0F)
8236 #define C_028C18_S2_X 0xFFF0FFFF
8237 #define S_028C18_S2_Y(x) (((x) & 0x0F) << 20)
8238 #define G_028C18_S2_Y(x) (((x) >> 20) & 0x0F)
8239 #define C_028C18_S2_Y 0xFF0FFFFF
8240 #define S_028C18_S3_X(x) (((x) & 0x0F) << 24)
8241 #define G_028C18_S3_X(x) (((x) >> 24) & 0x0F)
8242 #define C_028C18_S3_X 0xF0FFFFFF
8243 #define S_028C18_S3_Y(x) (((x) & 0x0F) << 28)
8244 #define G_028C18_S3_Y(x) (((x) >> 28) & 0x0F)
8245 #define C_028C18_S3_Y 0x0FFFFFFF
8246 #define R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x028C1C
8247 #define S_028C1C_S4_X(x) (((x) & 0x0F) << 0)
8248 #define G_028C1C_S4_X(x) (((x) >> 0) & 0x0F)
8249 #define C_028C1C_S4_X 0xFFFFFFF0
8250 #define S_028C1C_S4_Y(x) (((x) & 0x0F) << 4)
8251 #define G_028C1C_S4_Y(x) (((x) >> 4) & 0x0F)
8252 #define C_028C1C_S4_Y 0xFFFFFF0F
8253 #define S_028C1C_S5_X(x) (((x) & 0x0F) << 8)
8254 #define G_028C1C_S5_X(x) (((x) >> 8) & 0x0F)
8255 #define C_028C1C_S5_X 0xFFFFF0FF
8256 #define S_028C1C_S5_Y(x) (((x) & 0x0F) << 12)
8257 #define G_028C1C_S5_Y(x) (((x) >> 12) & 0x0F)
8258 #define C_028C1C_S5_Y 0xFFFF0FFF
8259 #define S_028C1C_S6_X(x) (((x) & 0x0F) << 16)
8260 #define G_028C1C_S6_X(x) (((x) >> 16) & 0x0F)
8261 #define C_028C1C_S6_X 0xFFF0FFFF
8262 #define S_028C1C_S6_Y(x) (((x) & 0x0F) << 20)
8263 #define G_028C1C_S6_Y(x) (((x) >> 20) & 0x0F)
8264 #define C_028C1C_S6_Y 0xFF0FFFFF
8265 #define S_028C1C_S7_X(x) (((x) & 0x0F) << 24)
8266 #define G_028C1C_S7_X(x) (((x) >> 24) & 0x0F)
8267 #define C_028C1C_S7_X 0xF0FFFFFF
8268 #define S_028C1C_S7_Y(x) (((x) & 0x0F) << 28)
8269 #define G_028C1C_S7_Y(x) (((x) >> 28) & 0x0F)
8270 #define C_028C1C_S7_Y 0x0FFFFFFF
8271 #define R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x028C20
8272 #define S_028C20_S8_X(x) (((x) & 0x0F) << 0)
8273 #define G_028C20_S8_X(x) (((x) >> 0) & 0x0F)
8274 #define C_028C20_S8_X 0xFFFFFFF0
8275 #define S_028C20_S8_Y(x) (((x) & 0x0F) << 4)
8276 #define G_028C20_S8_Y(x) (((x) >> 4) & 0x0F)
8277 #define C_028C20_S8_Y 0xFFFFFF0F
8278 #define S_028C20_S9_X(x) (((x) & 0x0F) << 8)
8279 #define G_028C20_S9_X(x) (((x) >> 8) & 0x0F)
8280 #define C_028C20_S9_X 0xFFFFF0FF
8281 #define S_028C20_S9_Y(x) (((x) & 0x0F) << 12)
8282 #define G_028C20_S9_Y(x) (((x) >> 12) & 0x0F)
8283 #define C_028C20_S9_Y 0xFFFF0FFF
8284 #define S_028C20_S10_X(x) (((x) & 0x0F) << 16)
8285 #define G_028C20_S10_X(x) (((x) >> 16) & 0x0F)
8286 #define C_028C20_S10_X 0xFFF0FFFF
8287 #define S_028C20_S10_Y(x) (((x) & 0x0F) << 20)
8288 #define G_028C20_S10_Y(x) (((x) >> 20) & 0x0F)
8289 #define C_028C20_S10_Y 0xFF0FFFFF
8290 #define S_028C20_S11_X(x) (((x) & 0x0F) << 24)
8291 #define G_028C20_S11_X(x) (((x) >> 24) & 0x0F)
8292 #define C_028C20_S11_X 0xF0FFFFFF
8293 #define S_028C20_S11_Y(x) (((x) & 0x0F) << 28)
8294 #define G_028C20_S11_Y(x) (((x) >> 28) & 0x0F)
8295 #define C_028C20_S11_Y 0x0FFFFFFF
8296 #define R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x028C24
8297 #define S_028C24_S12_X(x) (((x) & 0x0F) << 0)
8298 #define G_028C24_S12_X(x) (((x) >> 0) & 0x0F)
8299 #define C_028C24_S12_X 0xFFFFFFF0
8300 #define S_028C24_S12_Y(x) (((x) & 0x0F) << 4)
8301 #define G_028C24_S12_Y(x) (((x) >> 4) & 0x0F)
8302 #define C_028C24_S12_Y 0xFFFFFF0F
8303 #define S_028C24_S13_X(x) (((x) & 0x0F) << 8)
8304 #define G_028C24_S13_X(x) (((x) >> 8) & 0x0F)
8305 #define C_028C24_S13_X 0xFFFFF0FF
8306 #define S_028C24_S13_Y(x) (((x) & 0x0F) << 12)
8307 #define G_028C24_S13_Y(x) (((x) >> 12) & 0x0F)
8308 #define C_028C24_S13_Y 0xFFFF0FFF
8309 #define S_028C24_S14_X(x) (((x) & 0x0F) << 16)
8310 #define G_028C24_S14_X(x) (((x) >> 16) & 0x0F)
8311 #define C_028C24_S14_X 0xFFF0FFFF
8312 #define S_028C24_S14_Y(x) (((x) & 0x0F) << 20)
8313 #define G_028C24_S14_Y(x) (((x) >> 20) & 0x0F)
8314 #define C_028C24_S14_Y 0xFF0FFFFF
8315 #define S_028C24_S15_X(x) (((x) & 0x0F) << 24)
8316 #define G_028C24_S15_X(x) (((x) >> 24) & 0x0F)
8317 #define C_028C24_S15_X 0xF0FFFFFF
8318 #define S_028C24_S15_Y(x) (((x) & 0x0F) << 28)
8319 #define G_028C24_S15_Y(x) (((x) >> 28) & 0x0F)
8320 #define C_028C24_S15_Y 0x0FFFFFFF
8321 #define R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x028C28
8322 #define S_028C28_S0_X(x) (((x) & 0x0F) << 0)
8323 #define G_028C28_S0_X(x) (((x) >> 0) & 0x0F)
8324 #define C_028C28_S0_X 0xFFFFFFF0
8325 #define S_028C28_S0_Y(x) (((x) & 0x0F) << 4)
8326 #define G_028C28_S0_Y(x) (((x) >> 4) & 0x0F)
8327 #define C_028C28_S0_Y 0xFFFFFF0F
8328 #define S_028C28_S1_X(x) (((x) & 0x0F) << 8)
8329 #define G_028C28_S1_X(x) (((x) >> 8) & 0x0F)
8330 #define C_028C28_S1_X 0xFFFFF0FF
8331 #define S_028C28_S1_Y(x) (((x) & 0x0F) << 12)
8332 #define G_028C28_S1_Y(x) (((x) >> 12) & 0x0F)
8333 #define C_028C28_S1_Y 0xFFFF0FFF
8334 #define S_028C28_S2_X(x) (((x) & 0x0F) << 16)
8335 #define G_028C28_S2_X(x) (((x) >> 16) & 0x0F)
8336 #define C_028C28_S2_X 0xFFF0FFFF
8337 #define S_028C28_S2_Y(x) (((x) & 0x0F) << 20)
8338 #define G_028C28_S2_Y(x) (((x) >> 20) & 0x0F)
8339 #define C_028C28_S2_Y 0xFF0FFFFF
8340 #define S_028C28_S3_X(x) (((x) & 0x0F) << 24)
8341 #define G_028C28_S3_X(x) (((x) >> 24) & 0x0F)
8342 #define C_028C28_S3_X 0xF0FFFFFF
8343 #define S_028C28_S3_Y(x) (((x) & 0x0F) << 28)
8344 #define G_028C28_S3_Y(x) (((x) >> 28) & 0x0F)
8345 #define C_028C28_S3_Y 0x0FFFFFFF
8346 #define R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x028C2C
8347 #define S_028C2C_S4_X(x) (((x) & 0x0F) << 0)
8348 #define G_028C2C_S4_X(x) (((x) >> 0) & 0x0F)
8349 #define C_028C2C_S4_X 0xFFFFFFF0
8350 #define S_028C2C_S4_Y(x) (((x) & 0x0F) << 4)
8351 #define G_028C2C_S4_Y(x) (((x) >> 4) & 0x0F)
8352 #define C_028C2C_S4_Y 0xFFFFFF0F
8353 #define S_028C2C_S5_X(x) (((x) & 0x0F) << 8)
8354 #define G_028C2C_S5_X(x) (((x) >> 8) & 0x0F)
8355 #define C_028C2C_S5_X 0xFFFFF0FF
8356 #define S_028C2C_S5_Y(x) (((x) & 0x0F) << 12)
8357 #define G_028C2C_S5_Y(x) (((x) >> 12) & 0x0F)
8358 #define C_028C2C_S5_Y 0xFFFF0FFF
8359 #define S_028C2C_S6_X(x) (((x) & 0x0F) << 16)
8360 #define G_028C2C_S6_X(x) (((x) >> 16) & 0x0F)
8361 #define C_028C2C_S6_X 0xFFF0FFFF
8362 #define S_028C2C_S6_Y(x) (((x) & 0x0F) << 20)
8363 #define G_028C2C_S6_Y(x) (((x) >> 20) & 0x0F)
8364 #define C_028C2C_S6_Y 0xFF0FFFFF
8365 #define S_028C2C_S7_X(x) (((x) & 0x0F) << 24)
8366 #define G_028C2C_S7_X(x) (((x) >> 24) & 0x0F)
8367 #define C_028C2C_S7_X 0xF0FFFFFF
8368 #define S_028C2C_S7_Y(x) (((x) & 0x0F) << 28)
8369 #define G_028C2C_S7_Y(x) (((x) >> 28) & 0x0F)
8370 #define C_028C2C_S7_Y 0x0FFFFFFF
8371 #define R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x028C30
8372 #define S_028C30_S8_X(x) (((x) & 0x0F) << 0)
8373 #define G_028C30_S8_X(x) (((x) >> 0) & 0x0F)
8374 #define C_028C30_S8_X 0xFFFFFFF0
8375 #define S_028C30_S8_Y(x) (((x) & 0x0F) << 4)
8376 #define G_028C30_S8_Y(x) (((x) >> 4) & 0x0F)
8377 #define C_028C30_S8_Y 0xFFFFFF0F
8378 #define S_028C30_S9_X(x) (((x) & 0x0F) << 8)
8379 #define G_028C30_S9_X(x) (((x) >> 8) & 0x0F)
8380 #define C_028C30_S9_X 0xFFFFF0FF
8381 #define S_028C30_S9_Y(x) (((x) & 0x0F) << 12)
8382 #define G_028C30_S9_Y(x) (((x) >> 12) & 0x0F)
8383 #define C_028C30_S9_Y 0xFFFF0FFF
8384 #define S_028C30_S10_X(x) (((x) & 0x0F) << 16)
8385 #define G_028C30_S10_X(x) (((x) >> 16) & 0x0F)
8386 #define C_028C30_S10_X 0xFFF0FFFF
8387 #define S_028C30_S10_Y(x) (((x) & 0x0F) << 20)
8388 #define G_028C30_S10_Y(x) (((x) >> 20) & 0x0F)
8389 #define C_028C30_S10_Y 0xFF0FFFFF
8390 #define S_028C30_S11_X(x) (((x) & 0x0F) << 24)
8391 #define G_028C30_S11_X(x) (((x) >> 24) & 0x0F)
8392 #define C_028C30_S11_X 0xF0FFFFFF
8393 #define S_028C30_S11_Y(x) (((x) & 0x0F) << 28)
8394 #define G_028C30_S11_Y(x) (((x) >> 28) & 0x0F)
8395 #define C_028C30_S11_Y 0x0FFFFFFF
8396 #define R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x028C34
8397 #define S_028C34_S12_X(x) (((x) & 0x0F) << 0)
8398 #define G_028C34_S12_X(x) (((x) >> 0) & 0x0F)
8399 #define C_028C34_S12_X 0xFFFFFFF0
8400 #define S_028C34_S12_Y(x) (((x) & 0x0F) << 4)
8401 #define G_028C34_S12_Y(x) (((x) >> 4) & 0x0F)
8402 #define C_028C34_S12_Y 0xFFFFFF0F
8403 #define S_028C34_S13_X(x) (((x) & 0x0F) << 8)
8404 #define G_028C34_S13_X(x) (((x) >> 8) & 0x0F)
8405 #define C_028C34_S13_X 0xFFFFF0FF
8406 #define S_028C34_S13_Y(x) (((x) & 0x0F) << 12)
8407 #define G_028C34_S13_Y(x) (((x) >> 12) & 0x0F)
8408 #define C_028C34_S13_Y 0xFFFF0FFF
8409 #define S_028C34_S14_X(x) (((x) & 0x0F) << 16)
8410 #define G_028C34_S14_X(x) (((x) >> 16) & 0x0F)
8411 #define C_028C34_S14_X 0xFFF0FFFF
8412 #define S_028C34_S14_Y(x) (((x) & 0x0F) << 20)
8413 #define G_028C34_S14_Y(x) (((x) >> 20) & 0x0F)
8414 #define C_028C34_S14_Y 0xFF0FFFFF
8415 #define S_028C34_S15_X(x) (((x) & 0x0F) << 24)
8416 #define G_028C34_S15_X(x) (((x) >> 24) & 0x0F)
8417 #define C_028C34_S15_X 0xF0FFFFFF
8418 #define S_028C34_S15_Y(x) (((x) & 0x0F) << 28)
8419 #define G_028C34_S15_Y(x) (((x) >> 28) & 0x0F)
8420 #define C_028C34_S15_Y 0x0FFFFFFF
8421 #define R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 0x028C38
8422 #define S_028C38_AA_MASK_X0Y0(x) (((x) & 0xFFFF) << 0)
8423 #define G_028C38_AA_MASK_X0Y0(x) (((x) >> 0) & 0xFFFF)
8424 #define C_028C38_AA_MASK_X0Y0 0xFFFF0000
8425 #define S_028C38_AA_MASK_X1Y0(x) (((x) & 0xFFFF) << 16)
8426 #define G_028C38_AA_MASK_X1Y0(x) (((x) >> 16) & 0xFFFF)
8427 #define C_028C38_AA_MASK_X1Y0 0x0000FFFF
8428 #define R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 0x028C3C
8429 #define S_028C3C_AA_MASK_X0Y1(x) (((x) & 0xFFFF) << 0)
8430 #define G_028C3C_AA_MASK_X0Y1(x) (((x) >> 0) & 0xFFFF)
8431 #define C_028C3C_AA_MASK_X0Y1 0xFFFF0000
8432 #define S_028C3C_AA_MASK_X1Y1(x) (((x) & 0xFFFF) << 16)
8433 #define G_028C3C_AA_MASK_X1Y1(x) (((x) >> 16) & 0xFFFF)
8434 #define C_028C3C_AA_MASK_X1Y1 0x0000FFFF
8435 #define R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL 0x028C58
8436 #define S_028C58_VTX_REUSE_DEPTH(x) (((x) & 0xFF) << 0)
8437 #define G_028C58_VTX_REUSE_DEPTH(x) (((x) >> 0) & 0xFF)
8438 #define C_028C58_VTX_REUSE_DEPTH 0xFFFFFF00
8439 #define R_028C5C_VGT_OUT_DEALLOC_CNTL 0x028C5C
8440 #define S_028C5C_DEALLOC_DIST(x) (((x) & 0x7F) << 0)
8441 #define G_028C5C_DEALLOC_DIST(x) (((x) >> 0) & 0x7F)
8442 #define C_028C5C_DEALLOC_DIST 0xFFFFFF80
8443 #define R_028C60_CB_COLOR0_BASE 0x028C60
8444 #define R_028C64_CB_COLOR0_PITCH 0x028C64
8445 #define S_028C64_TILE_MAX(x) (((x) & 0x7FF) << 0)
8446 #define G_028C64_TILE_MAX(x) (((x) >> 0) & 0x7FF)
8447 #define C_028C64_TILE_MAX 0xFFFFF800
8448 /* CIK */
8449 #define S_028C64_FMASK_TILE_MAX(x) (((x) & 0x7FF) << 20)
8450 #define G_028C64_FMASK_TILE_MAX(x) (((x) >> 20) & 0x7FF)
8451 #define C_028C64_FMASK_TILE_MAX 0x800FFFFF
8452 /* */
8453 #define R_028C68_CB_COLOR0_SLICE 0x028C68
8454 #define S_028C68_TILE_MAX(x) (((x) & 0x3FFFFF) << 0)
8455 #define G_028C68_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF)
8456 #define C_028C68_TILE_MAX 0xFFC00000
8457 #define R_028C6C_CB_COLOR0_VIEW 0x028C6C
8458 #define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0)
8459 #define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF)
8460 #define C_028C6C_SLICE_START 0xFFFFF800
8461 #define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13)
8462 #define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
8463 #define C_028C6C_SLICE_MAX 0xFF001FFF
8464 #define R_028C70_CB_COLOR0_INFO 0x028C70
8465 #define S_028C70_ENDIAN(x) (((x) & 0x03) << 0)
8466 #define G_028C70_ENDIAN(x) (((x) >> 0) & 0x03)
8467 #define C_028C70_ENDIAN 0xFFFFFFFC
8468 #define V_028C70_ENDIAN_NONE 0x00
8469 #define V_028C70_ENDIAN_8IN16 0x01
8470 #define V_028C70_ENDIAN_8IN32 0x02
8471 #define V_028C70_ENDIAN_8IN64 0x03
8472 #define S_028C70_FORMAT(x) (((x) & 0x1F) << 2)
8473 #define G_028C70_FORMAT(x) (((x) >> 2) & 0x1F)
8474 #define C_028C70_FORMAT 0xFFFFFF83
8475 #define V_028C70_COLOR_INVALID 0x00
8476 #define V_028C70_COLOR_8 0x01
8477 #define V_028C70_COLOR_16 0x02
8478 #define V_028C70_COLOR_8_8 0x03
8479 #define V_028C70_COLOR_32 0x04
8480 #define V_028C70_COLOR_16_16 0x05
8481 #define V_028C70_COLOR_10_11_11 0x06
8482 #define V_028C70_COLOR_11_11_10 0x07
8483 #define V_028C70_COLOR_10_10_10_2 0x08
8484 #define V_028C70_COLOR_2_10_10_10 0x09
8485 #define V_028C70_COLOR_8_8_8_8 0x0A
8486 #define V_028C70_COLOR_32_32 0x0B
8487 #define V_028C70_COLOR_16_16_16_16 0x0C
8488 #define V_028C70_COLOR_32_32_32_32 0x0E
8489 #define V_028C70_COLOR_5_6_5 0x10
8490 #define V_028C70_COLOR_1_5_5_5 0x11
8491 #define V_028C70_COLOR_5_5_5_1 0x12
8492 #define V_028C70_COLOR_4_4_4_4 0x13
8493 #define V_028C70_COLOR_8_24 0x14
8494 #define V_028C70_COLOR_24_8 0x15
8495 #define V_028C70_COLOR_X24_8_32_FLOAT 0x16
8496 #define S_028C70_LINEAR_GENERAL(x) (((x) & 0x1) << 7)
8497 #define G_028C70_LINEAR_GENERAL(x) (((x) >> 7) & 0x1)
8498 #define C_028C70_LINEAR_GENERAL 0xFFFFFF7F
8499 #define S_028C70_NUMBER_TYPE(x) (((x) & 0x07) << 8)
8500 #define G_028C70_NUMBER_TYPE(x) (((x) >> 8) & 0x07)
8501 #define C_028C70_NUMBER_TYPE 0xFFFFF8FF
8502 #define V_028C70_NUMBER_UNORM 0x00
8503 #define V_028C70_NUMBER_SNORM 0x01
8504 #define V_028C70_NUMBER_UINT 0x04
8505 #define V_028C70_NUMBER_SINT 0x05
8506 #define V_028C70_NUMBER_SRGB 0x06
8507 #define V_028C70_NUMBER_FLOAT 0x07
8508 #define S_028C70_COMP_SWAP(x) (((x) & 0x03) << 11)
8509 #define G_028C70_COMP_SWAP(x) (((x) >> 11) & 0x03)
8510 #define C_028C70_COMP_SWAP 0xFFFFE7FF
8511 #define V_028C70_SWAP_STD 0x00
8512 #define V_028C70_SWAP_ALT 0x01
8513 #define V_028C70_SWAP_STD_REV 0x02
8514 #define V_028C70_SWAP_ALT_REV 0x03
8515 #define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 13)
8516 #define G_028C70_FAST_CLEAR(x) (((x) >> 13) & 0x1)
8517 #define C_028C70_FAST_CLEAR 0xFFFFDFFF
8518 #define S_028C70_COMPRESSION(x) (((x) & 0x1) << 14)
8519 #define G_028C70_COMPRESSION(x) (((x) >> 14) & 0x1)
8520 #define C_028C70_COMPRESSION 0xFFFFBFFF
8521 #define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 15)
8522 #define G_028C70_BLEND_CLAMP(x) (((x) >> 15) & 0x1)
8523 #define C_028C70_BLEND_CLAMP 0xFFFF7FFF
8524 #define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 16)
8525 #define G_028C70_BLEND_BYPASS(x) (((x) >> 16) & 0x1)
8526 #define C_028C70_BLEND_BYPASS 0xFFFEFFFF
8527 #define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 17)
8528 #define G_028C70_SIMPLE_FLOAT(x) (((x) >> 17) & 0x1)
8529 #define C_028C70_SIMPLE_FLOAT 0xFFFDFFFF
8530 #define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 18)
8531 #define G_028C70_ROUND_MODE(x) (((x) >> 18) & 0x1)
8532 #define C_028C70_ROUND_MODE 0xFFFBFFFF
8533 #define S_028C70_CMASK_IS_LINEAR(x) (((x) & 0x1) << 19)
8534 #define G_028C70_CMASK_IS_LINEAR(x) (((x) >> 19) & 0x1)
8535 #define C_028C70_CMASK_IS_LINEAR 0xFFF7FFFF
8536 #define S_028C70_BLEND_OPT_DONT_RD_DST(x) (((x) & 0x07) << 20)
8537 #define G_028C70_BLEND_OPT_DONT_RD_DST(x) (((x) >> 20) & 0x07)
8538 #define C_028C70_BLEND_OPT_DONT_RD_DST 0xFF8FFFFF
8539 #define V_028C70_FORCE_OPT_AUTO 0x00
8540 #define V_028C70_FORCE_OPT_DISABLE 0x01
8541 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_0 0x02
8542 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_0 0x03
8543 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_0 0x04
8544 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_1 0x05
8545 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_1 0x06
8546 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_1 0x07
8547 #define S_028C70_BLEND_OPT_DISCARD_PIXEL(x) (((x) & 0x07) << 23)
8548 #define G_028C70_BLEND_OPT_DISCARD_PIXEL(x) (((x) >> 23) & 0x07)
8549 #define C_028C70_BLEND_OPT_DISCARD_PIXEL 0xFC7FFFFF
8550 #define V_028C70_FORCE_OPT_AUTO 0x00
8551 #define V_028C70_FORCE_OPT_DISABLE 0x01
8552 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_0 0x02
8553 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_0 0x03
8554 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_0 0x04
8555 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_1 0x05
8556 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_1 0x06
8557 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_1 0x07
8558 /* CIK */
8559 #define S_028C70_FMASK_COMPRESSION_DISABLE(x) (((x) & 0x1) << 26)
8560 #define G_028C70_FMASK_COMPRESSION_DISABLE(x) (((x) >> 26) & 0x1)
8561 #define C_028C70_FMASK_COMPRESSION_DISABLE 0xFBFFFFFF
8562 /* */
8563 #define R_028C74_CB_COLOR0_ATTRIB 0x028C74
8564 #define S_028C74_TILE_MODE_INDEX(x) (((x) & 0x1F) << 0)
8565 #define G_028C74_TILE_MODE_INDEX(x) (((x) >> 0) & 0x1F)
8566 #define C_028C74_TILE_MODE_INDEX 0xFFFFFFE0
8567 #define S_028C74_FMASK_TILE_MODE_INDEX(x) (((x) & 0x1F) << 5)
8568 #define G_028C74_FMASK_TILE_MODE_INDEX(x) (((x) >> 5) & 0x1F)
8569 #define C_028C74_FMASK_TILE_MODE_INDEX 0xFFFFFC1F
8570 #define S_028C74_FMASK_BANK_HEIGHT(x) (((x) & 0x3) << 10) /* SI errata */
8571 #define S_028C74_NUM_SAMPLES(x) (((x) & 0x07) << 12)
8572 #define G_028C74_NUM_SAMPLES(x) (((x) >> 12) & 0x07)
8573 #define C_028C74_NUM_SAMPLES 0xFFFF8FFF
8574 #define S_028C74_NUM_FRAGMENTS(x) (((x) & 0x03) << 15)
8575 #define G_028C74_NUM_FRAGMENTS(x) (((x) >> 15) & 0x03)
8576 #define C_028C74_NUM_FRAGMENTS 0xFFFE7FFF
8577 #define S_028C74_FORCE_DST_ALPHA_1(x) (((x) & 0x1) << 17)
8578 #define G_028C74_FORCE_DST_ALPHA_1(x) (((x) >> 17) & 0x1)
8579 #define C_028C74_FORCE_DST_ALPHA_1 0xFFFDFFFF
8580 #define R_028C7C_CB_COLOR0_CMASK 0x028C7C
8581 #define R_028C80_CB_COLOR0_CMASK_SLICE 0x028C80
8582 #define S_028C80_TILE_MAX(x) (((x) & 0x3FFF) << 0)
8583 #define G_028C80_TILE_MAX(x) (((x) >> 0) & 0x3FFF)
8584 #define C_028C80_TILE_MAX 0xFFFFC000
8585 #define R_028C84_CB_COLOR0_FMASK 0x028C84
8586 #define R_028C88_CB_COLOR0_FMASK_SLICE 0x028C88
8587 #define S_028C88_TILE_MAX(x) (((x) & 0x3FFFFF) << 0)
8588 #define G_028C88_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF)
8589 #define C_028C88_TILE_MAX 0xFFC00000
8590 #define R_028C8C_CB_COLOR0_CLEAR_WORD0 0x028C8C
8591 #define R_028C90_CB_COLOR0_CLEAR_WORD1 0x028C90
8592 #define R_028C9C_CB_COLOR1_BASE 0x028C9C
8593 #define R_028CA0_CB_COLOR1_PITCH 0x028CA0
8594 #define R_028CA4_CB_COLOR1_SLICE 0x028CA4
8595 #define R_028CA8_CB_COLOR1_VIEW 0x028CA8
8596 #define R_028CAC_CB_COLOR1_INFO 0x028CAC
8597 #define R_028CB0_CB_COLOR1_ATTRIB 0x028CB0
8598 #define R_028CD4_CB_COLOR1_CMASK 0x028CB8
8599 #define R_028CBC_CB_COLOR1_CMASK_SLICE 0x028CBC
8600 #define R_028CC0_CB_COLOR1_FMASK 0x028CC0
8601 #define R_028CC4_CB_COLOR1_FMASK_SLICE 0x028CC4
8602 #define R_028CC8_CB_COLOR1_CLEAR_WORD0 0x028CC8
8603 #define R_028CCC_CB_COLOR1_CLEAR_WORD1 0x028CCC
8604 #define R_028CD8_CB_COLOR2_BASE 0x028CD8
8605 #define R_028CDC_CB_COLOR2_PITCH 0x028CDC
8606 #define R_028CE0_CB_COLOR2_SLICE 0x028CE0
8607 #define R_028CE4_CB_COLOR2_VIEW 0x028CE4
8608 #define R_028CE8_CB_COLOR2_INFO 0x028CE8
8609 #define R_028CEC_CB_COLOR2_ATTRIB 0x028CEC
8610 #define R_028CF4_CB_COLOR2_CMASK 0x028CF4
8611 #define R_028CF8_CB_COLOR2_CMASK_SLICE 0x028CF8
8612 #define R_028CFC_CB_COLOR2_FMASK 0x028CFC
8613 #define R_028D00_CB_COLOR2_FMASK_SLICE 0x028D00
8614 #define R_028D04_CB_COLOR2_CLEAR_WORD0 0x028D04
8615 #define R_028D08_CB_COLOR2_CLEAR_WORD1 0x028D08
8616 #define R_028D14_CB_COLOR3_BASE 0x028D14
8617 #define R_028D18_CB_COLOR3_PITCH 0x028D18
8618 #define R_028D1C_CB_COLOR3_SLICE 0x028D1C
8619 #define R_028D20_CB_COLOR3_VIEW 0x028D20
8620 #define R_028D24_CB_COLOR3_INFO 0x028D24
8621 #define R_028D28_CB_COLOR3_ATTRIB 0x028D28
8622 #define R_028D30_CB_COLOR3_CMASK 0x028D30
8623 #define R_028D34_CB_COLOR3_CMASK_SLICE 0x028D34
8624 #define R_028D38_CB_COLOR3_FMASK 0x028D38
8625 #define R_028D3C_CB_COLOR3_FMASK_SLICE 0x028D3C
8626 #define R_028D40_CB_COLOR3_CLEAR_WORD0 0x028D40
8627 #define R_028D44_CB_COLOR3_CLEAR_WORD1 0x028D44
8628 #define R_028D50_CB_COLOR4_BASE 0x028D50
8629 #define R_028D54_CB_COLOR4_PITCH 0x028D54
8630 #define R_028D58_CB_COLOR4_SLICE 0x028D58
8631 #define R_028D5C_CB_COLOR4_VIEW 0x028D5C
8632 #define R_028D60_CB_COLOR4_INFO 0x028D60
8633 #define R_028D64_CB_COLOR4_ATTRIB 0x028D64
8634 #define R_028D6C_CB_COLOR4_CMASK 0x028D6C
8635 #define R_028D70_CB_COLOR4_CMASK_SLICE 0x028D70
8636 #define R_028D74_CB_COLOR4_FMASK 0x028D74
8637 #define R_028D78_CB_COLOR4_FMASK_SLICE 0x028D78
8638 #define R_028D7C_CB_COLOR4_CLEAR_WORD0 0x028D7C
8639 #define R_028D80_CB_COLOR4_CLEAR_WORD1 0x028D80
8640 #define R_028D8C_CB_COLOR5_BASE 0x028D8C
8641 #define R_028D90_CB_COLOR5_PITCH 0x028D90
8642 #define R_028D94_CB_COLOR5_SLICE 0x028D94
8643 #define R_028D98_CB_COLOR5_VIEW 0x028D98
8644 #define R_028D9C_CB_COLOR5_INFO 0x028D9C
8645 #define R_028DA0_CB_COLOR5_ATTRIB 0x028DA0
8646 #define R_028DA8_CB_COLOR5_CMASK 0x028DA8
8647 #define R_028DAC_CB_COLOR5_CMASK_SLICE 0x028DAC
8648 #define R_028DB0_CB_COLOR5_FMASK 0x028DB0
8649 #define R_028DB4_CB_COLOR5_FMASK_SLICE 0x028DB4
8650 #define R_028DB8_CB_COLOR5_CLEAR_WORD0 0x028DB8
8651 #define R_028DBC_CB_COLOR5_CLEAR_WORD1 0x028DBC
8652 #define R_028DC8_CB_COLOR6_BASE 0x028DC8
8653 #define R_028DCC_CB_COLOR6_PITCH 0x028DCC
8654 #define R_028DD0_CB_COLOR6_SLICE 0x028DD0
8655 #define R_028DD4_CB_COLOR6_VIEW 0x028DD4
8656 #define R_028DD8_CB_COLOR6_INFO 0x028DD8
8657 #define R_028DDC_CB_COLOR6_ATTRIB 0x028DDC
8658 #define R_028DE4_CB_COLOR6_CMASK 0x028DE4
8659 #define R_028DE8_CB_COLOR6_CMASK_SLICE 0x028DE8
8660 #define R_028DEC_CB_COLOR6_FMASK 0x028DEC
8661 #define R_028DF0_CB_COLOR6_FMASK_SLICE 0x028DF0
8662 #define R_028DF4_CB_COLOR6_CLEAR_WORD0 0x028DF4
8663 #define R_028DF8_CB_COLOR6_CLEAR_WORD1 0x028DF8
8664 #define R_028E04_CB_COLOR7_BASE 0x028E04
8665 #define R_028E08_CB_COLOR7_PITCH 0x028E08
8666 #define R_028E0C_CB_COLOR7_SLICE 0x028E0C
8667 #define R_028E10_CB_COLOR7_VIEW 0x028E10
8668 #define R_028E14_CB_COLOR7_INFO 0x028E14
8669 #define R_028E18_CB_COLOR7_ATTRIB 0x028E18
8670 #define R_028E20_CB_COLOR7_CMASK 0x028E20
8671 #define R_028E24_CB_COLOR7_CMASK_SLICE 0x028E24
8672 #define R_028E28_CB_COLOR7_FMASK 0x028E28
8673 #define R_028E2C_CB_COLOR7_FMASK_SLICE 0x028E2C
8674 #define R_028E30_CB_COLOR7_CLEAR_WORD0 0x028E30
8675 #define R_028E34_CB_COLOR7_CLEAR_WORD1 0x028E34
8676
8677 /* SI async DMA packets */
8678 #define SI_DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) | \
8679 (((sub_cmd) & 0xFF) << 20) |\
8680 (((n) & 0xFFFFF) << 0))
8681 /* SI async DMA Packet types */
8682 #define SI_DMA_PACKET_WRITE 0x2
8683 #define SI_DMA_PACKET_COPY 0x3
8684 #define SI_DMA_COPY_MAX_SIZE 0xfffe0
8685 #define SI_DMA_COPY_MAX_SIZE_DW 0xffff8
8686 #define SI_DMA_COPY_DWORD_ALIGNED 0x00
8687 #define SI_DMA_COPY_BYTE_ALIGNED 0x40
8688 #define SI_DMA_COPY_TILED 0x8
8689 #define SI_DMA_PACKET_INDIRECT_BUFFER 0x4
8690 #define SI_DMA_PACKET_SEMAPHORE 0x5
8691 #define SI_DMA_PACKET_FENCE 0x6
8692 #define SI_DMA_PACKET_TRAP 0x7
8693 #define SI_DMA_PACKET_SRBM_WRITE 0x9
8694 #define SI_DMA_PACKET_CONSTANT_FILL 0xd
8695 #define SI_DMA_PACKET_NOP 0xf
8696
8697 #endif /* _SID_H */
8698