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radeonsi: add VI register definitions
[mesa.git] / src / gallium / drivers / radeonsi / sid.h
1 /*
2 * Southern Islands Register documentation
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef SID_H
25 #define SID_H
26
27 /* si values */
28 #define SI_CONFIG_REG_OFFSET 0x00008000
29 #define SI_CONFIG_REG_END 0x0000B000
30 #define SI_SH_REG_OFFSET 0x0000B000
31 #define SI_SH_REG_END 0x0000C000
32 #define SI_CONTEXT_REG_OFFSET 0x00028000
33 #define SI_CONTEXT_REG_END 0x00029000
34 #define CIK_UCONFIG_REG_OFFSET 0x00030000
35 #define CIK_UCONFIG_REG_END 0x00031000
36
37 #define EVENT_TYPE_CACHE_FLUSH 0x6
38 #define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10
39 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14
40 #define EVENT_TYPE_ZPASS_DONE 0x15
41 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16
42 #define EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH 0x1f
43 #define EVENT_TYPE_SAMPLE_STREAMOUTSTATS 0x20
44 #define EVENT_TYPE(x) ((x) << 0)
45 #define EVENT_INDEX(x) ((x) << 8)
46 /* 0 - any non-TS event
47 * 1 - ZPASS_DONE
48 * 2 - SAMPLE_PIPELINESTAT
49 * 3 - SAMPLE_STREAMOUTSTAT*
50 * 4 - *S_PARTIAL_FLUSH
51 * 5 - TS events
52 */
53 #define EVENT_WRITE_INV_L2 0x100000
54
55
56 #define PREDICATION_OP_CLEAR 0x0
57 #define PREDICATION_OP_ZPASS 0x1
58 #define PREDICATION_OP_PRIMCOUNT 0x2
59
60 #define PRED_OP(x) ((x) << 16)
61
62 #define PREDICATION_CONTINUE (1 << 31)
63
64 #define PREDICATION_HINT_WAIT (0 << 12)
65 #define PREDICATION_HINT_NOWAIT_DRAW (1 << 12)
66
67 #define PREDICATION_DRAW_NOT_VISIBLE (0 << 8)
68 #define PREDICATION_DRAW_VISIBLE (1 << 8)
69
70 #define R600_TEXEL_PITCH_ALIGNMENT_MASK 0x7
71
72 #define PKT3_NOP 0x10
73 #define PKT3_SET_BASE 0x11
74 #define PKT3_CLEAR_STATE 0x12
75 #define PKT3_INDEX_BUFFER_SIZE 0x13
76 #define PKT3_DISPATCH_DIRECT 0x15
77 #define PKT3_DISPATCH_INDIRECT 0x16
78 #define PKT3_OCCLUSION_QUERY 0x1F /* new for CIK */
79 #define PKT3_SET_PREDICATION 0x20
80 #define PKT3_COND_EXEC 0x22
81 #define PKT3_PRED_EXEC 0x23
82 #define PKT3_DRAW_INDIRECT 0x24
83 #define PKT3_DRAW_INDEX_INDIRECT 0x25
84 #define PKT3_INDEX_BASE 0x26
85 #define PKT3_DRAW_INDEX_2 0x27
86 #define PKT3_CONTEXT_CONTROL 0x28
87 #define PKT3_INDEX_TYPE 0x2A
88 #define PKT3_DRAW_INDIRECT_MULTI 0x2C
89 #define PKT3_DRAW_INDEX_AUTO 0x2D
90 #define PKT3_DRAW_INDEX_IMMD 0x2E /* not on CIK */
91 #define PKT3_NUM_INSTANCES 0x2F
92 #define PKT3_DRAW_INDEX_MULTI_AUTO 0x30
93 #define PKT3_INDIRECT_BUFFER 0x32
94 #define PKT3_STRMOUT_BUFFER_UPDATE 0x34
95 #define PKT3_DRAW_INDEX_OFFSET_2 0x35
96 #define PKT3_DRAW_PREAMBLE 0x36 /* new on CIK, required on GFX7.2 and later */
97 #define PKT3_WRITE_DATA 0x37
98 #define PKT3_WRITE_DATA_DST_SEL(x) ((x) << 8)
99 #define PKT3_WRITE_DATA_DST_SEL_REG 0
100 #define PKT3_WRITE_DATA_DST_SEL_MEM_SYNC 1
101 #define PKT3_WRITE_DATA_DST_SEL_TC_L2 2
102 #define PKT3_WRITE_DATA_DST_SEL_GDS 3
103 #define PKT3_WRITE_DATA_DST_SEL_RESERVED_4 4
104 #define PKT3_WRITE_DATA_DST_SEL_MEM_ASYNC 5
105 #define PKT3_WR_ONE_ADDR (1 << 16)
106 #define PKT3_WRITE_DATA_WR_CONFIRM (1 << 20)
107 #define PKT3_WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
108 #define PKT3_WRITE_DATA_ENGINE_SEL_ME 0
109 #define PKT3_WRITE_DATA_ENGINE_SEL_PFP 1
110 #define PKT3_WRITE_DATA_ENGINE_SEL_CE 2
111 #define PKT3_DRAW_INDEX_INDIRECT_MULTI 0x38
112 #define PKT3_MEM_SEMAPHORE 0x39
113 #define PKT3_MPEG_INDEX 0x3A /* not on CIK */
114 #define PKT3_WAIT_REG_MEM 0x3C
115 #define WAIT_REG_MEM_EQUAL 3
116 #define PKT3_MEM_WRITE 0x3D /* not on CIK */
117 #define PKT3_COPY_DATA 0x40
118 #define COPY_DATA_SRC_SEL(x) ((x) & 0xf)
119 #define COPY_DATA_REG 0
120 #define COPY_DATA_MEM 1
121 #define COPY_DATA_DST_SEL(x) (((x) & 0xf) << 8)
122 #define COPY_DATA_WR_CONFIRM (1 << 20)
123 #define PKT3_SURFACE_SYNC 0x43 /* deprecated on CIK, use ACQUIRE_MEM */
124 #define PKT3_ME_INITIALIZE 0x44 /* not on CIK */
125 #define PKT3_COND_WRITE 0x45
126 #define PKT3_EVENT_WRITE 0x46
127 #define PKT3_EVENT_WRITE_EOP 0x47
128 #define PKT3_EVENT_WRITE_EOS 0x48
129 #define PKT3_ONE_REG_WRITE 0x57 /* not on CIK */
130 #define PKT3_ACQUIRE_MEM 0x58 /* new for CIK */
131 #define PKT3_SET_CONFIG_REG 0x68
132 #define PKT3_SET_CONTEXT_REG 0x69
133 #define PKT3_SET_SH_REG 0x76
134 #define PKT3_SET_SH_REG_OFFSET 0x77
135 #define PKT3_SET_UCONFIG_REG 0x79 /* new for CIK */
136
137 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
138 #define PKT_TYPE_G(x) (((x) >> 30) & 0x3)
139 #define PKT_TYPE_C 0x3FFFFFFF
140 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
141 #define PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF)
142 #define PKT_COUNT_C 0xC000FFFF
143 #define PKT0_BASE_INDEX_S(x) (((x) & 0xFFFF) << 0)
144 #define PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF)
145 #define PKT0_BASE_INDEX_C 0xFFFF0000
146 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
147 #define PKT3_IT_OPCODE_G(x) (((x) >> 8) & 0xFF)
148 #define PKT3_IT_OPCODE_C 0xFFFF00FF
149 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
150 #define PKT3_SHADER_TYPE_S(x) (((x) & 0x1) << 1)
151 #define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count))
152 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
153
154 #define PKT3_CP_DMA 0x41
155 /* 1. header
156 * 2. SRC_ADDR_LO [31:0] or DATA [31:0]
157 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | SRC_ADDR_HI [15:0]
158 * 4. DST_ADDR_LO [31:0]
159 * 5. DST_ADDR_HI [15:0]
160 * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
161 */
162 #define PKT3_CP_DMA_CP_SYNC (1 << 31)
163 #define PKT3_CP_DMA_SRC_SEL(x) ((x) << 29)
164 /* 0 - SRC_ADDR
165 * 1 - GDS (program SAS to 1 as well)
166 * 2 - DATA
167 * 3 - SRC_ADDR using TC L2 (DMA_DATA only)
168 */
169 #define PKT3_CP_DMA_DST_SEL(x) ((x) << 20)
170 /* 0 - DST_ADDR
171 * 1 - GDS (program DAS to 1 as well)
172 * 3 - DST_ADDR using TC L2 (DMA_DATA only)
173 */
174 /* COMMAND */
175 #define PKT3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
176 /* 0 - none
177 * 1 - 8 in 16
178 * 2 - 8 in 32
179 * 3 - 8 in 64
180 */
181 #define PKT3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
182 /* 0 - none
183 * 1 - 8 in 16
184 * 2 - 8 in 32
185 * 3 - 8 in 64
186 */
187 #define PKT3_CP_DMA_CMD_SAS (1 << 26)
188 /* 0 - memory
189 * 1 - register
190 */
191 #define PKT3_CP_DMA_CMD_DAS (1 << 27)
192 /* 0 - memory
193 * 1 - register
194 */
195 #define PKT3_CP_DMA_CMD_SAIC (1 << 28)
196 #define PKT3_CP_DMA_CMD_DAIC (1 << 29)
197 #define PKT3_CP_DMA_CMD_RAW_WAIT (1 << 30)
198
199 #define PKT3_DMA_DATA 0x50 /* new for CIK */
200 /* 1. header
201 * 2. CP_SYNC [31] | SRC_SEL [30:29] | DST_SEL [21:20] | ENGINE [0]
202 * 2. SRC_ADDR_LO [31:0] or DATA [31:0]
203 * 3. SRC_ADDR_HI [31:0]
204 * 4. DST_ADDR_LO [31:0]
205 * 5. DST_ADDR_HI [31:0]
206 * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
207 */
208
209
210 #define R_008010_GRBM_STATUS 0x008010
211 #define S_008010_ME0PIPE0_CMDFIFO_AVAIL(x) (((x) & 0x0F) << 0)
212 #define G_008010_ME0PIPE0_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x0F)
213 #define C_008010_ME0PIPE0_CMDFIFO_AVAIL 0xFFFFFFF0
214 #define S_008010_SRBM_RQ_PENDING(x) (((x) & 0x1) << 5)
215 #define G_008010_SRBM_RQ_PENDING(x) (((x) >> 5) & 0x1)
216 #define C_008010_SRBM_RQ_PENDING 0xFFFFFFDF
217 #define S_008010_ME0PIPE0_CF_RQ_PENDING(x) (((x) & 0x1) << 7)
218 #define G_008010_ME0PIPE0_CF_RQ_PENDING(x) (((x) >> 7) & 0x1)
219 #define C_008010_ME0PIPE0_CF_RQ_PENDING 0xFFFFFF7F
220 #define S_008010_ME0PIPE0_PF_RQ_PENDING(x) (((x) & 0x1) << 8)
221 #define G_008010_ME0PIPE0_PF_RQ_PENDING(x) (((x) >> 8) & 0x1)
222 #define C_008010_ME0PIPE0_PF_RQ_PENDING 0xFFFFFEFF
223 #define S_008010_GDS_DMA_RQ_PENDING(x) (((x) & 0x1) << 9)
224 #define G_008010_GDS_DMA_RQ_PENDING(x) (((x) >> 9) & 0x1)
225 #define C_008010_GDS_DMA_RQ_PENDING 0xFFFFFDFF
226 #define S_008010_DB_CLEAN(x) (((x) & 0x1) << 12)
227 #define G_008010_DB_CLEAN(x) (((x) >> 12) & 0x1)
228 #define C_008010_DB_CLEAN 0xFFFFEFFF
229 #define S_008010_CB_CLEAN(x) (((x) & 0x1) << 13)
230 #define G_008010_CB_CLEAN(x) (((x) >> 13) & 0x1)
231 #define C_008010_CB_CLEAN 0xFFFFDFFF
232 #define S_008010_TA_BUSY(x) (((x) & 0x1) << 14)
233 #define G_008010_TA_BUSY(x) (((x) >> 14) & 0x1)
234 #define C_008010_TA_BUSY 0xFFFFBFFF
235 #define S_008010_GDS_BUSY(x) (((x) & 0x1) << 15)
236 #define G_008010_GDS_BUSY(x) (((x) >> 15) & 0x1)
237 #define C_008010_GDS_BUSY 0xFFFF7FFF
238 #define S_008010_WD_BUSY_NO_DMA(x) (((x) & 0x1) << 16)
239 #define G_008010_WD_BUSY_NO_DMA(x) (((x) >> 16) & 0x1)
240 #define C_008010_WD_BUSY_NO_DMA 0xFFFEFFFF
241 #define S_008010_VGT_BUSY(x) (((x) & 0x1) << 17)
242 #define G_008010_VGT_BUSY(x) (((x) >> 17) & 0x1)
243 #define C_008010_VGT_BUSY 0xFFFDFFFF
244 #define S_008010_IA_BUSY_NO_DMA(x) (((x) & 0x1) << 18)
245 #define G_008010_IA_BUSY_NO_DMA(x) (((x) >> 18) & 0x1)
246 #define C_008010_IA_BUSY_NO_DMA 0xFFFBFFFF
247 #define S_008010_IA_BUSY(x) (((x) & 0x1) << 19)
248 #define G_008010_IA_BUSY(x) (((x) >> 19) & 0x1)
249 #define C_008010_IA_BUSY 0xFFF7FFFF
250 #define S_008010_SX_BUSY(x) (((x) & 0x1) << 20)
251 #define G_008010_SX_BUSY(x) (((x) >> 20) & 0x1)
252 #define C_008010_SX_BUSY 0xFFEFFFFF
253 #define S_008010_WD_BUSY(x) (((x) & 0x1) << 21)
254 #define G_008010_WD_BUSY(x) (((x) >> 21) & 0x1)
255 #define C_008010_WD_BUSY 0xFFDFFFFF
256 #define S_008010_SPI_BUSY(x) (((x) & 0x1) << 22)
257 #define G_008010_SPI_BUSY(x) (((x) >> 22) & 0x1)
258 #define C_008010_SPI_BUSY 0xFFBFFFFF
259 #define S_008010_BCI_BUSY(x) (((x) & 0x1) << 23)
260 #define G_008010_BCI_BUSY(x) (((x) >> 23) & 0x1)
261 #define C_008010_BCI_BUSY 0xFF7FFFFF
262 #define S_008010_SC_BUSY(x) (((x) & 0x1) << 24)
263 #define G_008010_SC_BUSY(x) (((x) >> 24) & 0x1)
264 #define C_008010_SC_BUSY 0xFEFFFFFF
265 #define S_008010_PA_BUSY(x) (((x) & 0x1) << 25)
266 #define G_008010_PA_BUSY(x) (((x) >> 25) & 0x1)
267 #define C_008010_PA_BUSY 0xFDFFFFFF
268 #define S_008010_DB_BUSY(x) (((x) & 0x1) << 26)
269 #define G_008010_DB_BUSY(x) (((x) >> 26) & 0x1)
270 #define C_008010_DB_BUSY 0xFBFFFFFF
271 #define S_008010_CP_COHERENCY_BUSY(x) (((x) & 0x1) << 28)
272 #define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 0x1)
273 #define C_008010_CP_COHERENCY_BUSY 0xEFFFFFFF
274 #define S_008010_CP_BUSY(x) (((x) & 0x1) << 29)
275 #define G_008010_CP_BUSY(x) (((x) >> 29) & 0x1)
276 #define C_008010_CP_BUSY 0xDFFFFFFF
277 #define S_008010_CB_BUSY(x) (((x) & 0x1) << 30)
278 #define G_008010_CB_BUSY(x) (((x) >> 30) & 0x1)
279 #define C_008010_CB_BUSY 0xBFFFFFFF
280 #define S_008010_GUI_ACTIVE(x) (((x) & 0x1) << 31)
281 #define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
282 #define C_008010_GUI_ACTIVE 0x7FFFFFFF
283 #define GRBM_GFX_INDEX 0x802C
284 #define INSTANCE_INDEX(x) ((x) << 0)
285 #define SH_INDEX(x) ((x) << 8)
286 #define SE_INDEX(x) ((x) << 16)
287 #define SH_BROADCAST_WRITES (1 << 29)
288 #define INSTANCE_BROADCAST_WRITES (1 << 30)
289 #define SE_BROADCAST_WRITES (1 << 31)
290 #define R_0084FC_CP_STRMOUT_CNTL 0x0084FC
291 #define S_0084FC_OFFSET_UPDATE_DONE(x) (((x) & 0x1) << 0)
292 #define R_0085F0_CP_COHER_CNTL 0x0085F0
293 #define S_0085F0_DEST_BASE_0_ENA(x) (((x) & 0x1) << 0)
294 #define G_0085F0_DEST_BASE_0_ENA(x) (((x) >> 0) & 0x1)
295 #define C_0085F0_DEST_BASE_0_ENA 0xFFFFFFFE
296 #define S_0085F0_DEST_BASE_1_ENA(x) (((x) & 0x1) << 1)
297 #define G_0085F0_DEST_BASE_1_ENA(x) (((x) >> 1) & 0x1)
298 #define C_0085F0_DEST_BASE_1_ENA 0xFFFFFFFD
299 #define S_0085F0_CB0_DEST_BASE_ENA_SHIFT 6
300 #define S_0085F0_CB0_DEST_BASE_ENA(x) (((x) & 0x1) << 6)
301 #define G_0085F0_CB0_DEST_BASE_ENA(x) (((x) >> 6) & 0x1)
302 #define C_0085F0_CB0_DEST_BASE_ENA 0xFFFFFFBF
303 #define S_0085F0_CB1_DEST_BASE_ENA(x) (((x) & 0x1) << 7)
304 #define G_0085F0_CB1_DEST_BASE_ENA(x) (((x) >> 7) & 0x1)
305 #define C_0085F0_CB1_DEST_BASE_ENA 0xFFFFFF7F
306 #define S_0085F0_CB2_DEST_BASE_ENA(x) (((x) & 0x1) << 8)
307 #define G_0085F0_CB2_DEST_BASE_ENA(x) (((x) >> 8) & 0x1)
308 #define C_0085F0_CB2_DEST_BASE_ENA 0xFFFFFEFF
309 #define S_0085F0_CB3_DEST_BASE_ENA(x) (((x) & 0x1) << 9)
310 #define G_0085F0_CB3_DEST_BASE_ENA(x) (((x) >> 9) & 0x1)
311 #define C_0085F0_CB3_DEST_BASE_ENA 0xFFFFFDFF
312 #define S_0085F0_CB4_DEST_BASE_ENA(x) (((x) & 0x1) << 10)
313 #define G_0085F0_CB4_DEST_BASE_ENA(x) (((x) >> 10) & 0x1)
314 #define C_0085F0_CB4_DEST_BASE_ENA 0xFFFFFBFF
315 #define S_0085F0_CB5_DEST_BASE_ENA(x) (((x) & 0x1) << 11)
316 #define G_0085F0_CB5_DEST_BASE_ENA(x) (((x) >> 11) & 0x1)
317 #define C_0085F0_CB5_DEST_BASE_ENA 0xFFFFF7FF
318 #define S_0085F0_CB6_DEST_BASE_ENA(x) (((x) & 0x1) << 12)
319 #define G_0085F0_CB6_DEST_BASE_ENA(x) (((x) >> 12) & 0x1)
320 #define C_0085F0_CB6_DEST_BASE_ENA 0xFFFFEFFF
321 #define S_0085F0_CB7_DEST_BASE_ENA(x) (((x) & 0x1) << 13)
322 #define G_0085F0_CB7_DEST_BASE_ENA(x) (((x) >> 13) & 0x1)
323 #define C_0085F0_CB7_DEST_BASE_ENA 0xFFFFDFFF
324 #define S_0085F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14)
325 #define G_0085F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1)
326 #define C_0085F0_DB_DEST_BASE_ENA 0xFFFFBFFF
327 #define S_0085F0_DEST_BASE_2_ENA(x) (((x) & 0x1) << 19)
328 #define G_0085F0_DEST_BASE_2_ENA(x) (((x) >> 19) & 0x1)
329 #define C_0085F0_DEST_BASE_2_ENA 0xFFF7FFFF
330 #define S_0085F0_DEST_BASE_3_ENA(x) (((x) & 0x1) << 21)
331 #define G_0085F0_DEST_BASE_3_ENA(x) (((x) >> 21) & 0x1)
332 #define C_0085F0_DEST_BASE_3_ENA 0xFFDFFFFF
333 #define S_0085F0_TCL1_ACTION_ENA(x) (((x) & 0x1) << 22)
334 #define G_0085F0_TCL1_ACTION_ENA(x) (((x) >> 22) & 0x1)
335 #define C_0085F0_TCL1_ACTION_ENA 0xFFBFFFFF
336 #define S_0085F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23)
337 #define G_0085F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1)
338 #define C_0085F0_TC_ACTION_ENA 0xFF7FFFFF
339 #define S_0085F0_CB_ACTION_ENA(x) (((x) & 0x1) << 25)
340 #define G_0085F0_CB_ACTION_ENA(x) (((x) >> 25) & 0x1)
341 #define C_0085F0_CB_ACTION_ENA 0xFDFFFFFF
342 #define S_0085F0_DB_ACTION_ENA(x) (((x) & 0x1) << 26)
343 #define G_0085F0_DB_ACTION_ENA(x) (((x) >> 26) & 0x1)
344 #define C_0085F0_DB_ACTION_ENA 0xFBFFFFFF
345 #define S_0085F0_SH_KCACHE_ACTION_ENA(x) (((x) & 0x1) << 27)
346 #define G_0085F0_SH_KCACHE_ACTION_ENA(x) (((x) >> 27) & 0x1)
347 #define C_0085F0_SH_KCACHE_ACTION_ENA 0xF7FFFFFF
348 #define S_0085F0_SH_ICACHE_ACTION_ENA(x) (((x) & 0x1) << 29)
349 #define G_0085F0_SH_ICACHE_ACTION_ENA(x) (((x) >> 29) & 0x1)
350 #define C_0085F0_SH_ICACHE_ACTION_ENA 0xDFFFFFFF
351 #define R_0085F4_CP_COHER_SIZE 0x0085F4
352 #define R_0085F8_CP_COHER_BASE 0x0085F8
353
354 /* CIK */
355 #define R_0300FC_CP_STRMOUT_CNTL 0x0300FC
356 #define S_0300FC_OFFSET_UPDATE_DONE(x) (((x) & 0x1) << 0)
357 #define G_0300FC_OFFSET_UPDATE_DONE(x) (((x) >> 0) & 0x1)
358 #define C_0300FC_OFFSET_UPDATE_DONE 0xFFFFFFFE
359 #define R_0301E4_CP_COHER_BASE_HI 0x0301E4
360 #define S_0301E4_COHER_BASE_HI_256B(x) (((x) & 0xFF) << 0)
361 #define G_0301E4_COHER_BASE_HI_256B(x) (((x) >> 0) & 0xFF)
362 #define C_0301E4_COHER_BASE_HI_256B 0xFFFFFF00
363 #define R_0301EC_CP_COHER_START_DELAY 0x0301EC
364 #define S_0301EC_START_DELAY_COUNT(x) (((x) & 0x3F) << 0)
365 #define G_0301EC_START_DELAY_COUNT(x) (((x) >> 0) & 0x3F)
366 #define C_0301EC_START_DELAY_COUNT 0xFFFFFFC0
367 #define R_0301F0_CP_COHER_CNTL 0x0301F0
368 #define S_0301F0_DEST_BASE_0_ENA(x) (((x) & 0x1) << 0)
369 #define G_0301F0_DEST_BASE_0_ENA(x) (((x) >> 0) & 0x1)
370 #define C_0301F0_DEST_BASE_0_ENA 0xFFFFFFFE
371 #define S_0301F0_DEST_BASE_1_ENA(x) (((x) & 0x1) << 1)
372 #define G_0301F0_DEST_BASE_1_ENA(x) (((x) >> 1) & 0x1)
373 #define C_0301F0_DEST_BASE_1_ENA 0xFFFFFFFD
374 /* VI */
375 #define S_0301F0_TC_SD_ACTION_ENA(x) (((x) & 0x1) << 2)
376 #define G_0301F0_TC_SD_ACTION_ENA(x) (((x) >> 2) & 0x1)
377 #define C_0301F0_TC_SD_ACTION_ENA 0xFFFFFFFB
378 #define S_0301F0_TC_NC_ACTION_ENA(x) (((x) & 0x1) << 3)
379 #define G_0301F0_TC_NC_ACTION_ENA(x) (((x) >> 3) & 0x1)
380 #define C_0301F0_TC_NC_ACTION_ENA 0xFFFFFFF7
381 /* */
382 #define S_0301F0_CB0_DEST_BASE_ENA(x) (((x) & 0x1) << 6)
383 #define G_0301F0_CB0_DEST_BASE_ENA(x) (((x) >> 6) & 0x1)
384 #define C_0301F0_CB0_DEST_BASE_ENA 0xFFFFFFBF
385 #define S_0301F0_CB1_DEST_BASE_ENA(x) (((x) & 0x1) << 7)
386 #define G_0301F0_CB1_DEST_BASE_ENA(x) (((x) >> 7) & 0x1)
387 #define C_0301F0_CB1_DEST_BASE_ENA 0xFFFFFF7F
388 #define S_0301F0_CB2_DEST_BASE_ENA(x) (((x) & 0x1) << 8)
389 #define G_0301F0_CB2_DEST_BASE_ENA(x) (((x) >> 8) & 0x1)
390 #define C_0301F0_CB2_DEST_BASE_ENA 0xFFFFFEFF
391 #define S_0301F0_CB3_DEST_BASE_ENA(x) (((x) & 0x1) << 9)
392 #define G_0301F0_CB3_DEST_BASE_ENA(x) (((x) >> 9) & 0x1)
393 #define C_0301F0_CB3_DEST_BASE_ENA 0xFFFFFDFF
394 #define S_0301F0_CB4_DEST_BASE_ENA(x) (((x) & 0x1) << 10)
395 #define G_0301F0_CB4_DEST_BASE_ENA(x) (((x) >> 10) & 0x1)
396 #define C_0301F0_CB4_DEST_BASE_ENA 0xFFFFFBFF
397 #define S_0301F0_CB5_DEST_BASE_ENA(x) (((x) & 0x1) << 11)
398 #define G_0301F0_CB5_DEST_BASE_ENA(x) (((x) >> 11) & 0x1)
399 #define C_0301F0_CB5_DEST_BASE_ENA 0xFFFFF7FF
400 #define S_0301F0_CB6_DEST_BASE_ENA(x) (((x) & 0x1) << 12)
401 #define G_0301F0_CB6_DEST_BASE_ENA(x) (((x) >> 12) & 0x1)
402 #define C_0301F0_CB6_DEST_BASE_ENA 0xFFFFEFFF
403 #define S_0301F0_CB7_DEST_BASE_ENA(x) (((x) & 0x1) << 13)
404 #define G_0301F0_CB7_DEST_BASE_ENA(x) (((x) >> 13) & 0x1)
405 #define C_0301F0_CB7_DEST_BASE_ENA 0xFFFFDFFF
406 #define S_0301F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14)
407 #define G_0301F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1)
408 #define C_0301F0_DB_DEST_BASE_ENA 0xFFFFBFFF
409 #define S_0301F0_TCL1_VOL_ACTION_ENA(x) (((x) & 0x1) << 15)
410 #define G_0301F0_TCL1_VOL_ACTION_ENA(x) (((x) >> 15) & 0x1)
411 #define C_0301F0_TCL1_VOL_ACTION_ENA 0xFFFF7FFF
412 #define S_0301F0_TC_VOL_ACTION_ENA(x) (((x) & 0x1) << 16) /* not on VI */
413 #define G_0301F0_TC_VOL_ACTION_ENA(x) (((x) >> 16) & 0x1)
414 #define C_0301F0_TC_VOL_ACTION_ENA 0xFFFEFFFF
415 #define S_0301F0_TC_WB_ACTION_ENA(x) (((x) & 0x1) << 18)
416 #define G_0301F0_TC_WB_ACTION_ENA(x) (((x) >> 18) & 0x1)
417 #define C_0301F0_TC_WB_ACTION_ENA 0xFFFBFFFF
418 #define S_0301F0_DEST_BASE_2_ENA(x) (((x) & 0x1) << 19)
419 #define G_0301F0_DEST_BASE_2_ENA(x) (((x) >> 19) & 0x1)
420 #define C_0301F0_DEST_BASE_2_ENA 0xFFF7FFFF
421 #define S_0301F0_DEST_BASE_3_ENA(x) (((x) & 0x1) << 21)
422 #define G_0301F0_DEST_BASE_3_ENA(x) (((x) >> 21) & 0x1)
423 #define C_0301F0_DEST_BASE_3_ENA 0xFFDFFFFF
424 #define S_0301F0_TCL1_ACTION_ENA(x) (((x) & 0x1) << 22)
425 #define G_0301F0_TCL1_ACTION_ENA(x) (((x) >> 22) & 0x1)
426 #define C_0301F0_TCL1_ACTION_ENA 0xFFBFFFFF
427 #define S_0301F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23)
428 #define G_0301F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1)
429 #define C_0301F0_TC_ACTION_ENA 0xFF7FFFFF
430 #define S_0301F0_CB_ACTION_ENA(x) (((x) & 0x1) << 25)
431 #define G_0301F0_CB_ACTION_ENA(x) (((x) >> 25) & 0x1)
432 #define C_0301F0_CB_ACTION_ENA 0xFDFFFFFF
433 #define S_0301F0_DB_ACTION_ENA(x) (((x) & 0x1) << 26)
434 #define G_0301F0_DB_ACTION_ENA(x) (((x) >> 26) & 0x1)
435 #define C_0301F0_DB_ACTION_ENA 0xFBFFFFFF
436 #define S_0301F0_SH_KCACHE_ACTION_ENA(x) (((x) & 0x1) << 27)
437 #define G_0301F0_SH_KCACHE_ACTION_ENA(x) (((x) >> 27) & 0x1)
438 #define C_0301F0_SH_KCACHE_ACTION_ENA 0xF7FFFFFF
439 #define S_0301F0_SH_KCACHE_VOL_ACTION_ENA(x) (((x) & 0x1) << 28)
440 #define G_0301F0_SH_KCACHE_VOL_ACTION_ENA(x) (((x) >> 28) & 0x1)
441 #define C_0301F0_SH_KCACHE_VOL_ACTION_ENA 0xEFFFFFFF
442 #define S_0301F0_SH_ICACHE_ACTION_ENA(x) (((x) & 0x1) << 29)
443 #define G_0301F0_SH_ICACHE_ACTION_ENA(x) (((x) >> 29) & 0x1)
444 #define C_0301F0_SH_ICACHE_ACTION_ENA 0xDFFFFFFF
445 /* VI */
446 #define S_0301F0_SH_KCACHE_WB_ACTION_ENA(x) (((x) & 0x1) << 30)
447 #define G_0301F0_SH_KCACHE_WB_ACTION_ENA(x) (((x) >> 30) & 0x1)
448 #define C_0301F0_SH_KCACHE_WB_ACTION_ENA 0xBFFFFFFF
449 #define S_0301F0_SH_SD_ACTION_ENA(x) (((x) & 0x1) << 31)
450 #define G_0301F0_SH_SD_ACTION_ENA(x) (((x) >> 31) & 0x1)
451 #define C_0301F0_SH_SD_ACTION_ENA 0x7FFFFFFF
452 /* */
453 #define R_0301F4_CP_COHER_SIZE 0x0301F4
454 #define R_0301F8_CP_COHER_BASE 0x0301F8
455 #define R_0301FC_CP_COHER_STATUS 0x0301FC
456 #define S_0301FC_MATCHING_GFX_CNTX(x) (((x) & 0xFF) << 0)
457 #define G_0301FC_MATCHING_GFX_CNTX(x) (((x) >> 0) & 0xFF)
458 #define C_0301FC_MATCHING_GFX_CNTX 0xFFFFFF00
459 #define S_0301FC_MEID(x) (((x) & 0x03) << 24)
460 #define G_0301FC_MEID(x) (((x) >> 24) & 0x03)
461 #define C_0301FC_MEID 0xFCFFFFFF
462 #define S_0301FC_PHASE1_STATUS(x) (((x) & 0x1) << 30)
463 #define G_0301FC_PHASE1_STATUS(x) (((x) >> 30) & 0x1)
464 #define C_0301FC_PHASE1_STATUS 0xBFFFFFFF
465 #define S_0301FC_STATUS(x) (((x) & 0x1) << 31)
466 #define G_0301FC_STATUS(x) (((x) >> 31) & 0x1)
467 #define C_0301FC_STATUS 0x7FFFFFFF
468 #define R_030230_CP_COHER_SIZE_HI 0x030230
469 #define S_030230_COHER_SIZE_HI_256B(x) (((x) & 0xFF) << 0)
470 #define G_030230_COHER_SIZE_HI_256B(x) (((x) >> 0) & 0xFF)
471 #define C_030230_COHER_SIZE_HI_256B 0xFFFFFF00
472 /* */
473 #define R_0088B0_VGT_VTX_VECT_EJECT_REG 0x0088B0
474 #define S_0088B0_PRIM_COUNT(x) (((x) & 0x3FF) << 0)
475 #define G_0088B0_PRIM_COUNT(x) (((x) >> 0) & 0x3FF)
476 #define C_0088B0_PRIM_COUNT 0xFFFFFC00
477 #define R_0088C4_VGT_CACHE_INVALIDATION 0x0088C4
478 #define S_0088C4_VS_NO_EXTRA_BUFFER(x) (((x) & 0x1) << 5)
479 #define G_0088C4_VS_NO_EXTRA_BUFFER(x) (((x) >> 5) & 0x1)
480 #define C_0088C4_VS_NO_EXTRA_BUFFER 0xFFFFFFDF
481 #define S_0088C4_STREAMOUT_FULL_FLUSH(x) (((x) & 0x1) << 13)
482 #define G_0088C4_STREAMOUT_FULL_FLUSH(x) (((x) >> 13) & 0x1)
483 #define C_0088C4_STREAMOUT_FULL_FLUSH 0xFFFFDFFF
484 #define S_0088C4_ES_LIMIT(x) (((x) & 0x1F) << 16)
485 #define G_0088C4_ES_LIMIT(x) (((x) >> 16) & 0x1F)
486 #define C_0088C4_ES_LIMIT 0xFFE0FFFF
487 #define R_0088C8_VGT_ESGS_RING_SIZE 0x0088C8
488 #define R_0088CC_VGT_GSVS_RING_SIZE 0x0088CC
489 #define R_0088D4_VGT_GS_VERTEX_REUSE 0x0088D4
490 #define S_0088D4_VERT_REUSE(x) (((x) & 0x1F) << 0)
491 #define G_0088D4_VERT_REUSE(x) (((x) >> 0) & 0x1F)
492 #define C_0088D4_VERT_REUSE 0xFFFFFFE0
493 #define R_008958_VGT_PRIMITIVE_TYPE 0x008958
494 #define S_008958_PRIM_TYPE(x) (((x) & 0x3F) << 0)
495 #define G_008958_PRIM_TYPE(x) (((x) >> 0) & 0x3F)
496 #define C_008958_PRIM_TYPE 0xFFFFFFC0
497 #define V_008958_DI_PT_NONE 0x00
498 #define V_008958_DI_PT_POINTLIST 0x01
499 #define V_008958_DI_PT_LINELIST 0x02
500 #define V_008958_DI_PT_LINESTRIP 0x03
501 #define V_008958_DI_PT_TRILIST 0x04
502 #define V_008958_DI_PT_TRIFAN 0x05
503 #define V_008958_DI_PT_TRISTRIP 0x06
504 #define V_008958_DI_PT_UNUSED_0 0x07
505 #define V_008958_DI_PT_UNUSED_1 0x08
506 #define V_008958_DI_PT_PATCH 0x09
507 #define V_008958_DI_PT_LINELIST_ADJ 0x0A
508 #define V_008958_DI_PT_LINESTRIP_ADJ 0x0B
509 #define V_008958_DI_PT_TRILIST_ADJ 0x0C
510 #define V_008958_DI_PT_TRISTRIP_ADJ 0x0D
511 #define V_008958_DI_PT_UNUSED_3 0x0E
512 #define V_008958_DI_PT_UNUSED_4 0x0F
513 #define V_008958_DI_PT_TRI_WITH_WFLAGS 0x10
514 #define V_008958_DI_PT_RECTLIST 0x11
515 #define V_008958_DI_PT_LINELOOP 0x12
516 #define V_008958_DI_PT_QUADLIST 0x13
517 #define V_008958_DI_PT_QUADSTRIP 0x14
518 #define V_008958_DI_PT_POLYGON 0x15
519 #define V_008958_DI_PT_2D_COPY_RECT_LIST_V0 0x16
520 #define V_008958_DI_PT_2D_COPY_RECT_LIST_V1 0x17
521 #define V_008958_DI_PT_2D_COPY_RECT_LIST_V2 0x18
522 #define V_008958_DI_PT_2D_COPY_RECT_LIST_V3 0x19
523 #define V_008958_DI_PT_2D_FILL_RECT_LIST 0x1A
524 #define V_008958_DI_PT_2D_LINE_STRIP 0x1B
525 #define V_008958_DI_PT_2D_TRI_STRIP 0x1C
526 #define R_00895C_VGT_INDEX_TYPE 0x00895C
527 #define S_00895C_INDEX_TYPE(x) (((x) & 0x03) << 0)
528 #define G_00895C_INDEX_TYPE(x) (((x) >> 0) & 0x03)
529 #define C_00895C_INDEX_TYPE 0xFFFFFFFC
530 #define V_00895C_DI_INDEX_SIZE_16_BIT 0x00
531 #define V_00895C_DI_INDEX_SIZE_32_BIT 0x01
532 #define R_008960_VGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x008960
533 #define R_008964_VGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x008964
534 #define R_008968_VGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x008968
535 #define R_00896C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x00896C
536 #define R_008970_VGT_NUM_INDICES 0x008970
537 #define R_008974_VGT_NUM_INSTANCES 0x008974
538 #define R_008988_VGT_TF_RING_SIZE 0x008988
539 #define S_008988_SIZE(x) (((x) & 0xFFFF) << 0)
540 #define G_008988_SIZE(x) (((x) >> 0) & 0xFFFF)
541 #define C_008988_SIZE 0xFFFF0000
542 #define R_0089B0_VGT_HS_OFFCHIP_PARAM 0x0089B0
543 #define S_0089B0_OFFCHIP_BUFFERING(x) (((x) & 0x7F) << 0)
544 #define G_0089B0_OFFCHIP_BUFFERING(x) (((x) >> 0) & 0x7F)
545 #define C_0089B0_OFFCHIP_BUFFERING 0xFFFFFF80
546 #define R_0089B8_VGT_TF_MEMORY_BASE 0x0089B8
547 #define R_008A14_PA_CL_ENHANCE 0x008A14
548 #define S_008A14_CLIP_VTX_REORDER_ENA(x) (((x) & 0x1) << 0)
549 #define G_008A14_CLIP_VTX_REORDER_ENA(x) (((x) >> 0) & 0x1)
550 #define C_008A14_CLIP_VTX_REORDER_ENA 0xFFFFFFFE
551 #define S_008A14_NUM_CLIP_SEQ(x) (((x) & 0x03) << 1)
552 #define G_008A14_NUM_CLIP_SEQ(x) (((x) >> 1) & 0x03)
553 #define C_008A14_NUM_CLIP_SEQ 0xFFFFFFF9
554 #define S_008A14_CLIPPED_PRIM_SEQ_STALL(x) (((x) & 0x1) << 3)
555 #define G_008A14_CLIPPED_PRIM_SEQ_STALL(x) (((x) >> 3) & 0x1)
556 #define C_008A14_CLIPPED_PRIM_SEQ_STALL 0xFFFFFFF7
557 #define S_008A14_VE_NAN_PROC_DISABLE(x) (((x) & 0x1) << 4)
558 #define G_008A14_VE_NAN_PROC_DISABLE(x) (((x) >> 4) & 0x1)
559 #define C_008A14_VE_NAN_PROC_DISABLE 0xFFFFFFEF
560 #define R_008A60_PA_SU_LINE_STIPPLE_VALUE 0x008A60
561 #define S_008A60_LINE_STIPPLE_VALUE(x) (((x) & 0xFFFFFF) << 0)
562 #define G_008A60_LINE_STIPPLE_VALUE(x) (((x) >> 0) & 0xFFFFFF)
563 #define C_008A60_LINE_STIPPLE_VALUE 0xFF000000
564 #define R_008B10_PA_SC_LINE_STIPPLE_STATE 0x008B10
565 #define S_008B10_CURRENT_PTR(x) (((x) & 0x0F) << 0)
566 #define G_008B10_CURRENT_PTR(x) (((x) >> 0) & 0x0F)
567 #define C_008B10_CURRENT_PTR 0xFFFFFFF0
568 #define S_008B10_CURRENT_COUNT(x) (((x) & 0xFF) << 8)
569 #define G_008B10_CURRENT_COUNT(x) (((x) >> 8) & 0xFF)
570 #define C_008B10_CURRENT_COUNT 0xFFFF00FF
571 /* CIK */
572 #define R_030800_GRBM_GFX_INDEX 0x030800
573 #define S_030800_INSTANCE_INDEX(x) (((x) & 0xFF) << 0)
574 #define G_030800_INSTANCE_INDEX(x) (((x) >> 0) & 0xFF)
575 #define C_030800_INSTANCE_INDEX 0xFFFFFF00
576 #define S_030800_SH_INDEX(x) (((x) & 0xFF) << 8)
577 #define G_030800_SH_INDEX(x) (((x) >> 8) & 0xFF)
578 #define C_030800_SH_INDEX 0xFFFF00FF
579 #define S_030800_SE_INDEX(x) (((x) & 0xFF) << 16)
580 #define G_030800_SE_INDEX(x) (((x) >> 16) & 0xFF)
581 #define C_030800_SE_INDEX 0xFF00FFFF
582 #define S_030800_SH_BROADCAST_WRITES(x) (((x) & 0x1) << 29)
583 #define G_030800_SH_BROADCAST_WRITES(x) (((x) >> 29) & 0x1)
584 #define C_030800_SH_BROADCAST_WRITES 0xDFFFFFFF
585 #define S_030800_INSTANCE_BROADCAST_WRITES(x) (((x) & 0x1) << 30)
586 #define G_030800_INSTANCE_BROADCAST_WRITES(x) (((x) >> 30) & 0x1)
587 #define C_030800_INSTANCE_BROADCAST_WRITES 0xBFFFFFFF
588 #define S_030800_SE_BROADCAST_WRITES(x) (((x) & 0x1) << 31)
589 #define G_030800_SE_BROADCAST_WRITES(x) (((x) >> 31) & 0x1)
590 #define C_030800_SE_BROADCAST_WRITES 0x7FFFFFFF
591 #define R_030900_VGT_ESGS_RING_SIZE 0x030900
592 #define R_030904_VGT_GSVS_RING_SIZE 0x030904
593 #define R_030908_VGT_PRIMITIVE_TYPE 0x030908
594 #define S_030908_PRIM_TYPE(x) (((x) & 0x3F) << 0)
595 #define G_030908_PRIM_TYPE(x) (((x) >> 0) & 0x3F)
596 #define C_030908_PRIM_TYPE 0xFFFFFFC0
597 #define V_030908_DI_PT_NONE 0x00
598 #define V_030908_DI_PT_POINTLIST 0x01
599 #define V_030908_DI_PT_LINELIST 0x02
600 #define V_030908_DI_PT_LINESTRIP 0x03
601 #define V_030908_DI_PT_TRILIST 0x04
602 #define V_030908_DI_PT_TRIFAN 0x05
603 #define V_030908_DI_PT_TRISTRIP 0x06
604 #define V_030908_DI_PT_PATCH 0x09
605 #define V_030908_DI_PT_LINELIST_ADJ 0x0A
606 #define V_030908_DI_PT_LINESTRIP_ADJ 0x0B
607 #define V_030908_DI_PT_TRILIST_ADJ 0x0C
608 #define V_030908_DI_PT_TRISTRIP_ADJ 0x0D
609 #define V_030908_DI_PT_TRI_WITH_WFLAGS 0x10
610 #define V_030908_DI_PT_RECTLIST 0x11
611 #define V_030908_DI_PT_LINELOOP 0x12
612 #define V_030908_DI_PT_QUADLIST 0x13
613 #define V_030908_DI_PT_QUADSTRIP 0x14
614 #define V_030908_DI_PT_POLYGON 0x15
615 #define V_030908_DI_PT_2D_COPY_RECT_LIST_V0 0x16
616 #define V_030908_DI_PT_2D_COPY_RECT_LIST_V1 0x17
617 #define V_030908_DI_PT_2D_COPY_RECT_LIST_V2 0x18
618 #define V_030908_DI_PT_2D_COPY_RECT_LIST_V3 0x19
619 #define V_030908_DI_PT_2D_FILL_RECT_LIST 0x1A
620 #define V_030908_DI_PT_2D_LINE_STRIP 0x1B
621 #define V_030908_DI_PT_2D_TRI_STRIP 0x1C
622 #define R_03090C_VGT_INDEX_TYPE 0x03090C
623 #define S_03090C_INDEX_TYPE(x) (((x) & 0x03) << 0)
624 #define G_03090C_INDEX_TYPE(x) (((x) >> 0) & 0x03)
625 #define C_03090C_INDEX_TYPE 0xFFFFFFFC
626 #define V_03090C_DI_INDEX_SIZE_16_BIT 0x00
627 #define V_03090C_DI_INDEX_SIZE_32_BIT 0x01
628 #define R_030910_VGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x030910
629 #define R_030914_VGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x030914
630 #define R_030918_VGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x030918
631 #define R_03091C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x03091C
632 #define R_030930_VGT_NUM_INDICES 0x030930
633 #define R_030934_VGT_NUM_INSTANCES 0x030934
634 #define R_030938_VGT_TF_RING_SIZE 0x030938
635 #define S_030938_SIZE(x) (((x) & 0xFFFF) << 0)
636 #define G_030938_SIZE(x) (((x) >> 0) & 0xFFFF)
637 #define C_030938_SIZE 0xFFFF0000
638 #define R_03093C_VGT_HS_OFFCHIP_PARAM 0x03093C
639 #define S_03093C_OFFCHIP_BUFFERING(x) (((x) & 0x1FF) << 0)
640 #define G_03093C_OFFCHIP_BUFFERING(x) (((x) >> 0) & 0x1FF)
641 #define C_03093C_OFFCHIP_BUFFERING 0xFFFFFE00
642 #define S_03093C_OFFCHIP_GRANULARITY(x) (((x) & 0x03) << 9)
643 #define G_03093C_OFFCHIP_GRANULARITY(x) (((x) >> 9) & 0x03)
644 #define C_03093C_OFFCHIP_GRANULARITY 0xFFFFF9FF
645 #define V_03093C_X_8K_DWORDS 0x00
646 #define V_03093C_X_4K_DWORDS 0x01
647 #define V_03093C_X_2K_DWORDS 0x02
648 #define V_03093C_X_1K_DWORDS 0x03
649 #define R_030940_VGT_TF_MEMORY_BASE 0x030940
650 #define R_030A00_PA_SU_LINE_STIPPLE_VALUE 0x030A00
651 #define S_030A00_LINE_STIPPLE_VALUE(x) (((x) & 0xFFFFFF) << 0)
652 #define G_030A00_LINE_STIPPLE_VALUE(x) (((x) >> 0) & 0xFFFFFF)
653 #define C_030A00_LINE_STIPPLE_VALUE 0xFF000000
654 #define R_030A04_PA_SC_LINE_STIPPLE_STATE 0x030A04
655 #define S_030A04_CURRENT_PTR(x) (((x) & 0x0F) << 0)
656 #define G_030A04_CURRENT_PTR(x) (((x) >> 0) & 0x0F)
657 #define C_030A04_CURRENT_PTR 0xFFFFFFF0
658 #define S_030A04_CURRENT_COUNT(x) (((x) & 0xFF) << 8)
659 #define G_030A04_CURRENT_COUNT(x) (((x) >> 8) & 0xFF)
660 #define C_030A04_CURRENT_COUNT 0xFFFF00FF
661 #define R_030A10_PA_SC_SCREEN_EXTENT_MIN_0 0x030A10
662 #define S_030A10_X(x) (((x) & 0xFFFF) << 0)
663 #define G_030A10_X(x) (((x) >> 0) & 0xFFFF)
664 #define C_030A10_X 0xFFFF0000
665 #define S_030A10_Y(x) (((x) & 0xFFFF) << 16)
666 #define G_030A10_Y(x) (((x) >> 16) & 0xFFFF)
667 #define C_030A10_Y 0x0000FFFF
668 #define R_030A14_PA_SC_SCREEN_EXTENT_MAX_0 0x030A14
669 #define S_030A14_X(x) (((x) & 0xFFFF) << 0)
670 #define G_030A14_X(x) (((x) >> 0) & 0xFFFF)
671 #define C_030A14_X 0xFFFF0000
672 #define S_030A14_Y(x) (((x) & 0xFFFF) << 16)
673 #define G_030A14_Y(x) (((x) >> 16) & 0xFFFF)
674 #define C_030A14_Y 0x0000FFFF
675 #define R_030A18_PA_SC_SCREEN_EXTENT_MIN_1 0x030A18
676 #define S_030A18_X(x) (((x) & 0xFFFF) << 0)
677 #define G_030A18_X(x) (((x) >> 0) & 0xFFFF)
678 #define C_030A18_X 0xFFFF0000
679 #define S_030A18_Y(x) (((x) & 0xFFFF) << 16)
680 #define G_030A18_Y(x) (((x) >> 16) & 0xFFFF)
681 #define C_030A18_Y 0x0000FFFF
682 #define R_030A2C_PA_SC_SCREEN_EXTENT_MAX_1 0x030A2C
683 #define S_030A2C_X(x) (((x) & 0xFFFF) << 0)
684 #define G_030A2C_X(x) (((x) >> 0) & 0xFFFF)
685 #define C_030A2C_X 0xFFFF0000
686 #define S_030A2C_Y(x) (((x) & 0xFFFF) << 16)
687 #define G_030A2C_Y(x) (((x) >> 16) & 0xFFFF)
688 #define C_030A2C_Y 0x0000FFFF
689 /* */
690 #define R_008BF0_PA_SC_ENHANCE 0x008BF0
691 #define S_008BF0_ENABLE_PA_SC_OUT_OF_ORDER(x) (((x) & 0x1) << 0)
692 #define G_008BF0_ENABLE_PA_SC_OUT_OF_ORDER(x) (((x) >> 0) & 0x1)
693 #define C_008BF0_ENABLE_PA_SC_OUT_OF_ORDER 0xFFFFFFFE
694 #define S_008BF0_DISABLE_SC_DB_TILE_FIX(x) (((x) & 0x1) << 1)
695 #define G_008BF0_DISABLE_SC_DB_TILE_FIX(x) (((x) >> 1) & 0x1)
696 #define C_008BF0_DISABLE_SC_DB_TILE_FIX 0xFFFFFFFD
697 #define S_008BF0_DISABLE_AA_MASK_FULL_FIX(x) (((x) & 0x1) << 2)
698 #define G_008BF0_DISABLE_AA_MASK_FULL_FIX(x) (((x) >> 2) & 0x1)
699 #define C_008BF0_DISABLE_AA_MASK_FULL_FIX 0xFFFFFFFB
700 #define S_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS(x) (((x) & 0x1) << 3)
701 #define G_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS(x) (((x) >> 3) & 0x1)
702 #define C_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS 0xFFFFFFF7
703 #define S_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID(x) (((x) & 0x1) << 4)
704 #define G_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID(x) (((x) >> 4) & 0x1)
705 #define C_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID 0xFFFFFFEF
706 #define S_008BF0_DISABLE_SCISSOR_FIX(x) (((x) & 0x1) << 5)
707 #define G_008BF0_DISABLE_SCISSOR_FIX(x) (((x) >> 5) & 0x1)
708 #define C_008BF0_DISABLE_SCISSOR_FIX 0xFFFFFFDF
709 #define S_008BF0_DISABLE_PW_BUBBLE_COLLAPSE(x) (((x) & 0x03) << 6)
710 #define G_008BF0_DISABLE_PW_BUBBLE_COLLAPSE(x) (((x) >> 6) & 0x03)
711 #define C_008BF0_DISABLE_PW_BUBBLE_COLLAPSE 0xFFFFFF3F
712 #define S_008BF0_SEND_UNLIT_STILES_TO_PACKER(x) (((x) & 0x1) << 8)
713 #define G_008BF0_SEND_UNLIT_STILES_TO_PACKER(x) (((x) >> 8) & 0x1)
714 #define C_008BF0_SEND_UNLIT_STILES_TO_PACKER 0xFFFFFEFF
715 #define S_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION(x) (((x) & 0x1) << 9)
716 #define G_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION(x) (((x) >> 9) & 0x1)
717 #define C_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION 0xFFFFFDFF
718 #define R_008C08_SQC_CACHES 0x008C08
719 #define S_008C08_INST_INVALIDATE(x) (((x) & 0x1) << 0)
720 #define G_008C08_INST_INVALIDATE(x) (((x) >> 0) & 0x1)
721 #define C_008C08_INST_INVALIDATE 0xFFFFFFFE
722 #define S_008C08_DATA_INVALIDATE(x) (((x) & 0x1) << 1)
723 #define G_008C08_DATA_INVALIDATE(x) (((x) >> 1) & 0x1)
724 #define C_008C08_DATA_INVALIDATE 0xFFFFFFFD
725 /* CIK */
726 #define R_030D20_SQC_CACHES 0x030D20
727 #define S_030D20_INST_INVALIDATE(x) (((x) & 0x1) << 0)
728 #define G_030D20_INST_INVALIDATE(x) (((x) >> 0) & 0x1)
729 #define C_030D20_INST_INVALIDATE 0xFFFFFFFE
730 #define S_030D20_DATA_INVALIDATE(x) (((x) & 0x1) << 1)
731 #define G_030D20_DATA_INVALIDATE(x) (((x) >> 1) & 0x1)
732 #define C_030D20_DATA_INVALIDATE 0xFFFFFFFD
733 #define S_030D20_INVALIDATE_VOLATILE(x) (((x) & 0x1) << 2)
734 #define G_030D20_INVALIDATE_VOLATILE(x) (((x) >> 2) & 0x1)
735 #define C_030D20_INVALIDATE_VOLATILE 0xFFFFFFFB
736 /* */
737 #define R_008C0C_SQ_RANDOM_WAVE_PRI 0x008C0C
738 #define S_008C0C_RET(x) (((x) & 0x7F) << 0)
739 #define G_008C0C_RET(x) (((x) >> 0) & 0x7F)
740 #define C_008C0C_RET 0xFFFFFF80
741 #define S_008C0C_RUI(x) (((x) & 0x07) << 7)
742 #define G_008C0C_RUI(x) (((x) >> 7) & 0x07)
743 #define C_008C0C_RUI 0xFFFFFC7F
744 #define S_008C0C_RNG(x) (((x) & 0x7FF) << 10)
745 #define G_008C0C_RNG(x) (((x) >> 10) & 0x7FF)
746 #define C_008C0C_RNG 0xFFE003FF
747 #if 0
748 /* CIK */
749 #define R_008DFC_SQ_FLAT_1 0x008DFC
750 #define S_008DFC_ADDR(x) (((x) & 0xFF) << 0)
751 #define G_008DFC_ADDR(x) (((x) >> 0) & 0xFF)
752 #define C_008DFC_ADDR 0xFFFFFF00
753 #define V_008DFC_SQ_VGPR 0x00
754 #define S_008DFC_DATA(x) (((x) & 0xFF) << 8)
755 #define G_008DFC_DATA(x) (((x) >> 8) & 0xFF)
756 #define C_008DFC_DATA 0xFFFF00FF
757 #define V_008DFC_SQ_VGPR 0x00
758 #define S_008DFC_TFE(x) (((x) & 0x1) << 23)
759 #define G_008DFC_TFE(x) (((x) >> 23) & 0x1)
760 #define C_008DFC_TFE 0xFF7FFFFF
761 #define S_008DFC_VDST(x) (((x) & 0xFF) << 24)
762 #define G_008DFC_VDST(x) (((x) >> 24) & 0xFF)
763 #define C_008DFC_VDST 0x00FFFFFF
764 #define V_008DFC_SQ_VGPR 0x00
765 /* */
766 #define R_008DFC_SQ_INST 0x008DFC
767 #define R_030D20_SQC_CACHES 0x030D20
768 #define S_030D20_TARGET_INST(x) (((x) & 0x1) << 0)
769 #define G_030D20_TARGET_INST(x) (((x) >> 0) & 0x1)
770 #define C_030D20_TARGET_INST 0xFFFFFFFE
771 #define S_030D20_TARGET_DATA(x) (((x) & 0x1) << 1)
772 #define G_030D20_TARGET_DATA(x) (((x) >> 1) & 0x1)
773 #define C_030D20_TARGET_DATA 0xFFFFFFFD
774 #define S_030D20_INVALIDATE(x) (((x) & 0x1) << 2)
775 #define G_030D20_INVALIDATE(x) (((x) >> 2) & 0x1)
776 #define C_030D20_INVALIDATE 0xFFFFFFFB
777 #define S_030D20_WRITEBACK(x) (((x) & 0x1) << 3)
778 #define G_030D20_WRITEBACK(x) (((x) >> 3) & 0x1)
779 #define C_030D20_WRITEBACK 0xFFFFFFF7
780 #define S_030D20_VOL(x) (((x) & 0x1) << 4)
781 #define G_030D20_VOL(x) (((x) >> 4) & 0x1)
782 #define C_030D20_VOL 0xFFFFFFEF
783 #define S_030D20_COMPLETE(x) (((x) & 0x1) << 16)
784 #define G_030D20_COMPLETE(x) (((x) >> 16) & 0x1)
785 #define C_030D20_COMPLETE 0xFFFEFFFF
786 #define R_030D24_SQC_WRITEBACK 0x030D24
787 #define S_030D24_DWB(x) (((x) & 0x1) << 0)
788 #define G_030D24_DWB(x) (((x) >> 0) & 0x1)
789 #define C_030D24_DWB 0xFFFFFFFE
790 #define S_030D24_DIRTY(x) (((x) & 0x1) << 1)
791 #define G_030D24_DIRTY(x) (((x) >> 1) & 0x1)
792 #define C_030D24_DIRTY 0xFFFFFFFD
793 #define R_008DFC_SQ_VOP1 0x008DFC
794 #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0)
795 #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF)
796 #define C_008DFC_SRC0 0xFFFFFE00
797 #define V_008DFC_SQ_SGPR 0x00
798 /* CIK */
799 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
800 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
801 /* */
802 #define V_008DFC_SQ_VCC_LO 0x6A
803 #define V_008DFC_SQ_VCC_HI 0x6B
804 #define V_008DFC_SQ_TBA_LO 0x6C
805 #define V_008DFC_SQ_TBA_HI 0x6D
806 #define V_008DFC_SQ_TMA_LO 0x6E
807 #define V_008DFC_SQ_TMA_HI 0x6F
808 #define V_008DFC_SQ_TTMP0 0x70
809 #define V_008DFC_SQ_TTMP1 0x71
810 #define V_008DFC_SQ_TTMP2 0x72
811 #define V_008DFC_SQ_TTMP3 0x73
812 #define V_008DFC_SQ_TTMP4 0x74
813 #define V_008DFC_SQ_TTMP5 0x75
814 #define V_008DFC_SQ_TTMP6 0x76
815 #define V_008DFC_SQ_TTMP7 0x77
816 #define V_008DFC_SQ_TTMP8 0x78
817 #define V_008DFC_SQ_TTMP9 0x79
818 #define V_008DFC_SQ_TTMP10 0x7A
819 #define V_008DFC_SQ_TTMP11 0x7B
820 #define V_008DFC_SQ_M0 0x7C
821 #define V_008DFC_SQ_EXEC_LO 0x7E
822 #define V_008DFC_SQ_EXEC_HI 0x7F
823 #define V_008DFC_SQ_SRC_0 0x80
824 #define V_008DFC_SQ_SRC_1_INT 0x81
825 #define V_008DFC_SQ_SRC_2_INT 0x82
826 #define V_008DFC_SQ_SRC_3_INT 0x83
827 #define V_008DFC_SQ_SRC_4_INT 0x84
828 #define V_008DFC_SQ_SRC_5_INT 0x85
829 #define V_008DFC_SQ_SRC_6_INT 0x86
830 #define V_008DFC_SQ_SRC_7_INT 0x87
831 #define V_008DFC_SQ_SRC_8_INT 0x88
832 #define V_008DFC_SQ_SRC_9_INT 0x89
833 #define V_008DFC_SQ_SRC_10_INT 0x8A
834 #define V_008DFC_SQ_SRC_11_INT 0x8B
835 #define V_008DFC_SQ_SRC_12_INT 0x8C
836 #define V_008DFC_SQ_SRC_13_INT 0x8D
837 #define V_008DFC_SQ_SRC_14_INT 0x8E
838 #define V_008DFC_SQ_SRC_15_INT 0x8F
839 #define V_008DFC_SQ_SRC_16_INT 0x90
840 #define V_008DFC_SQ_SRC_17_INT 0x91
841 #define V_008DFC_SQ_SRC_18_INT 0x92
842 #define V_008DFC_SQ_SRC_19_INT 0x93
843 #define V_008DFC_SQ_SRC_20_INT 0x94
844 #define V_008DFC_SQ_SRC_21_INT 0x95
845 #define V_008DFC_SQ_SRC_22_INT 0x96
846 #define V_008DFC_SQ_SRC_23_INT 0x97
847 #define V_008DFC_SQ_SRC_24_INT 0x98
848 #define V_008DFC_SQ_SRC_25_INT 0x99
849 #define V_008DFC_SQ_SRC_26_INT 0x9A
850 #define V_008DFC_SQ_SRC_27_INT 0x9B
851 #define V_008DFC_SQ_SRC_28_INT 0x9C
852 #define V_008DFC_SQ_SRC_29_INT 0x9D
853 #define V_008DFC_SQ_SRC_30_INT 0x9E
854 #define V_008DFC_SQ_SRC_31_INT 0x9F
855 #define V_008DFC_SQ_SRC_32_INT 0xA0
856 #define V_008DFC_SQ_SRC_33_INT 0xA1
857 #define V_008DFC_SQ_SRC_34_INT 0xA2
858 #define V_008DFC_SQ_SRC_35_INT 0xA3
859 #define V_008DFC_SQ_SRC_36_INT 0xA4
860 #define V_008DFC_SQ_SRC_37_INT 0xA5
861 #define V_008DFC_SQ_SRC_38_INT 0xA6
862 #define V_008DFC_SQ_SRC_39_INT 0xA7
863 #define V_008DFC_SQ_SRC_40_INT 0xA8
864 #define V_008DFC_SQ_SRC_41_INT 0xA9
865 #define V_008DFC_SQ_SRC_42_INT 0xAA
866 #define V_008DFC_SQ_SRC_43_INT 0xAB
867 #define V_008DFC_SQ_SRC_44_INT 0xAC
868 #define V_008DFC_SQ_SRC_45_INT 0xAD
869 #define V_008DFC_SQ_SRC_46_INT 0xAE
870 #define V_008DFC_SQ_SRC_47_INT 0xAF
871 #define V_008DFC_SQ_SRC_48_INT 0xB0
872 #define V_008DFC_SQ_SRC_49_INT 0xB1
873 #define V_008DFC_SQ_SRC_50_INT 0xB2
874 #define V_008DFC_SQ_SRC_51_INT 0xB3
875 #define V_008DFC_SQ_SRC_52_INT 0xB4
876 #define V_008DFC_SQ_SRC_53_INT 0xB5
877 #define V_008DFC_SQ_SRC_54_INT 0xB6
878 #define V_008DFC_SQ_SRC_55_INT 0xB7
879 #define V_008DFC_SQ_SRC_56_INT 0xB8
880 #define V_008DFC_SQ_SRC_57_INT 0xB9
881 #define V_008DFC_SQ_SRC_58_INT 0xBA
882 #define V_008DFC_SQ_SRC_59_INT 0xBB
883 #define V_008DFC_SQ_SRC_60_INT 0xBC
884 #define V_008DFC_SQ_SRC_61_INT 0xBD
885 #define V_008DFC_SQ_SRC_62_INT 0xBE
886 #define V_008DFC_SQ_SRC_63_INT 0xBF
887 #define V_008DFC_SQ_SRC_64_INT 0xC0
888 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
889 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
890 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
891 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
892 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
893 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
894 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
895 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
896 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
897 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
898 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
899 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
900 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
901 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
902 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
903 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
904 #define V_008DFC_SQ_SRC_0_5 0xF0
905 #define V_008DFC_SQ_SRC_M_0_5 0xF1
906 #define V_008DFC_SQ_SRC_1 0xF2
907 #define V_008DFC_SQ_SRC_M_1 0xF3
908 #define V_008DFC_SQ_SRC_2 0xF4
909 #define V_008DFC_SQ_SRC_M_2 0xF5
910 #define V_008DFC_SQ_SRC_4 0xF6
911 #define V_008DFC_SQ_SRC_M_4 0xF7
912 #define V_008DFC_SQ_SRC_VCCZ 0xFB
913 #define V_008DFC_SQ_SRC_EXECZ 0xFC
914 #define V_008DFC_SQ_SRC_SCC 0xFD
915 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
916 #define V_008DFC_SQ_SRC_VGPR 0x100
917 #define S_008DFC_OP(x) (((x) & 0xFF) << 9)
918 #define G_008DFC_OP(x) (((x) >> 9) & 0xFF)
919 #define C_008DFC_OP 0xFFFE01FF
920 #define V_008DFC_SQ_V_NOP 0x00
921 #define V_008DFC_SQ_V_MOV_B32 0x01
922 #define V_008DFC_SQ_V_READFIRSTLANE_B32 0x02
923 #define V_008DFC_SQ_V_CVT_I32_F64 0x03
924 #define V_008DFC_SQ_V_CVT_F64_I32 0x04
925 #define V_008DFC_SQ_V_CVT_F32_I32 0x05
926 #define V_008DFC_SQ_V_CVT_F32_U32 0x06
927 #define V_008DFC_SQ_V_CVT_U32_F32 0x07
928 #define V_008DFC_SQ_V_CVT_I32_F32 0x08
929 #define V_008DFC_SQ_V_MOV_FED_B32 0x09
930 #define V_008DFC_SQ_V_CVT_F16_F32 0x0A
931 #define V_008DFC_SQ_V_CVT_F32_F16 0x0B
932 #define V_008DFC_SQ_V_CVT_RPI_I32_F32 0x0C
933 #define V_008DFC_SQ_V_CVT_FLR_I32_F32 0x0D
934 #define V_008DFC_SQ_V_CVT_OFF_F32_I4 0x0E
935 #define V_008DFC_SQ_V_CVT_F32_F64 0x0F
936 #define V_008DFC_SQ_V_CVT_F64_F32 0x10
937 #define V_008DFC_SQ_V_CVT_F32_UBYTE0 0x11
938 #define V_008DFC_SQ_V_CVT_F32_UBYTE1 0x12
939 #define V_008DFC_SQ_V_CVT_F32_UBYTE2 0x13
940 #define V_008DFC_SQ_V_CVT_F32_UBYTE3 0x14
941 #define V_008DFC_SQ_V_CVT_U32_F64 0x15
942 #define V_008DFC_SQ_V_CVT_F64_U32 0x16
943 /* CIK */
944 #define V_008DFC_SQ_V_TRUNC_F64 0x17
945 #define V_008DFC_SQ_V_CEIL_F64 0x18
946 #define V_008DFC_SQ_V_RNDNE_F64 0x19
947 #define V_008DFC_SQ_V_FLOOR_F64 0x1A
948 /* */
949 #define V_008DFC_SQ_V_FRACT_F32 0x20
950 #define V_008DFC_SQ_V_TRUNC_F32 0x21
951 #define V_008DFC_SQ_V_CEIL_F32 0x22
952 #define V_008DFC_SQ_V_RNDNE_F32 0x23
953 #define V_008DFC_SQ_V_FLOOR_F32 0x24
954 #define V_008DFC_SQ_V_EXP_F32 0x25
955 #define V_008DFC_SQ_V_LOG_CLAMP_F32 0x26
956 #define V_008DFC_SQ_V_LOG_F32 0x27
957 #define V_008DFC_SQ_V_RCP_CLAMP_F32 0x28
958 #define V_008DFC_SQ_V_RCP_LEGACY_F32 0x29
959 #define V_008DFC_SQ_V_RCP_F32 0x2A
960 #define V_008DFC_SQ_V_RCP_IFLAG_F32 0x2B
961 #define V_008DFC_SQ_V_RSQ_CLAMP_F32 0x2C
962 #define V_008DFC_SQ_V_RSQ_LEGACY_F32 0x2D
963 #define V_008DFC_SQ_V_RSQ_F32 0x2E
964 #define V_008DFC_SQ_V_RCP_F64 0x2F
965 #define V_008DFC_SQ_V_RCP_CLAMP_F64 0x30
966 #define V_008DFC_SQ_V_RSQ_F64 0x31
967 #define V_008DFC_SQ_V_RSQ_CLAMP_F64 0x32
968 #define V_008DFC_SQ_V_SQRT_F32 0x33
969 #define V_008DFC_SQ_V_SQRT_F64 0x34
970 #define V_008DFC_SQ_V_SIN_F32 0x35
971 #define V_008DFC_SQ_V_COS_F32 0x36
972 #define V_008DFC_SQ_V_NOT_B32 0x37
973 #define V_008DFC_SQ_V_BFREV_B32 0x38
974 #define V_008DFC_SQ_V_FFBH_U32 0x39
975 #define V_008DFC_SQ_V_FFBL_B32 0x3A
976 #define V_008DFC_SQ_V_FFBH_I32 0x3B
977 #define V_008DFC_SQ_V_FREXP_EXP_I32_F64 0x3C
978 #define V_008DFC_SQ_V_FREXP_MANT_F64 0x3D
979 #define V_008DFC_SQ_V_FRACT_F64 0x3E
980 #define V_008DFC_SQ_V_FREXP_EXP_I32_F32 0x3F
981 #define V_008DFC_SQ_V_FREXP_MANT_F32 0x40
982 #define V_008DFC_SQ_V_CLREXCP 0x41
983 #define V_008DFC_SQ_V_MOVRELD_B32 0x42
984 #define V_008DFC_SQ_V_MOVRELS_B32 0x43
985 #define V_008DFC_SQ_V_MOVRELSD_B32 0x44
986 /* CIK */
987 #define V_008DFC_SQ_V_LOG_LEGACY_F32 0x45
988 #define V_008DFC_SQ_V_EXP_LEGACY_F32 0x46
989 /* */
990 #define S_008DFC_VDST(x) (((x) & 0xFF) << 17)
991 #define G_008DFC_VDST(x) (((x) >> 17) & 0xFF)
992 #define C_008DFC_VDST 0xFE01FFFF
993 #define V_008DFC_SQ_VGPR 0x00
994 #define S_008DFC_ENCODING(x) (((x) & 0x7F) << 25)
995 #define G_008DFC_ENCODING(x) (((x) >> 25) & 0x7F)
996 #define C_008DFC_ENCODING 0x01FFFFFF
997 #define V_008DFC_SQ_ENC_VOP1_FIELD 0x3F
998 #define R_008DFC_SQ_MIMG_1 0x008DFC
999 #define S_008DFC_VADDR(x) (((x) & 0xFF) << 0)
1000 #define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF)
1001 #define C_008DFC_VADDR 0xFFFFFF00
1002 #define V_008DFC_SQ_VGPR 0x00
1003 #define S_008DFC_VDATA(x) (((x) & 0xFF) << 8)
1004 #define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF)
1005 #define C_008DFC_VDATA 0xFFFF00FF
1006 #define V_008DFC_SQ_VGPR 0x00
1007 #define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16)
1008 #define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F)
1009 #define C_008DFC_SRSRC 0xFFE0FFFF
1010 #define S_008DFC_SSAMP(x) (((x) & 0x1F) << 21)
1011 #define G_008DFC_SSAMP(x) (((x) >> 21) & 0x1F)
1012 #define C_008DFC_SSAMP 0xFC1FFFFF
1013 #define R_008DFC_SQ_VOP3_1 0x008DFC
1014 #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0)
1015 #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF)
1016 #define C_008DFC_SRC0 0xFFFFFE00
1017 #define V_008DFC_SQ_SGPR 0x00
1018 /* CIK */
1019 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
1020 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
1021 /* */
1022 #define V_008DFC_SQ_VCC_LO 0x6A
1023 #define V_008DFC_SQ_VCC_HI 0x6B
1024 #define V_008DFC_SQ_TBA_LO 0x6C
1025 #define V_008DFC_SQ_TBA_HI 0x6D
1026 #define V_008DFC_SQ_TMA_LO 0x6E
1027 #define V_008DFC_SQ_TMA_HI 0x6F
1028 #define V_008DFC_SQ_TTMP0 0x70
1029 #define V_008DFC_SQ_TTMP1 0x71
1030 #define V_008DFC_SQ_TTMP2 0x72
1031 #define V_008DFC_SQ_TTMP3 0x73
1032 #define V_008DFC_SQ_TTMP4 0x74
1033 #define V_008DFC_SQ_TTMP5 0x75
1034 #define V_008DFC_SQ_TTMP6 0x76
1035 #define V_008DFC_SQ_TTMP7 0x77
1036 #define V_008DFC_SQ_TTMP8 0x78
1037 #define V_008DFC_SQ_TTMP9 0x79
1038 #define V_008DFC_SQ_TTMP10 0x7A
1039 #define V_008DFC_SQ_TTMP11 0x7B
1040 #define V_008DFC_SQ_M0 0x7C
1041 #define V_008DFC_SQ_EXEC_LO 0x7E
1042 #define V_008DFC_SQ_EXEC_HI 0x7F
1043 #define V_008DFC_SQ_SRC_0 0x80
1044 #define V_008DFC_SQ_SRC_1_INT 0x81
1045 #define V_008DFC_SQ_SRC_2_INT 0x82
1046 #define V_008DFC_SQ_SRC_3_INT 0x83
1047 #define V_008DFC_SQ_SRC_4_INT 0x84
1048 #define V_008DFC_SQ_SRC_5_INT 0x85
1049 #define V_008DFC_SQ_SRC_6_INT 0x86
1050 #define V_008DFC_SQ_SRC_7_INT 0x87
1051 #define V_008DFC_SQ_SRC_8_INT 0x88
1052 #define V_008DFC_SQ_SRC_9_INT 0x89
1053 #define V_008DFC_SQ_SRC_10_INT 0x8A
1054 #define V_008DFC_SQ_SRC_11_INT 0x8B
1055 #define V_008DFC_SQ_SRC_12_INT 0x8C
1056 #define V_008DFC_SQ_SRC_13_INT 0x8D
1057 #define V_008DFC_SQ_SRC_14_INT 0x8E
1058 #define V_008DFC_SQ_SRC_15_INT 0x8F
1059 #define V_008DFC_SQ_SRC_16_INT 0x90
1060 #define V_008DFC_SQ_SRC_17_INT 0x91
1061 #define V_008DFC_SQ_SRC_18_INT 0x92
1062 #define V_008DFC_SQ_SRC_19_INT 0x93
1063 #define V_008DFC_SQ_SRC_20_INT 0x94
1064 #define V_008DFC_SQ_SRC_21_INT 0x95
1065 #define V_008DFC_SQ_SRC_22_INT 0x96
1066 #define V_008DFC_SQ_SRC_23_INT 0x97
1067 #define V_008DFC_SQ_SRC_24_INT 0x98
1068 #define V_008DFC_SQ_SRC_25_INT 0x99
1069 #define V_008DFC_SQ_SRC_26_INT 0x9A
1070 #define V_008DFC_SQ_SRC_27_INT 0x9B
1071 #define V_008DFC_SQ_SRC_28_INT 0x9C
1072 #define V_008DFC_SQ_SRC_29_INT 0x9D
1073 #define V_008DFC_SQ_SRC_30_INT 0x9E
1074 #define V_008DFC_SQ_SRC_31_INT 0x9F
1075 #define V_008DFC_SQ_SRC_32_INT 0xA0
1076 #define V_008DFC_SQ_SRC_33_INT 0xA1
1077 #define V_008DFC_SQ_SRC_34_INT 0xA2
1078 #define V_008DFC_SQ_SRC_35_INT 0xA3
1079 #define V_008DFC_SQ_SRC_36_INT 0xA4
1080 #define V_008DFC_SQ_SRC_37_INT 0xA5
1081 #define V_008DFC_SQ_SRC_38_INT 0xA6
1082 #define V_008DFC_SQ_SRC_39_INT 0xA7
1083 #define V_008DFC_SQ_SRC_40_INT 0xA8
1084 #define V_008DFC_SQ_SRC_41_INT 0xA9
1085 #define V_008DFC_SQ_SRC_42_INT 0xAA
1086 #define V_008DFC_SQ_SRC_43_INT 0xAB
1087 #define V_008DFC_SQ_SRC_44_INT 0xAC
1088 #define V_008DFC_SQ_SRC_45_INT 0xAD
1089 #define V_008DFC_SQ_SRC_46_INT 0xAE
1090 #define V_008DFC_SQ_SRC_47_INT 0xAF
1091 #define V_008DFC_SQ_SRC_48_INT 0xB0
1092 #define V_008DFC_SQ_SRC_49_INT 0xB1
1093 #define V_008DFC_SQ_SRC_50_INT 0xB2
1094 #define V_008DFC_SQ_SRC_51_INT 0xB3
1095 #define V_008DFC_SQ_SRC_52_INT 0xB4
1096 #define V_008DFC_SQ_SRC_53_INT 0xB5
1097 #define V_008DFC_SQ_SRC_54_INT 0xB6
1098 #define V_008DFC_SQ_SRC_55_INT 0xB7
1099 #define V_008DFC_SQ_SRC_56_INT 0xB8
1100 #define V_008DFC_SQ_SRC_57_INT 0xB9
1101 #define V_008DFC_SQ_SRC_58_INT 0xBA
1102 #define V_008DFC_SQ_SRC_59_INT 0xBB
1103 #define V_008DFC_SQ_SRC_60_INT 0xBC
1104 #define V_008DFC_SQ_SRC_61_INT 0xBD
1105 #define V_008DFC_SQ_SRC_62_INT 0xBE
1106 #define V_008DFC_SQ_SRC_63_INT 0xBF
1107 #define V_008DFC_SQ_SRC_64_INT 0xC0
1108 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
1109 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
1110 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
1111 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
1112 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
1113 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
1114 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
1115 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
1116 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
1117 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
1118 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
1119 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
1120 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
1121 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
1122 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
1123 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
1124 #define V_008DFC_SQ_SRC_0_5 0xF0
1125 #define V_008DFC_SQ_SRC_M_0_5 0xF1
1126 #define V_008DFC_SQ_SRC_1 0xF2
1127 #define V_008DFC_SQ_SRC_M_1 0xF3
1128 #define V_008DFC_SQ_SRC_2 0xF4
1129 #define V_008DFC_SQ_SRC_M_2 0xF5
1130 #define V_008DFC_SQ_SRC_4 0xF6
1131 #define V_008DFC_SQ_SRC_M_4 0xF7
1132 #define V_008DFC_SQ_SRC_VCCZ 0xFB
1133 #define V_008DFC_SQ_SRC_EXECZ 0xFC
1134 #define V_008DFC_SQ_SRC_SCC 0xFD
1135 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
1136 #define V_008DFC_SQ_SRC_VGPR 0x100
1137 #define S_008DFC_SRC1(x) (((x) & 0x1FF) << 9)
1138 #define G_008DFC_SRC1(x) (((x) >> 9) & 0x1FF)
1139 #define C_008DFC_SRC1 0xFFFC01FF
1140 #define V_008DFC_SQ_SGPR 0x00
1141 /* CIK */
1142 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
1143 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
1144 /* */
1145 #define V_008DFC_SQ_VCC_LO 0x6A
1146 #define V_008DFC_SQ_VCC_HI 0x6B
1147 #define V_008DFC_SQ_TBA_LO 0x6C
1148 #define V_008DFC_SQ_TBA_HI 0x6D
1149 #define V_008DFC_SQ_TMA_LO 0x6E
1150 #define V_008DFC_SQ_TMA_HI 0x6F
1151 #define V_008DFC_SQ_TTMP0 0x70
1152 #define V_008DFC_SQ_TTMP1 0x71
1153 #define V_008DFC_SQ_TTMP2 0x72
1154 #define V_008DFC_SQ_TTMP3 0x73
1155 #define V_008DFC_SQ_TTMP4 0x74
1156 #define V_008DFC_SQ_TTMP5 0x75
1157 #define V_008DFC_SQ_TTMP6 0x76
1158 #define V_008DFC_SQ_TTMP7 0x77
1159 #define V_008DFC_SQ_TTMP8 0x78
1160 #define V_008DFC_SQ_TTMP9 0x79
1161 #define V_008DFC_SQ_TTMP10 0x7A
1162 #define V_008DFC_SQ_TTMP11 0x7B
1163 #define V_008DFC_SQ_M0 0x7C
1164 #define V_008DFC_SQ_EXEC_LO 0x7E
1165 #define V_008DFC_SQ_EXEC_HI 0x7F
1166 #define V_008DFC_SQ_SRC_0 0x80
1167 #define V_008DFC_SQ_SRC_1_INT 0x81
1168 #define V_008DFC_SQ_SRC_2_INT 0x82
1169 #define V_008DFC_SQ_SRC_3_INT 0x83
1170 #define V_008DFC_SQ_SRC_4_INT 0x84
1171 #define V_008DFC_SQ_SRC_5_INT 0x85
1172 #define V_008DFC_SQ_SRC_6_INT 0x86
1173 #define V_008DFC_SQ_SRC_7_INT 0x87
1174 #define V_008DFC_SQ_SRC_8_INT 0x88
1175 #define V_008DFC_SQ_SRC_9_INT 0x89
1176 #define V_008DFC_SQ_SRC_10_INT 0x8A
1177 #define V_008DFC_SQ_SRC_11_INT 0x8B
1178 #define V_008DFC_SQ_SRC_12_INT 0x8C
1179 #define V_008DFC_SQ_SRC_13_INT 0x8D
1180 #define V_008DFC_SQ_SRC_14_INT 0x8E
1181 #define V_008DFC_SQ_SRC_15_INT 0x8F
1182 #define V_008DFC_SQ_SRC_16_INT 0x90
1183 #define V_008DFC_SQ_SRC_17_INT 0x91
1184 #define V_008DFC_SQ_SRC_18_INT 0x92
1185 #define V_008DFC_SQ_SRC_19_INT 0x93
1186 #define V_008DFC_SQ_SRC_20_INT 0x94
1187 #define V_008DFC_SQ_SRC_21_INT 0x95
1188 #define V_008DFC_SQ_SRC_22_INT 0x96
1189 #define V_008DFC_SQ_SRC_23_INT 0x97
1190 #define V_008DFC_SQ_SRC_24_INT 0x98
1191 #define V_008DFC_SQ_SRC_25_INT 0x99
1192 #define V_008DFC_SQ_SRC_26_INT 0x9A
1193 #define V_008DFC_SQ_SRC_27_INT 0x9B
1194 #define V_008DFC_SQ_SRC_28_INT 0x9C
1195 #define V_008DFC_SQ_SRC_29_INT 0x9D
1196 #define V_008DFC_SQ_SRC_30_INT 0x9E
1197 #define V_008DFC_SQ_SRC_31_INT 0x9F
1198 #define V_008DFC_SQ_SRC_32_INT 0xA0
1199 #define V_008DFC_SQ_SRC_33_INT 0xA1
1200 #define V_008DFC_SQ_SRC_34_INT 0xA2
1201 #define V_008DFC_SQ_SRC_35_INT 0xA3
1202 #define V_008DFC_SQ_SRC_36_INT 0xA4
1203 #define V_008DFC_SQ_SRC_37_INT 0xA5
1204 #define V_008DFC_SQ_SRC_38_INT 0xA6
1205 #define V_008DFC_SQ_SRC_39_INT 0xA7
1206 #define V_008DFC_SQ_SRC_40_INT 0xA8
1207 #define V_008DFC_SQ_SRC_41_INT 0xA9
1208 #define V_008DFC_SQ_SRC_42_INT 0xAA
1209 #define V_008DFC_SQ_SRC_43_INT 0xAB
1210 #define V_008DFC_SQ_SRC_44_INT 0xAC
1211 #define V_008DFC_SQ_SRC_45_INT 0xAD
1212 #define V_008DFC_SQ_SRC_46_INT 0xAE
1213 #define V_008DFC_SQ_SRC_47_INT 0xAF
1214 #define V_008DFC_SQ_SRC_48_INT 0xB0
1215 #define V_008DFC_SQ_SRC_49_INT 0xB1
1216 #define V_008DFC_SQ_SRC_50_INT 0xB2
1217 #define V_008DFC_SQ_SRC_51_INT 0xB3
1218 #define V_008DFC_SQ_SRC_52_INT 0xB4
1219 #define V_008DFC_SQ_SRC_53_INT 0xB5
1220 #define V_008DFC_SQ_SRC_54_INT 0xB6
1221 #define V_008DFC_SQ_SRC_55_INT 0xB7
1222 #define V_008DFC_SQ_SRC_56_INT 0xB8
1223 #define V_008DFC_SQ_SRC_57_INT 0xB9
1224 #define V_008DFC_SQ_SRC_58_INT 0xBA
1225 #define V_008DFC_SQ_SRC_59_INT 0xBB
1226 #define V_008DFC_SQ_SRC_60_INT 0xBC
1227 #define V_008DFC_SQ_SRC_61_INT 0xBD
1228 #define V_008DFC_SQ_SRC_62_INT 0xBE
1229 #define V_008DFC_SQ_SRC_63_INT 0xBF
1230 #define V_008DFC_SQ_SRC_64_INT 0xC0
1231 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
1232 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
1233 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
1234 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
1235 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
1236 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
1237 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
1238 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
1239 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
1240 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
1241 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
1242 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
1243 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
1244 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
1245 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
1246 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
1247 #define V_008DFC_SQ_SRC_0_5 0xF0
1248 #define V_008DFC_SQ_SRC_M_0_5 0xF1
1249 #define V_008DFC_SQ_SRC_1 0xF2
1250 #define V_008DFC_SQ_SRC_M_1 0xF3
1251 #define V_008DFC_SQ_SRC_2 0xF4
1252 #define V_008DFC_SQ_SRC_M_2 0xF5
1253 #define V_008DFC_SQ_SRC_4 0xF6
1254 #define V_008DFC_SQ_SRC_M_4 0xF7
1255 #define V_008DFC_SQ_SRC_VCCZ 0xFB
1256 #define V_008DFC_SQ_SRC_EXECZ 0xFC
1257 #define V_008DFC_SQ_SRC_SCC 0xFD
1258 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
1259 #define V_008DFC_SQ_SRC_VGPR 0x100
1260 #define S_008DFC_SRC2(x) (((x) & 0x1FF) << 18)
1261 #define G_008DFC_SRC2(x) (((x) >> 18) & 0x1FF)
1262 #define C_008DFC_SRC2 0xF803FFFF
1263 #define V_008DFC_SQ_SGPR 0x00
1264 /* CIK */
1265 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
1266 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
1267 /* */
1268 #define V_008DFC_SQ_VCC_LO 0x6A
1269 #define V_008DFC_SQ_VCC_HI 0x6B
1270 #define V_008DFC_SQ_TBA_LO 0x6C
1271 #define V_008DFC_SQ_TBA_HI 0x6D
1272 #define V_008DFC_SQ_TMA_LO 0x6E
1273 #define V_008DFC_SQ_TMA_HI 0x6F
1274 #define V_008DFC_SQ_TTMP0 0x70
1275 #define V_008DFC_SQ_TTMP1 0x71
1276 #define V_008DFC_SQ_TTMP2 0x72
1277 #define V_008DFC_SQ_TTMP3 0x73
1278 #define V_008DFC_SQ_TTMP4 0x74
1279 #define V_008DFC_SQ_TTMP5 0x75
1280 #define V_008DFC_SQ_TTMP6 0x76
1281 #define V_008DFC_SQ_TTMP7 0x77
1282 #define V_008DFC_SQ_TTMP8 0x78
1283 #define V_008DFC_SQ_TTMP9 0x79
1284 #define V_008DFC_SQ_TTMP10 0x7A
1285 #define V_008DFC_SQ_TTMP11 0x7B
1286 #define V_008DFC_SQ_M0 0x7C
1287 #define V_008DFC_SQ_EXEC_LO 0x7E
1288 #define V_008DFC_SQ_EXEC_HI 0x7F
1289 #define V_008DFC_SQ_SRC_0 0x80
1290 #define V_008DFC_SQ_SRC_1_INT 0x81
1291 #define V_008DFC_SQ_SRC_2_INT 0x82
1292 #define V_008DFC_SQ_SRC_3_INT 0x83
1293 #define V_008DFC_SQ_SRC_4_INT 0x84
1294 #define V_008DFC_SQ_SRC_5_INT 0x85
1295 #define V_008DFC_SQ_SRC_6_INT 0x86
1296 #define V_008DFC_SQ_SRC_7_INT 0x87
1297 #define V_008DFC_SQ_SRC_8_INT 0x88
1298 #define V_008DFC_SQ_SRC_9_INT 0x89
1299 #define V_008DFC_SQ_SRC_10_INT 0x8A
1300 #define V_008DFC_SQ_SRC_11_INT 0x8B
1301 #define V_008DFC_SQ_SRC_12_INT 0x8C
1302 #define V_008DFC_SQ_SRC_13_INT 0x8D
1303 #define V_008DFC_SQ_SRC_14_INT 0x8E
1304 #define V_008DFC_SQ_SRC_15_INT 0x8F
1305 #define V_008DFC_SQ_SRC_16_INT 0x90
1306 #define V_008DFC_SQ_SRC_17_INT 0x91
1307 #define V_008DFC_SQ_SRC_18_INT 0x92
1308 #define V_008DFC_SQ_SRC_19_INT 0x93
1309 #define V_008DFC_SQ_SRC_20_INT 0x94
1310 #define V_008DFC_SQ_SRC_21_INT 0x95
1311 #define V_008DFC_SQ_SRC_22_INT 0x96
1312 #define V_008DFC_SQ_SRC_23_INT 0x97
1313 #define V_008DFC_SQ_SRC_24_INT 0x98
1314 #define V_008DFC_SQ_SRC_25_INT 0x99
1315 #define V_008DFC_SQ_SRC_26_INT 0x9A
1316 #define V_008DFC_SQ_SRC_27_INT 0x9B
1317 #define V_008DFC_SQ_SRC_28_INT 0x9C
1318 #define V_008DFC_SQ_SRC_29_INT 0x9D
1319 #define V_008DFC_SQ_SRC_30_INT 0x9E
1320 #define V_008DFC_SQ_SRC_31_INT 0x9F
1321 #define V_008DFC_SQ_SRC_32_INT 0xA0
1322 #define V_008DFC_SQ_SRC_33_INT 0xA1
1323 #define V_008DFC_SQ_SRC_34_INT 0xA2
1324 #define V_008DFC_SQ_SRC_35_INT 0xA3
1325 #define V_008DFC_SQ_SRC_36_INT 0xA4
1326 #define V_008DFC_SQ_SRC_37_INT 0xA5
1327 #define V_008DFC_SQ_SRC_38_INT 0xA6
1328 #define V_008DFC_SQ_SRC_39_INT 0xA7
1329 #define V_008DFC_SQ_SRC_40_INT 0xA8
1330 #define V_008DFC_SQ_SRC_41_INT 0xA9
1331 #define V_008DFC_SQ_SRC_42_INT 0xAA
1332 #define V_008DFC_SQ_SRC_43_INT 0xAB
1333 #define V_008DFC_SQ_SRC_44_INT 0xAC
1334 #define V_008DFC_SQ_SRC_45_INT 0xAD
1335 #define V_008DFC_SQ_SRC_46_INT 0xAE
1336 #define V_008DFC_SQ_SRC_47_INT 0xAF
1337 #define V_008DFC_SQ_SRC_48_INT 0xB0
1338 #define V_008DFC_SQ_SRC_49_INT 0xB1
1339 #define V_008DFC_SQ_SRC_50_INT 0xB2
1340 #define V_008DFC_SQ_SRC_51_INT 0xB3
1341 #define V_008DFC_SQ_SRC_52_INT 0xB4
1342 #define V_008DFC_SQ_SRC_53_INT 0xB5
1343 #define V_008DFC_SQ_SRC_54_INT 0xB6
1344 #define V_008DFC_SQ_SRC_55_INT 0xB7
1345 #define V_008DFC_SQ_SRC_56_INT 0xB8
1346 #define V_008DFC_SQ_SRC_57_INT 0xB9
1347 #define V_008DFC_SQ_SRC_58_INT 0xBA
1348 #define V_008DFC_SQ_SRC_59_INT 0xBB
1349 #define V_008DFC_SQ_SRC_60_INT 0xBC
1350 #define V_008DFC_SQ_SRC_61_INT 0xBD
1351 #define V_008DFC_SQ_SRC_62_INT 0xBE
1352 #define V_008DFC_SQ_SRC_63_INT 0xBF
1353 #define V_008DFC_SQ_SRC_64_INT 0xC0
1354 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
1355 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
1356 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
1357 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
1358 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
1359 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
1360 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
1361 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
1362 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
1363 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
1364 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
1365 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
1366 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
1367 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
1368 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
1369 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
1370 #define V_008DFC_SQ_SRC_0_5 0xF0
1371 #define V_008DFC_SQ_SRC_M_0_5 0xF1
1372 #define V_008DFC_SQ_SRC_1 0xF2
1373 #define V_008DFC_SQ_SRC_M_1 0xF3
1374 #define V_008DFC_SQ_SRC_2 0xF4
1375 #define V_008DFC_SQ_SRC_M_2 0xF5
1376 #define V_008DFC_SQ_SRC_4 0xF6
1377 #define V_008DFC_SQ_SRC_M_4 0xF7
1378 #define V_008DFC_SQ_SRC_VCCZ 0xFB
1379 #define V_008DFC_SQ_SRC_EXECZ 0xFC
1380 #define V_008DFC_SQ_SRC_SCC 0xFD
1381 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
1382 #define V_008DFC_SQ_SRC_VGPR 0x100
1383 #define S_008DFC_OMOD(x) (((x) & 0x03) << 27)
1384 #define G_008DFC_OMOD(x) (((x) >> 27) & 0x03)
1385 #define C_008DFC_OMOD 0xE7FFFFFF
1386 #define V_008DFC_SQ_OMOD_OFF 0x00
1387 #define V_008DFC_SQ_OMOD_M2 0x01
1388 #define V_008DFC_SQ_OMOD_M4 0x02
1389 #define V_008DFC_SQ_OMOD_D2 0x03
1390 #define S_008DFC_NEG(x) (((x) & 0x07) << 29)
1391 #define G_008DFC_NEG(x) (((x) >> 29) & 0x07)
1392 #define C_008DFC_NEG 0x1FFFFFFF
1393 #define R_008DFC_SQ_MUBUF_1 0x008DFC
1394 #define S_008DFC_VADDR(x) (((x) & 0xFF) << 0)
1395 #define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF)
1396 #define C_008DFC_VADDR 0xFFFFFF00
1397 #define V_008DFC_SQ_VGPR 0x00
1398 #define S_008DFC_VDATA(x) (((x) & 0xFF) << 8)
1399 #define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF)
1400 #define C_008DFC_VDATA 0xFFFF00FF
1401 #define V_008DFC_SQ_VGPR 0x00
1402 #define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16)
1403 #define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F)
1404 #define C_008DFC_SRSRC 0xFFE0FFFF
1405 #define S_008DFC_SLC(x) (((x) & 0x1) << 22)
1406 #define G_008DFC_SLC(x) (((x) >> 22) & 0x1)
1407 #define C_008DFC_SLC 0xFFBFFFFF
1408 #define S_008DFC_TFE(x) (((x) & 0x1) << 23)
1409 #define G_008DFC_TFE(x) (((x) >> 23) & 0x1)
1410 #define C_008DFC_TFE 0xFF7FFFFF
1411 #define S_008DFC_SOFFSET(x) (((x) & 0xFF) << 24)
1412 #define G_008DFC_SOFFSET(x) (((x) >> 24) & 0xFF)
1413 #define C_008DFC_SOFFSET 0x00FFFFFF
1414 #define V_008DFC_SQ_SGPR 0x00
1415 /* CIK */
1416 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
1417 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
1418 /* */
1419 #define V_008DFC_SQ_VCC_LO 0x6A
1420 #define V_008DFC_SQ_VCC_HI 0x6B
1421 #define V_008DFC_SQ_TBA_LO 0x6C
1422 #define V_008DFC_SQ_TBA_HI 0x6D
1423 #define V_008DFC_SQ_TMA_LO 0x6E
1424 #define V_008DFC_SQ_TMA_HI 0x6F
1425 #define V_008DFC_SQ_TTMP0 0x70
1426 #define V_008DFC_SQ_TTMP1 0x71
1427 #define V_008DFC_SQ_TTMP2 0x72
1428 #define V_008DFC_SQ_TTMP3 0x73
1429 #define V_008DFC_SQ_TTMP4 0x74
1430 #define V_008DFC_SQ_TTMP5 0x75
1431 #define V_008DFC_SQ_TTMP6 0x76
1432 #define V_008DFC_SQ_TTMP7 0x77
1433 #define V_008DFC_SQ_TTMP8 0x78
1434 #define V_008DFC_SQ_TTMP9 0x79
1435 #define V_008DFC_SQ_TTMP10 0x7A
1436 #define V_008DFC_SQ_TTMP11 0x7B
1437 #define V_008DFC_SQ_M0 0x7C
1438 #define V_008DFC_SQ_EXEC_LO 0x7E
1439 #define V_008DFC_SQ_EXEC_HI 0x7F
1440 #define V_008DFC_SQ_SRC_0 0x80
1441 #define V_008DFC_SQ_SRC_1_INT 0x81
1442 #define V_008DFC_SQ_SRC_2_INT 0x82
1443 #define V_008DFC_SQ_SRC_3_INT 0x83
1444 #define V_008DFC_SQ_SRC_4_INT 0x84
1445 #define V_008DFC_SQ_SRC_5_INT 0x85
1446 #define V_008DFC_SQ_SRC_6_INT 0x86
1447 #define V_008DFC_SQ_SRC_7_INT 0x87
1448 #define V_008DFC_SQ_SRC_8_INT 0x88
1449 #define V_008DFC_SQ_SRC_9_INT 0x89
1450 #define V_008DFC_SQ_SRC_10_INT 0x8A
1451 #define V_008DFC_SQ_SRC_11_INT 0x8B
1452 #define V_008DFC_SQ_SRC_12_INT 0x8C
1453 #define V_008DFC_SQ_SRC_13_INT 0x8D
1454 #define V_008DFC_SQ_SRC_14_INT 0x8E
1455 #define V_008DFC_SQ_SRC_15_INT 0x8F
1456 #define V_008DFC_SQ_SRC_16_INT 0x90
1457 #define V_008DFC_SQ_SRC_17_INT 0x91
1458 #define V_008DFC_SQ_SRC_18_INT 0x92
1459 #define V_008DFC_SQ_SRC_19_INT 0x93
1460 #define V_008DFC_SQ_SRC_20_INT 0x94
1461 #define V_008DFC_SQ_SRC_21_INT 0x95
1462 #define V_008DFC_SQ_SRC_22_INT 0x96
1463 #define V_008DFC_SQ_SRC_23_INT 0x97
1464 #define V_008DFC_SQ_SRC_24_INT 0x98
1465 #define V_008DFC_SQ_SRC_25_INT 0x99
1466 #define V_008DFC_SQ_SRC_26_INT 0x9A
1467 #define V_008DFC_SQ_SRC_27_INT 0x9B
1468 #define V_008DFC_SQ_SRC_28_INT 0x9C
1469 #define V_008DFC_SQ_SRC_29_INT 0x9D
1470 #define V_008DFC_SQ_SRC_30_INT 0x9E
1471 #define V_008DFC_SQ_SRC_31_INT 0x9F
1472 #define V_008DFC_SQ_SRC_32_INT 0xA0
1473 #define V_008DFC_SQ_SRC_33_INT 0xA1
1474 #define V_008DFC_SQ_SRC_34_INT 0xA2
1475 #define V_008DFC_SQ_SRC_35_INT 0xA3
1476 #define V_008DFC_SQ_SRC_36_INT 0xA4
1477 #define V_008DFC_SQ_SRC_37_INT 0xA5
1478 #define V_008DFC_SQ_SRC_38_INT 0xA6
1479 #define V_008DFC_SQ_SRC_39_INT 0xA7
1480 #define V_008DFC_SQ_SRC_40_INT 0xA8
1481 #define V_008DFC_SQ_SRC_41_INT 0xA9
1482 #define V_008DFC_SQ_SRC_42_INT 0xAA
1483 #define V_008DFC_SQ_SRC_43_INT 0xAB
1484 #define V_008DFC_SQ_SRC_44_INT 0xAC
1485 #define V_008DFC_SQ_SRC_45_INT 0xAD
1486 #define V_008DFC_SQ_SRC_46_INT 0xAE
1487 #define V_008DFC_SQ_SRC_47_INT 0xAF
1488 #define V_008DFC_SQ_SRC_48_INT 0xB0
1489 #define V_008DFC_SQ_SRC_49_INT 0xB1
1490 #define V_008DFC_SQ_SRC_50_INT 0xB2
1491 #define V_008DFC_SQ_SRC_51_INT 0xB3
1492 #define V_008DFC_SQ_SRC_52_INT 0xB4
1493 #define V_008DFC_SQ_SRC_53_INT 0xB5
1494 #define V_008DFC_SQ_SRC_54_INT 0xB6
1495 #define V_008DFC_SQ_SRC_55_INT 0xB7
1496 #define V_008DFC_SQ_SRC_56_INT 0xB8
1497 #define V_008DFC_SQ_SRC_57_INT 0xB9
1498 #define V_008DFC_SQ_SRC_58_INT 0xBA
1499 #define V_008DFC_SQ_SRC_59_INT 0xBB
1500 #define V_008DFC_SQ_SRC_60_INT 0xBC
1501 #define V_008DFC_SQ_SRC_61_INT 0xBD
1502 #define V_008DFC_SQ_SRC_62_INT 0xBE
1503 #define V_008DFC_SQ_SRC_63_INT 0xBF
1504 #define V_008DFC_SQ_SRC_64_INT 0xC0
1505 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
1506 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
1507 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
1508 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
1509 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
1510 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
1511 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
1512 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
1513 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
1514 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
1515 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
1516 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
1517 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
1518 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
1519 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
1520 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
1521 #define V_008DFC_SQ_SRC_0_5 0xF0
1522 #define V_008DFC_SQ_SRC_M_0_5 0xF1
1523 #define V_008DFC_SQ_SRC_1 0xF2
1524 #define V_008DFC_SQ_SRC_M_1 0xF3
1525 #define V_008DFC_SQ_SRC_2 0xF4
1526 #define V_008DFC_SQ_SRC_M_2 0xF5
1527 #define V_008DFC_SQ_SRC_4 0xF6
1528 #define V_008DFC_SQ_SRC_M_4 0xF7
1529 #define V_008DFC_SQ_SRC_VCCZ 0xFB
1530 #define V_008DFC_SQ_SRC_EXECZ 0xFC
1531 #define V_008DFC_SQ_SRC_SCC 0xFD
1532 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
1533 #define R_008DFC_SQ_DS_0 0x008DFC
1534 #define S_008DFC_OFFSET0(x) (((x) & 0xFF) << 0)
1535 #define G_008DFC_OFFSET0(x) (((x) >> 0) & 0xFF)
1536 #define C_008DFC_OFFSET0 0xFFFFFF00
1537 #define S_008DFC_OFFSET1(x) (((x) & 0xFF) << 8)
1538 #define G_008DFC_OFFSET1(x) (((x) >> 8) & 0xFF)
1539 #define C_008DFC_OFFSET1 0xFFFF00FF
1540 #define S_008DFC_GDS(x) (((x) & 0x1) << 17)
1541 #define G_008DFC_GDS(x) (((x) >> 17) & 0x1)
1542 #define C_008DFC_GDS 0xFFFDFFFF
1543 #define S_008DFC_OP(x) (((x) & 0xFF) << 18)
1544 #define G_008DFC_OP(x) (((x) >> 18) & 0xFF)
1545 #define C_008DFC_OP 0xFC03FFFF
1546 #define V_008DFC_SQ_DS_ADD_U32 0x00
1547 #define V_008DFC_SQ_DS_SUB_U32 0x01
1548 #define V_008DFC_SQ_DS_RSUB_U32 0x02
1549 #define V_008DFC_SQ_DS_INC_U32 0x03
1550 #define V_008DFC_SQ_DS_DEC_U32 0x04
1551 #define V_008DFC_SQ_DS_MIN_I32 0x05
1552 #define V_008DFC_SQ_DS_MAX_I32 0x06
1553 #define V_008DFC_SQ_DS_MIN_U32 0x07
1554 #define V_008DFC_SQ_DS_MAX_U32 0x08
1555 #define V_008DFC_SQ_DS_AND_B32 0x09
1556 #define V_008DFC_SQ_DS_OR_B32 0x0A
1557 #define V_008DFC_SQ_DS_XOR_B32 0x0B
1558 #define V_008DFC_SQ_DS_MSKOR_B32 0x0C
1559 #define V_008DFC_SQ_DS_WRITE_B32 0x0D
1560 #define V_008DFC_SQ_DS_WRITE2_B32 0x0E
1561 #define V_008DFC_SQ_DS_WRITE2ST64_B32 0x0F
1562 #define V_008DFC_SQ_DS_CMPST_B32 0x10
1563 #define V_008DFC_SQ_DS_CMPST_F32 0x11
1564 #define V_008DFC_SQ_DS_MIN_F32 0x12
1565 #define V_008DFC_SQ_DS_MAX_F32 0x13
1566 /* CIK */
1567 #define V_008DFC_SQ_DS_NOP 0x14
1568 /* */
1569 #define V_008DFC_SQ_DS_GWS_INIT 0x19
1570 #define V_008DFC_SQ_DS_GWS_SEMA_V 0x1A
1571 #define V_008DFC_SQ_DS_GWS_SEMA_BR 0x1B
1572 #define V_008DFC_SQ_DS_GWS_SEMA_P 0x1C
1573 #define V_008DFC_SQ_DS_GWS_BARRIER 0x1D
1574 #define V_008DFC_SQ_DS_WRITE_B8 0x1E
1575 #define V_008DFC_SQ_DS_WRITE_B16 0x1F
1576 #define V_008DFC_SQ_DS_ADD_RTN_U32 0x20
1577 #define V_008DFC_SQ_DS_SUB_RTN_U32 0x21
1578 #define V_008DFC_SQ_DS_RSUB_RTN_U32 0x22
1579 #define V_008DFC_SQ_DS_INC_RTN_U32 0x23
1580 #define V_008DFC_SQ_DS_DEC_RTN_U32 0x24
1581 #define V_008DFC_SQ_DS_MIN_RTN_I32 0x25
1582 #define V_008DFC_SQ_DS_MAX_RTN_I32 0x26
1583 #define V_008DFC_SQ_DS_MIN_RTN_U32 0x27
1584 #define V_008DFC_SQ_DS_MAX_RTN_U32 0x28
1585 #define V_008DFC_SQ_DS_AND_RTN_B32 0x29
1586 #define V_008DFC_SQ_DS_OR_RTN_B32 0x2A
1587 #define V_008DFC_SQ_DS_XOR_RTN_B32 0x2B
1588 #define V_008DFC_SQ_DS_MSKOR_RTN_B32 0x2C
1589 #define V_008DFC_SQ_DS_WRXCHG_RTN_B32 0x2D
1590 #define V_008DFC_SQ_DS_WRXCHG2_RTN_B32 0x2E
1591 #define V_008DFC_SQ_DS_WRXCHG2ST64_RTN_B32 0x2F
1592 #define V_008DFC_SQ_DS_CMPST_RTN_B32 0x30
1593 #define V_008DFC_SQ_DS_CMPST_RTN_F32 0x31
1594 #define V_008DFC_SQ_DS_MIN_RTN_F32 0x32
1595 #define V_008DFC_SQ_DS_MAX_RTN_F32 0x33
1596 #define V_008DFC_SQ_DS_SWIZZLE_B32 0x35
1597 #define V_008DFC_SQ_DS_READ_B32 0x36
1598 #define V_008DFC_SQ_DS_READ2_B32 0x37
1599 #define V_008DFC_SQ_DS_READ2ST64_B32 0x38
1600 #define V_008DFC_SQ_DS_READ_I8 0x39
1601 #define V_008DFC_SQ_DS_READ_U8 0x3A
1602 #define V_008DFC_SQ_DS_READ_I16 0x3B
1603 #define V_008DFC_SQ_DS_READ_U16 0x3C
1604 #define V_008DFC_SQ_DS_CONSUME 0x3D
1605 #define V_008DFC_SQ_DS_APPEND 0x3E
1606 #define V_008DFC_SQ_DS_ORDERED_COUNT 0x3F
1607 #define V_008DFC_SQ_DS_ADD_U64 0x40
1608 #define V_008DFC_SQ_DS_SUB_U64 0x41
1609 #define V_008DFC_SQ_DS_RSUB_U64 0x42
1610 #define V_008DFC_SQ_DS_INC_U64 0x43
1611 #define V_008DFC_SQ_DS_DEC_U64 0x44
1612 #define V_008DFC_SQ_DS_MIN_I64 0x45
1613 #define V_008DFC_SQ_DS_MAX_I64 0x46
1614 #define V_008DFC_SQ_DS_MIN_U64 0x47
1615 #define V_008DFC_SQ_DS_MAX_U64 0x48
1616 #define V_008DFC_SQ_DS_AND_B64 0x49
1617 #define V_008DFC_SQ_DS_OR_B64 0x4A
1618 #define V_008DFC_SQ_DS_XOR_B64 0x4B
1619 #define V_008DFC_SQ_DS_MSKOR_B64 0x4C
1620 #define V_008DFC_SQ_DS_WRITE_B64 0x4D
1621 #define V_008DFC_SQ_DS_WRITE2_B64 0x4E
1622 #define V_008DFC_SQ_DS_WRITE2ST64_B64 0x4F
1623 #define V_008DFC_SQ_DS_CMPST_B64 0x50
1624 #define V_008DFC_SQ_DS_CMPST_F64 0x51
1625 #define V_008DFC_SQ_DS_MIN_F64 0x52
1626 #define V_008DFC_SQ_DS_MAX_F64 0x53
1627 #define V_008DFC_SQ_DS_ADD_RTN_U64 0x60
1628 #define V_008DFC_SQ_DS_SUB_RTN_U64 0x61
1629 #define V_008DFC_SQ_DS_RSUB_RTN_U64 0x62
1630 #define V_008DFC_SQ_DS_INC_RTN_U64 0x63
1631 #define V_008DFC_SQ_DS_DEC_RTN_U64 0x64
1632 #define V_008DFC_SQ_DS_MIN_RTN_I64 0x65
1633 #define V_008DFC_SQ_DS_MAX_RTN_I64 0x66
1634 #define V_008DFC_SQ_DS_MIN_RTN_U64 0x67
1635 #define V_008DFC_SQ_DS_MAX_RTN_U64 0x68
1636 #define V_008DFC_SQ_DS_AND_RTN_B64 0x69
1637 #define V_008DFC_SQ_DS_OR_RTN_B64 0x6A
1638 #define V_008DFC_SQ_DS_XOR_RTN_B64 0x6B
1639 #define V_008DFC_SQ_DS_MSKOR_RTN_B64 0x6C
1640 #define V_008DFC_SQ_DS_WRXCHG_RTN_B64 0x6D
1641 #define V_008DFC_SQ_DS_WRXCHG2_RTN_B64 0x6E
1642 #define V_008DFC_SQ_DS_WRXCHG2ST64_RTN_B64 0x6F
1643 #define V_008DFC_SQ_DS_CMPST_RTN_B64 0x70
1644 #define V_008DFC_SQ_DS_CMPST_RTN_F64 0x71
1645 #define V_008DFC_SQ_DS_MIN_RTN_F64 0x72
1646 #define V_008DFC_SQ_DS_MAX_RTN_F64 0x73
1647 #define V_008DFC_SQ_DS_READ_B64 0x76
1648 #define V_008DFC_SQ_DS_READ2_B64 0x77
1649 #define V_008DFC_SQ_DS_READ2ST64_B64 0x78
1650 /* CIK */
1651 #define V_008DFC_SQ_DS_CONDXCHG32_RTN_B64 0x7E
1652 /* */
1653 #define V_008DFC_SQ_DS_ADD_SRC2_U32 0x80
1654 #define V_008DFC_SQ_DS_SUB_SRC2_U32 0x81
1655 #define V_008DFC_SQ_DS_RSUB_SRC2_U32 0x82
1656 #define V_008DFC_SQ_DS_INC_SRC2_U32 0x83
1657 #define V_008DFC_SQ_DS_DEC_SRC2_U32 0x84
1658 #define V_008DFC_SQ_DS_MIN_SRC2_I32 0x85
1659 #define V_008DFC_SQ_DS_MAX_SRC2_I32 0x86
1660 #define V_008DFC_SQ_DS_MIN_SRC2_U32 0x87
1661 #define V_008DFC_SQ_DS_MAX_SRC2_U32 0x88
1662 #define V_008DFC_SQ_DS_AND_SRC2_B32 0x89
1663 #define V_008DFC_SQ_DS_OR_SRC2_B32 0x8A
1664 #define V_008DFC_SQ_DS_XOR_SRC2_B32 0x8B
1665 #define V_008DFC_SQ_DS_WRITE_SRC2_B32 0x8D
1666 #define V_008DFC_SQ_DS_MIN_SRC2_F32 0x92
1667 #define V_008DFC_SQ_DS_MAX_SRC2_F32 0x93
1668 #define V_008DFC_SQ_DS_ADD_SRC2_U64 0xC0
1669 #define V_008DFC_SQ_DS_SUB_SRC2_U64 0xC1
1670 #define V_008DFC_SQ_DS_RSUB_SRC2_U64 0xC2
1671 #define V_008DFC_SQ_DS_INC_SRC2_U64 0xC3
1672 #define V_008DFC_SQ_DS_DEC_SRC2_U64 0xC4
1673 #define V_008DFC_SQ_DS_MIN_SRC2_I64 0xC5
1674 #define V_008DFC_SQ_DS_MAX_SRC2_I64 0xC6
1675 #define V_008DFC_SQ_DS_MIN_SRC2_U64 0xC7
1676 #define V_008DFC_SQ_DS_MAX_SRC2_U64 0xC8
1677 #define V_008DFC_SQ_DS_AND_SRC2_B64 0xC9
1678 #define V_008DFC_SQ_DS_OR_SRC2_B64 0xCA
1679 #define V_008DFC_SQ_DS_XOR_SRC2_B64 0xCB
1680 #define V_008DFC_SQ_DS_WRITE_SRC2_B64 0xCD
1681 #define V_008DFC_SQ_DS_MIN_SRC2_F64 0xD2
1682 #define V_008DFC_SQ_DS_MAX_SRC2_F64 0xD3
1683 /* CIK */
1684 #define V_008DFC_SQ_DS_WRITE_B96 0xDE
1685 #define V_008DFC_SQ_DS_WRITE_B128 0xDF
1686 #define V_008DFC_SQ_DS_CONDXCHG32_RTN_B128 0xFD
1687 #define V_008DFC_SQ_DS_READ_B96 0xFE
1688 #define V_008DFC_SQ_DS_READ_B128 0xFF
1689 /* */
1690 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
1691 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
1692 #define C_008DFC_ENCODING 0x03FFFFFF
1693 #define V_008DFC_SQ_ENC_DS_FIELD 0x36
1694 #define R_008DFC_SQ_SOPC 0x008DFC
1695 #define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0)
1696 #define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF)
1697 #define C_008DFC_SSRC0 0xFFFFFF00
1698 #define V_008DFC_SQ_SGPR 0x00
1699 /* CIK */
1700 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
1701 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
1702 /* */
1703 #define V_008DFC_SQ_VCC_LO 0x6A
1704 #define V_008DFC_SQ_VCC_HI 0x6B
1705 #define V_008DFC_SQ_TBA_LO 0x6C
1706 #define V_008DFC_SQ_TBA_HI 0x6D
1707 #define V_008DFC_SQ_TMA_LO 0x6E
1708 #define V_008DFC_SQ_TMA_HI 0x6F
1709 #define V_008DFC_SQ_TTMP0 0x70
1710 #define V_008DFC_SQ_TTMP1 0x71
1711 #define V_008DFC_SQ_TTMP2 0x72
1712 #define V_008DFC_SQ_TTMP3 0x73
1713 #define V_008DFC_SQ_TTMP4 0x74
1714 #define V_008DFC_SQ_TTMP5 0x75
1715 #define V_008DFC_SQ_TTMP6 0x76
1716 #define V_008DFC_SQ_TTMP7 0x77
1717 #define V_008DFC_SQ_TTMP8 0x78
1718 #define V_008DFC_SQ_TTMP9 0x79
1719 #define V_008DFC_SQ_TTMP10 0x7A
1720 #define V_008DFC_SQ_TTMP11 0x7B
1721 #define V_008DFC_SQ_M0 0x7C
1722 #define V_008DFC_SQ_EXEC_LO 0x7E
1723 #define V_008DFC_SQ_EXEC_HI 0x7F
1724 #define V_008DFC_SQ_SRC_0 0x80
1725 #define V_008DFC_SQ_SRC_1_INT 0x81
1726 #define V_008DFC_SQ_SRC_2_INT 0x82
1727 #define V_008DFC_SQ_SRC_3_INT 0x83
1728 #define V_008DFC_SQ_SRC_4_INT 0x84
1729 #define V_008DFC_SQ_SRC_5_INT 0x85
1730 #define V_008DFC_SQ_SRC_6_INT 0x86
1731 #define V_008DFC_SQ_SRC_7_INT 0x87
1732 #define V_008DFC_SQ_SRC_8_INT 0x88
1733 #define V_008DFC_SQ_SRC_9_INT 0x89
1734 #define V_008DFC_SQ_SRC_10_INT 0x8A
1735 #define V_008DFC_SQ_SRC_11_INT 0x8B
1736 #define V_008DFC_SQ_SRC_12_INT 0x8C
1737 #define V_008DFC_SQ_SRC_13_INT 0x8D
1738 #define V_008DFC_SQ_SRC_14_INT 0x8E
1739 #define V_008DFC_SQ_SRC_15_INT 0x8F
1740 #define V_008DFC_SQ_SRC_16_INT 0x90
1741 #define V_008DFC_SQ_SRC_17_INT 0x91
1742 #define V_008DFC_SQ_SRC_18_INT 0x92
1743 #define V_008DFC_SQ_SRC_19_INT 0x93
1744 #define V_008DFC_SQ_SRC_20_INT 0x94
1745 #define V_008DFC_SQ_SRC_21_INT 0x95
1746 #define V_008DFC_SQ_SRC_22_INT 0x96
1747 #define V_008DFC_SQ_SRC_23_INT 0x97
1748 #define V_008DFC_SQ_SRC_24_INT 0x98
1749 #define V_008DFC_SQ_SRC_25_INT 0x99
1750 #define V_008DFC_SQ_SRC_26_INT 0x9A
1751 #define V_008DFC_SQ_SRC_27_INT 0x9B
1752 #define V_008DFC_SQ_SRC_28_INT 0x9C
1753 #define V_008DFC_SQ_SRC_29_INT 0x9D
1754 #define V_008DFC_SQ_SRC_30_INT 0x9E
1755 #define V_008DFC_SQ_SRC_31_INT 0x9F
1756 #define V_008DFC_SQ_SRC_32_INT 0xA0
1757 #define V_008DFC_SQ_SRC_33_INT 0xA1
1758 #define V_008DFC_SQ_SRC_34_INT 0xA2
1759 #define V_008DFC_SQ_SRC_35_INT 0xA3
1760 #define V_008DFC_SQ_SRC_36_INT 0xA4
1761 #define V_008DFC_SQ_SRC_37_INT 0xA5
1762 #define V_008DFC_SQ_SRC_38_INT 0xA6
1763 #define V_008DFC_SQ_SRC_39_INT 0xA7
1764 #define V_008DFC_SQ_SRC_40_INT 0xA8
1765 #define V_008DFC_SQ_SRC_41_INT 0xA9
1766 #define V_008DFC_SQ_SRC_42_INT 0xAA
1767 #define V_008DFC_SQ_SRC_43_INT 0xAB
1768 #define V_008DFC_SQ_SRC_44_INT 0xAC
1769 #define V_008DFC_SQ_SRC_45_INT 0xAD
1770 #define V_008DFC_SQ_SRC_46_INT 0xAE
1771 #define V_008DFC_SQ_SRC_47_INT 0xAF
1772 #define V_008DFC_SQ_SRC_48_INT 0xB0
1773 #define V_008DFC_SQ_SRC_49_INT 0xB1
1774 #define V_008DFC_SQ_SRC_50_INT 0xB2
1775 #define V_008DFC_SQ_SRC_51_INT 0xB3
1776 #define V_008DFC_SQ_SRC_52_INT 0xB4
1777 #define V_008DFC_SQ_SRC_53_INT 0xB5
1778 #define V_008DFC_SQ_SRC_54_INT 0xB6
1779 #define V_008DFC_SQ_SRC_55_INT 0xB7
1780 #define V_008DFC_SQ_SRC_56_INT 0xB8
1781 #define V_008DFC_SQ_SRC_57_INT 0xB9
1782 #define V_008DFC_SQ_SRC_58_INT 0xBA
1783 #define V_008DFC_SQ_SRC_59_INT 0xBB
1784 #define V_008DFC_SQ_SRC_60_INT 0xBC
1785 #define V_008DFC_SQ_SRC_61_INT 0xBD
1786 #define V_008DFC_SQ_SRC_62_INT 0xBE
1787 #define V_008DFC_SQ_SRC_63_INT 0xBF
1788 #define V_008DFC_SQ_SRC_64_INT 0xC0
1789 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
1790 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
1791 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
1792 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
1793 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
1794 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
1795 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
1796 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
1797 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
1798 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
1799 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
1800 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
1801 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
1802 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
1803 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
1804 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
1805 #define V_008DFC_SQ_SRC_0_5 0xF0
1806 #define V_008DFC_SQ_SRC_M_0_5 0xF1
1807 #define V_008DFC_SQ_SRC_1 0xF2
1808 #define V_008DFC_SQ_SRC_M_1 0xF3
1809 #define V_008DFC_SQ_SRC_2 0xF4
1810 #define V_008DFC_SQ_SRC_M_2 0xF5
1811 #define V_008DFC_SQ_SRC_4 0xF6
1812 #define V_008DFC_SQ_SRC_M_4 0xF7
1813 #define V_008DFC_SQ_SRC_VCCZ 0xFB
1814 #define V_008DFC_SQ_SRC_EXECZ 0xFC
1815 #define V_008DFC_SQ_SRC_SCC 0xFD
1816 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
1817 #define S_008DFC_SSRC1(x) (((x) & 0xFF) << 8)
1818 #define G_008DFC_SSRC1(x) (((x) >> 8) & 0xFF)
1819 #define C_008DFC_SSRC1 0xFFFF00FF
1820 #define V_008DFC_SQ_SGPR 0x00
1821 /* CIK */
1822 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
1823 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
1824 /* */
1825 #define V_008DFC_SQ_VCC_LO 0x6A
1826 #define V_008DFC_SQ_VCC_HI 0x6B
1827 #define V_008DFC_SQ_TBA_LO 0x6C
1828 #define V_008DFC_SQ_TBA_HI 0x6D
1829 #define V_008DFC_SQ_TMA_LO 0x6E
1830 #define V_008DFC_SQ_TMA_HI 0x6F
1831 #define V_008DFC_SQ_TTMP0 0x70
1832 #define V_008DFC_SQ_TTMP1 0x71
1833 #define V_008DFC_SQ_TTMP2 0x72
1834 #define V_008DFC_SQ_TTMP3 0x73
1835 #define V_008DFC_SQ_TTMP4 0x74
1836 #define V_008DFC_SQ_TTMP5 0x75
1837 #define V_008DFC_SQ_TTMP6 0x76
1838 #define V_008DFC_SQ_TTMP7 0x77
1839 #define V_008DFC_SQ_TTMP8 0x78
1840 #define V_008DFC_SQ_TTMP9 0x79
1841 #define V_008DFC_SQ_TTMP10 0x7A
1842 #define V_008DFC_SQ_TTMP11 0x7B
1843 #define V_008DFC_SQ_M0 0x7C
1844 #define V_008DFC_SQ_EXEC_LO 0x7E
1845 #define V_008DFC_SQ_EXEC_HI 0x7F
1846 #define V_008DFC_SQ_SRC_0 0x80
1847 #define V_008DFC_SQ_SRC_1_INT 0x81
1848 #define V_008DFC_SQ_SRC_2_INT 0x82
1849 #define V_008DFC_SQ_SRC_3_INT 0x83
1850 #define V_008DFC_SQ_SRC_4_INT 0x84
1851 #define V_008DFC_SQ_SRC_5_INT 0x85
1852 #define V_008DFC_SQ_SRC_6_INT 0x86
1853 #define V_008DFC_SQ_SRC_7_INT 0x87
1854 #define V_008DFC_SQ_SRC_8_INT 0x88
1855 #define V_008DFC_SQ_SRC_9_INT 0x89
1856 #define V_008DFC_SQ_SRC_10_INT 0x8A
1857 #define V_008DFC_SQ_SRC_11_INT 0x8B
1858 #define V_008DFC_SQ_SRC_12_INT 0x8C
1859 #define V_008DFC_SQ_SRC_13_INT 0x8D
1860 #define V_008DFC_SQ_SRC_14_INT 0x8E
1861 #define V_008DFC_SQ_SRC_15_INT 0x8F
1862 #define V_008DFC_SQ_SRC_16_INT 0x90
1863 #define V_008DFC_SQ_SRC_17_INT 0x91
1864 #define V_008DFC_SQ_SRC_18_INT 0x92
1865 #define V_008DFC_SQ_SRC_19_INT 0x93
1866 #define V_008DFC_SQ_SRC_20_INT 0x94
1867 #define V_008DFC_SQ_SRC_21_INT 0x95
1868 #define V_008DFC_SQ_SRC_22_INT 0x96
1869 #define V_008DFC_SQ_SRC_23_INT 0x97
1870 #define V_008DFC_SQ_SRC_24_INT 0x98
1871 #define V_008DFC_SQ_SRC_25_INT 0x99
1872 #define V_008DFC_SQ_SRC_26_INT 0x9A
1873 #define V_008DFC_SQ_SRC_27_INT 0x9B
1874 #define V_008DFC_SQ_SRC_28_INT 0x9C
1875 #define V_008DFC_SQ_SRC_29_INT 0x9D
1876 #define V_008DFC_SQ_SRC_30_INT 0x9E
1877 #define V_008DFC_SQ_SRC_31_INT 0x9F
1878 #define V_008DFC_SQ_SRC_32_INT 0xA0
1879 #define V_008DFC_SQ_SRC_33_INT 0xA1
1880 #define V_008DFC_SQ_SRC_34_INT 0xA2
1881 #define V_008DFC_SQ_SRC_35_INT 0xA3
1882 #define V_008DFC_SQ_SRC_36_INT 0xA4
1883 #define V_008DFC_SQ_SRC_37_INT 0xA5
1884 #define V_008DFC_SQ_SRC_38_INT 0xA6
1885 #define V_008DFC_SQ_SRC_39_INT 0xA7
1886 #define V_008DFC_SQ_SRC_40_INT 0xA8
1887 #define V_008DFC_SQ_SRC_41_INT 0xA9
1888 #define V_008DFC_SQ_SRC_42_INT 0xAA
1889 #define V_008DFC_SQ_SRC_43_INT 0xAB
1890 #define V_008DFC_SQ_SRC_44_INT 0xAC
1891 #define V_008DFC_SQ_SRC_45_INT 0xAD
1892 #define V_008DFC_SQ_SRC_46_INT 0xAE
1893 #define V_008DFC_SQ_SRC_47_INT 0xAF
1894 #define V_008DFC_SQ_SRC_48_INT 0xB0
1895 #define V_008DFC_SQ_SRC_49_INT 0xB1
1896 #define V_008DFC_SQ_SRC_50_INT 0xB2
1897 #define V_008DFC_SQ_SRC_51_INT 0xB3
1898 #define V_008DFC_SQ_SRC_52_INT 0xB4
1899 #define V_008DFC_SQ_SRC_53_INT 0xB5
1900 #define V_008DFC_SQ_SRC_54_INT 0xB6
1901 #define V_008DFC_SQ_SRC_55_INT 0xB7
1902 #define V_008DFC_SQ_SRC_56_INT 0xB8
1903 #define V_008DFC_SQ_SRC_57_INT 0xB9
1904 #define V_008DFC_SQ_SRC_58_INT 0xBA
1905 #define V_008DFC_SQ_SRC_59_INT 0xBB
1906 #define V_008DFC_SQ_SRC_60_INT 0xBC
1907 #define V_008DFC_SQ_SRC_61_INT 0xBD
1908 #define V_008DFC_SQ_SRC_62_INT 0xBE
1909 #define V_008DFC_SQ_SRC_63_INT 0xBF
1910 #define V_008DFC_SQ_SRC_64_INT 0xC0
1911 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
1912 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
1913 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
1914 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
1915 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
1916 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
1917 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
1918 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
1919 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
1920 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
1921 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
1922 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
1923 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
1924 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
1925 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
1926 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
1927 #define V_008DFC_SQ_SRC_0_5 0xF0
1928 #define V_008DFC_SQ_SRC_M_0_5 0xF1
1929 #define V_008DFC_SQ_SRC_1 0xF2
1930 #define V_008DFC_SQ_SRC_M_1 0xF3
1931 #define V_008DFC_SQ_SRC_2 0xF4
1932 #define V_008DFC_SQ_SRC_M_2 0xF5
1933 #define V_008DFC_SQ_SRC_4 0xF6
1934 #define V_008DFC_SQ_SRC_M_4 0xF7
1935 #define V_008DFC_SQ_SRC_VCCZ 0xFB
1936 #define V_008DFC_SQ_SRC_EXECZ 0xFC
1937 #define V_008DFC_SQ_SRC_SCC 0xFD
1938 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
1939 #define S_008DFC_OP(x) (((x) & 0x7F) << 16)
1940 #define G_008DFC_OP(x) (((x) >> 16) & 0x7F)
1941 #define C_008DFC_OP 0xFF80FFFF
1942 #define V_008DFC_SQ_S_CMP_EQ_I32 0x00
1943 #define V_008DFC_SQ_S_CMP_LG_I32 0x01
1944 #define V_008DFC_SQ_S_CMP_GT_I32 0x02
1945 #define V_008DFC_SQ_S_CMP_GE_I32 0x03
1946 #define V_008DFC_SQ_S_CMP_LT_I32 0x04
1947 #define V_008DFC_SQ_S_CMP_LE_I32 0x05
1948 #define V_008DFC_SQ_S_CMP_EQ_U32 0x06
1949 #define V_008DFC_SQ_S_CMP_LG_U32 0x07
1950 #define V_008DFC_SQ_S_CMP_GT_U32 0x08
1951 #define V_008DFC_SQ_S_CMP_GE_U32 0x09
1952 #define V_008DFC_SQ_S_CMP_LT_U32 0x0A
1953 #define V_008DFC_SQ_S_CMP_LE_U32 0x0B
1954 #define V_008DFC_SQ_S_BITCMP0_B32 0x0C
1955 #define V_008DFC_SQ_S_BITCMP1_B32 0x0D
1956 #define V_008DFC_SQ_S_BITCMP0_B64 0x0E
1957 #define V_008DFC_SQ_S_BITCMP1_B64 0x0F
1958 #define V_008DFC_SQ_S_SETVSKIP 0x10
1959 #define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23)
1960 #define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF)
1961 #define C_008DFC_ENCODING 0x007FFFFF
1962 #define V_008DFC_SQ_ENC_SOPC_FIELD 0x17E
1963 #endif
1964 #define R_008DFC_SQ_EXP_0 0x008DFC
1965 #define S_008DFC_EN(x) (((x) & 0x0F) << 0)
1966 #define G_008DFC_EN(x) (((x) >> 0) & 0x0F)
1967 #define C_008DFC_EN 0xFFFFFFF0
1968 #define S_008DFC_TGT(x) (((x) & 0x3F) << 4)
1969 #define G_008DFC_TGT(x) (((x) >> 4) & 0x3F)
1970 #define C_008DFC_TGT 0xFFFFFC0F
1971 #define V_008DFC_SQ_EXP_MRT 0x00
1972 #define V_008DFC_SQ_EXP_MRTZ 0x08
1973 #define V_008DFC_SQ_EXP_NULL 0x09
1974 #define V_008DFC_SQ_EXP_POS 0x0C
1975 #define V_008DFC_SQ_EXP_PARAM 0x20
1976 #define S_008DFC_COMPR(x) (((x) & 0x1) << 10)
1977 #define G_008DFC_COMPR(x) (((x) >> 10) & 0x1)
1978 #define C_008DFC_COMPR 0xFFFFFBFF
1979 #define S_008DFC_DONE(x) (((x) & 0x1) << 11)
1980 #define G_008DFC_DONE(x) (((x) >> 11) & 0x1)
1981 #define C_008DFC_DONE 0xFFFFF7FF
1982 #define S_008DFC_VM(x) (((x) & 0x1) << 12)
1983 #define G_008DFC_VM(x) (((x) >> 12) & 0x1)
1984 #define C_008DFC_VM 0xFFFFEFFF
1985 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
1986 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
1987 #define C_008DFC_ENCODING 0x03FFFFFF
1988 #define V_008DFC_SQ_ENC_EXP_FIELD 0x3E
1989 #if 0
1990 #define R_008DFC_SQ_MIMG_0 0x008DFC
1991 #define S_008DFC_DMASK(x) (((x) & 0x0F) << 8)
1992 #define G_008DFC_DMASK(x) (((x) >> 8) & 0x0F)
1993 #define C_008DFC_DMASK 0xFFFFF0FF
1994 #define S_008DFC_UNORM(x) (((x) & 0x1) << 12)
1995 #define G_008DFC_UNORM(x) (((x) >> 12) & 0x1)
1996 #define C_008DFC_UNORM 0xFFFFEFFF
1997 #define S_008DFC_GLC(x) (((x) & 0x1) << 13)
1998 #define G_008DFC_GLC(x) (((x) >> 13) & 0x1)
1999 #define C_008DFC_GLC 0xFFFFDFFF
2000 #define S_008DFC_DA(x) (((x) & 0x1) << 14)
2001 #define G_008DFC_DA(x) (((x) >> 14) & 0x1)
2002 #define C_008DFC_DA 0xFFFFBFFF
2003 #define S_008DFC_R128(x) (((x) & 0x1) << 15)
2004 #define G_008DFC_R128(x) (((x) >> 15) & 0x1)
2005 #define C_008DFC_R128 0xFFFF7FFF
2006 #define S_008DFC_TFE(x) (((x) & 0x1) << 16)
2007 #define G_008DFC_TFE(x) (((x) >> 16) & 0x1)
2008 #define C_008DFC_TFE 0xFFFEFFFF
2009 #define S_008DFC_LWE(x) (((x) & 0x1) << 17)
2010 #define G_008DFC_LWE(x) (((x) >> 17) & 0x1)
2011 #define C_008DFC_LWE 0xFFFDFFFF
2012 #define S_008DFC_OP(x) (((x) & 0x7F) << 18)
2013 #define G_008DFC_OP(x) (((x) >> 18) & 0x7F)
2014 #define C_008DFC_OP 0xFE03FFFF
2015 #define V_008DFC_SQ_IMAGE_LOAD 0x00
2016 #define V_008DFC_SQ_IMAGE_LOAD_MIP 0x01
2017 #define V_008DFC_SQ_IMAGE_LOAD_PCK 0x02
2018 #define V_008DFC_SQ_IMAGE_LOAD_PCK_SGN 0x03
2019 #define V_008DFC_SQ_IMAGE_LOAD_MIP_PCK 0x04
2020 #define V_008DFC_SQ_IMAGE_LOAD_MIP_PCK_SGN 0x05
2021 #define V_008DFC_SQ_IMAGE_STORE 0x08
2022 #define V_008DFC_SQ_IMAGE_STORE_MIP 0x09
2023 #define V_008DFC_SQ_IMAGE_STORE_PCK 0x0A
2024 #define V_008DFC_SQ_IMAGE_STORE_MIP_PCK 0x0B
2025 #define V_008DFC_SQ_IMAGE_GET_RESINFO 0x0E
2026 #define V_008DFC_SQ_IMAGE_ATOMIC_SWAP 0x0F
2027 #define V_008DFC_SQ_IMAGE_ATOMIC_CMPSWAP 0x10
2028 #define V_008DFC_SQ_IMAGE_ATOMIC_ADD 0x11
2029 #define V_008DFC_SQ_IMAGE_ATOMIC_SUB 0x12
2030 #define V_008DFC_SQ_IMAGE_ATOMIC_RSUB 0x13 /* not on CIK */
2031 #define V_008DFC_SQ_IMAGE_ATOMIC_SMIN 0x14
2032 #define V_008DFC_SQ_IMAGE_ATOMIC_UMIN 0x15
2033 #define V_008DFC_SQ_IMAGE_ATOMIC_SMAX 0x16
2034 #define V_008DFC_SQ_IMAGE_ATOMIC_UMAX 0x17
2035 #define V_008DFC_SQ_IMAGE_ATOMIC_AND 0x18
2036 #define V_008DFC_SQ_IMAGE_ATOMIC_OR 0x19
2037 #define V_008DFC_SQ_IMAGE_ATOMIC_XOR 0x1A
2038 #define V_008DFC_SQ_IMAGE_ATOMIC_INC 0x1B
2039 #define V_008DFC_SQ_IMAGE_ATOMIC_DEC 0x1C
2040 #define V_008DFC_SQ_IMAGE_ATOMIC_FCMPSWAP 0x1D
2041 #define V_008DFC_SQ_IMAGE_ATOMIC_FMIN 0x1E
2042 #define V_008DFC_SQ_IMAGE_ATOMIC_FMAX 0x1F
2043 #define V_008DFC_SQ_IMAGE_SAMPLE 0x20
2044 #define V_008DFC_SQ_IMAGE_SAMPLE_CL 0x21
2045 #define V_008DFC_SQ_IMAGE_SAMPLE_D 0x22
2046 #define V_008DFC_SQ_IMAGE_SAMPLE_D_CL 0x23
2047 #define V_008DFC_SQ_IMAGE_SAMPLE_L 0x24
2048 #define V_008DFC_SQ_IMAGE_SAMPLE_B 0x25
2049 #define V_008DFC_SQ_IMAGE_SAMPLE_B_CL 0x26
2050 #define V_008DFC_SQ_IMAGE_SAMPLE_LZ 0x27
2051 #define V_008DFC_SQ_IMAGE_SAMPLE_C 0x28
2052 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CL 0x29
2053 #define V_008DFC_SQ_IMAGE_SAMPLE_C_D 0x2A
2054 #define V_008DFC_SQ_IMAGE_SAMPLE_C_D_CL 0x2B
2055 #define V_008DFC_SQ_IMAGE_SAMPLE_C_L 0x2C
2056 #define V_008DFC_SQ_IMAGE_SAMPLE_C_B 0x2D
2057 #define V_008DFC_SQ_IMAGE_SAMPLE_C_B_CL 0x2E
2058 #define V_008DFC_SQ_IMAGE_SAMPLE_C_LZ 0x2F
2059 #define V_008DFC_SQ_IMAGE_SAMPLE_O 0x30
2060 #define V_008DFC_SQ_IMAGE_SAMPLE_CL_O 0x31
2061 #define V_008DFC_SQ_IMAGE_SAMPLE_D_O 0x32
2062 #define V_008DFC_SQ_IMAGE_SAMPLE_D_CL_O 0x33
2063 #define V_008DFC_SQ_IMAGE_SAMPLE_L_O 0x34
2064 #define V_008DFC_SQ_IMAGE_SAMPLE_B_O 0x35
2065 #define V_008DFC_SQ_IMAGE_SAMPLE_B_CL_O 0x36
2066 #define V_008DFC_SQ_IMAGE_SAMPLE_LZ_O 0x37
2067 #define V_008DFC_SQ_IMAGE_SAMPLE_C_O 0x38
2068 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CL_O 0x39
2069 #define V_008DFC_SQ_IMAGE_SAMPLE_C_D_O 0x3A
2070 #define V_008DFC_SQ_IMAGE_SAMPLE_C_D_CL_O 0x3B
2071 #define V_008DFC_SQ_IMAGE_SAMPLE_C_L_O 0x3C
2072 #define V_008DFC_SQ_IMAGE_SAMPLE_C_B_O 0x3D
2073 #define V_008DFC_SQ_IMAGE_SAMPLE_C_B_CL_O 0x3E
2074 #define V_008DFC_SQ_IMAGE_SAMPLE_C_LZ_O 0x3F
2075 #define V_008DFC_SQ_IMAGE_GATHER4 0x40
2076 #define V_008DFC_SQ_IMAGE_GATHER4_CL 0x41
2077 #define V_008DFC_SQ_IMAGE_GATHER4_L 0x44
2078 #define V_008DFC_SQ_IMAGE_GATHER4_B 0x45
2079 #define V_008DFC_SQ_IMAGE_GATHER4_B_CL 0x46
2080 #define V_008DFC_SQ_IMAGE_GATHER4_LZ 0x47
2081 #define V_008DFC_SQ_IMAGE_GATHER4_C 0x48
2082 #define V_008DFC_SQ_IMAGE_GATHER4_C_CL 0x49
2083 #define V_008DFC_SQ_IMAGE_GATHER4_C_L 0x4C
2084 #define V_008DFC_SQ_IMAGE_GATHER4_C_B 0x4D
2085 #define V_008DFC_SQ_IMAGE_GATHER4_C_B_CL 0x4E
2086 #define V_008DFC_SQ_IMAGE_GATHER4_C_LZ 0x4F
2087 #define V_008DFC_SQ_IMAGE_GATHER4_O 0x50
2088 #define V_008DFC_SQ_IMAGE_GATHER4_CL_O 0x51
2089 #define V_008DFC_SQ_IMAGE_GATHER4_L_O 0x54
2090 #define V_008DFC_SQ_IMAGE_GATHER4_B_O 0x55
2091 #define V_008DFC_SQ_IMAGE_GATHER4_B_CL_O 0x56
2092 #define V_008DFC_SQ_IMAGE_GATHER4_LZ_O 0x57
2093 #define V_008DFC_SQ_IMAGE_GATHER4_C_O 0x58
2094 #define V_008DFC_SQ_IMAGE_GATHER4_C_CL_O 0x59
2095 #define V_008DFC_SQ_IMAGE_GATHER4_C_L_O 0x5C
2096 #define V_008DFC_SQ_IMAGE_GATHER4_C_B_O 0x5D
2097 #define V_008DFC_SQ_IMAGE_GATHER4_C_B_CL_O 0x5E
2098 #define V_008DFC_SQ_IMAGE_GATHER4_C_LZ_O 0x5F
2099 #define V_008DFC_SQ_IMAGE_GET_LOD 0x60
2100 #define V_008DFC_SQ_IMAGE_SAMPLE_CD 0x68
2101 #define V_008DFC_SQ_IMAGE_SAMPLE_CD_CL 0x69
2102 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD 0x6A
2103 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_CL 0x6B
2104 #define V_008DFC_SQ_IMAGE_SAMPLE_CD_O 0x6C
2105 #define V_008DFC_SQ_IMAGE_SAMPLE_CD_CL_O 0x6D
2106 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_O 0x6E
2107 #define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_CL_O 0x6F
2108 #define S_008DFC_SLC(x) (((x) & 0x1) << 25)
2109 #define G_008DFC_SLC(x) (((x) >> 25) & 0x1)
2110 #define C_008DFC_SLC 0xFDFFFFFF
2111 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
2112 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
2113 #define C_008DFC_ENCODING 0x03FFFFFF
2114 #define V_008DFC_SQ_ENC_MIMG_FIELD 0x3C
2115 #define R_008DFC_SQ_SOPP 0x008DFC
2116 #define S_008DFC_SIMM16(x) (((x) & 0xFFFF) << 0)
2117 #define G_008DFC_SIMM16(x) (((x) >> 0) & 0xFFFF)
2118 #define C_008DFC_SIMM16 0xFFFF0000
2119 #define S_008DFC_OP(x) (((x) & 0x7F) << 16)
2120 #define G_008DFC_OP(x) (((x) >> 16) & 0x7F)
2121 #define C_008DFC_OP 0xFF80FFFF
2122 #define V_008DFC_SQ_S_NOP 0x00
2123 #define V_008DFC_SQ_S_ENDPGM 0x01
2124 #define V_008DFC_SQ_S_BRANCH 0x02
2125 #define V_008DFC_SQ_S_CBRANCH_SCC0 0x04
2126 #define V_008DFC_SQ_S_CBRANCH_SCC1 0x05
2127 #define V_008DFC_SQ_S_CBRANCH_VCCZ 0x06
2128 #define V_008DFC_SQ_S_CBRANCH_VCCNZ 0x07
2129 #define V_008DFC_SQ_S_CBRANCH_EXECZ 0x08
2130 #define V_008DFC_SQ_S_CBRANCH_EXECNZ 0x09
2131 #define V_008DFC_SQ_S_BARRIER 0x0A
2132 /* CIK */
2133 #define V_008DFC_SQ_S_SETKILL 0x0B
2134 /* */
2135 #define V_008DFC_SQ_S_WAITCNT 0x0C
2136 #define V_008DFC_SQ_S_SETHALT 0x0D
2137 #define V_008DFC_SQ_S_SLEEP 0x0E
2138 #define V_008DFC_SQ_S_SETPRIO 0x0F
2139 #define V_008DFC_SQ_S_SENDMSG 0x10
2140 #define V_008DFC_SQ_S_SENDMSGHALT 0x11
2141 #define V_008DFC_SQ_S_TRAP 0x12
2142 #define V_008DFC_SQ_S_ICACHE_INV 0x13
2143 #define V_008DFC_SQ_S_INCPERFLEVEL 0x14
2144 #define V_008DFC_SQ_S_DECPERFLEVEL 0x15
2145 #define V_008DFC_SQ_S_TTRACEDATA 0x16
2146 /* CIK */
2147 #define V_008DFC_SQ_S_CBRANCH_CDBGSYS 0x17
2148 #define V_008DFC_SQ_S_CBRANCH_CDBGUSER 0x18
2149 #define V_008DFC_SQ_S_CBRANCH_CDBGSYS_OR_USER 0x19
2150 #define V_008DFC_SQ_S_CBRANCH_CDBGSYS_AND_USER 0x1A
2151 /* */
2152 #define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23)
2153 #define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF)
2154 #define C_008DFC_ENCODING 0x007FFFFF
2155 #define V_008DFC_SQ_ENC_SOPP_FIELD 0x17F
2156 #define R_008DFC_SQ_VINTRP 0x008DFC
2157 #define S_008DFC_VSRC(x) (((x) & 0xFF) << 0)
2158 #define G_008DFC_VSRC(x) (((x) >> 0) & 0xFF)
2159 #define C_008DFC_VSRC 0xFFFFFF00
2160 #define V_008DFC_SQ_VGPR 0x00
2161 #define S_008DFC_ATTRCHAN(x) (((x) & 0x03) << 8)
2162 #define G_008DFC_ATTRCHAN(x) (((x) >> 8) & 0x03)
2163 #define C_008DFC_ATTRCHAN 0xFFFFFCFF
2164 #define V_008DFC_SQ_CHAN_X 0x00
2165 #define V_008DFC_SQ_CHAN_Y 0x01
2166 #define V_008DFC_SQ_CHAN_Z 0x02
2167 #define V_008DFC_SQ_CHAN_W 0x03
2168 #define S_008DFC_ATTR(x) (((x) & 0x3F) << 10)
2169 #define G_008DFC_ATTR(x) (((x) >> 10) & 0x3F)
2170 #define C_008DFC_ATTR 0xFFFF03FF
2171 #define V_008DFC_SQ_ATTR 0x00
2172 #define S_008DFC_OP(x) (((x) & 0x03) << 16)
2173 #define G_008DFC_OP(x) (((x) >> 16) & 0x03)
2174 #define C_008DFC_OP 0xFFFCFFFF
2175 #define V_008DFC_SQ_V_INTERP_P1_F32 0x00
2176 #define V_008DFC_SQ_V_INTERP_P2_F32 0x01
2177 #define V_008DFC_SQ_V_INTERP_MOV_F32 0x02
2178 #define S_008DFC_VDST(x) (((x) & 0xFF) << 18)
2179 #define G_008DFC_VDST(x) (((x) >> 18) & 0xFF)
2180 #define C_008DFC_VDST 0xFC03FFFF
2181 #define V_008DFC_SQ_VGPR 0x00
2182 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
2183 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
2184 #define C_008DFC_ENCODING 0x03FFFFFF
2185 #define V_008DFC_SQ_ENC_VINTRP_FIELD 0x32
2186 #define R_008DFC_SQ_MTBUF_0 0x008DFC
2187 #define S_008DFC_OFFSET(x) (((x) & 0xFFF) << 0)
2188 #define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFFF)
2189 #define C_008DFC_OFFSET 0xFFFFF000
2190 #define S_008DFC_OFFEN(x) (((x) & 0x1) << 12)
2191 #define G_008DFC_OFFEN(x) (((x) >> 12) & 0x1)
2192 #define C_008DFC_OFFEN 0xFFFFEFFF
2193 #define S_008DFC_IDXEN(x) (((x) & 0x1) << 13)
2194 #define G_008DFC_IDXEN(x) (((x) >> 13) & 0x1)
2195 #define C_008DFC_IDXEN 0xFFFFDFFF
2196 #define S_008DFC_GLC(x) (((x) & 0x1) << 14)
2197 #define G_008DFC_GLC(x) (((x) >> 14) & 0x1)
2198 #define C_008DFC_GLC 0xFFFFBFFF
2199 #define S_008DFC_ADDR64(x) (((x) & 0x1) << 15)
2200 #define G_008DFC_ADDR64(x) (((x) >> 15) & 0x1)
2201 #define C_008DFC_ADDR64 0xFFFF7FFF
2202 #define S_008DFC_OP(x) (((x) & 0x07) << 16)
2203 #define G_008DFC_OP(x) (((x) >> 16) & 0x07)
2204 #define C_008DFC_OP 0xFFF8FFFF
2205 #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_X 0x00
2206 #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XY 0x01
2207 #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XYZ 0x02
2208 #define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XYZW 0x03
2209 #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_X 0x04
2210 #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XY 0x05
2211 #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XYZ 0x06
2212 #define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XYZW 0x07
2213 #define S_008DFC_DFMT(x) (((x) & 0x0F) << 19)
2214 #define G_008DFC_DFMT(x) (((x) >> 19) & 0x0F)
2215 #define C_008DFC_DFMT 0xFF87FFFF
2216 #define S_008DFC_NFMT(x) (((x) & 0x07) << 23)
2217 #define G_008DFC_NFMT(x) (((x) >> 23) & 0x07)
2218 #define C_008DFC_NFMT 0xFC7FFFFF
2219 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
2220 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
2221 #define C_008DFC_ENCODING 0x03FFFFFF
2222 #define V_008DFC_SQ_ENC_MTBUF_FIELD 0x3A
2223 #define R_008DFC_SQ_SMRD 0x008DFC
2224 #define S_008DFC_OFFSET(x) (((x) & 0xFF) << 0)
2225 #define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFF)
2226 #define C_008DFC_OFFSET 0xFFFFFF00
2227 #define V_008DFC_SQ_SGPR 0x00
2228 /* CIK */
2229 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
2230 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
2231 /* */
2232 #define V_008DFC_SQ_VCC_LO 0x6A
2233 #define V_008DFC_SQ_VCC_HI 0x6B
2234 #define V_008DFC_SQ_TBA_LO 0x6C
2235 #define V_008DFC_SQ_TBA_HI 0x6D
2236 #define V_008DFC_SQ_TMA_LO 0x6E
2237 #define V_008DFC_SQ_TMA_HI 0x6F
2238 #define V_008DFC_SQ_TTMP0 0x70
2239 #define V_008DFC_SQ_TTMP1 0x71
2240 #define V_008DFC_SQ_TTMP2 0x72
2241 #define V_008DFC_SQ_TTMP3 0x73
2242 #define V_008DFC_SQ_TTMP4 0x74
2243 #define V_008DFC_SQ_TTMP5 0x75
2244 #define V_008DFC_SQ_TTMP6 0x76
2245 #define V_008DFC_SQ_TTMP7 0x77
2246 #define V_008DFC_SQ_TTMP8 0x78
2247 #define V_008DFC_SQ_TTMP9 0x79
2248 #define V_008DFC_SQ_TTMP10 0x7A
2249 #define V_008DFC_SQ_TTMP11 0x7B
2250 /* CIK */
2251 #define V_008DFC_SQ_SRC_LITERAL 0xFF
2252 /* */
2253 #define S_008DFC_IMM(x) (((x) & 0x1) << 8)
2254 #define G_008DFC_IMM(x) (((x) >> 8) & 0x1)
2255 #define C_008DFC_IMM 0xFFFFFEFF
2256 #define S_008DFC_SBASE(x) (((x) & 0x3F) << 9)
2257 #define G_008DFC_SBASE(x) (((x) >> 9) & 0x3F)
2258 #define C_008DFC_SBASE 0xFFFF81FF
2259 #define S_008DFC_SDST(x) (((x) & 0x7F) << 15)
2260 #define G_008DFC_SDST(x) (((x) >> 15) & 0x7F)
2261 #define C_008DFC_SDST 0xFFC07FFF
2262 #define V_008DFC_SQ_SGPR 0x00
2263 /* CIK */
2264 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
2265 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
2266 /* */
2267 #define V_008DFC_SQ_VCC_LO 0x6A
2268 #define V_008DFC_SQ_VCC_HI 0x6B
2269 #define V_008DFC_SQ_TBA_LO 0x6C
2270 #define V_008DFC_SQ_TBA_HI 0x6D
2271 #define V_008DFC_SQ_TMA_LO 0x6E
2272 #define V_008DFC_SQ_TMA_HI 0x6F
2273 #define V_008DFC_SQ_TTMP0 0x70
2274 #define V_008DFC_SQ_TTMP1 0x71
2275 #define V_008DFC_SQ_TTMP2 0x72
2276 #define V_008DFC_SQ_TTMP3 0x73
2277 #define V_008DFC_SQ_TTMP4 0x74
2278 #define V_008DFC_SQ_TTMP5 0x75
2279 #define V_008DFC_SQ_TTMP6 0x76
2280 #define V_008DFC_SQ_TTMP7 0x77
2281 #define V_008DFC_SQ_TTMP8 0x78
2282 #define V_008DFC_SQ_TTMP9 0x79
2283 #define V_008DFC_SQ_TTMP10 0x7A
2284 #define V_008DFC_SQ_TTMP11 0x7B
2285 #define V_008DFC_SQ_M0 0x7C
2286 #define V_008DFC_SQ_EXEC_LO 0x7E
2287 #define V_008DFC_SQ_EXEC_HI 0x7F
2288 #define S_008DFC_OP(x) (((x) & 0x1F) << 22)
2289 #define G_008DFC_OP(x) (((x) >> 22) & 0x1F)
2290 #define C_008DFC_OP 0xF83FFFFF
2291 #define V_008DFC_SQ_S_LOAD_DWORD 0x00
2292 #define V_008DFC_SQ_S_LOAD_DWORDX2 0x01
2293 #define V_008DFC_SQ_S_LOAD_DWORDX4 0x02
2294 #define V_008DFC_SQ_S_LOAD_DWORDX8 0x03
2295 #define V_008DFC_SQ_S_LOAD_DWORDX16 0x04
2296 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORD 0x08
2297 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX2 0x09
2298 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX4 0x0A
2299 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX8 0x0B
2300 #define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX16 0x0C
2301 /* CIK */
2302 #define V_008DFC_SQ_S_DCACHE_INV_VOL 0x1D
2303 /* */
2304 #define V_008DFC_SQ_S_MEMTIME 0x1E
2305 #define V_008DFC_SQ_S_DCACHE_INV 0x1F
2306 #define S_008DFC_ENCODING(x) (((x) & 0x1F) << 27)
2307 #define G_008DFC_ENCODING(x) (((x) >> 27) & 0x1F)
2308 #define C_008DFC_ENCODING 0x07FFFFFF
2309 #define V_008DFC_SQ_ENC_SMRD_FIELD 0x18
2310 /* CIK */
2311 #define R_008DFC_SQ_FLAT_0 0x008DFC
2312 #define S_008DFC_GLC(x) (((x) & 0x1) << 16)
2313 #define G_008DFC_GLC(x) (((x) >> 16) & 0x1)
2314 #define C_008DFC_GLC 0xFFFEFFFF
2315 #define S_008DFC_SLC(x) (((x) & 0x1) << 17)
2316 #define G_008DFC_SLC(x) (((x) >> 17) & 0x1)
2317 #define C_008DFC_SLC 0xFFFDFFFF
2318 #define S_008DFC_OP(x) (((x) & 0x7F) << 18)
2319 #define G_008DFC_OP(x) (((x) >> 18) & 0x7F)
2320 #define C_008DFC_OP 0xFE03FFFF
2321 #define V_008DFC_SQ_FLAT_LOAD_UBYTE 0x08
2322 #define V_008DFC_SQ_FLAT_LOAD_SBYTE 0x09
2323 #define V_008DFC_SQ_FLAT_LOAD_USHORT 0x0A
2324 #define V_008DFC_SQ_FLAT_LOAD_SSHORT 0x0B
2325 #define V_008DFC_SQ_FLAT_LOAD_DWORD 0x0C
2326 #define V_008DFC_SQ_FLAT_LOAD_DWORDX2 0x0D
2327 #define V_008DFC_SQ_FLAT_LOAD_DWORDX4 0x0E
2328 #define V_008DFC_SQ_FLAT_LOAD_DWORDX3 0x0F
2329 #define V_008DFC_SQ_FLAT_STORE_BYTE 0x18
2330 #define V_008DFC_SQ_FLAT_STORE_SHORT 0x1A
2331 #define V_008DFC_SQ_FLAT_STORE_DWORD 0x1C
2332 #define V_008DFC_SQ_FLAT_STORE_DWORDX2 0x1D
2333 #define V_008DFC_SQ_FLAT_STORE_DWORDX4 0x1E
2334 #define V_008DFC_SQ_FLAT_STORE_DWORDX3 0x1F
2335 #define V_008DFC_SQ_FLAT_ATOMIC_SWAP 0x30
2336 #define V_008DFC_SQ_FLAT_ATOMIC_CMPSWAP 0x31
2337 #define V_008DFC_SQ_FLAT_ATOMIC_ADD 0x32
2338 #define V_008DFC_SQ_FLAT_ATOMIC_SUB 0x33
2339 #define V_008DFC_SQ_FLAT_ATOMIC_SMIN 0x35
2340 #define V_008DFC_SQ_FLAT_ATOMIC_UMIN 0x36
2341 #define V_008DFC_SQ_FLAT_ATOMIC_SMAX 0x37
2342 #define V_008DFC_SQ_FLAT_ATOMIC_UMAX 0x38
2343 #define V_008DFC_SQ_FLAT_ATOMIC_AND 0x39
2344 #define V_008DFC_SQ_FLAT_ATOMIC_OR 0x3A
2345 #define V_008DFC_SQ_FLAT_ATOMIC_XOR 0x3B
2346 #define V_008DFC_SQ_FLAT_ATOMIC_INC 0x3C
2347 #define V_008DFC_SQ_FLAT_ATOMIC_DEC 0x3D
2348 #define V_008DFC_SQ_FLAT_ATOMIC_FCMPSWAP 0x3E
2349 #define V_008DFC_SQ_FLAT_ATOMIC_FMIN 0x3F
2350 #define V_008DFC_SQ_FLAT_ATOMIC_FMAX 0x40
2351 #define V_008DFC_SQ_FLAT_ATOMIC_SWAP_X2 0x50
2352 #define V_008DFC_SQ_FLAT_ATOMIC_CMPSWAP_X2 0x51
2353 #define V_008DFC_SQ_FLAT_ATOMIC_ADD_X2 0x52
2354 #define V_008DFC_SQ_FLAT_ATOMIC_SUB_X2 0x53
2355 #define V_008DFC_SQ_FLAT_ATOMIC_SMIN_X2 0x55
2356 #define V_008DFC_SQ_FLAT_ATOMIC_UMIN_X2 0x56
2357 #define V_008DFC_SQ_FLAT_ATOMIC_SMAX_X2 0x57
2358 #define V_008DFC_SQ_FLAT_ATOMIC_UMAX_X2 0x58
2359 #define V_008DFC_SQ_FLAT_ATOMIC_AND_X2 0x59
2360 #define V_008DFC_SQ_FLAT_ATOMIC_OR_X2 0x5A
2361 #define V_008DFC_SQ_FLAT_ATOMIC_XOR_X2 0x5B
2362 #define V_008DFC_SQ_FLAT_ATOMIC_INC_X2 0x5C
2363 #define V_008DFC_SQ_FLAT_ATOMIC_DEC_X2 0x5D
2364 #define V_008DFC_SQ_FLAT_ATOMIC_FCMPSWAP_X2 0x5E
2365 #define V_008DFC_SQ_FLAT_ATOMIC_FMIN_X2 0x5F
2366 #define V_008DFC_SQ_FLAT_ATOMIC_FMAX_X2 0x60
2367 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
2368 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
2369 #define C_008DFC_ENCODING 0x03FFFFFF
2370 #define V_008DFC_SQ_ENC_FLAT_FIELD 0x37
2371 /* */
2372 #define R_008DFC_SQ_EXP_1 0x008DFC
2373 #define S_008DFC_VSRC0(x) (((x) & 0xFF) << 0)
2374 #define G_008DFC_VSRC0(x) (((x) >> 0) & 0xFF)
2375 #define C_008DFC_VSRC0 0xFFFFFF00
2376 #define V_008DFC_SQ_VGPR 0x00
2377 #define S_008DFC_VSRC1(x) (((x) & 0xFF) << 8)
2378 #define G_008DFC_VSRC1(x) (((x) >> 8) & 0xFF)
2379 #define C_008DFC_VSRC1 0xFFFF00FF
2380 #define V_008DFC_SQ_VGPR 0x00
2381 #define S_008DFC_VSRC2(x) (((x) & 0xFF) << 16)
2382 #define G_008DFC_VSRC2(x) (((x) >> 16) & 0xFF)
2383 #define C_008DFC_VSRC2 0xFF00FFFF
2384 #define V_008DFC_SQ_VGPR 0x00
2385 #define S_008DFC_VSRC3(x) (((x) & 0xFF) << 24)
2386 #define G_008DFC_VSRC3(x) (((x) >> 24) & 0xFF)
2387 #define C_008DFC_VSRC3 0x00FFFFFF
2388 #define V_008DFC_SQ_VGPR 0x00
2389 #define R_008DFC_SQ_DS_1 0x008DFC
2390 #define S_008DFC_ADDR(x) (((x) & 0xFF) << 0)
2391 #define G_008DFC_ADDR(x) (((x) >> 0) & 0xFF)
2392 #define C_008DFC_ADDR 0xFFFFFF00
2393 #define V_008DFC_SQ_VGPR 0x00
2394 #define S_008DFC_DATA0(x) (((x) & 0xFF) << 8)
2395 #define G_008DFC_DATA0(x) (((x) >> 8) & 0xFF)
2396 #define C_008DFC_DATA0 0xFFFF00FF
2397 #define V_008DFC_SQ_VGPR 0x00
2398 #define S_008DFC_DATA1(x) (((x) & 0xFF) << 16)
2399 #define G_008DFC_DATA1(x) (((x) >> 16) & 0xFF)
2400 #define C_008DFC_DATA1 0xFF00FFFF
2401 #define V_008DFC_SQ_VGPR 0x00
2402 #define S_008DFC_VDST(x) (((x) & 0xFF) << 24)
2403 #define G_008DFC_VDST(x) (((x) >> 24) & 0xFF)
2404 #define C_008DFC_VDST 0x00FFFFFF
2405 #define V_008DFC_SQ_VGPR 0x00
2406 #define R_008DFC_SQ_VOPC 0x008DFC
2407 #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0)
2408 #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF)
2409 #define C_008DFC_SRC0 0xFFFFFE00
2410 #define V_008DFC_SQ_SGPR 0x00
2411 #define V_008DFC_SQ_VCC_LO 0x6A
2412 #define V_008DFC_SQ_VCC_HI 0x6B
2413 #define V_008DFC_SQ_TBA_LO 0x6C
2414 #define V_008DFC_SQ_TBA_HI 0x6D
2415 #define V_008DFC_SQ_TMA_LO 0x6E
2416 #define V_008DFC_SQ_TMA_HI 0x6F
2417 #define V_008DFC_SQ_TTMP0 0x70
2418 #define V_008DFC_SQ_TTMP1 0x71
2419 #define V_008DFC_SQ_TTMP2 0x72
2420 #define V_008DFC_SQ_TTMP3 0x73
2421 #define V_008DFC_SQ_TTMP4 0x74
2422 #define V_008DFC_SQ_TTMP5 0x75
2423 #define V_008DFC_SQ_TTMP6 0x76
2424 #define V_008DFC_SQ_TTMP7 0x77
2425 #define V_008DFC_SQ_TTMP8 0x78
2426 #define V_008DFC_SQ_TTMP9 0x79
2427 #define V_008DFC_SQ_TTMP10 0x7A
2428 #define V_008DFC_SQ_TTMP11 0x7B
2429 #define V_008DFC_SQ_M0 0x7C
2430 #define V_008DFC_SQ_EXEC_LO 0x7E
2431 #define V_008DFC_SQ_EXEC_HI 0x7F
2432 #define V_008DFC_SQ_SRC_0 0x80
2433 #define V_008DFC_SQ_SRC_1_INT 0x81
2434 #define V_008DFC_SQ_SRC_2_INT 0x82
2435 #define V_008DFC_SQ_SRC_3_INT 0x83
2436 #define V_008DFC_SQ_SRC_4_INT 0x84
2437 #define V_008DFC_SQ_SRC_5_INT 0x85
2438 #define V_008DFC_SQ_SRC_6_INT 0x86
2439 #define V_008DFC_SQ_SRC_7_INT 0x87
2440 #define V_008DFC_SQ_SRC_8_INT 0x88
2441 #define V_008DFC_SQ_SRC_9_INT 0x89
2442 #define V_008DFC_SQ_SRC_10_INT 0x8A
2443 #define V_008DFC_SQ_SRC_11_INT 0x8B
2444 #define V_008DFC_SQ_SRC_12_INT 0x8C
2445 #define V_008DFC_SQ_SRC_13_INT 0x8D
2446 #define V_008DFC_SQ_SRC_14_INT 0x8E
2447 #define V_008DFC_SQ_SRC_15_INT 0x8F
2448 #define V_008DFC_SQ_SRC_16_INT 0x90
2449 #define V_008DFC_SQ_SRC_17_INT 0x91
2450 #define V_008DFC_SQ_SRC_18_INT 0x92
2451 #define V_008DFC_SQ_SRC_19_INT 0x93
2452 #define V_008DFC_SQ_SRC_20_INT 0x94
2453 #define V_008DFC_SQ_SRC_21_INT 0x95
2454 #define V_008DFC_SQ_SRC_22_INT 0x96
2455 #define V_008DFC_SQ_SRC_23_INT 0x97
2456 #define V_008DFC_SQ_SRC_24_INT 0x98
2457 #define V_008DFC_SQ_SRC_25_INT 0x99
2458 #define V_008DFC_SQ_SRC_26_INT 0x9A
2459 #define V_008DFC_SQ_SRC_27_INT 0x9B
2460 #define V_008DFC_SQ_SRC_28_INT 0x9C
2461 #define V_008DFC_SQ_SRC_29_INT 0x9D
2462 #define V_008DFC_SQ_SRC_30_INT 0x9E
2463 #define V_008DFC_SQ_SRC_31_INT 0x9F
2464 #define V_008DFC_SQ_SRC_32_INT 0xA0
2465 #define V_008DFC_SQ_SRC_33_INT 0xA1
2466 #define V_008DFC_SQ_SRC_34_INT 0xA2
2467 #define V_008DFC_SQ_SRC_35_INT 0xA3
2468 #define V_008DFC_SQ_SRC_36_INT 0xA4
2469 #define V_008DFC_SQ_SRC_37_INT 0xA5
2470 #define V_008DFC_SQ_SRC_38_INT 0xA6
2471 #define V_008DFC_SQ_SRC_39_INT 0xA7
2472 #define V_008DFC_SQ_SRC_40_INT 0xA8
2473 #define V_008DFC_SQ_SRC_41_INT 0xA9
2474 #define V_008DFC_SQ_SRC_42_INT 0xAA
2475 #define V_008DFC_SQ_SRC_43_INT 0xAB
2476 #define V_008DFC_SQ_SRC_44_INT 0xAC
2477 #define V_008DFC_SQ_SRC_45_INT 0xAD
2478 #define V_008DFC_SQ_SRC_46_INT 0xAE
2479 #define V_008DFC_SQ_SRC_47_INT 0xAF
2480 #define V_008DFC_SQ_SRC_48_INT 0xB0
2481 #define V_008DFC_SQ_SRC_49_INT 0xB1
2482 #define V_008DFC_SQ_SRC_50_INT 0xB2
2483 #define V_008DFC_SQ_SRC_51_INT 0xB3
2484 #define V_008DFC_SQ_SRC_52_INT 0xB4
2485 #define V_008DFC_SQ_SRC_53_INT 0xB5
2486 #define V_008DFC_SQ_SRC_54_INT 0xB6
2487 #define V_008DFC_SQ_SRC_55_INT 0xB7
2488 #define V_008DFC_SQ_SRC_56_INT 0xB8
2489 #define V_008DFC_SQ_SRC_57_INT 0xB9
2490 #define V_008DFC_SQ_SRC_58_INT 0xBA
2491 #define V_008DFC_SQ_SRC_59_INT 0xBB
2492 #define V_008DFC_SQ_SRC_60_INT 0xBC
2493 #define V_008DFC_SQ_SRC_61_INT 0xBD
2494 #define V_008DFC_SQ_SRC_62_INT 0xBE
2495 #define V_008DFC_SQ_SRC_63_INT 0xBF
2496 #define V_008DFC_SQ_SRC_64_INT 0xC0
2497 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
2498 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
2499 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
2500 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
2501 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
2502 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
2503 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
2504 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
2505 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
2506 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
2507 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
2508 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
2509 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
2510 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
2511 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
2512 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
2513 #define V_008DFC_SQ_SRC_0_5 0xF0
2514 #define V_008DFC_SQ_SRC_M_0_5 0xF1
2515 #define V_008DFC_SQ_SRC_1 0xF2
2516 #define V_008DFC_SQ_SRC_M_1 0xF3
2517 #define V_008DFC_SQ_SRC_2 0xF4
2518 #define V_008DFC_SQ_SRC_M_2 0xF5
2519 #define V_008DFC_SQ_SRC_4 0xF6
2520 #define V_008DFC_SQ_SRC_M_4 0xF7
2521 #define V_008DFC_SQ_SRC_VCCZ 0xFB
2522 #define V_008DFC_SQ_SRC_EXECZ 0xFC
2523 #define V_008DFC_SQ_SRC_SCC 0xFD
2524 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
2525 #define V_008DFC_SQ_SRC_VGPR 0x100
2526 #define S_008DFC_VSRC1(x) (((x) & 0xFF) << 9)
2527 #define G_008DFC_VSRC1(x) (((x) >> 9) & 0xFF)
2528 #define C_008DFC_VSRC1 0xFFFE01FF
2529 #define V_008DFC_SQ_VGPR 0x00
2530 #define S_008DFC_OP(x) (((x) & 0xFF) << 17)
2531 #define G_008DFC_OP(x) (((x) >> 17) & 0xFF)
2532 #define C_008DFC_OP 0xFE01FFFF
2533 #define V_008DFC_SQ_V_CMP_F_F32 0x00
2534 #define V_008DFC_SQ_V_CMP_LT_F32 0x01
2535 #define V_008DFC_SQ_V_CMP_EQ_F32 0x02
2536 #define V_008DFC_SQ_V_CMP_LE_F32 0x03
2537 #define V_008DFC_SQ_V_CMP_GT_F32 0x04
2538 #define V_008DFC_SQ_V_CMP_LG_F32 0x05
2539 #define V_008DFC_SQ_V_CMP_GE_F32 0x06
2540 #define V_008DFC_SQ_V_CMP_O_F32 0x07
2541 #define V_008DFC_SQ_V_CMP_U_F32 0x08
2542 #define V_008DFC_SQ_V_CMP_NGE_F32 0x09
2543 #define V_008DFC_SQ_V_CMP_NLG_F32 0x0A
2544 #define V_008DFC_SQ_V_CMP_NGT_F32 0x0B
2545 #define V_008DFC_SQ_V_CMP_NLE_F32 0x0C
2546 #define V_008DFC_SQ_V_CMP_NEQ_F32 0x0D
2547 #define V_008DFC_SQ_V_CMP_NLT_F32 0x0E
2548 #define V_008DFC_SQ_V_CMP_TRU_F32 0x0F
2549 #define V_008DFC_SQ_V_CMPX_F_F32 0x10
2550 #define V_008DFC_SQ_V_CMPX_LT_F32 0x11
2551 #define V_008DFC_SQ_V_CMPX_EQ_F32 0x12
2552 #define V_008DFC_SQ_V_CMPX_LE_F32 0x13
2553 #define V_008DFC_SQ_V_CMPX_GT_F32 0x14
2554 #define V_008DFC_SQ_V_CMPX_LG_F32 0x15
2555 #define V_008DFC_SQ_V_CMPX_GE_F32 0x16
2556 #define V_008DFC_SQ_V_CMPX_O_F32 0x17
2557 #define V_008DFC_SQ_V_CMPX_U_F32 0x18
2558 #define V_008DFC_SQ_V_CMPX_NGE_F32 0x19
2559 #define V_008DFC_SQ_V_CMPX_NLG_F32 0x1A
2560 #define V_008DFC_SQ_V_CMPX_NGT_F32 0x1B
2561 #define V_008DFC_SQ_V_CMPX_NLE_F32 0x1C
2562 #define V_008DFC_SQ_V_CMPX_NEQ_F32 0x1D
2563 #define V_008DFC_SQ_V_CMPX_NLT_F32 0x1E
2564 #define V_008DFC_SQ_V_CMPX_TRU_F32 0x1F
2565 #define V_008DFC_SQ_V_CMP_F_F64 0x20
2566 #define V_008DFC_SQ_V_CMP_LT_F64 0x21
2567 #define V_008DFC_SQ_V_CMP_EQ_F64 0x22
2568 #define V_008DFC_SQ_V_CMP_LE_F64 0x23
2569 #define V_008DFC_SQ_V_CMP_GT_F64 0x24
2570 #define V_008DFC_SQ_V_CMP_LG_F64 0x25
2571 #define V_008DFC_SQ_V_CMP_GE_F64 0x26
2572 #define V_008DFC_SQ_V_CMP_O_F64 0x27
2573 #define V_008DFC_SQ_V_CMP_U_F64 0x28
2574 #define V_008DFC_SQ_V_CMP_NGE_F64 0x29
2575 #define V_008DFC_SQ_V_CMP_NLG_F64 0x2A
2576 #define V_008DFC_SQ_V_CMP_NGT_F64 0x2B
2577 #define V_008DFC_SQ_V_CMP_NLE_F64 0x2C
2578 #define V_008DFC_SQ_V_CMP_NEQ_F64 0x2D
2579 #define V_008DFC_SQ_V_CMP_NLT_F64 0x2E
2580 #define V_008DFC_SQ_V_CMP_TRU_F64 0x2F
2581 #define V_008DFC_SQ_V_CMPX_F_F64 0x30
2582 #define V_008DFC_SQ_V_CMPX_LT_F64 0x31
2583 #define V_008DFC_SQ_V_CMPX_EQ_F64 0x32
2584 #define V_008DFC_SQ_V_CMPX_LE_F64 0x33
2585 #define V_008DFC_SQ_V_CMPX_GT_F64 0x34
2586 #define V_008DFC_SQ_V_CMPX_LG_F64 0x35
2587 #define V_008DFC_SQ_V_CMPX_GE_F64 0x36
2588 #define V_008DFC_SQ_V_CMPX_O_F64 0x37
2589 #define V_008DFC_SQ_V_CMPX_U_F64 0x38
2590 #define V_008DFC_SQ_V_CMPX_NGE_F64 0x39
2591 #define V_008DFC_SQ_V_CMPX_NLG_F64 0x3A
2592 #define V_008DFC_SQ_V_CMPX_NGT_F64 0x3B
2593 #define V_008DFC_SQ_V_CMPX_NLE_F64 0x3C
2594 #define V_008DFC_SQ_V_CMPX_NEQ_F64 0x3D
2595 #define V_008DFC_SQ_V_CMPX_NLT_F64 0x3E
2596 #define V_008DFC_SQ_V_CMPX_TRU_F64 0x3F
2597 #define V_008DFC_SQ_V_CMPS_F_F32 0x40
2598 #define V_008DFC_SQ_V_CMPS_LT_F32 0x41
2599 #define V_008DFC_SQ_V_CMPS_EQ_F32 0x42
2600 #define V_008DFC_SQ_V_CMPS_LE_F32 0x43
2601 #define V_008DFC_SQ_V_CMPS_GT_F32 0x44
2602 #define V_008DFC_SQ_V_CMPS_LG_F32 0x45
2603 #define V_008DFC_SQ_V_CMPS_GE_F32 0x46
2604 #define V_008DFC_SQ_V_CMPS_O_F32 0x47
2605 #define V_008DFC_SQ_V_CMPS_U_F32 0x48
2606 #define V_008DFC_SQ_V_CMPS_NGE_F32 0x49
2607 #define V_008DFC_SQ_V_CMPS_NLG_F32 0x4A
2608 #define V_008DFC_SQ_V_CMPS_NGT_F32 0x4B
2609 #define V_008DFC_SQ_V_CMPS_NLE_F32 0x4C
2610 #define V_008DFC_SQ_V_CMPS_NEQ_F32 0x4D
2611 #define V_008DFC_SQ_V_CMPS_NLT_F32 0x4E
2612 #define V_008DFC_SQ_V_CMPS_TRU_F32 0x4F
2613 #define V_008DFC_SQ_V_CMPSX_F_F32 0x50
2614 #define V_008DFC_SQ_V_CMPSX_LT_F32 0x51
2615 #define V_008DFC_SQ_V_CMPSX_EQ_F32 0x52
2616 #define V_008DFC_SQ_V_CMPSX_LE_F32 0x53
2617 #define V_008DFC_SQ_V_CMPSX_GT_F32 0x54
2618 #define V_008DFC_SQ_V_CMPSX_LG_F32 0x55
2619 #define V_008DFC_SQ_V_CMPSX_GE_F32 0x56
2620 #define V_008DFC_SQ_V_CMPSX_O_F32 0x57
2621 #define V_008DFC_SQ_V_CMPSX_U_F32 0x58
2622 #define V_008DFC_SQ_V_CMPSX_NGE_F32 0x59
2623 #define V_008DFC_SQ_V_CMPSX_NLG_F32 0x5A
2624 #define V_008DFC_SQ_V_CMPSX_NGT_F32 0x5B
2625 #define V_008DFC_SQ_V_CMPSX_NLE_F32 0x5C
2626 #define V_008DFC_SQ_V_CMPSX_NEQ_F32 0x5D
2627 #define V_008DFC_SQ_V_CMPSX_NLT_F32 0x5E
2628 #define V_008DFC_SQ_V_CMPSX_TRU_F32 0x5F
2629 #define V_008DFC_SQ_V_CMPS_F_F64 0x60
2630 #define V_008DFC_SQ_V_CMPS_LT_F64 0x61
2631 #define V_008DFC_SQ_V_CMPS_EQ_F64 0x62
2632 #define V_008DFC_SQ_V_CMPS_LE_F64 0x63
2633 #define V_008DFC_SQ_V_CMPS_GT_F64 0x64
2634 #define V_008DFC_SQ_V_CMPS_LG_F64 0x65
2635 #define V_008DFC_SQ_V_CMPS_GE_F64 0x66
2636 #define V_008DFC_SQ_V_CMPS_O_F64 0x67
2637 #define V_008DFC_SQ_V_CMPS_U_F64 0x68
2638 #define V_008DFC_SQ_V_CMPS_NGE_F64 0x69
2639 #define V_008DFC_SQ_V_CMPS_NLG_F64 0x6A
2640 #define V_008DFC_SQ_V_CMPS_NGT_F64 0x6B
2641 #define V_008DFC_SQ_V_CMPS_NLE_F64 0x6C
2642 #define V_008DFC_SQ_V_CMPS_NEQ_F64 0x6D
2643 #define V_008DFC_SQ_V_CMPS_NLT_F64 0x6E
2644 #define V_008DFC_SQ_V_CMPS_TRU_F64 0x6F
2645 #define V_008DFC_SQ_V_CMPSX_F_F64 0x70
2646 #define V_008DFC_SQ_V_CMPSX_LT_F64 0x71
2647 #define V_008DFC_SQ_V_CMPSX_EQ_F64 0x72
2648 #define V_008DFC_SQ_V_CMPSX_LE_F64 0x73
2649 #define V_008DFC_SQ_V_CMPSX_GT_F64 0x74
2650 #define V_008DFC_SQ_V_CMPSX_LG_F64 0x75
2651 #define V_008DFC_SQ_V_CMPSX_GE_F64 0x76
2652 #define V_008DFC_SQ_V_CMPSX_O_F64 0x77
2653 #define V_008DFC_SQ_V_CMPSX_U_F64 0x78
2654 #define V_008DFC_SQ_V_CMPSX_NGE_F64 0x79
2655 #define V_008DFC_SQ_V_CMPSX_NLG_F64 0x7A
2656 #define V_008DFC_SQ_V_CMPSX_NGT_F64 0x7B
2657 #define V_008DFC_SQ_V_CMPSX_NLE_F64 0x7C
2658 #define V_008DFC_SQ_V_CMPSX_NEQ_F64 0x7D
2659 #define V_008DFC_SQ_V_CMPSX_NLT_F64 0x7E
2660 #define V_008DFC_SQ_V_CMPSX_TRU_F64 0x7F
2661 #define V_008DFC_SQ_V_CMP_F_I32 0x80
2662 #define V_008DFC_SQ_V_CMP_LT_I32 0x81
2663 #define V_008DFC_SQ_V_CMP_EQ_I32 0x82
2664 #define V_008DFC_SQ_V_CMP_LE_I32 0x83
2665 #define V_008DFC_SQ_V_CMP_GT_I32 0x84
2666 #define V_008DFC_SQ_V_CMP_NE_I32 0x85
2667 #define V_008DFC_SQ_V_CMP_GE_I32 0x86
2668 #define V_008DFC_SQ_V_CMP_T_I32 0x87
2669 #define V_008DFC_SQ_V_CMP_CLASS_F32 0x88
2670 #define V_008DFC_SQ_V_CMPX_F_I32 0x90
2671 #define V_008DFC_SQ_V_CMPX_LT_I32 0x91
2672 #define V_008DFC_SQ_V_CMPX_EQ_I32 0x92
2673 #define V_008DFC_SQ_V_CMPX_LE_I32 0x93
2674 #define V_008DFC_SQ_V_CMPX_GT_I32 0x94
2675 #define V_008DFC_SQ_V_CMPX_NE_I32 0x95
2676 #define V_008DFC_SQ_V_CMPX_GE_I32 0x96
2677 #define V_008DFC_SQ_V_CMPX_T_I32 0x97
2678 #define V_008DFC_SQ_V_CMPX_CLASS_F32 0x98
2679 #define V_008DFC_SQ_V_CMP_F_I64 0xA0
2680 #define V_008DFC_SQ_V_CMP_LT_I64 0xA1
2681 #define V_008DFC_SQ_V_CMP_EQ_I64 0xA2
2682 #define V_008DFC_SQ_V_CMP_LE_I64 0xA3
2683 #define V_008DFC_SQ_V_CMP_GT_I64 0xA4
2684 #define V_008DFC_SQ_V_CMP_NE_I64 0xA5
2685 #define V_008DFC_SQ_V_CMP_GE_I64 0xA6
2686 #define V_008DFC_SQ_V_CMP_T_I64 0xA7
2687 #define V_008DFC_SQ_V_CMP_CLASS_F64 0xA8
2688 #define V_008DFC_SQ_V_CMPX_F_I64 0xB0
2689 #define V_008DFC_SQ_V_CMPX_LT_I64 0xB1
2690 #define V_008DFC_SQ_V_CMPX_EQ_I64 0xB2
2691 #define V_008DFC_SQ_V_CMPX_LE_I64 0xB3
2692 #define V_008DFC_SQ_V_CMPX_GT_I64 0xB4
2693 #define V_008DFC_SQ_V_CMPX_NE_I64 0xB5
2694 #define V_008DFC_SQ_V_CMPX_GE_I64 0xB6
2695 #define V_008DFC_SQ_V_CMPX_T_I64 0xB7
2696 #define V_008DFC_SQ_V_CMPX_CLASS_F64 0xB8
2697 #define V_008DFC_SQ_V_CMP_F_U32 0xC0
2698 #define V_008DFC_SQ_V_CMP_LT_U32 0xC1
2699 #define V_008DFC_SQ_V_CMP_EQ_U32 0xC2
2700 #define V_008DFC_SQ_V_CMP_LE_U32 0xC3
2701 #define V_008DFC_SQ_V_CMP_GT_U32 0xC4
2702 #define V_008DFC_SQ_V_CMP_NE_U32 0xC5
2703 #define V_008DFC_SQ_V_CMP_GE_U32 0xC6
2704 #define V_008DFC_SQ_V_CMP_T_U32 0xC7
2705 #define V_008DFC_SQ_V_CMPX_F_U32 0xD0
2706 #define V_008DFC_SQ_V_CMPX_LT_U32 0xD1
2707 #define V_008DFC_SQ_V_CMPX_EQ_U32 0xD2
2708 #define V_008DFC_SQ_V_CMPX_LE_U32 0xD3
2709 #define V_008DFC_SQ_V_CMPX_GT_U32 0xD4
2710 #define V_008DFC_SQ_V_CMPX_NE_U32 0xD5
2711 #define V_008DFC_SQ_V_CMPX_GE_U32 0xD6
2712 #define V_008DFC_SQ_V_CMPX_T_U32 0xD7
2713 #define V_008DFC_SQ_V_CMP_F_U64 0xE0
2714 #define V_008DFC_SQ_V_CMP_LT_U64 0xE1
2715 #define V_008DFC_SQ_V_CMP_EQ_U64 0xE2
2716 #define V_008DFC_SQ_V_CMP_LE_U64 0xE3
2717 #define V_008DFC_SQ_V_CMP_GT_U64 0xE4
2718 #define V_008DFC_SQ_V_CMP_NE_U64 0xE5
2719 #define V_008DFC_SQ_V_CMP_GE_U64 0xE6
2720 #define V_008DFC_SQ_V_CMP_T_U64 0xE7
2721 #define V_008DFC_SQ_V_CMPX_F_U64 0xF0
2722 #define V_008DFC_SQ_V_CMPX_LT_U64 0xF1
2723 #define V_008DFC_SQ_V_CMPX_EQ_U64 0xF2
2724 #define V_008DFC_SQ_V_CMPX_LE_U64 0xF3
2725 #define V_008DFC_SQ_V_CMPX_GT_U64 0xF4
2726 #define V_008DFC_SQ_V_CMPX_NE_U64 0xF5
2727 #define V_008DFC_SQ_V_CMPX_GE_U64 0xF6
2728 #define V_008DFC_SQ_V_CMPX_T_U64 0xF7
2729 #define S_008DFC_ENCODING(x) (((x) & 0x7F) << 25)
2730 #define G_008DFC_ENCODING(x) (((x) >> 25) & 0x7F)
2731 #define C_008DFC_ENCODING 0x01FFFFFF
2732 #define V_008DFC_SQ_ENC_VOPC_FIELD 0x3E
2733 #define R_008DFC_SQ_SOP1 0x008DFC
2734 #define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0)
2735 #define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF)
2736 #define C_008DFC_SSRC0 0xFFFFFF00
2737 #define V_008DFC_SQ_SGPR 0x00
2738 /* CIK */
2739 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
2740 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
2741 /* */
2742 #define V_008DFC_SQ_VCC_LO 0x6A
2743 #define V_008DFC_SQ_VCC_HI 0x6B
2744 #define V_008DFC_SQ_TBA_LO 0x6C
2745 #define V_008DFC_SQ_TBA_HI 0x6D
2746 #define V_008DFC_SQ_TMA_LO 0x6E
2747 #define V_008DFC_SQ_TMA_HI 0x6F
2748 #define V_008DFC_SQ_TTMP0 0x70
2749 #define V_008DFC_SQ_TTMP1 0x71
2750 #define V_008DFC_SQ_TTMP2 0x72
2751 #define V_008DFC_SQ_TTMP3 0x73
2752 #define V_008DFC_SQ_TTMP4 0x74
2753 #define V_008DFC_SQ_TTMP5 0x75
2754 #define V_008DFC_SQ_TTMP6 0x76
2755 #define V_008DFC_SQ_TTMP7 0x77
2756 #define V_008DFC_SQ_TTMP8 0x78
2757 #define V_008DFC_SQ_TTMP9 0x79
2758 #define V_008DFC_SQ_TTMP10 0x7A
2759 #define V_008DFC_SQ_TTMP11 0x7B
2760 #define V_008DFC_SQ_M0 0x7C
2761 #define V_008DFC_SQ_EXEC_LO 0x7E
2762 #define V_008DFC_SQ_EXEC_HI 0x7F
2763 #define V_008DFC_SQ_SRC_0 0x80
2764 #define V_008DFC_SQ_SRC_1_INT 0x81
2765 #define V_008DFC_SQ_SRC_2_INT 0x82
2766 #define V_008DFC_SQ_SRC_3_INT 0x83
2767 #define V_008DFC_SQ_SRC_4_INT 0x84
2768 #define V_008DFC_SQ_SRC_5_INT 0x85
2769 #define V_008DFC_SQ_SRC_6_INT 0x86
2770 #define V_008DFC_SQ_SRC_7_INT 0x87
2771 #define V_008DFC_SQ_SRC_8_INT 0x88
2772 #define V_008DFC_SQ_SRC_9_INT 0x89
2773 #define V_008DFC_SQ_SRC_10_INT 0x8A
2774 #define V_008DFC_SQ_SRC_11_INT 0x8B
2775 #define V_008DFC_SQ_SRC_12_INT 0x8C
2776 #define V_008DFC_SQ_SRC_13_INT 0x8D
2777 #define V_008DFC_SQ_SRC_14_INT 0x8E
2778 #define V_008DFC_SQ_SRC_15_INT 0x8F
2779 #define V_008DFC_SQ_SRC_16_INT 0x90
2780 #define V_008DFC_SQ_SRC_17_INT 0x91
2781 #define V_008DFC_SQ_SRC_18_INT 0x92
2782 #define V_008DFC_SQ_SRC_19_INT 0x93
2783 #define V_008DFC_SQ_SRC_20_INT 0x94
2784 #define V_008DFC_SQ_SRC_21_INT 0x95
2785 #define V_008DFC_SQ_SRC_22_INT 0x96
2786 #define V_008DFC_SQ_SRC_23_INT 0x97
2787 #define V_008DFC_SQ_SRC_24_INT 0x98
2788 #define V_008DFC_SQ_SRC_25_INT 0x99
2789 #define V_008DFC_SQ_SRC_26_INT 0x9A
2790 #define V_008DFC_SQ_SRC_27_INT 0x9B
2791 #define V_008DFC_SQ_SRC_28_INT 0x9C
2792 #define V_008DFC_SQ_SRC_29_INT 0x9D
2793 #define V_008DFC_SQ_SRC_30_INT 0x9E
2794 #define V_008DFC_SQ_SRC_31_INT 0x9F
2795 #define V_008DFC_SQ_SRC_32_INT 0xA0
2796 #define V_008DFC_SQ_SRC_33_INT 0xA1
2797 #define V_008DFC_SQ_SRC_34_INT 0xA2
2798 #define V_008DFC_SQ_SRC_35_INT 0xA3
2799 #define V_008DFC_SQ_SRC_36_INT 0xA4
2800 #define V_008DFC_SQ_SRC_37_INT 0xA5
2801 #define V_008DFC_SQ_SRC_38_INT 0xA6
2802 #define V_008DFC_SQ_SRC_39_INT 0xA7
2803 #define V_008DFC_SQ_SRC_40_INT 0xA8
2804 #define V_008DFC_SQ_SRC_41_INT 0xA9
2805 #define V_008DFC_SQ_SRC_42_INT 0xAA
2806 #define V_008DFC_SQ_SRC_43_INT 0xAB
2807 #define V_008DFC_SQ_SRC_44_INT 0xAC
2808 #define V_008DFC_SQ_SRC_45_INT 0xAD
2809 #define V_008DFC_SQ_SRC_46_INT 0xAE
2810 #define V_008DFC_SQ_SRC_47_INT 0xAF
2811 #define V_008DFC_SQ_SRC_48_INT 0xB0
2812 #define V_008DFC_SQ_SRC_49_INT 0xB1
2813 #define V_008DFC_SQ_SRC_50_INT 0xB2
2814 #define V_008DFC_SQ_SRC_51_INT 0xB3
2815 #define V_008DFC_SQ_SRC_52_INT 0xB4
2816 #define V_008DFC_SQ_SRC_53_INT 0xB5
2817 #define V_008DFC_SQ_SRC_54_INT 0xB6
2818 #define V_008DFC_SQ_SRC_55_INT 0xB7
2819 #define V_008DFC_SQ_SRC_56_INT 0xB8
2820 #define V_008DFC_SQ_SRC_57_INT 0xB9
2821 #define V_008DFC_SQ_SRC_58_INT 0xBA
2822 #define V_008DFC_SQ_SRC_59_INT 0xBB
2823 #define V_008DFC_SQ_SRC_60_INT 0xBC
2824 #define V_008DFC_SQ_SRC_61_INT 0xBD
2825 #define V_008DFC_SQ_SRC_62_INT 0xBE
2826 #define V_008DFC_SQ_SRC_63_INT 0xBF
2827 #define V_008DFC_SQ_SRC_64_INT 0xC0
2828 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
2829 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
2830 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
2831 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
2832 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
2833 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
2834 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
2835 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
2836 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
2837 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
2838 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
2839 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
2840 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
2841 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
2842 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
2843 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
2844 #define V_008DFC_SQ_SRC_0_5 0xF0
2845 #define V_008DFC_SQ_SRC_M_0_5 0xF1
2846 #define V_008DFC_SQ_SRC_1 0xF2
2847 #define V_008DFC_SQ_SRC_M_1 0xF3
2848 #define V_008DFC_SQ_SRC_2 0xF4
2849 #define V_008DFC_SQ_SRC_M_2 0xF5
2850 #define V_008DFC_SQ_SRC_4 0xF6
2851 #define V_008DFC_SQ_SRC_M_4 0xF7
2852 #define V_008DFC_SQ_SRC_VCCZ 0xFB
2853 #define V_008DFC_SQ_SRC_EXECZ 0xFC
2854 #define V_008DFC_SQ_SRC_SCC 0xFD
2855 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
2856 #define S_008DFC_OP(x) (((x) & 0xFF) << 8)
2857 #define G_008DFC_OP(x) (((x) >> 8) & 0xFF)
2858 #define C_008DFC_OP 0xFFFF00FF
2859 #define V_008DFC_SQ_S_MOV_B32 0x03
2860 #define V_008DFC_SQ_S_MOV_B64 0x04
2861 #define V_008DFC_SQ_S_CMOV_B32 0x05
2862 #define V_008DFC_SQ_S_CMOV_B64 0x06
2863 #define V_008DFC_SQ_S_NOT_B32 0x07
2864 #define V_008DFC_SQ_S_NOT_B64 0x08
2865 #define V_008DFC_SQ_S_WQM_B32 0x09
2866 #define V_008DFC_SQ_S_WQM_B64 0x0A
2867 #define V_008DFC_SQ_S_BREV_B32 0x0B
2868 #define V_008DFC_SQ_S_BREV_B64 0x0C
2869 #define V_008DFC_SQ_S_BCNT0_I32_B32 0x0D
2870 #define V_008DFC_SQ_S_BCNT0_I32_B64 0x0E
2871 #define V_008DFC_SQ_S_BCNT1_I32_B32 0x0F
2872 #define V_008DFC_SQ_S_BCNT1_I32_B64 0x10
2873 #define V_008DFC_SQ_S_FF0_I32_B32 0x11
2874 #define V_008DFC_SQ_S_FF0_I32_B64 0x12
2875 #define V_008DFC_SQ_S_FF1_I32_B32 0x13
2876 #define V_008DFC_SQ_S_FF1_I32_B64 0x14
2877 #define V_008DFC_SQ_S_FLBIT_I32_B32 0x15
2878 #define V_008DFC_SQ_S_FLBIT_I32_B64 0x16
2879 #define V_008DFC_SQ_S_FLBIT_I32 0x17
2880 #define V_008DFC_SQ_S_FLBIT_I32_I64 0x18
2881 #define V_008DFC_SQ_S_SEXT_I32_I8 0x19
2882 #define V_008DFC_SQ_S_SEXT_I32_I16 0x1A
2883 #define V_008DFC_SQ_S_BITSET0_B32 0x1B
2884 #define V_008DFC_SQ_S_BITSET0_B64 0x1C
2885 #define V_008DFC_SQ_S_BITSET1_B32 0x1D
2886 #define V_008DFC_SQ_S_BITSET1_B64 0x1E
2887 #define V_008DFC_SQ_S_GETPC_B64 0x1F
2888 #define V_008DFC_SQ_S_SETPC_B64 0x20
2889 #define V_008DFC_SQ_S_SWAPPC_B64 0x21
2890 #define V_008DFC_SQ_S_RFE_B64 0x22
2891 #define V_008DFC_SQ_S_AND_SAVEEXEC_B64 0x24
2892 #define V_008DFC_SQ_S_OR_SAVEEXEC_B64 0x25
2893 #define V_008DFC_SQ_S_XOR_SAVEEXEC_B64 0x26
2894 #define V_008DFC_SQ_S_ANDN2_SAVEEXEC_B64 0x27
2895 #define V_008DFC_SQ_S_ORN2_SAVEEXEC_B64 0x28
2896 #define V_008DFC_SQ_S_NAND_SAVEEXEC_B64 0x29
2897 #define V_008DFC_SQ_S_NOR_SAVEEXEC_B64 0x2A
2898 #define V_008DFC_SQ_S_XNOR_SAVEEXEC_B64 0x2B
2899 #define V_008DFC_SQ_S_QUADMASK_B32 0x2C
2900 #define V_008DFC_SQ_S_QUADMASK_B64 0x2D
2901 #define V_008DFC_SQ_S_MOVRELS_B32 0x2E
2902 #define V_008DFC_SQ_S_MOVRELS_B64 0x2F
2903 #define V_008DFC_SQ_S_MOVRELD_B32 0x30
2904 #define V_008DFC_SQ_S_MOVRELD_B64 0x31
2905 #define V_008DFC_SQ_S_CBRANCH_JOIN 0x32
2906 #define V_008DFC_SQ_S_MOV_REGRD_B32 0x33
2907 #define V_008DFC_SQ_S_ABS_I32 0x34
2908 #define V_008DFC_SQ_S_MOV_FED_B32 0x35
2909 #define S_008DFC_SDST(x) (((x) & 0x7F) << 16)
2910 #define G_008DFC_SDST(x) (((x) >> 16) & 0x7F)
2911 #define C_008DFC_SDST 0xFF80FFFF
2912 #define V_008DFC_SQ_SGPR 0x00
2913 /* CIK */
2914 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
2915 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
2916 /* */
2917 #define V_008DFC_SQ_VCC_LO 0x6A
2918 #define V_008DFC_SQ_VCC_HI 0x6B
2919 #define V_008DFC_SQ_TBA_LO 0x6C
2920 #define V_008DFC_SQ_TBA_HI 0x6D
2921 #define V_008DFC_SQ_TMA_LO 0x6E
2922 #define V_008DFC_SQ_TMA_HI 0x6F
2923 #define V_008DFC_SQ_TTMP0 0x70
2924 #define V_008DFC_SQ_TTMP1 0x71
2925 #define V_008DFC_SQ_TTMP2 0x72
2926 #define V_008DFC_SQ_TTMP3 0x73
2927 #define V_008DFC_SQ_TTMP4 0x74
2928 #define V_008DFC_SQ_TTMP5 0x75
2929 #define V_008DFC_SQ_TTMP6 0x76
2930 #define V_008DFC_SQ_TTMP7 0x77
2931 #define V_008DFC_SQ_TTMP8 0x78
2932 #define V_008DFC_SQ_TTMP9 0x79
2933 #define V_008DFC_SQ_TTMP10 0x7A
2934 #define V_008DFC_SQ_TTMP11 0x7B
2935 #define V_008DFC_SQ_M0 0x7C
2936 #define V_008DFC_SQ_EXEC_LO 0x7E
2937 #define V_008DFC_SQ_EXEC_HI 0x7F
2938 #define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23)
2939 #define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF)
2940 #define C_008DFC_ENCODING 0x007FFFFF
2941 #define V_008DFC_SQ_ENC_SOP1_FIELD 0x17D
2942 #define R_008DFC_SQ_MTBUF_1 0x008DFC
2943 #define S_008DFC_VADDR(x) (((x) & 0xFF) << 0)
2944 #define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF)
2945 #define C_008DFC_VADDR 0xFFFFFF00
2946 #define V_008DFC_SQ_VGPR 0x00
2947 #define S_008DFC_VDATA(x) (((x) & 0xFF) << 8)
2948 #define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF)
2949 #define C_008DFC_VDATA 0xFFFF00FF
2950 #define V_008DFC_SQ_VGPR 0x00
2951 #define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16)
2952 #define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F)
2953 #define C_008DFC_SRSRC 0xFFE0FFFF
2954 #define S_008DFC_SLC(x) (((x) & 0x1) << 22)
2955 #define G_008DFC_SLC(x) (((x) >> 22) & 0x1)
2956 #define C_008DFC_SLC 0xFFBFFFFF
2957 #define S_008DFC_TFE(x) (((x) & 0x1) << 23)
2958 #define G_008DFC_TFE(x) (((x) >> 23) & 0x1)
2959 #define C_008DFC_TFE 0xFF7FFFFF
2960 #define S_008DFC_SOFFSET(x) (((x) & 0xFF) << 24)
2961 #define G_008DFC_SOFFSET(x) (((x) >> 24) & 0xFF)
2962 #define C_008DFC_SOFFSET 0x00FFFFFF
2963 #define V_008DFC_SQ_SGPR 0x00
2964 /* CIK */
2965 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
2966 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
2967 /* */
2968 #define V_008DFC_SQ_VCC_LO 0x6A
2969 #define V_008DFC_SQ_VCC_HI 0x6B
2970 #define V_008DFC_SQ_TBA_LO 0x6C
2971 #define V_008DFC_SQ_TBA_HI 0x6D
2972 #define V_008DFC_SQ_TMA_LO 0x6E
2973 #define V_008DFC_SQ_TMA_HI 0x6F
2974 #define V_008DFC_SQ_TTMP0 0x70
2975 #define V_008DFC_SQ_TTMP1 0x71
2976 #define V_008DFC_SQ_TTMP2 0x72
2977 #define V_008DFC_SQ_TTMP3 0x73
2978 #define V_008DFC_SQ_TTMP4 0x74
2979 #define V_008DFC_SQ_TTMP5 0x75
2980 #define V_008DFC_SQ_TTMP6 0x76
2981 #define V_008DFC_SQ_TTMP7 0x77
2982 #define V_008DFC_SQ_TTMP8 0x78
2983 #define V_008DFC_SQ_TTMP9 0x79
2984 #define V_008DFC_SQ_TTMP10 0x7A
2985 #define V_008DFC_SQ_TTMP11 0x7B
2986 #define V_008DFC_SQ_M0 0x7C
2987 #define V_008DFC_SQ_EXEC_LO 0x7E
2988 #define V_008DFC_SQ_EXEC_HI 0x7F
2989 #define V_008DFC_SQ_SRC_0 0x80
2990 #define V_008DFC_SQ_SRC_1_INT 0x81
2991 #define V_008DFC_SQ_SRC_2_INT 0x82
2992 #define V_008DFC_SQ_SRC_3_INT 0x83
2993 #define V_008DFC_SQ_SRC_4_INT 0x84
2994 #define V_008DFC_SQ_SRC_5_INT 0x85
2995 #define V_008DFC_SQ_SRC_6_INT 0x86
2996 #define V_008DFC_SQ_SRC_7_INT 0x87
2997 #define V_008DFC_SQ_SRC_8_INT 0x88
2998 #define V_008DFC_SQ_SRC_9_INT 0x89
2999 #define V_008DFC_SQ_SRC_10_INT 0x8A
3000 #define V_008DFC_SQ_SRC_11_INT 0x8B
3001 #define V_008DFC_SQ_SRC_12_INT 0x8C
3002 #define V_008DFC_SQ_SRC_13_INT 0x8D
3003 #define V_008DFC_SQ_SRC_14_INT 0x8E
3004 #define V_008DFC_SQ_SRC_15_INT 0x8F
3005 #define V_008DFC_SQ_SRC_16_INT 0x90
3006 #define V_008DFC_SQ_SRC_17_INT 0x91
3007 #define V_008DFC_SQ_SRC_18_INT 0x92
3008 #define V_008DFC_SQ_SRC_19_INT 0x93
3009 #define V_008DFC_SQ_SRC_20_INT 0x94
3010 #define V_008DFC_SQ_SRC_21_INT 0x95
3011 #define V_008DFC_SQ_SRC_22_INT 0x96
3012 #define V_008DFC_SQ_SRC_23_INT 0x97
3013 #define V_008DFC_SQ_SRC_24_INT 0x98
3014 #define V_008DFC_SQ_SRC_25_INT 0x99
3015 #define V_008DFC_SQ_SRC_26_INT 0x9A
3016 #define V_008DFC_SQ_SRC_27_INT 0x9B
3017 #define V_008DFC_SQ_SRC_28_INT 0x9C
3018 #define V_008DFC_SQ_SRC_29_INT 0x9D
3019 #define V_008DFC_SQ_SRC_30_INT 0x9E
3020 #define V_008DFC_SQ_SRC_31_INT 0x9F
3021 #define V_008DFC_SQ_SRC_32_INT 0xA0
3022 #define V_008DFC_SQ_SRC_33_INT 0xA1
3023 #define V_008DFC_SQ_SRC_34_INT 0xA2
3024 #define V_008DFC_SQ_SRC_35_INT 0xA3
3025 #define V_008DFC_SQ_SRC_36_INT 0xA4
3026 #define V_008DFC_SQ_SRC_37_INT 0xA5
3027 #define V_008DFC_SQ_SRC_38_INT 0xA6
3028 #define V_008DFC_SQ_SRC_39_INT 0xA7
3029 #define V_008DFC_SQ_SRC_40_INT 0xA8
3030 #define V_008DFC_SQ_SRC_41_INT 0xA9
3031 #define V_008DFC_SQ_SRC_42_INT 0xAA
3032 #define V_008DFC_SQ_SRC_43_INT 0xAB
3033 #define V_008DFC_SQ_SRC_44_INT 0xAC
3034 #define V_008DFC_SQ_SRC_45_INT 0xAD
3035 #define V_008DFC_SQ_SRC_46_INT 0xAE
3036 #define V_008DFC_SQ_SRC_47_INT 0xAF
3037 #define V_008DFC_SQ_SRC_48_INT 0xB0
3038 #define V_008DFC_SQ_SRC_49_INT 0xB1
3039 #define V_008DFC_SQ_SRC_50_INT 0xB2
3040 #define V_008DFC_SQ_SRC_51_INT 0xB3
3041 #define V_008DFC_SQ_SRC_52_INT 0xB4
3042 #define V_008DFC_SQ_SRC_53_INT 0xB5
3043 #define V_008DFC_SQ_SRC_54_INT 0xB6
3044 #define V_008DFC_SQ_SRC_55_INT 0xB7
3045 #define V_008DFC_SQ_SRC_56_INT 0xB8
3046 #define V_008DFC_SQ_SRC_57_INT 0xB9
3047 #define V_008DFC_SQ_SRC_58_INT 0xBA
3048 #define V_008DFC_SQ_SRC_59_INT 0xBB
3049 #define V_008DFC_SQ_SRC_60_INT 0xBC
3050 #define V_008DFC_SQ_SRC_61_INT 0xBD
3051 #define V_008DFC_SQ_SRC_62_INT 0xBE
3052 #define V_008DFC_SQ_SRC_63_INT 0xBF
3053 #define V_008DFC_SQ_SRC_64_INT 0xC0
3054 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
3055 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
3056 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
3057 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
3058 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
3059 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
3060 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
3061 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
3062 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
3063 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
3064 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
3065 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
3066 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
3067 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
3068 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
3069 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
3070 #define V_008DFC_SQ_SRC_0_5 0xF0
3071 #define V_008DFC_SQ_SRC_M_0_5 0xF1
3072 #define V_008DFC_SQ_SRC_1 0xF2
3073 #define V_008DFC_SQ_SRC_M_1 0xF3
3074 #define V_008DFC_SQ_SRC_2 0xF4
3075 #define V_008DFC_SQ_SRC_M_2 0xF5
3076 #define V_008DFC_SQ_SRC_4 0xF6
3077 #define V_008DFC_SQ_SRC_M_4 0xF7
3078 #define V_008DFC_SQ_SRC_VCCZ 0xFB
3079 #define V_008DFC_SQ_SRC_EXECZ 0xFC
3080 #define V_008DFC_SQ_SRC_SCC 0xFD
3081 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
3082 #define R_008DFC_SQ_SOP2 0x008DFC
3083 #define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0)
3084 #define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF)
3085 #define C_008DFC_SSRC0 0xFFFFFF00
3086 #define V_008DFC_SQ_SGPR 0x00
3087 /* CIK */
3088 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
3089 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
3090 /* */
3091 #define V_008DFC_SQ_VCC_LO 0x6A
3092 #define V_008DFC_SQ_VCC_HI 0x6B
3093 #define V_008DFC_SQ_TBA_LO 0x6C
3094 #define V_008DFC_SQ_TBA_HI 0x6D
3095 #define V_008DFC_SQ_TMA_LO 0x6E
3096 #define V_008DFC_SQ_TMA_HI 0x6F
3097 #define V_008DFC_SQ_TTMP0 0x70
3098 #define V_008DFC_SQ_TTMP1 0x71
3099 #define V_008DFC_SQ_TTMP2 0x72
3100 #define V_008DFC_SQ_TTMP3 0x73
3101 #define V_008DFC_SQ_TTMP4 0x74
3102 #define V_008DFC_SQ_TTMP5 0x75
3103 #define V_008DFC_SQ_TTMP6 0x76
3104 #define V_008DFC_SQ_TTMP7 0x77
3105 #define V_008DFC_SQ_TTMP8 0x78
3106 #define V_008DFC_SQ_TTMP9 0x79
3107 #define V_008DFC_SQ_TTMP10 0x7A
3108 #define V_008DFC_SQ_TTMP11 0x7B
3109 #define V_008DFC_SQ_M0 0x7C
3110 #define V_008DFC_SQ_EXEC_LO 0x7E
3111 #define V_008DFC_SQ_EXEC_HI 0x7F
3112 #define V_008DFC_SQ_SRC_0 0x80
3113 #define V_008DFC_SQ_SRC_1_INT 0x81
3114 #define V_008DFC_SQ_SRC_2_INT 0x82
3115 #define V_008DFC_SQ_SRC_3_INT 0x83
3116 #define V_008DFC_SQ_SRC_4_INT 0x84
3117 #define V_008DFC_SQ_SRC_5_INT 0x85
3118 #define V_008DFC_SQ_SRC_6_INT 0x86
3119 #define V_008DFC_SQ_SRC_7_INT 0x87
3120 #define V_008DFC_SQ_SRC_8_INT 0x88
3121 #define V_008DFC_SQ_SRC_9_INT 0x89
3122 #define V_008DFC_SQ_SRC_10_INT 0x8A
3123 #define V_008DFC_SQ_SRC_11_INT 0x8B
3124 #define V_008DFC_SQ_SRC_12_INT 0x8C
3125 #define V_008DFC_SQ_SRC_13_INT 0x8D
3126 #define V_008DFC_SQ_SRC_14_INT 0x8E
3127 #define V_008DFC_SQ_SRC_15_INT 0x8F
3128 #define V_008DFC_SQ_SRC_16_INT 0x90
3129 #define V_008DFC_SQ_SRC_17_INT 0x91
3130 #define V_008DFC_SQ_SRC_18_INT 0x92
3131 #define V_008DFC_SQ_SRC_19_INT 0x93
3132 #define V_008DFC_SQ_SRC_20_INT 0x94
3133 #define V_008DFC_SQ_SRC_21_INT 0x95
3134 #define V_008DFC_SQ_SRC_22_INT 0x96
3135 #define V_008DFC_SQ_SRC_23_INT 0x97
3136 #define V_008DFC_SQ_SRC_24_INT 0x98
3137 #define V_008DFC_SQ_SRC_25_INT 0x99
3138 #define V_008DFC_SQ_SRC_26_INT 0x9A
3139 #define V_008DFC_SQ_SRC_27_INT 0x9B
3140 #define V_008DFC_SQ_SRC_28_INT 0x9C
3141 #define V_008DFC_SQ_SRC_29_INT 0x9D
3142 #define V_008DFC_SQ_SRC_30_INT 0x9E
3143 #define V_008DFC_SQ_SRC_31_INT 0x9F
3144 #define V_008DFC_SQ_SRC_32_INT 0xA0
3145 #define V_008DFC_SQ_SRC_33_INT 0xA1
3146 #define V_008DFC_SQ_SRC_34_INT 0xA2
3147 #define V_008DFC_SQ_SRC_35_INT 0xA3
3148 #define V_008DFC_SQ_SRC_36_INT 0xA4
3149 #define V_008DFC_SQ_SRC_37_INT 0xA5
3150 #define V_008DFC_SQ_SRC_38_INT 0xA6
3151 #define V_008DFC_SQ_SRC_39_INT 0xA7
3152 #define V_008DFC_SQ_SRC_40_INT 0xA8
3153 #define V_008DFC_SQ_SRC_41_INT 0xA9
3154 #define V_008DFC_SQ_SRC_42_INT 0xAA
3155 #define V_008DFC_SQ_SRC_43_INT 0xAB
3156 #define V_008DFC_SQ_SRC_44_INT 0xAC
3157 #define V_008DFC_SQ_SRC_45_INT 0xAD
3158 #define V_008DFC_SQ_SRC_46_INT 0xAE
3159 #define V_008DFC_SQ_SRC_47_INT 0xAF
3160 #define V_008DFC_SQ_SRC_48_INT 0xB0
3161 #define V_008DFC_SQ_SRC_49_INT 0xB1
3162 #define V_008DFC_SQ_SRC_50_INT 0xB2
3163 #define V_008DFC_SQ_SRC_51_INT 0xB3
3164 #define V_008DFC_SQ_SRC_52_INT 0xB4
3165 #define V_008DFC_SQ_SRC_53_INT 0xB5
3166 #define V_008DFC_SQ_SRC_54_INT 0xB6
3167 #define V_008DFC_SQ_SRC_55_INT 0xB7
3168 #define V_008DFC_SQ_SRC_56_INT 0xB8
3169 #define V_008DFC_SQ_SRC_57_INT 0xB9
3170 #define V_008DFC_SQ_SRC_58_INT 0xBA
3171 #define V_008DFC_SQ_SRC_59_INT 0xBB
3172 #define V_008DFC_SQ_SRC_60_INT 0xBC
3173 #define V_008DFC_SQ_SRC_61_INT 0xBD
3174 #define V_008DFC_SQ_SRC_62_INT 0xBE
3175 #define V_008DFC_SQ_SRC_63_INT 0xBF
3176 #define V_008DFC_SQ_SRC_64_INT 0xC0
3177 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
3178 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
3179 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
3180 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
3181 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
3182 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
3183 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
3184 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
3185 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
3186 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
3187 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
3188 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
3189 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
3190 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
3191 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
3192 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
3193 #define V_008DFC_SQ_SRC_0_5 0xF0
3194 #define V_008DFC_SQ_SRC_M_0_5 0xF1
3195 #define V_008DFC_SQ_SRC_1 0xF2
3196 #define V_008DFC_SQ_SRC_M_1 0xF3
3197 #define V_008DFC_SQ_SRC_2 0xF4
3198 #define V_008DFC_SQ_SRC_M_2 0xF5
3199 #define V_008DFC_SQ_SRC_4 0xF6
3200 #define V_008DFC_SQ_SRC_M_4 0xF7
3201 #define V_008DFC_SQ_SRC_VCCZ 0xFB
3202 #define V_008DFC_SQ_SRC_EXECZ 0xFC
3203 #define V_008DFC_SQ_SRC_SCC 0xFD
3204 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
3205 #define S_008DFC_SSRC1(x) (((x) & 0xFF) << 8)
3206 #define G_008DFC_SSRC1(x) (((x) >> 8) & 0xFF)
3207 #define C_008DFC_SSRC1 0xFFFF00FF
3208 #define V_008DFC_SQ_SGPR 0x00
3209 /* CIK */
3210 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
3211 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
3212 /* */
3213 #define V_008DFC_SQ_VCC_LO 0x6A
3214 #define V_008DFC_SQ_VCC_HI 0x6B
3215 #define V_008DFC_SQ_TBA_LO 0x6C
3216 #define V_008DFC_SQ_TBA_HI 0x6D
3217 #define V_008DFC_SQ_TMA_LO 0x6E
3218 #define V_008DFC_SQ_TMA_HI 0x6F
3219 #define V_008DFC_SQ_TTMP0 0x70
3220 #define V_008DFC_SQ_TTMP1 0x71
3221 #define V_008DFC_SQ_TTMP2 0x72
3222 #define V_008DFC_SQ_TTMP3 0x73
3223 #define V_008DFC_SQ_TTMP4 0x74
3224 #define V_008DFC_SQ_TTMP5 0x75
3225 #define V_008DFC_SQ_TTMP6 0x76
3226 #define V_008DFC_SQ_TTMP7 0x77
3227 #define V_008DFC_SQ_TTMP8 0x78
3228 #define V_008DFC_SQ_TTMP9 0x79
3229 #define V_008DFC_SQ_TTMP10 0x7A
3230 #define V_008DFC_SQ_TTMP11 0x7B
3231 #define V_008DFC_SQ_M0 0x7C
3232 #define V_008DFC_SQ_EXEC_LO 0x7E
3233 #define V_008DFC_SQ_EXEC_HI 0x7F
3234 #define V_008DFC_SQ_SRC_0 0x80
3235 #define V_008DFC_SQ_SRC_1_INT 0x81
3236 #define V_008DFC_SQ_SRC_2_INT 0x82
3237 #define V_008DFC_SQ_SRC_3_INT 0x83
3238 #define V_008DFC_SQ_SRC_4_INT 0x84
3239 #define V_008DFC_SQ_SRC_5_INT 0x85
3240 #define V_008DFC_SQ_SRC_6_INT 0x86
3241 #define V_008DFC_SQ_SRC_7_INT 0x87
3242 #define V_008DFC_SQ_SRC_8_INT 0x88
3243 #define V_008DFC_SQ_SRC_9_INT 0x89
3244 #define V_008DFC_SQ_SRC_10_INT 0x8A
3245 #define V_008DFC_SQ_SRC_11_INT 0x8B
3246 #define V_008DFC_SQ_SRC_12_INT 0x8C
3247 #define V_008DFC_SQ_SRC_13_INT 0x8D
3248 #define V_008DFC_SQ_SRC_14_INT 0x8E
3249 #define V_008DFC_SQ_SRC_15_INT 0x8F
3250 #define V_008DFC_SQ_SRC_16_INT 0x90
3251 #define V_008DFC_SQ_SRC_17_INT 0x91
3252 #define V_008DFC_SQ_SRC_18_INT 0x92
3253 #define V_008DFC_SQ_SRC_19_INT 0x93
3254 #define V_008DFC_SQ_SRC_20_INT 0x94
3255 #define V_008DFC_SQ_SRC_21_INT 0x95
3256 #define V_008DFC_SQ_SRC_22_INT 0x96
3257 #define V_008DFC_SQ_SRC_23_INT 0x97
3258 #define V_008DFC_SQ_SRC_24_INT 0x98
3259 #define V_008DFC_SQ_SRC_25_INT 0x99
3260 #define V_008DFC_SQ_SRC_26_INT 0x9A
3261 #define V_008DFC_SQ_SRC_27_INT 0x9B
3262 #define V_008DFC_SQ_SRC_28_INT 0x9C
3263 #define V_008DFC_SQ_SRC_29_INT 0x9D
3264 #define V_008DFC_SQ_SRC_30_INT 0x9E
3265 #define V_008DFC_SQ_SRC_31_INT 0x9F
3266 #define V_008DFC_SQ_SRC_32_INT 0xA0
3267 #define V_008DFC_SQ_SRC_33_INT 0xA1
3268 #define V_008DFC_SQ_SRC_34_INT 0xA2
3269 #define V_008DFC_SQ_SRC_35_INT 0xA3
3270 #define V_008DFC_SQ_SRC_36_INT 0xA4
3271 #define V_008DFC_SQ_SRC_37_INT 0xA5
3272 #define V_008DFC_SQ_SRC_38_INT 0xA6
3273 #define V_008DFC_SQ_SRC_39_INT 0xA7
3274 #define V_008DFC_SQ_SRC_40_INT 0xA8
3275 #define V_008DFC_SQ_SRC_41_INT 0xA9
3276 #define V_008DFC_SQ_SRC_42_INT 0xAA
3277 #define V_008DFC_SQ_SRC_43_INT 0xAB
3278 #define V_008DFC_SQ_SRC_44_INT 0xAC
3279 #define V_008DFC_SQ_SRC_45_INT 0xAD
3280 #define V_008DFC_SQ_SRC_46_INT 0xAE
3281 #define V_008DFC_SQ_SRC_47_INT 0xAF
3282 #define V_008DFC_SQ_SRC_48_INT 0xB0
3283 #define V_008DFC_SQ_SRC_49_INT 0xB1
3284 #define V_008DFC_SQ_SRC_50_INT 0xB2
3285 #define V_008DFC_SQ_SRC_51_INT 0xB3
3286 #define V_008DFC_SQ_SRC_52_INT 0xB4
3287 #define V_008DFC_SQ_SRC_53_INT 0xB5
3288 #define V_008DFC_SQ_SRC_54_INT 0xB6
3289 #define V_008DFC_SQ_SRC_55_INT 0xB7
3290 #define V_008DFC_SQ_SRC_56_INT 0xB8
3291 #define V_008DFC_SQ_SRC_57_INT 0xB9
3292 #define V_008DFC_SQ_SRC_58_INT 0xBA
3293 #define V_008DFC_SQ_SRC_59_INT 0xBB
3294 #define V_008DFC_SQ_SRC_60_INT 0xBC
3295 #define V_008DFC_SQ_SRC_61_INT 0xBD
3296 #define V_008DFC_SQ_SRC_62_INT 0xBE
3297 #define V_008DFC_SQ_SRC_63_INT 0xBF
3298 #define V_008DFC_SQ_SRC_64_INT 0xC0
3299 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
3300 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
3301 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
3302 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
3303 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
3304 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
3305 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
3306 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
3307 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
3308 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
3309 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
3310 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
3311 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
3312 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
3313 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
3314 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
3315 #define V_008DFC_SQ_SRC_0_5 0xF0
3316 #define V_008DFC_SQ_SRC_M_0_5 0xF1
3317 #define V_008DFC_SQ_SRC_1 0xF2
3318 #define V_008DFC_SQ_SRC_M_1 0xF3
3319 #define V_008DFC_SQ_SRC_2 0xF4
3320 #define V_008DFC_SQ_SRC_M_2 0xF5
3321 #define V_008DFC_SQ_SRC_4 0xF6
3322 #define V_008DFC_SQ_SRC_M_4 0xF7
3323 #define V_008DFC_SQ_SRC_VCCZ 0xFB
3324 #define V_008DFC_SQ_SRC_EXECZ 0xFC
3325 #define V_008DFC_SQ_SRC_SCC 0xFD
3326 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
3327 #define S_008DFC_SDST(x) (((x) & 0x7F) << 16)
3328 #define G_008DFC_SDST(x) (((x) >> 16) & 0x7F)
3329 #define C_008DFC_SDST 0xFF80FFFF
3330 #define V_008DFC_SQ_SGPR 0x00
3331 /* CIK */
3332 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
3333 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
3334 /* */
3335 #define V_008DFC_SQ_VCC_LO 0x6A
3336 #define V_008DFC_SQ_VCC_HI 0x6B
3337 #define V_008DFC_SQ_TBA_LO 0x6C
3338 #define V_008DFC_SQ_TBA_HI 0x6D
3339 #define V_008DFC_SQ_TMA_LO 0x6E
3340 #define V_008DFC_SQ_TMA_HI 0x6F
3341 #define V_008DFC_SQ_TTMP0 0x70
3342 #define V_008DFC_SQ_TTMP1 0x71
3343 #define V_008DFC_SQ_TTMP2 0x72
3344 #define V_008DFC_SQ_TTMP3 0x73
3345 #define V_008DFC_SQ_TTMP4 0x74
3346 #define V_008DFC_SQ_TTMP5 0x75
3347 #define V_008DFC_SQ_TTMP6 0x76
3348 #define V_008DFC_SQ_TTMP7 0x77
3349 #define V_008DFC_SQ_TTMP8 0x78
3350 #define V_008DFC_SQ_TTMP9 0x79
3351 #define V_008DFC_SQ_TTMP10 0x7A
3352 #define V_008DFC_SQ_TTMP11 0x7B
3353 #define V_008DFC_SQ_M0 0x7C
3354 #define V_008DFC_SQ_EXEC_LO 0x7E
3355 #define V_008DFC_SQ_EXEC_HI 0x7F
3356 #define S_008DFC_OP(x) (((x) & 0x7F) << 23)
3357 #define G_008DFC_OP(x) (((x) >> 23) & 0x7F)
3358 #define C_008DFC_OP 0xC07FFFFF
3359 #define V_008DFC_SQ_S_ADD_U32 0x00
3360 #define V_008DFC_SQ_S_SUB_U32 0x01
3361 #define V_008DFC_SQ_S_ADD_I32 0x02
3362 #define V_008DFC_SQ_S_SUB_I32 0x03
3363 #define V_008DFC_SQ_S_ADDC_U32 0x04
3364 #define V_008DFC_SQ_S_SUBB_U32 0x05
3365 #define V_008DFC_SQ_S_MIN_I32 0x06
3366 #define V_008DFC_SQ_S_MIN_U32 0x07
3367 #define V_008DFC_SQ_S_MAX_I32 0x08
3368 #define V_008DFC_SQ_S_MAX_U32 0x09
3369 #define V_008DFC_SQ_S_CSELECT_B32 0x0A
3370 #define V_008DFC_SQ_S_CSELECT_B64 0x0B
3371 #define V_008DFC_SQ_S_AND_B32 0x0E
3372 #define V_008DFC_SQ_S_AND_B64 0x0F
3373 #define V_008DFC_SQ_S_OR_B32 0x10
3374 #define V_008DFC_SQ_S_OR_B64 0x11
3375 #define V_008DFC_SQ_S_XOR_B32 0x12
3376 #define V_008DFC_SQ_S_XOR_B64 0x13
3377 #define V_008DFC_SQ_S_ANDN2_B32 0x14
3378 #define V_008DFC_SQ_S_ANDN2_B64 0x15
3379 #define V_008DFC_SQ_S_ORN2_B32 0x16
3380 #define V_008DFC_SQ_S_ORN2_B64 0x17
3381 #define V_008DFC_SQ_S_NAND_B32 0x18
3382 #define V_008DFC_SQ_S_NAND_B64 0x19
3383 #define V_008DFC_SQ_S_NOR_B32 0x1A
3384 #define V_008DFC_SQ_S_NOR_B64 0x1B
3385 #define V_008DFC_SQ_S_XNOR_B32 0x1C
3386 #define V_008DFC_SQ_S_XNOR_B64 0x1D
3387 #define V_008DFC_SQ_S_LSHL_B32 0x1E
3388 #define V_008DFC_SQ_S_LSHL_B64 0x1F
3389 #define V_008DFC_SQ_S_LSHR_B32 0x20
3390 #define V_008DFC_SQ_S_LSHR_B64 0x21
3391 #define V_008DFC_SQ_S_ASHR_I32 0x22
3392 #define V_008DFC_SQ_S_ASHR_I64 0x23
3393 #define V_008DFC_SQ_S_BFM_B32 0x24
3394 #define V_008DFC_SQ_S_BFM_B64 0x25
3395 #define V_008DFC_SQ_S_MUL_I32 0x26
3396 #define V_008DFC_SQ_S_BFE_U32 0x27
3397 #define V_008DFC_SQ_S_BFE_I32 0x28
3398 #define V_008DFC_SQ_S_BFE_U64 0x29
3399 #define V_008DFC_SQ_S_BFE_I64 0x2A
3400 #define V_008DFC_SQ_S_CBRANCH_G_FORK 0x2B
3401 #define V_008DFC_SQ_S_ABSDIFF_I32 0x2C
3402 #define S_008DFC_ENCODING(x) (((x) & 0x03) << 30)
3403 #define G_008DFC_ENCODING(x) (((x) >> 30) & 0x03)
3404 #define C_008DFC_ENCODING 0x3FFFFFFF
3405 #define V_008DFC_SQ_ENC_SOP2_FIELD 0x02
3406 #define R_008DFC_SQ_SOPK 0x008DFC
3407 #define S_008DFC_SIMM16(x) (((x) & 0xFFFF) << 0)
3408 #define G_008DFC_SIMM16(x) (((x) >> 0) & 0xFFFF)
3409 #define C_008DFC_SIMM16 0xFFFF0000
3410 #define S_008DFC_SDST(x) (((x) & 0x7F) << 16)
3411 #define G_008DFC_SDST(x) (((x) >> 16) & 0x7F)
3412 #define C_008DFC_SDST 0xFF80FFFF
3413 #define V_008DFC_SQ_SGPR 0x00
3414 /* CIK */
3415 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
3416 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
3417 /* */
3418 #define V_008DFC_SQ_VCC_LO 0x6A
3419 #define V_008DFC_SQ_VCC_HI 0x6B
3420 #define V_008DFC_SQ_TBA_LO 0x6C
3421 #define V_008DFC_SQ_TBA_HI 0x6D
3422 #define V_008DFC_SQ_TMA_LO 0x6E
3423 #define V_008DFC_SQ_TMA_HI 0x6F
3424 #define V_008DFC_SQ_TTMP0 0x70
3425 #define V_008DFC_SQ_TTMP1 0x71
3426 #define V_008DFC_SQ_TTMP2 0x72
3427 #define V_008DFC_SQ_TTMP3 0x73
3428 #define V_008DFC_SQ_TTMP4 0x74
3429 #define V_008DFC_SQ_TTMP5 0x75
3430 #define V_008DFC_SQ_TTMP6 0x76
3431 #define V_008DFC_SQ_TTMP7 0x77
3432 #define V_008DFC_SQ_TTMP8 0x78
3433 #define V_008DFC_SQ_TTMP9 0x79
3434 #define V_008DFC_SQ_TTMP10 0x7A
3435 #define V_008DFC_SQ_TTMP11 0x7B
3436 #define V_008DFC_SQ_M0 0x7C
3437 #define V_008DFC_SQ_EXEC_LO 0x7E
3438 #define V_008DFC_SQ_EXEC_HI 0x7F
3439 #define S_008DFC_OP(x) (((x) & 0x1F) << 23)
3440 #define G_008DFC_OP(x) (((x) >> 23) & 0x1F)
3441 #define C_008DFC_OP 0xF07FFFFF
3442 #define V_008DFC_SQ_S_MOVK_I32 0x00
3443 #define V_008DFC_SQ_S_CMOVK_I32 0x02
3444 #define V_008DFC_SQ_S_CMPK_EQ_I32 0x03
3445 #define V_008DFC_SQ_S_CMPK_LG_I32 0x04
3446 #define V_008DFC_SQ_S_CMPK_GT_I32 0x05
3447 #define V_008DFC_SQ_S_CMPK_GE_I32 0x06
3448 #define V_008DFC_SQ_S_CMPK_LT_I32 0x07
3449 #define V_008DFC_SQ_S_CMPK_LE_I32 0x08
3450 #define V_008DFC_SQ_S_CMPK_EQ_U32 0x09
3451 #define V_008DFC_SQ_S_CMPK_LG_U32 0x0A
3452 #define V_008DFC_SQ_S_CMPK_GT_U32 0x0B
3453 #define V_008DFC_SQ_S_CMPK_GE_U32 0x0C
3454 #define V_008DFC_SQ_S_CMPK_LT_U32 0x0D
3455 #define V_008DFC_SQ_S_CMPK_LE_U32 0x0E
3456 #define V_008DFC_SQ_S_ADDK_I32 0x0F
3457 #define V_008DFC_SQ_S_MULK_I32 0x10
3458 #define V_008DFC_SQ_S_CBRANCH_I_FORK 0x11
3459 #define V_008DFC_SQ_S_GETREG_B32 0x12
3460 #define V_008DFC_SQ_S_SETREG_B32 0x13
3461 #define V_008DFC_SQ_S_GETREG_REGRD_B32 0x14
3462 #define V_008DFC_SQ_S_SETREG_IMM32_B32 0x15
3463 #define S_008DFC_ENCODING(x) (((x) & 0x0F) << 28)
3464 #define G_008DFC_ENCODING(x) (((x) >> 28) & 0x0F)
3465 #define C_008DFC_ENCODING 0x0FFFFFFF
3466 #define V_008DFC_SQ_ENC_SOPK_FIELD 0x0B
3467 #define R_008DFC_SQ_VOP3_0 0x008DFC
3468 #define S_008DFC_VDST(x) (((x) & 0xFF) << 0)
3469 #define G_008DFC_VDST(x) (((x) >> 0) & 0xFF)
3470 #define C_008DFC_VDST 0xFFFFFF00
3471 #define V_008DFC_SQ_VGPR 0x00
3472 #define S_008DFC_ABS(x) (((x) & 0x07) << 8)
3473 #define G_008DFC_ABS(x) (((x) >> 8) & 0x07)
3474 #define C_008DFC_ABS 0xFFFFF8FF
3475 #define S_008DFC_CLAMP(x) (((x) & 0x1) << 11)
3476 #define G_008DFC_CLAMP(x) (((x) >> 11) & 0x1)
3477 #define C_008DFC_CLAMP 0xFFFFF7FF
3478 #define S_008DFC_OP(x) (((x) & 0x1FF) << 17)
3479 #define G_008DFC_OP(x) (((x) >> 17) & 0x1FF)
3480 #define C_008DFC_OP 0xFC01FFFF
3481 #define V_008DFC_SQ_V_OPC_OFFSET 0x00
3482 #define V_008DFC_SQ_V_OP2_OFFSET 0x100
3483 #define V_008DFC_SQ_V_MAD_LEGACY_F32 0x140
3484 #define V_008DFC_SQ_V_MAD_F32 0x141
3485 #define V_008DFC_SQ_V_MAD_I32_I24 0x142
3486 #define V_008DFC_SQ_V_MAD_U32_U24 0x143
3487 #define V_008DFC_SQ_V_CUBEID_F32 0x144
3488 #define V_008DFC_SQ_V_CUBESC_F32 0x145
3489 #define V_008DFC_SQ_V_CUBETC_F32 0x146
3490 #define V_008DFC_SQ_V_CUBEMA_F32 0x147
3491 #define V_008DFC_SQ_V_BFE_U32 0x148
3492 #define V_008DFC_SQ_V_BFE_I32 0x149
3493 #define V_008DFC_SQ_V_BFI_B32 0x14A
3494 #define V_008DFC_SQ_V_FMA_F32 0x14B
3495 #define V_008DFC_SQ_V_FMA_F64 0x14C
3496 #define V_008DFC_SQ_V_LERP_U8 0x14D
3497 #define V_008DFC_SQ_V_ALIGNBIT_B32 0x14E
3498 #define V_008DFC_SQ_V_ALIGNBYTE_B32 0x14F
3499 #define V_008DFC_SQ_V_MULLIT_F32 0x150
3500 #define V_008DFC_SQ_V_MIN3_F32 0x151
3501 #define V_008DFC_SQ_V_MIN3_I32 0x152
3502 #define V_008DFC_SQ_V_MIN3_U32 0x153
3503 #define V_008DFC_SQ_V_MAX3_F32 0x154
3504 #define V_008DFC_SQ_V_MAX3_I32 0x155
3505 #define V_008DFC_SQ_V_MAX3_U32 0x156
3506 #define V_008DFC_SQ_V_MED3_F32 0x157
3507 #define V_008DFC_SQ_V_MED3_I32 0x158
3508 #define V_008DFC_SQ_V_MED3_U32 0x159
3509 #define V_008DFC_SQ_V_SAD_U8 0x15A
3510 #define V_008DFC_SQ_V_SAD_HI_U8 0x15B
3511 #define V_008DFC_SQ_V_SAD_U16 0x15C
3512 #define V_008DFC_SQ_V_SAD_U32 0x15D
3513 #define V_008DFC_SQ_V_CVT_PK_U8_F32 0x15E
3514 #define V_008DFC_SQ_V_DIV_FIXUP_F32 0x15F
3515 #define V_008DFC_SQ_V_DIV_FIXUP_F64 0x160
3516 #define V_008DFC_SQ_V_LSHL_B64 0x161
3517 #define V_008DFC_SQ_V_LSHR_B64 0x162
3518 #define V_008DFC_SQ_V_ASHR_I64 0x163
3519 #define V_008DFC_SQ_V_ADD_F64 0x164
3520 #define V_008DFC_SQ_V_MUL_F64 0x165
3521 #define V_008DFC_SQ_V_MIN_F64 0x166
3522 #define V_008DFC_SQ_V_MAX_F64 0x167
3523 #define V_008DFC_SQ_V_LDEXP_F64 0x168
3524 #define V_008DFC_SQ_V_MUL_LO_U32 0x169
3525 #define V_008DFC_SQ_V_MUL_HI_U32 0x16A
3526 #define V_008DFC_SQ_V_MUL_LO_I32 0x16B
3527 #define V_008DFC_SQ_V_MUL_HI_I32 0x16C
3528 #define V_008DFC_SQ_V_DIV_SCALE_F32 0x16D
3529 #define V_008DFC_SQ_V_DIV_SCALE_F64 0x16E
3530 #define V_008DFC_SQ_V_DIV_FMAS_F32 0x16F
3531 #define V_008DFC_SQ_V_DIV_FMAS_F64 0x170
3532 #define V_008DFC_SQ_V_MSAD_U8 0x171
3533 #define V_008DFC_SQ_V_QSAD_U8 0x172
3534 #define V_008DFC_SQ_V_MQSAD_U8 0x173
3535 #define V_008DFC_SQ_V_TRIG_PREOP_F64 0x174
3536 /* CIK */
3537 #define V_008DFC_SQ_V_MQSAD_U32_U8 0x175
3538 #define V_008DFC_SQ_V_MAD_U64_U32 0x176
3539 #define V_008DFC_SQ_V_MAD_I64_I32 0x177
3540 /* */
3541 #define V_008DFC_SQ_V_OP1_OFFSET 0x180
3542 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
3543 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
3544 #define C_008DFC_ENCODING 0x03FFFFFF
3545 #define V_008DFC_SQ_ENC_VOP3_FIELD 0x34
3546 #define R_008DFC_SQ_VOP2 0x008DFC
3547 #define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0)
3548 #define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF)
3549 #define C_008DFC_SRC0 0xFFFFFE00
3550 #define V_008DFC_SQ_SGPR 0x00
3551 /* CIK */
3552 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
3553 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
3554 /* */
3555 #define V_008DFC_SQ_VCC_LO 0x6A
3556 #define V_008DFC_SQ_VCC_HI 0x6B
3557 #define V_008DFC_SQ_TBA_LO 0x6C
3558 #define V_008DFC_SQ_TBA_HI 0x6D
3559 #define V_008DFC_SQ_TMA_LO 0x6E
3560 #define V_008DFC_SQ_TMA_HI 0x6F
3561 #define V_008DFC_SQ_TTMP0 0x70
3562 #define V_008DFC_SQ_TTMP1 0x71
3563 #define V_008DFC_SQ_TTMP2 0x72
3564 #define V_008DFC_SQ_TTMP3 0x73
3565 #define V_008DFC_SQ_TTMP4 0x74
3566 #define V_008DFC_SQ_TTMP5 0x75
3567 #define V_008DFC_SQ_TTMP6 0x76
3568 #define V_008DFC_SQ_TTMP7 0x77
3569 #define V_008DFC_SQ_TTMP8 0x78
3570 #define V_008DFC_SQ_TTMP9 0x79
3571 #define V_008DFC_SQ_TTMP10 0x7A
3572 #define V_008DFC_SQ_TTMP11 0x7B
3573 #define V_008DFC_SQ_M0 0x7C
3574 #define V_008DFC_SQ_EXEC_LO 0x7E
3575 #define V_008DFC_SQ_EXEC_HI 0x7F
3576 #define V_008DFC_SQ_SRC_0 0x80
3577 #define V_008DFC_SQ_SRC_1_INT 0x81
3578 #define V_008DFC_SQ_SRC_2_INT 0x82
3579 #define V_008DFC_SQ_SRC_3_INT 0x83
3580 #define V_008DFC_SQ_SRC_4_INT 0x84
3581 #define V_008DFC_SQ_SRC_5_INT 0x85
3582 #define V_008DFC_SQ_SRC_6_INT 0x86
3583 #define V_008DFC_SQ_SRC_7_INT 0x87
3584 #define V_008DFC_SQ_SRC_8_INT 0x88
3585 #define V_008DFC_SQ_SRC_9_INT 0x89
3586 #define V_008DFC_SQ_SRC_10_INT 0x8A
3587 #define V_008DFC_SQ_SRC_11_INT 0x8B
3588 #define V_008DFC_SQ_SRC_12_INT 0x8C
3589 #define V_008DFC_SQ_SRC_13_INT 0x8D
3590 #define V_008DFC_SQ_SRC_14_INT 0x8E
3591 #define V_008DFC_SQ_SRC_15_INT 0x8F
3592 #define V_008DFC_SQ_SRC_16_INT 0x90
3593 #define V_008DFC_SQ_SRC_17_INT 0x91
3594 #define V_008DFC_SQ_SRC_18_INT 0x92
3595 #define V_008DFC_SQ_SRC_19_INT 0x93
3596 #define V_008DFC_SQ_SRC_20_INT 0x94
3597 #define V_008DFC_SQ_SRC_21_INT 0x95
3598 #define V_008DFC_SQ_SRC_22_INT 0x96
3599 #define V_008DFC_SQ_SRC_23_INT 0x97
3600 #define V_008DFC_SQ_SRC_24_INT 0x98
3601 #define V_008DFC_SQ_SRC_25_INT 0x99
3602 #define V_008DFC_SQ_SRC_26_INT 0x9A
3603 #define V_008DFC_SQ_SRC_27_INT 0x9B
3604 #define V_008DFC_SQ_SRC_28_INT 0x9C
3605 #define V_008DFC_SQ_SRC_29_INT 0x9D
3606 #define V_008DFC_SQ_SRC_30_INT 0x9E
3607 #define V_008DFC_SQ_SRC_31_INT 0x9F
3608 #define V_008DFC_SQ_SRC_32_INT 0xA0
3609 #define V_008DFC_SQ_SRC_33_INT 0xA1
3610 #define V_008DFC_SQ_SRC_34_INT 0xA2
3611 #define V_008DFC_SQ_SRC_35_INT 0xA3
3612 #define V_008DFC_SQ_SRC_36_INT 0xA4
3613 #define V_008DFC_SQ_SRC_37_INT 0xA5
3614 #define V_008DFC_SQ_SRC_38_INT 0xA6
3615 #define V_008DFC_SQ_SRC_39_INT 0xA7
3616 #define V_008DFC_SQ_SRC_40_INT 0xA8
3617 #define V_008DFC_SQ_SRC_41_INT 0xA9
3618 #define V_008DFC_SQ_SRC_42_INT 0xAA
3619 #define V_008DFC_SQ_SRC_43_INT 0xAB
3620 #define V_008DFC_SQ_SRC_44_INT 0xAC
3621 #define V_008DFC_SQ_SRC_45_INT 0xAD
3622 #define V_008DFC_SQ_SRC_46_INT 0xAE
3623 #define V_008DFC_SQ_SRC_47_INT 0xAF
3624 #define V_008DFC_SQ_SRC_48_INT 0xB0
3625 #define V_008DFC_SQ_SRC_49_INT 0xB1
3626 #define V_008DFC_SQ_SRC_50_INT 0xB2
3627 #define V_008DFC_SQ_SRC_51_INT 0xB3
3628 #define V_008DFC_SQ_SRC_52_INT 0xB4
3629 #define V_008DFC_SQ_SRC_53_INT 0xB5
3630 #define V_008DFC_SQ_SRC_54_INT 0xB6
3631 #define V_008DFC_SQ_SRC_55_INT 0xB7
3632 #define V_008DFC_SQ_SRC_56_INT 0xB8
3633 #define V_008DFC_SQ_SRC_57_INT 0xB9
3634 #define V_008DFC_SQ_SRC_58_INT 0xBA
3635 #define V_008DFC_SQ_SRC_59_INT 0xBB
3636 #define V_008DFC_SQ_SRC_60_INT 0xBC
3637 #define V_008DFC_SQ_SRC_61_INT 0xBD
3638 #define V_008DFC_SQ_SRC_62_INT 0xBE
3639 #define V_008DFC_SQ_SRC_63_INT 0xBF
3640 #define V_008DFC_SQ_SRC_64_INT 0xC0
3641 #define V_008DFC_SQ_SRC_M_1_INT 0xC1
3642 #define V_008DFC_SQ_SRC_M_2_INT 0xC2
3643 #define V_008DFC_SQ_SRC_M_3_INT 0xC3
3644 #define V_008DFC_SQ_SRC_M_4_INT 0xC4
3645 #define V_008DFC_SQ_SRC_M_5_INT 0xC5
3646 #define V_008DFC_SQ_SRC_M_6_INT 0xC6
3647 #define V_008DFC_SQ_SRC_M_7_INT 0xC7
3648 #define V_008DFC_SQ_SRC_M_8_INT 0xC8
3649 #define V_008DFC_SQ_SRC_M_9_INT 0xC9
3650 #define V_008DFC_SQ_SRC_M_10_INT 0xCA
3651 #define V_008DFC_SQ_SRC_M_11_INT 0xCB
3652 #define V_008DFC_SQ_SRC_M_12_INT 0xCC
3653 #define V_008DFC_SQ_SRC_M_13_INT 0xCD
3654 #define V_008DFC_SQ_SRC_M_14_INT 0xCE
3655 #define V_008DFC_SQ_SRC_M_15_INT 0xCF
3656 #define V_008DFC_SQ_SRC_M_16_INT 0xD0
3657 #define V_008DFC_SQ_SRC_0_5 0xF0
3658 #define V_008DFC_SQ_SRC_M_0_5 0xF1
3659 #define V_008DFC_SQ_SRC_1 0xF2
3660 #define V_008DFC_SQ_SRC_M_1 0xF3
3661 #define V_008DFC_SQ_SRC_2 0xF4
3662 #define V_008DFC_SQ_SRC_M_2 0xF5
3663 #define V_008DFC_SQ_SRC_4 0xF6
3664 #define V_008DFC_SQ_SRC_M_4 0xF7
3665 #define V_008DFC_SQ_SRC_VCCZ 0xFB
3666 #define V_008DFC_SQ_SRC_EXECZ 0xFC
3667 #define V_008DFC_SQ_SRC_SCC 0xFD
3668 #define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE
3669 #define V_008DFC_SQ_SRC_VGPR 0x100
3670 #define S_008DFC_VSRC1(x) (((x) & 0xFF) << 9)
3671 #define G_008DFC_VSRC1(x) (((x) >> 9) & 0xFF)
3672 #define C_008DFC_VSRC1 0xFFFE01FF
3673 #define V_008DFC_SQ_VGPR 0x00
3674 #define S_008DFC_VDST(x) (((x) & 0xFF) << 17)
3675 #define G_008DFC_VDST(x) (((x) >> 17) & 0xFF)
3676 #define C_008DFC_VDST 0xFE01FFFF
3677 #define V_008DFC_SQ_VGPR 0x00
3678 #define S_008DFC_OP(x) (((x) & 0x3F) << 25)
3679 #define G_008DFC_OP(x) (((x) >> 25) & 0x3F)
3680 #define C_008DFC_OP 0x81FFFFFF
3681 #define V_008DFC_SQ_V_CNDMASK_B32 0x00
3682 #define V_008DFC_SQ_V_READLANE_B32 0x01
3683 #define V_008DFC_SQ_V_WRITELANE_B32 0x02
3684 #define V_008DFC_SQ_V_ADD_F32 0x03
3685 #define V_008DFC_SQ_V_SUB_F32 0x04
3686 #define V_008DFC_SQ_V_SUBREV_F32 0x05
3687 #define V_008DFC_SQ_V_MAC_LEGACY_F32 0x06
3688 #define V_008DFC_SQ_V_MUL_LEGACY_F32 0x07
3689 #define V_008DFC_SQ_V_MUL_F32 0x08
3690 #define V_008DFC_SQ_V_MUL_I32_I24 0x09
3691 #define V_008DFC_SQ_V_MUL_HI_I32_I24 0x0A
3692 #define V_008DFC_SQ_V_MUL_U32_U24 0x0B
3693 #define V_008DFC_SQ_V_MUL_HI_U32_U24 0x0C
3694 #define V_008DFC_SQ_V_MIN_LEGACY_F32 0x0D
3695 #define V_008DFC_SQ_V_MAX_LEGACY_F32 0x0E
3696 #define V_008DFC_SQ_V_MIN_F32 0x0F
3697 #define V_008DFC_SQ_V_MAX_F32 0x10
3698 #define V_008DFC_SQ_V_MIN_I32 0x11
3699 #define V_008DFC_SQ_V_MAX_I32 0x12
3700 #define V_008DFC_SQ_V_MIN_U32 0x13
3701 #define V_008DFC_SQ_V_MAX_U32 0x14
3702 #define V_008DFC_SQ_V_LSHR_B32 0x15
3703 #define V_008DFC_SQ_V_LSHRREV_B32 0x16
3704 #define V_008DFC_SQ_V_ASHR_I32 0x17
3705 #define V_008DFC_SQ_V_ASHRREV_I32 0x18
3706 #define V_008DFC_SQ_V_LSHL_B32 0x19
3707 #define V_008DFC_SQ_V_LSHLREV_B32 0x1A
3708 #define V_008DFC_SQ_V_AND_B32 0x1B
3709 #define V_008DFC_SQ_V_OR_B32 0x1C
3710 #define V_008DFC_SQ_V_XOR_B32 0x1D
3711 #define V_008DFC_SQ_V_BFM_B32 0x1E
3712 #define V_008DFC_SQ_V_MAC_F32 0x1F
3713 #define V_008DFC_SQ_V_MADMK_F32 0x20
3714 #define V_008DFC_SQ_V_MADAK_F32 0x21
3715 #define V_008DFC_SQ_V_BCNT_U32_B32 0x22
3716 #define V_008DFC_SQ_V_MBCNT_LO_U32_B32 0x23
3717 #define V_008DFC_SQ_V_MBCNT_HI_U32_B32 0x24
3718 #define V_008DFC_SQ_V_ADD_I32 0x25
3719 #define V_008DFC_SQ_V_SUB_I32 0x26
3720 #define V_008DFC_SQ_V_SUBREV_I32 0x27
3721 #define V_008DFC_SQ_V_ADDC_U32 0x28
3722 #define V_008DFC_SQ_V_SUBB_U32 0x29
3723 #define V_008DFC_SQ_V_SUBBREV_U32 0x2A
3724 #define V_008DFC_SQ_V_LDEXP_F32 0x2B
3725 #define V_008DFC_SQ_V_CVT_PKACCUM_U8_F32 0x2C
3726 #define V_008DFC_SQ_V_CVT_PKNORM_I16_F32 0x2D
3727 #define V_008DFC_SQ_V_CVT_PKNORM_U16_F32 0x2E
3728 #define V_008DFC_SQ_V_CVT_PKRTZ_F16_F32 0x2F
3729 #define V_008DFC_SQ_V_CVT_PK_U16_U32 0x30
3730 #define V_008DFC_SQ_V_CVT_PK_I16_I32 0x31
3731 #define S_008DFC_ENCODING(x) (((x) & 0x1) << 31)
3732 #define G_008DFC_ENCODING(x) (((x) >> 31) & 0x1)
3733 #define C_008DFC_ENCODING 0x7FFFFFFF
3734 #define R_008DFC_SQ_VOP3_0_SDST_ENC 0x008DFC
3735 #define S_008DFC_VDST(x) (((x) & 0xFF) << 0)
3736 #define G_008DFC_VDST(x) (((x) >> 0) & 0xFF)
3737 #define C_008DFC_VDST 0xFFFFFF00
3738 #define V_008DFC_SQ_VGPR 0x00
3739 #define S_008DFC_SDST(x) (((x) & 0x7F) << 8)
3740 #define G_008DFC_SDST(x) (((x) >> 8) & 0x7F)
3741 #define C_008DFC_SDST 0xFFFF80FF
3742 #define V_008DFC_SQ_SGPR 0x00
3743 /* CIK */
3744 #define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68
3745 #define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69
3746 /* */
3747 #define V_008DFC_SQ_VCC_LO 0x6A
3748 #define V_008DFC_SQ_VCC_HI 0x6B
3749 #define V_008DFC_SQ_TBA_LO 0x6C
3750 #define V_008DFC_SQ_TBA_HI 0x6D
3751 #define V_008DFC_SQ_TMA_LO 0x6E
3752 #define V_008DFC_SQ_TMA_HI 0x6F
3753 #define V_008DFC_SQ_TTMP0 0x70
3754 #define V_008DFC_SQ_TTMP1 0x71
3755 #define V_008DFC_SQ_TTMP2 0x72
3756 #define V_008DFC_SQ_TTMP3 0x73
3757 #define V_008DFC_SQ_TTMP4 0x74
3758 #define V_008DFC_SQ_TTMP5 0x75
3759 #define V_008DFC_SQ_TTMP6 0x76
3760 #define V_008DFC_SQ_TTMP7 0x77
3761 #define V_008DFC_SQ_TTMP8 0x78
3762 #define V_008DFC_SQ_TTMP9 0x79
3763 #define V_008DFC_SQ_TTMP10 0x7A
3764 #define V_008DFC_SQ_TTMP11 0x7B
3765 #define S_008DFC_OP(x) (((x) & 0x1FF) << 17)
3766 #define G_008DFC_OP(x) (((x) >> 17) & 0x1FF)
3767 #define C_008DFC_OP 0xFC01FFFF
3768 #define V_008DFC_SQ_V_OPC_OFFSET 0x00
3769 #define V_008DFC_SQ_V_OP2_OFFSET 0x100
3770 #define V_008DFC_SQ_V_MAD_LEGACY_F32 0x140
3771 #define V_008DFC_SQ_V_MAD_F32 0x141
3772 #define V_008DFC_SQ_V_MAD_I32_I24 0x142
3773 #define V_008DFC_SQ_V_MAD_U32_U24 0x143
3774 #define V_008DFC_SQ_V_CUBEID_F32 0x144
3775 #define V_008DFC_SQ_V_CUBESC_F32 0x145
3776 #define V_008DFC_SQ_V_CUBETC_F32 0x146
3777 #define V_008DFC_SQ_V_CUBEMA_F32 0x147
3778 #define V_008DFC_SQ_V_BFE_U32 0x148
3779 #define V_008DFC_SQ_V_BFE_I32 0x149
3780 #define V_008DFC_SQ_V_BFI_B32 0x14A
3781 #define V_008DFC_SQ_V_FMA_F32 0x14B
3782 #define V_008DFC_SQ_V_FMA_F64 0x14C
3783 #define V_008DFC_SQ_V_LERP_U8 0x14D
3784 #define V_008DFC_SQ_V_ALIGNBIT_B32 0x14E
3785 #define V_008DFC_SQ_V_ALIGNBYTE_B32 0x14F
3786 #define V_008DFC_SQ_V_MULLIT_F32 0x150
3787 #define V_008DFC_SQ_V_MIN3_F32 0x151
3788 #define V_008DFC_SQ_V_MIN3_I32 0x152
3789 #define V_008DFC_SQ_V_MIN3_U32 0x153
3790 #define V_008DFC_SQ_V_MAX3_F32 0x154
3791 #define V_008DFC_SQ_V_MAX3_I32 0x155
3792 #define V_008DFC_SQ_V_MAX3_U32 0x156
3793 #define V_008DFC_SQ_V_MED3_F32 0x157
3794 #define V_008DFC_SQ_V_MED3_I32 0x158
3795 #define V_008DFC_SQ_V_MED3_U32 0x159
3796 #define V_008DFC_SQ_V_SAD_U8 0x15A
3797 #define V_008DFC_SQ_V_SAD_HI_U8 0x15B
3798 #define V_008DFC_SQ_V_SAD_U16 0x15C
3799 #define V_008DFC_SQ_V_SAD_U32 0x15D
3800 #define V_008DFC_SQ_V_CVT_PK_U8_F32 0x15E
3801 #define V_008DFC_SQ_V_DIV_FIXUP_F32 0x15F
3802 #define V_008DFC_SQ_V_DIV_FIXUP_F64 0x160
3803 #define V_008DFC_SQ_V_LSHL_B64 0x161
3804 #define V_008DFC_SQ_V_LSHR_B64 0x162
3805 #define V_008DFC_SQ_V_ASHR_I64 0x163
3806 #define V_008DFC_SQ_V_ADD_F64 0x164
3807 #define V_008DFC_SQ_V_MUL_F64 0x165
3808 #define V_008DFC_SQ_V_MIN_F64 0x166
3809 #define V_008DFC_SQ_V_MAX_F64 0x167
3810 #define V_008DFC_SQ_V_LDEXP_F64 0x168
3811 #define V_008DFC_SQ_V_MUL_LO_U32 0x169
3812 #define V_008DFC_SQ_V_MUL_HI_U32 0x16A
3813 #define V_008DFC_SQ_V_MUL_LO_I32 0x16B
3814 #define V_008DFC_SQ_V_MUL_HI_I32 0x16C
3815 #define V_008DFC_SQ_V_DIV_SCALE_F32 0x16D
3816 #define V_008DFC_SQ_V_DIV_SCALE_F64 0x16E
3817 #define V_008DFC_SQ_V_DIV_FMAS_F32 0x16F
3818 #define V_008DFC_SQ_V_DIV_FMAS_F64 0x170
3819 #define V_008DFC_SQ_V_MSAD_U8 0x171
3820 #define V_008DFC_SQ_V_QSAD_U8 0x172
3821 #define V_008DFC_SQ_V_MQSAD_U8 0x173
3822 #define V_008DFC_SQ_V_TRIG_PREOP_F64 0x174
3823 /* CIK */
3824 #define V_008DFC_SQ_V_MQSAD_U32_U8 0x175
3825 #define V_008DFC_SQ_V_MAD_U64_U32 0x176
3826 #define V_008DFC_SQ_V_MAD_I64_I32 0x177
3827 /* */
3828 #define V_008DFC_SQ_V_OP1_OFFSET 0x180
3829 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
3830 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
3831 #define C_008DFC_ENCODING 0x03FFFFFF
3832 #define V_008DFC_SQ_ENC_VOP3_FIELD 0x34
3833 #define R_008DFC_SQ_MUBUF_0 0x008DFC
3834 #define S_008DFC_OFFSET(x) (((x) & 0xFFF) << 0)
3835 #define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFFF)
3836 #define C_008DFC_OFFSET 0xFFFFF000
3837 #define S_008DFC_OFFEN(x) (((x) & 0x1) << 12)
3838 #define G_008DFC_OFFEN(x) (((x) >> 12) & 0x1)
3839 #define C_008DFC_OFFEN 0xFFFFEFFF
3840 #define S_008DFC_IDXEN(x) (((x) & 0x1) << 13)
3841 #define G_008DFC_IDXEN(x) (((x) >> 13) & 0x1)
3842 #define C_008DFC_IDXEN 0xFFFFDFFF
3843 #define S_008DFC_GLC(x) (((x) & 0x1) << 14)
3844 #define G_008DFC_GLC(x) (((x) >> 14) & 0x1)
3845 #define C_008DFC_GLC 0xFFFFBFFF
3846 #define S_008DFC_ADDR64(x) (((x) & 0x1) << 15)
3847 #define G_008DFC_ADDR64(x) (((x) >> 15) & 0x1)
3848 #define C_008DFC_ADDR64 0xFFFF7FFF
3849 #define S_008DFC_LDS(x) (((x) & 0x1) << 16)
3850 #define G_008DFC_LDS(x) (((x) >> 16) & 0x1)
3851 #define C_008DFC_LDS 0xFFFEFFFF
3852 #define S_008DFC_OP(x) (((x) & 0x7F) << 18)
3853 #define G_008DFC_OP(x) (((x) >> 18) & 0x7F)
3854 #define C_008DFC_OP 0xFE03FFFF
3855 #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_X 0x00
3856 #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XY 0x01
3857 #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XYZ 0x02
3858 #define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XYZW 0x03
3859 #define V_008DFC_SQ_BUFFER_STORE_FORMAT_X 0x04
3860 #define V_008DFC_SQ_BUFFER_STORE_FORMAT_XY 0x05
3861 #define V_008DFC_SQ_BUFFER_STORE_FORMAT_XYZ 0x06
3862 #define V_008DFC_SQ_BUFFER_STORE_FORMAT_XYZW 0x07
3863 #define V_008DFC_SQ_BUFFER_LOAD_UBYTE 0x08
3864 #define V_008DFC_SQ_BUFFER_LOAD_SBYTE 0x09
3865 #define V_008DFC_SQ_BUFFER_LOAD_USHORT 0x0A
3866 #define V_008DFC_SQ_BUFFER_LOAD_SSHORT 0x0B
3867 #define V_008DFC_SQ_BUFFER_LOAD_DWORD 0x0C
3868 #define V_008DFC_SQ_BUFFER_LOAD_DWORDX2 0x0D
3869 #define V_008DFC_SQ_BUFFER_LOAD_DWORDX4 0x0E
3870 /* CIK */
3871 #define V_008DFC_SQ_BUFFER_LOAD_DWORDX3 0x0F
3872 /* */
3873 #define V_008DFC_SQ_BUFFER_STORE_BYTE 0x18
3874 #define V_008DFC_SQ_BUFFER_STORE_SHORT 0x1A
3875 #define V_008DFC_SQ_BUFFER_STORE_DWORD 0x1C
3876 #define V_008DFC_SQ_BUFFER_STORE_DWORDX2 0x1D
3877 #define V_008DFC_SQ_BUFFER_STORE_DWORDX4 0x1E
3878 /* CIK */
3879 #define V_008DFC_SQ_BUFFER_STORE_DWORDX3 0x1F
3880 /* */
3881 #define V_008DFC_SQ_BUFFER_ATOMIC_SWAP 0x30
3882 #define V_008DFC_SQ_BUFFER_ATOMIC_CMPSWAP 0x31
3883 #define V_008DFC_SQ_BUFFER_ATOMIC_ADD 0x32
3884 #define V_008DFC_SQ_BUFFER_ATOMIC_SUB 0x33
3885 #define V_008DFC_SQ_BUFFER_ATOMIC_RSUB 0x34 /* not on CIK */
3886 #define V_008DFC_SQ_BUFFER_ATOMIC_SMIN 0x35
3887 #define V_008DFC_SQ_BUFFER_ATOMIC_UMIN 0x36
3888 #define V_008DFC_SQ_BUFFER_ATOMIC_SMAX 0x37
3889 #define V_008DFC_SQ_BUFFER_ATOMIC_UMAX 0x38
3890 #define V_008DFC_SQ_BUFFER_ATOMIC_AND 0x39
3891 #define V_008DFC_SQ_BUFFER_ATOMIC_OR 0x3A
3892 #define V_008DFC_SQ_BUFFER_ATOMIC_XOR 0x3B
3893 #define V_008DFC_SQ_BUFFER_ATOMIC_INC 0x3C
3894 #define V_008DFC_SQ_BUFFER_ATOMIC_DEC 0x3D
3895 #define V_008DFC_SQ_BUFFER_ATOMIC_FCMPSWAP 0x3E
3896 #define V_008DFC_SQ_BUFFER_ATOMIC_FMIN 0x3F
3897 #define V_008DFC_SQ_BUFFER_ATOMIC_FMAX 0x40
3898 #define V_008DFC_SQ_BUFFER_ATOMIC_SWAP_X2 0x50
3899 #define V_008DFC_SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x51
3900 #define V_008DFC_SQ_BUFFER_ATOMIC_ADD_X2 0x52
3901 #define V_008DFC_SQ_BUFFER_ATOMIC_SUB_X2 0x53
3902 #define V_008DFC_SQ_BUFFER_ATOMIC_RSUB_X2 0x54 /* not on CIK */
3903 #define V_008DFC_SQ_BUFFER_ATOMIC_SMIN_X2 0x55
3904 #define V_008DFC_SQ_BUFFER_ATOMIC_UMIN_X2 0x56
3905 #define V_008DFC_SQ_BUFFER_ATOMIC_SMAX_X2 0x57
3906 #define V_008DFC_SQ_BUFFER_ATOMIC_UMAX_X2 0x58
3907 #define V_008DFC_SQ_BUFFER_ATOMIC_AND_X2 0x59
3908 #define V_008DFC_SQ_BUFFER_ATOMIC_OR_X2 0x5A
3909 #define V_008DFC_SQ_BUFFER_ATOMIC_XOR_X2 0x5B
3910 #define V_008DFC_SQ_BUFFER_ATOMIC_INC_X2 0x5C
3911 #define V_008DFC_SQ_BUFFER_ATOMIC_DEC_X2 0x5D
3912 #define V_008DFC_SQ_BUFFER_ATOMIC_FCMPSWAP_X2 0x5E
3913 #define V_008DFC_SQ_BUFFER_ATOMIC_FMIN_X2 0x5F
3914 #define V_008DFC_SQ_BUFFER_ATOMIC_FMAX_X2 0x60
3915 #define V_008DFC_SQ_BUFFER_WBINVL1_SC 0x70
3916 /* CIK */
3917 #define V_008DFC_SQ_BUFFER_WBINVL1_VOL 0x70
3918 /* */
3919 #define V_008DFC_SQ_BUFFER_WBINVL1 0x71
3920 #define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26)
3921 #define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F)
3922 #define C_008DFC_ENCODING 0x03FFFFFF
3923 #define V_008DFC_SQ_ENC_MUBUF_FIELD 0x38
3924 #endif
3925 #define R_030E00_TA_CS_BC_BASE_ADDR 0x030E00
3926 #define R_030E04_TA_CS_BC_BASE_ADDR_HI 0x030E04
3927 #define S_030E04_ADDRESS(x) (((x) & 0xFF) << 0)
3928 #define G_030E04_ADDRESS(x) (((x) >> 0) & 0xFF)
3929 #define C_030E04_ADDRESS 0xFFFFFF00
3930 #define R_030F00_DB_OCCLUSION_COUNT0_LOW 0x030F00
3931 #define R_008F00_SQ_BUF_RSRC_WORD0 0x008F00
3932 #define R_030F04_DB_OCCLUSION_COUNT0_HI 0x030F04
3933 #define S_030F04_COUNT_HI(x) (((x) & 0x7FFFFFFF) << 0)
3934 #define G_030F04_COUNT_HI(x) (((x) >> 0) & 0x7FFFFFFF)
3935 #define C_030F04_COUNT_HI 0x80000000
3936 #define R_008F04_SQ_BUF_RSRC_WORD1 0x008F04
3937 #define S_008F04_BASE_ADDRESS_HI(x) (((x) & 0xFFFF) << 0)
3938 #define G_008F04_BASE_ADDRESS_HI(x) (((x) >> 0) & 0xFFFF)
3939 #define C_008F04_BASE_ADDRESS_HI 0xFFFF0000
3940 #define S_008F04_STRIDE(x) (((x) & 0x3FFF) << 16)
3941 #define G_008F04_STRIDE(x) (((x) >> 16) & 0x3FFF)
3942 #define C_008F04_STRIDE 0xC000FFFF
3943 #define S_008F04_CACHE_SWIZZLE(x) (((x) & 0x1) << 30)
3944 #define G_008F04_CACHE_SWIZZLE(x) (((x) >> 30) & 0x1)
3945 #define C_008F04_CACHE_SWIZZLE 0xBFFFFFFF
3946 #define S_008F04_SWIZZLE_ENABLE(x) (((x) & 0x1) << 31)
3947 #define G_008F04_SWIZZLE_ENABLE(x) (((x) >> 31) & 0x1)
3948 #define C_008F04_SWIZZLE_ENABLE 0x7FFFFFFF
3949 #define R_030F08_DB_OCCLUSION_COUNT1_LOW 0x030F08
3950 #define R_008F08_SQ_BUF_RSRC_WORD2 0x008F08
3951 #define R_030F0C_DB_OCCLUSION_COUNT1_HI 0x030F0C
3952 #define S_030F0C_COUNT_HI(x) (((x) & 0x7FFFFFFF) << 0)
3953 #define G_030F0C_COUNT_HI(x) (((x) >> 0) & 0x7FFFFFFF)
3954 #define C_030F0C_COUNT_HI 0x80000000
3955 #define R_008F0C_SQ_BUF_RSRC_WORD3 0x008F0C
3956 #define S_008F0C_DST_SEL_X(x) (((x) & 0x07) << 0)
3957 #define G_008F0C_DST_SEL_X(x) (((x) >> 0) & 0x07)
3958 #define C_008F0C_DST_SEL_X 0xFFFFFFF8
3959 #define V_008F0C_SQ_SEL_0 0x00
3960 #define V_008F0C_SQ_SEL_1 0x01
3961 #define V_008F0C_SQ_SEL_RESERVED_0 0x02
3962 #define V_008F0C_SQ_SEL_RESERVED_1 0x03
3963 #define V_008F0C_SQ_SEL_X 0x04
3964 #define V_008F0C_SQ_SEL_Y 0x05
3965 #define V_008F0C_SQ_SEL_Z 0x06
3966 #define V_008F0C_SQ_SEL_W 0x07
3967 #define S_008F0C_DST_SEL_Y(x) (((x) & 0x07) << 3)
3968 #define G_008F0C_DST_SEL_Y(x) (((x) >> 3) & 0x07)
3969 #define C_008F0C_DST_SEL_Y 0xFFFFFFC7
3970 #define V_008F0C_SQ_SEL_0 0x00
3971 #define V_008F0C_SQ_SEL_1 0x01
3972 #define V_008F0C_SQ_SEL_RESERVED_0 0x02
3973 #define V_008F0C_SQ_SEL_RESERVED_1 0x03
3974 #define V_008F0C_SQ_SEL_X 0x04
3975 #define V_008F0C_SQ_SEL_Y 0x05
3976 #define V_008F0C_SQ_SEL_Z 0x06
3977 #define V_008F0C_SQ_SEL_W 0x07
3978 #define S_008F0C_DST_SEL_Z(x) (((x) & 0x07) << 6)
3979 #define G_008F0C_DST_SEL_Z(x) (((x) >> 6) & 0x07)
3980 #define C_008F0C_DST_SEL_Z 0xFFFFFE3F
3981 #define V_008F0C_SQ_SEL_0 0x00
3982 #define V_008F0C_SQ_SEL_1 0x01
3983 #define V_008F0C_SQ_SEL_RESERVED_0 0x02
3984 #define V_008F0C_SQ_SEL_RESERVED_1 0x03
3985 #define V_008F0C_SQ_SEL_X 0x04
3986 #define V_008F0C_SQ_SEL_Y 0x05
3987 #define V_008F0C_SQ_SEL_Z 0x06
3988 #define V_008F0C_SQ_SEL_W 0x07
3989 #define S_008F0C_DST_SEL_W(x) (((x) & 0x07) << 9)
3990 #define G_008F0C_DST_SEL_W(x) (((x) >> 9) & 0x07)
3991 #define C_008F0C_DST_SEL_W 0xFFFFF1FF
3992 #define V_008F0C_SQ_SEL_0 0x00
3993 #define V_008F0C_SQ_SEL_1 0x01
3994 #define V_008F0C_SQ_SEL_RESERVED_0 0x02
3995 #define V_008F0C_SQ_SEL_RESERVED_1 0x03
3996 #define V_008F0C_SQ_SEL_X 0x04
3997 #define V_008F0C_SQ_SEL_Y 0x05
3998 #define V_008F0C_SQ_SEL_Z 0x06
3999 #define V_008F0C_SQ_SEL_W 0x07
4000 #define S_008F0C_NUM_FORMAT(x) (((x) & 0x07) << 12)
4001 #define G_008F0C_NUM_FORMAT(x) (((x) >> 12) & 0x07)
4002 #define C_008F0C_NUM_FORMAT 0xFFFF8FFF
4003 #define V_008F0C_BUF_NUM_FORMAT_UNORM 0x00
4004 #define V_008F0C_BUF_NUM_FORMAT_SNORM 0x01
4005 #define V_008F0C_BUF_NUM_FORMAT_USCALED 0x02
4006 #define V_008F0C_BUF_NUM_FORMAT_SSCALED 0x03
4007 #define V_008F0C_BUF_NUM_FORMAT_UINT 0x04
4008 #define V_008F0C_BUF_NUM_FORMAT_SINT 0x05
4009 #define V_008F0C_BUF_NUM_FORMAT_SNORM_OGL 0x06
4010 #define V_008F0C_BUF_NUM_FORMAT_FLOAT 0x07
4011 #define S_008F0C_DATA_FORMAT(x) (((x) & 0x0F) << 15)
4012 #define G_008F0C_DATA_FORMAT(x) (((x) >> 15) & 0x0F)
4013 #define C_008F0C_DATA_FORMAT 0xFFF87FFF
4014 #define V_008F0C_BUF_DATA_FORMAT_INVALID 0x00
4015 #define V_008F0C_BUF_DATA_FORMAT_8 0x01
4016 #define V_008F0C_BUF_DATA_FORMAT_16 0x02
4017 #define V_008F0C_BUF_DATA_FORMAT_8_8 0x03
4018 #define V_008F0C_BUF_DATA_FORMAT_32 0x04
4019 #define V_008F0C_BUF_DATA_FORMAT_16_16 0x05
4020 #define V_008F0C_BUF_DATA_FORMAT_10_11_11 0x06
4021 #define V_008F0C_BUF_DATA_FORMAT_11_11_10 0x07
4022 #define V_008F0C_BUF_DATA_FORMAT_10_10_10_2 0x08
4023 #define V_008F0C_BUF_DATA_FORMAT_2_10_10_10 0x09
4024 #define V_008F0C_BUF_DATA_FORMAT_8_8_8_8 0x0A
4025 #define V_008F0C_BUF_DATA_FORMAT_32_32 0x0B
4026 #define V_008F0C_BUF_DATA_FORMAT_16_16_16_16 0x0C
4027 #define V_008F0C_BUF_DATA_FORMAT_32_32_32 0x0D
4028 #define V_008F0C_BUF_DATA_FORMAT_32_32_32_32 0x0E
4029 #define V_008F0C_BUF_DATA_FORMAT_RESERVED_15 0x0F
4030 #define S_008F0C_ELEMENT_SIZE(x) (((x) & 0x03) << 19)
4031 #define G_008F0C_ELEMENT_SIZE(x) (((x) >> 19) & 0x03)
4032 #define C_008F0C_ELEMENT_SIZE 0xFFE7FFFF
4033 #define S_008F0C_INDEX_STRIDE(x) (((x) & 0x03) << 21)
4034 #define G_008F0C_INDEX_STRIDE(x) (((x) >> 21) & 0x03)
4035 #define C_008F0C_INDEX_STRIDE 0xFF9FFFFF
4036 #define S_008F0C_ADD_TID_ENABLE(x) (((x) & 0x1) << 23)
4037 #define G_008F0C_ADD_TID_ENABLE(x) (((x) >> 23) & 0x1)
4038 #define C_008F0C_ADD_TID_ENABLE 0xFF7FFFFF
4039 /* CIK */
4040 #define S_008F0C_ATC(x) (((x) & 0x1) << 24)
4041 #define G_008F0C_ATC(x) (((x) >> 24) & 0x1)
4042 #define C_008F0C_ATC 0xFEFFFFFF
4043 /* */
4044 #define S_008F0C_HASH_ENABLE(x) (((x) & 0x1) << 25)
4045 #define G_008F0C_HASH_ENABLE(x) (((x) >> 25) & 0x1)
4046 #define C_008F0C_HASH_ENABLE 0xFDFFFFFF
4047 #define S_008F0C_HEAP(x) (((x) & 0x1) << 26)
4048 #define G_008F0C_HEAP(x) (((x) >> 26) & 0x1)
4049 #define C_008F0C_HEAP 0xFBFFFFFF
4050 /* CIK */
4051 #define S_008F0C_MTYPE(x) (((x) & 0x07) << 27)
4052 #define G_008F0C_MTYPE(x) (((x) >> 27) & 0x07)
4053 #define C_008F0C_MTYPE 0xC7FFFFFF
4054 /* */
4055 #define S_008F0C_TYPE(x) (((x) & 0x03) << 30)
4056 #define G_008F0C_TYPE(x) (((x) >> 30) & 0x03)
4057 #define C_008F0C_TYPE 0x3FFFFFFF
4058 #define V_008F0C_SQ_RSRC_BUF 0x00
4059 #define V_008F0C_SQ_RSRC_BUF_RSVD_1 0x01
4060 #define V_008F0C_SQ_RSRC_BUF_RSVD_2 0x02
4061 #define V_008F0C_SQ_RSRC_BUF_RSVD_3 0x03
4062 #define R_030F10_DB_OCCLUSION_COUNT2_LOW 0x030F10
4063 #define R_008F10_SQ_IMG_RSRC_WORD0 0x008F10
4064 #define R_030F14_DB_OCCLUSION_COUNT2_HI 0x030F14
4065 #define S_030F14_COUNT_HI(x) (((x) & 0x7FFFFFFF) << 0)
4066 #define G_030F14_COUNT_HI(x) (((x) >> 0) & 0x7FFFFFFF)
4067 #define C_030F14_COUNT_HI 0x80000000
4068 #define R_008F14_SQ_IMG_RSRC_WORD1 0x008F14
4069 #define S_008F14_BASE_ADDRESS_HI(x) (((x) & 0xFF) << 0)
4070 #define G_008F14_BASE_ADDRESS_HI(x) (((x) >> 0) & 0xFF)
4071 #define C_008F14_BASE_ADDRESS_HI 0xFFFFFF00
4072 #define S_008F14_MIN_LOD(x) (((x) & 0xFFF) << 8)
4073 #define G_008F14_MIN_LOD(x) (((x) >> 8) & 0xFFF)
4074 #define C_008F14_MIN_LOD 0xFFF000FF
4075 #define S_008F14_DATA_FORMAT(x) (((x) & 0x3F) << 20)
4076 #define G_008F14_DATA_FORMAT(x) (((x) >> 20) & 0x3F)
4077 #define C_008F14_DATA_FORMAT 0xFC0FFFFF
4078 #define V_008F14_IMG_DATA_FORMAT_INVALID 0x00
4079 #define V_008F14_IMG_DATA_FORMAT_8 0x01
4080 #define V_008F14_IMG_DATA_FORMAT_16 0x02
4081 #define V_008F14_IMG_DATA_FORMAT_8_8 0x03
4082 #define V_008F14_IMG_DATA_FORMAT_32 0x04
4083 #define V_008F14_IMG_DATA_FORMAT_16_16 0x05
4084 #define V_008F14_IMG_DATA_FORMAT_10_11_11 0x06
4085 #define V_008F14_IMG_DATA_FORMAT_11_11_10 0x07
4086 #define V_008F14_IMG_DATA_FORMAT_10_10_10_2 0x08
4087 #define V_008F14_IMG_DATA_FORMAT_2_10_10_10 0x09
4088 #define V_008F14_IMG_DATA_FORMAT_8_8_8_8 0x0A
4089 #define V_008F14_IMG_DATA_FORMAT_32_32 0x0B
4090 #define V_008F14_IMG_DATA_FORMAT_16_16_16_16 0x0C
4091 #define V_008F14_IMG_DATA_FORMAT_32_32_32 0x0D
4092 #define V_008F14_IMG_DATA_FORMAT_32_32_32_32 0x0E
4093 #define V_008F14_IMG_DATA_FORMAT_RESERVED_15 0x0F
4094 #define V_008F14_IMG_DATA_FORMAT_5_6_5 0x10
4095 #define V_008F14_IMG_DATA_FORMAT_1_5_5_5 0x11
4096 #define V_008F14_IMG_DATA_FORMAT_5_5_5_1 0x12
4097 #define V_008F14_IMG_DATA_FORMAT_4_4_4_4 0x13
4098 #define V_008F14_IMG_DATA_FORMAT_8_24 0x14
4099 #define V_008F14_IMG_DATA_FORMAT_24_8 0x15
4100 #define V_008F14_IMG_DATA_FORMAT_X24_8_32 0x16
4101 #define V_008F14_IMG_DATA_FORMAT_RESERVED_23 0x17
4102 #define V_008F14_IMG_DATA_FORMAT_RESERVED_24 0x18
4103 #define V_008F14_IMG_DATA_FORMAT_RESERVED_25 0x19
4104 #define V_008F14_IMG_DATA_FORMAT_RESERVED_26 0x1A
4105 #define V_008F14_IMG_DATA_FORMAT_RESERVED_27 0x1B
4106 #define V_008F14_IMG_DATA_FORMAT_RESERVED_28 0x1C
4107 #define V_008F14_IMG_DATA_FORMAT_RESERVED_29 0x1D
4108 #define V_008F14_IMG_DATA_FORMAT_RESERVED_30 0x1E
4109 #define V_008F14_IMG_DATA_FORMAT_RESERVED_31 0x1F
4110 #define V_008F14_IMG_DATA_FORMAT_GB_GR 0x20
4111 #define V_008F14_IMG_DATA_FORMAT_BG_RG 0x21
4112 #define V_008F14_IMG_DATA_FORMAT_5_9_9_9 0x22
4113 #define V_008F14_IMG_DATA_FORMAT_BC1 0x23
4114 #define V_008F14_IMG_DATA_FORMAT_BC2 0x24
4115 #define V_008F14_IMG_DATA_FORMAT_BC3 0x25
4116 #define V_008F14_IMG_DATA_FORMAT_BC4 0x26
4117 #define V_008F14_IMG_DATA_FORMAT_BC5 0x27
4118 #define V_008F14_IMG_DATA_FORMAT_BC6 0x28
4119 #define V_008F14_IMG_DATA_FORMAT_BC7 0x29
4120 #define V_008F14_IMG_DATA_FORMAT_RESERVED_42 0x2A
4121 #define V_008F14_IMG_DATA_FORMAT_RESERVED_43 0x2B
4122 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1 0x2C
4123 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1 0x2D
4124 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1 0x2E
4125 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2 0x2F
4126 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2 0x30
4127 #define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4 0x31
4128 #define V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1 0x32
4129 #define V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2 0x33
4130 #define V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2 0x34
4131 #define V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4 0x35
4132 #define V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8 0x36
4133 #define V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4 0x37
4134 #define V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8 0x38
4135 #define V_008F14_IMG_DATA_FORMAT_4_4 0x39
4136 #define V_008F14_IMG_DATA_FORMAT_6_5_5 0x3A
4137 #define V_008F14_IMG_DATA_FORMAT_1 0x3B
4138 #define V_008F14_IMG_DATA_FORMAT_1_REVERSED 0x3C
4139 #define V_008F14_IMG_DATA_FORMAT_32_AS_8 0x3D
4140 #define V_008F14_IMG_DATA_FORMAT_32_AS_8_8 0x3E
4141 #define V_008F14_IMG_DATA_FORMAT_32_AS_32_32_32_32 0x3F
4142 #define S_008F14_NUM_FORMAT(x) (((x) & 0x0F) << 26)
4143 #define G_008F14_NUM_FORMAT(x) (((x) >> 26) & 0x0F)
4144 #define C_008F14_NUM_FORMAT 0xC3FFFFFF
4145 #define V_008F14_IMG_NUM_FORMAT_UNORM 0x00
4146 #define V_008F14_IMG_NUM_FORMAT_SNORM 0x01
4147 #define V_008F14_IMG_NUM_FORMAT_USCALED 0x02
4148 #define V_008F14_IMG_NUM_FORMAT_SSCALED 0x03
4149 #define V_008F14_IMG_NUM_FORMAT_UINT 0x04
4150 #define V_008F14_IMG_NUM_FORMAT_SINT 0x05
4151 #define V_008F14_IMG_NUM_FORMAT_SNORM_OGL 0x06
4152 #define V_008F14_IMG_NUM_FORMAT_FLOAT 0x07
4153 #define V_008F14_IMG_NUM_FORMAT_RESERVED_8 0x08
4154 #define V_008F14_IMG_NUM_FORMAT_SRGB 0x09
4155 #define V_008F14_IMG_NUM_FORMAT_UBNORM 0x0A
4156 #define V_008F14_IMG_NUM_FORMAT_UBNORM_OGL 0x0B
4157 #define V_008F14_IMG_NUM_FORMAT_UBINT 0x0C
4158 #define V_008F14_IMG_NUM_FORMAT_UBSCALED 0x0D
4159 #define V_008F14_IMG_NUM_FORMAT_RESERVED_14 0x0E
4160 #define V_008F14_IMG_NUM_FORMAT_RESERVED_15 0x0F
4161 /* CIK */
4162 #define S_008F14_MTYPE(x) (((x) & 0x03) << 30)
4163 #define G_008F14_MTYPE(x) (((x) >> 30) & 0x03)
4164 #define C_008F14_MTYPE 0x3FFFFFFF
4165 /* */
4166 #define R_030F18_DB_OCCLUSION_COUNT3_LOW 0x030F18
4167 #define R_008F18_SQ_IMG_RSRC_WORD2 0x008F18
4168 #define S_008F18_WIDTH(x) (((x) & 0x3FFF) << 0)
4169 #define G_008F18_WIDTH(x) (((x) >> 0) & 0x3FFF)
4170 #define C_008F18_WIDTH 0xFFFFC000
4171 #define S_008F18_HEIGHT(x) (((x) & 0x3FFF) << 14)
4172 #define G_008F18_HEIGHT(x) (((x) >> 14) & 0x3FFF)
4173 #define C_008F18_HEIGHT 0xF0003FFF
4174 #define S_008F18_PERF_MOD(x) (((x) & 0x07) << 28)
4175 #define G_008F18_PERF_MOD(x) (((x) >> 28) & 0x07)
4176 #define C_008F18_PERF_MOD 0x8FFFFFFF
4177 #define S_008F18_INTERLACED(x) (((x) & 0x1) << 31)
4178 #define G_008F18_INTERLACED(x) (((x) >> 31) & 0x1)
4179 #define C_008F18_INTERLACED 0x7FFFFFFF
4180 #define R_030F1C_DB_OCCLUSION_COUNT3_HI 0x030F1C
4181 #define S_030F1C_COUNT_HI(x) (((x) & 0x7FFFFFFF) << 0)
4182 #define G_030F1C_COUNT_HI(x) (((x) >> 0) & 0x7FFFFFFF)
4183 #define C_030F1C_COUNT_HI 0x80000000
4184 #define R_008F1C_SQ_IMG_RSRC_WORD3 0x008F1C
4185 #define S_008F1C_DST_SEL_X(x) (((x) & 0x07) << 0)
4186 #define G_008F1C_DST_SEL_X(x) (((x) >> 0) & 0x07)
4187 #define C_008F1C_DST_SEL_X 0xFFFFFFF8
4188 #define V_008F1C_SQ_SEL_0 0x00
4189 #define V_008F1C_SQ_SEL_1 0x01
4190 #define V_008F1C_SQ_SEL_RESERVED_0 0x02
4191 #define V_008F1C_SQ_SEL_RESERVED_1 0x03
4192 #define V_008F1C_SQ_SEL_X 0x04
4193 #define V_008F1C_SQ_SEL_Y 0x05
4194 #define V_008F1C_SQ_SEL_Z 0x06
4195 #define V_008F1C_SQ_SEL_W 0x07
4196 #define S_008F1C_DST_SEL_Y(x) (((x) & 0x07) << 3)
4197 #define G_008F1C_DST_SEL_Y(x) (((x) >> 3) & 0x07)
4198 #define C_008F1C_DST_SEL_Y 0xFFFFFFC7
4199 #define V_008F1C_SQ_SEL_0 0x00
4200 #define V_008F1C_SQ_SEL_1 0x01
4201 #define V_008F1C_SQ_SEL_RESERVED_0 0x02
4202 #define V_008F1C_SQ_SEL_RESERVED_1 0x03
4203 #define V_008F1C_SQ_SEL_X 0x04
4204 #define V_008F1C_SQ_SEL_Y 0x05
4205 #define V_008F1C_SQ_SEL_Z 0x06
4206 #define V_008F1C_SQ_SEL_W 0x07
4207 #define S_008F1C_DST_SEL_Z(x) (((x) & 0x07) << 6)
4208 #define G_008F1C_DST_SEL_Z(x) (((x) >> 6) & 0x07)
4209 #define C_008F1C_DST_SEL_Z 0xFFFFFE3F
4210 #define V_008F1C_SQ_SEL_0 0x00
4211 #define V_008F1C_SQ_SEL_1 0x01
4212 #define V_008F1C_SQ_SEL_RESERVED_0 0x02
4213 #define V_008F1C_SQ_SEL_RESERVED_1 0x03
4214 #define V_008F1C_SQ_SEL_X 0x04
4215 #define V_008F1C_SQ_SEL_Y 0x05
4216 #define V_008F1C_SQ_SEL_Z 0x06
4217 #define V_008F1C_SQ_SEL_W 0x07
4218 #define S_008F1C_DST_SEL_W(x) (((x) & 0x07) << 9)
4219 #define G_008F1C_DST_SEL_W(x) (((x) >> 9) & 0x07)
4220 #define C_008F1C_DST_SEL_W 0xFFFFF1FF
4221 #define V_008F1C_SQ_SEL_0 0x00
4222 #define V_008F1C_SQ_SEL_1 0x01
4223 #define V_008F1C_SQ_SEL_RESERVED_0 0x02
4224 #define V_008F1C_SQ_SEL_RESERVED_1 0x03
4225 #define V_008F1C_SQ_SEL_X 0x04
4226 #define V_008F1C_SQ_SEL_Y 0x05
4227 #define V_008F1C_SQ_SEL_Z 0x06
4228 #define V_008F1C_SQ_SEL_W 0x07
4229 #define S_008F1C_BASE_LEVEL(x) (((x) & 0x0F) << 12)
4230 #define G_008F1C_BASE_LEVEL(x) (((x) >> 12) & 0x0F)
4231 #define C_008F1C_BASE_LEVEL 0xFFFF0FFF
4232 #define S_008F1C_LAST_LEVEL(x) (((x) & 0x0F) << 16)
4233 #define G_008F1C_LAST_LEVEL(x) (((x) >> 16) & 0x0F)
4234 #define C_008F1C_LAST_LEVEL 0xFFF0FFFF
4235 #define S_008F1C_TILING_INDEX(x) (((x) & 0x1F) << 20)
4236 #define G_008F1C_TILING_INDEX(x) (((x) >> 20) & 0x1F)
4237 #define C_008F1C_TILING_INDEX 0xFE0FFFFF
4238 #define S_008F1C_POW2_PAD(x) (((x) & 0x1) << 25)
4239 #define G_008F1C_POW2_PAD(x) (((x) >> 25) & 0x1)
4240 #define C_008F1C_POW2_PAD 0xFDFFFFFF
4241 /* CIK */
4242 #define S_008F1C_MTYPE(x) (((x) & 0x1) << 26)
4243 #define G_008F1C_MTYPE(x) (((x) >> 26) & 0x1)
4244 #define C_008F1C_MTYPE 0xFBFFFFFF
4245 #define S_008F1C_ATC(x) (((x) & 0x1) << 27)
4246 #define G_008F1C_ATC(x) (((x) >> 27) & 0x1)
4247 #define C_008F1C_ATC 0xF7FFFFFF
4248 /* */
4249 #define S_008F1C_TYPE(x) (((x) & 0x0F) << 28)
4250 #define G_008F1C_TYPE(x) (((x) >> 28) & 0x0F)
4251 #define C_008F1C_TYPE 0x0FFFFFFF
4252 #define V_008F1C_SQ_RSRC_IMG_RSVD_0 0x00
4253 #define V_008F1C_SQ_RSRC_IMG_RSVD_1 0x01
4254 #define V_008F1C_SQ_RSRC_IMG_RSVD_2 0x02
4255 #define V_008F1C_SQ_RSRC_IMG_RSVD_3 0x03
4256 #define V_008F1C_SQ_RSRC_IMG_RSVD_4 0x04
4257 #define V_008F1C_SQ_RSRC_IMG_RSVD_5 0x05
4258 #define V_008F1C_SQ_RSRC_IMG_RSVD_6 0x06
4259 #define V_008F1C_SQ_RSRC_IMG_RSVD_7 0x07
4260 #define V_008F1C_SQ_RSRC_IMG_1D 0x08
4261 #define V_008F1C_SQ_RSRC_IMG_2D 0x09
4262 #define V_008F1C_SQ_RSRC_IMG_3D 0x0A
4263 #define V_008F1C_SQ_RSRC_IMG_CUBE 0x0B
4264 #define V_008F1C_SQ_RSRC_IMG_1D_ARRAY 0x0C
4265 #define V_008F1C_SQ_RSRC_IMG_2D_ARRAY 0x0D
4266 #define V_008F1C_SQ_RSRC_IMG_2D_MSAA 0x0E
4267 #define V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY 0x0F
4268 #define R_008F20_SQ_IMG_RSRC_WORD4 0x008F20
4269 #define S_008F20_DEPTH(x) (((x) & 0x1FFF) << 0)
4270 #define G_008F20_DEPTH(x) (((x) >> 0) & 0x1FFF)
4271 #define C_008F20_DEPTH 0xFFFFE000
4272 #define S_008F20_PITCH(x) (((x) & 0x3FFF) << 13)
4273 #define G_008F20_PITCH(x) (((x) >> 13) & 0x3FFF)
4274 #define C_008F20_PITCH 0xF8001FFF
4275 #define R_008F24_SQ_IMG_RSRC_WORD5 0x008F24
4276 #define S_008F24_BASE_ARRAY(x) (((x) & 0x1FFF) << 0)
4277 #define G_008F24_BASE_ARRAY(x) (((x) >> 0) & 0x1FFF)
4278 #define C_008F24_BASE_ARRAY 0xFFFFE000
4279 #define S_008F24_LAST_ARRAY(x) (((x) & 0x1FFF) << 13)
4280 #define G_008F24_LAST_ARRAY(x) (((x) >> 13) & 0x1FFF)
4281 #define C_008F24_LAST_ARRAY 0xFC001FFF
4282 #define R_008F28_SQ_IMG_RSRC_WORD6 0x008F28
4283 #define S_008F28_MIN_LOD_WARN(x) (((x) & 0xFFF) << 0)
4284 #define G_008F28_MIN_LOD_WARN(x) (((x) >> 0) & 0xFFF)
4285 #define C_008F28_MIN_LOD_WARN 0xFFFFF000
4286 /* CIK */
4287 #define S_008F28_COUNTER_BANK_ID(x) (((x) & 0xFF) << 12)
4288 #define G_008F28_COUNTER_BANK_ID(x) (((x) >> 12) & 0xFF)
4289 #define C_008F28_COUNTER_BANK_ID 0xFFF00FFF
4290 #define S_008F28_LOD_HDW_CNT_EN(x) (((x) & 0x1) << 20)
4291 #define G_008F28_LOD_HDW_CNT_EN(x) (((x) >> 20) & 0x1)
4292 #define C_008F28_LOD_HDW_CNT_EN 0xFFEFFFFF
4293 /* */
4294 /* VI */
4295 #define S_008F28_COMPRESSION_EN(x) (((x) & 0x1) << 21)
4296 #define G_008F28_COMPRESSION_EN(x) (((x) >> 21) & 0x1)
4297 #define C_008F28_COMPRESSION_EN 0xFFDFFFFF
4298 #define S_008F28_ALPHA_IS_ON_MSB(x) (((x) & 0x1) << 22)
4299 #define G_008F28_ALPHA_IS_ON_MSB(x) (((x) >> 22) & 0x1)
4300 #define C_008F28_ALPHA_IS_ON_MSB 0xFFBFFFFF
4301 #define S_008F28_COLOR_TRANSFORM(x) (((x) & 0x1) << 23)
4302 #define G_008F28_COLOR_TRANSFORM(x) (((x) >> 23) & 0x1)
4303 #define C_008F28_COLOR_TRANSFORM 0xFF7FFFFF
4304 #define S_008F28_LOST_ALPHA_BITS(x) (((x) & 0x0F) << 24)
4305 #define G_008F28_LOST_ALPHA_BITS(x) (((x) >> 24) & 0x0F)
4306 #define C_008F28_LOST_ALPHA_BITS 0xF0FFFFFF
4307 #define S_008F28_LOST_COLOR_BITS(x) (((x) & 0x0F) << 28)
4308 #define G_008F28_LOST_COLOR_BITS(x) (((x) >> 28) & 0x0F)
4309 #define C_008F28_LOST_COLOR_BITS 0x0FFFFFFF
4310 /* */
4311 #define R_008F2C_SQ_IMG_RSRC_WORD7 0x008F2C
4312 #define R_008F30_SQ_IMG_SAMP_WORD0 0x008F30
4313 #define S_008F30_CLAMP_X(x) (((x) & 0x07) << 0)
4314 #define G_008F30_CLAMP_X(x) (((x) >> 0) & 0x07)
4315 #define C_008F30_CLAMP_X 0xFFFFFFF8
4316 #define V_008F30_SQ_TEX_WRAP 0x00
4317 #define V_008F30_SQ_TEX_MIRROR 0x01
4318 #define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02
4319 #define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03
4320 #define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04
4321 #define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05
4322 #define V_008F30_SQ_TEX_CLAMP_BORDER 0x06
4323 #define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07
4324 #define S_008F30_CLAMP_Y(x) (((x) & 0x07) << 3)
4325 #define G_008F30_CLAMP_Y(x) (((x) >> 3) & 0x07)
4326 #define C_008F30_CLAMP_Y 0xFFFFFFC7
4327 #define V_008F30_SQ_TEX_WRAP 0x00
4328 #define V_008F30_SQ_TEX_MIRROR 0x01
4329 #define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02
4330 #define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03
4331 #define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04
4332 #define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05
4333 #define V_008F30_SQ_TEX_CLAMP_BORDER 0x06
4334 #define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07
4335 #define S_008F30_CLAMP_Z(x) (((x) & 0x07) << 6)
4336 #define G_008F30_CLAMP_Z(x) (((x) >> 6) & 0x07)
4337 #define C_008F30_CLAMP_Z 0xFFFFFE3F
4338 #define V_008F30_SQ_TEX_WRAP 0x00
4339 #define V_008F30_SQ_TEX_MIRROR 0x01
4340 #define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02
4341 #define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03
4342 #define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04
4343 #define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05
4344 #define V_008F30_SQ_TEX_CLAMP_BORDER 0x06
4345 #define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07
4346 #define S_008F30_DEPTH_COMPARE_FUNC(x) (((x) & 0x07) << 12)
4347 #define G_008F30_DEPTH_COMPARE_FUNC(x) (((x) >> 12) & 0x07)
4348 #define C_008F30_DEPTH_COMPARE_FUNC 0xFFFF8FFF
4349 #define V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER 0x00
4350 #define V_008F30_SQ_TEX_DEPTH_COMPARE_LESS 0x01
4351 #define V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL 0x02
4352 #define V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL 0x03
4353 #define V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER 0x04
4354 #define V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL 0x05
4355 #define V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL 0x06
4356 #define V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS 0x07
4357 #define S_008F30_FORCE_UNNORMALIZED(x) (((x) & 0x1) << 15)
4358 #define G_008F30_FORCE_UNNORMALIZED(x) (((x) >> 15) & 0x1)
4359 #define C_008F30_FORCE_UNNORMALIZED 0xFFFF7FFF
4360 #define S_008F30_MC_COORD_TRUNC(x) (((x) & 0x1) << 19)
4361 #define G_008F30_MC_COORD_TRUNC(x) (((x) >> 19) & 0x1)
4362 #define C_008F30_MC_COORD_TRUNC 0xFFF7FFFF
4363 #define S_008F30_FORCE_DEGAMMA(x) (((x) & 0x1) << 20)
4364 #define G_008F30_FORCE_DEGAMMA(x) (((x) >> 20) & 0x1)
4365 #define C_008F30_FORCE_DEGAMMA 0xFFEFFFFF
4366 #define S_008F30_TRUNC_COORD(x) (((x) & 0x1) << 27)
4367 #define G_008F30_TRUNC_COORD(x) (((x) >> 27) & 0x1)
4368 #define C_008F30_TRUNC_COORD 0xF7FFFFFF
4369 #define S_008F30_DISABLE_CUBE_WRAP(x) (((x) & 0x1) << 28)
4370 #define G_008F30_DISABLE_CUBE_WRAP(x) (((x) >> 28) & 0x1)
4371 #define C_008F30_DISABLE_CUBE_WRAP 0xEFFFFFFF
4372 #define S_008F30_FILTER_MODE(x) (((x) & 0x03) << 29)
4373 #define G_008F30_FILTER_MODE(x) (((x) >> 29) & 0x03)
4374 #define C_008F30_FILTER_MODE 0x9FFFFFFF
4375 /* VI */
4376 #define S_008F30_COMPAT_MODE(x) (((x) & 0x1) << 31)
4377 #define G_008F30_COMPAT_MODE(x) (((x) >> 31) & 0x1)
4378 #define C_008F30_COMPAT_MODE 0x7FFFFFFF
4379 /* */
4380 #define R_008F34_SQ_IMG_SAMP_WORD1 0x008F34
4381 #define S_008F34_MIN_LOD(x) (((x) & 0xFFF) << 0)
4382 #define G_008F34_MIN_LOD(x) (((x) >> 0) & 0xFFF)
4383 #define C_008F34_MIN_LOD 0xFFFFF000
4384 #define S_008F34_MAX_LOD(x) (((x) & 0xFFF) << 12)
4385 #define G_008F34_MAX_LOD(x) (((x) >> 12) & 0xFFF)
4386 #define C_008F34_MAX_LOD 0xFF000FFF
4387 #define S_008F34_PERF_MIP(x) (((x) & 0x0F) << 24)
4388 #define G_008F34_PERF_MIP(x) (((x) >> 24) & 0x0F)
4389 #define C_008F34_PERF_MIP 0xF0FFFFFF
4390 #define S_008F34_PERF_Z(x) (((x) & 0x0F) << 28)
4391 #define G_008F34_PERF_Z(x) (((x) >> 28) & 0x0F)
4392 #define C_008F34_PERF_Z 0x0FFFFFFF
4393 #define R_008F38_SQ_IMG_SAMP_WORD2 0x008F38
4394 #define S_008F38_LOD_BIAS(x) (((x) & 0x3FFF) << 0)
4395 #define G_008F38_LOD_BIAS(x) (((x) >> 0) & 0x3FFF)
4396 #define C_008F38_LOD_BIAS 0xFFFFC000
4397 #define S_008F38_LOD_BIAS_SEC(x) (((x) & 0x3F) << 14)
4398 #define G_008F38_LOD_BIAS_SEC(x) (((x) >> 14) & 0x3F)
4399 #define C_008F38_LOD_BIAS_SEC 0xFFF03FFF
4400 #define S_008F38_XY_MAG_FILTER(x) (((x) & 0x03) << 20)
4401 #define G_008F38_XY_MAG_FILTER(x) (((x) >> 20) & 0x03)
4402 #define C_008F38_XY_MAG_FILTER 0xFFCFFFFF
4403 #define V_008F38_SQ_TEX_XY_FILTER_POINT 0x00
4404 #define V_008F38_SQ_TEX_XY_FILTER_BILINEAR 0x01
4405 #define S_008F38_XY_MIN_FILTER(x) (((x) & 0x03) << 22)
4406 #define G_008F38_XY_MIN_FILTER(x) (((x) >> 22) & 0x03)
4407 #define C_008F38_XY_MIN_FILTER 0xFF3FFFFF
4408 #define V_008F38_SQ_TEX_XY_FILTER_POINT 0x00
4409 #define V_008F38_SQ_TEX_XY_FILTER_BILINEAR 0x01
4410 #define S_008F38_Z_FILTER(x) (((x) & 0x03) << 24)
4411 #define G_008F38_Z_FILTER(x) (((x) >> 24) & 0x03)
4412 #define C_008F38_Z_FILTER 0xFCFFFFFF
4413 #define V_008F38_SQ_TEX_Z_FILTER_NONE 0x00
4414 #define V_008F38_SQ_TEX_Z_FILTER_POINT 0x01
4415 #define V_008F38_SQ_TEX_Z_FILTER_LINEAR 0x02
4416 #define S_008F38_MIP_FILTER(x) (((x) & 0x03) << 26)
4417 #define G_008F38_MIP_FILTER(x) (((x) >> 26) & 0x03)
4418 #define C_008F38_MIP_FILTER 0xF3FFFFFF
4419 #define V_008F38_SQ_TEX_Z_FILTER_NONE 0x00
4420 #define V_008F38_SQ_TEX_Z_FILTER_POINT 0x01
4421 #define V_008F38_SQ_TEX_Z_FILTER_LINEAR 0x02
4422 #define S_008F38_MIP_POINT_PRECLAMP(x) (((x) & 0x1) << 28)
4423 #define G_008F38_MIP_POINT_PRECLAMP(x) (((x) >> 28) & 0x1)
4424 #define C_008F38_MIP_POINT_PRECLAMP 0xEFFFFFFF
4425 #define S_008F38_DISABLE_LSB_CEIL(x) (((x) & 0x1) << 29)
4426 #define G_008F38_DISABLE_LSB_CEIL(x) (((x) >> 29) & 0x1)
4427 #define C_008F38_DISABLE_LSB_CEIL 0xDFFFFFFF
4428 #define S_008F38_FILTER_PREC_FIX(x) (((x) & 0x1) << 30)
4429 #define G_008F38_FILTER_PREC_FIX(x) (((x) >> 30) & 0x1)
4430 #define C_008F38_FILTER_PREC_FIX 0xBFFFFFFF
4431 #define R_008F3C_SQ_IMG_SAMP_WORD3 0x008F3C
4432 #define S_008F3C_BORDER_COLOR_PTR(x) (((x) & 0xFFF) << 0)
4433 #define G_008F3C_BORDER_COLOR_PTR(x) (((x) >> 0) & 0xFFF)
4434 #define C_008F3C_BORDER_COLOR_PTR 0xFFFFF000
4435 #define S_008F3C_BORDER_COLOR_TYPE(x) (((x) & 0x03) << 30)
4436 #define G_008F3C_BORDER_COLOR_TYPE(x) (((x) >> 30) & 0x03)
4437 #define C_008F3C_BORDER_COLOR_TYPE 0x3FFFFFFF
4438 #define V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK 0x00
4439 #define V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK 0x01
4440 #define V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE 0x02
4441 #define V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER 0x03
4442 #define R_0090DC_SPI_DYN_GPR_LOCK_EN 0x0090DC /* not on CIK */
4443 #define S_0090DC_VS_LOW_THRESHOLD(x) (((x) & 0x0F) << 0)
4444 #define G_0090DC_VS_LOW_THRESHOLD(x) (((x) >> 0) & 0x0F)
4445 #define C_0090DC_VS_LOW_THRESHOLD 0xFFFFFFF0
4446 #define S_0090DC_GS_LOW_THRESHOLD(x) (((x) & 0x0F) << 4)
4447 #define G_0090DC_GS_LOW_THRESHOLD(x) (((x) >> 4) & 0x0F)
4448 #define C_0090DC_GS_LOW_THRESHOLD 0xFFFFFF0F
4449 #define S_0090DC_ES_LOW_THRESHOLD(x) (((x) & 0x0F) << 8)
4450 #define G_0090DC_ES_LOW_THRESHOLD(x) (((x) >> 8) & 0x0F)
4451 #define C_0090DC_ES_LOW_THRESHOLD 0xFFFFF0FF
4452 #define S_0090DC_HS_LOW_THRESHOLD(x) (((x) & 0x0F) << 12)
4453 #define G_0090DC_HS_LOW_THRESHOLD(x) (((x) >> 12) & 0x0F)
4454 #define C_0090DC_HS_LOW_THRESHOLD 0xFFFF0FFF
4455 #define S_0090DC_LS_LOW_THRESHOLD(x) (((x) & 0x0F) << 16)
4456 #define G_0090DC_LS_LOW_THRESHOLD(x) (((x) >> 16) & 0x0F)
4457 #define C_0090DC_LS_LOW_THRESHOLD 0xFFF0FFFF
4458 #define R_0090E0_SPI_STATIC_THREAD_MGMT_1 0x0090E0 /* not on CIK */
4459 #define S_0090E0_PS_CU_EN(x) (((x) & 0xFFFF) << 0)
4460 #define G_0090E0_PS_CU_EN(x) (((x) >> 0) & 0xFFFF)
4461 #define C_0090E0_PS_CU_EN 0xFFFF0000
4462 #define S_0090E0_VS_CU_EN(x) (((x) & 0xFFFF) << 16)
4463 #define G_0090E0_VS_CU_EN(x) (((x) >> 16) & 0xFFFF)
4464 #define C_0090E0_VS_CU_EN 0x0000FFFF
4465 #define R_0090E4_SPI_STATIC_THREAD_MGMT_2 0x0090E4 /* not on CIK */
4466 #define S_0090E4_GS_CU_EN(x) (((x) & 0xFFFF) << 0)
4467 #define G_0090E4_GS_CU_EN(x) (((x) >> 0) & 0xFFFF)
4468 #define C_0090E4_GS_CU_EN 0xFFFF0000
4469 #define S_0090E4_ES_CU_EN(x) (((x) & 0xFFFF) << 16)
4470 #define G_0090E4_ES_CU_EN(x) (((x) >> 16) & 0xFFFF)
4471 #define C_0090E4_ES_CU_EN 0x0000FFFF
4472 #define R_0090E8_SPI_STATIC_THREAD_MGMT_3 0x0090E8 /* not on CIK */
4473 #define S_0090E8_LSHS_CU_EN(x) (((x) & 0xFFFF) << 0)
4474 #define G_0090E8_LSHS_CU_EN(x) (((x) >> 0) & 0xFFFF)
4475 #define C_0090E8_LSHS_CU_EN 0xFFFF0000
4476 #define R_0090EC_SPI_PS_MAX_WAVE_ID 0x0090EC
4477 #define S_0090EC_MAX_WAVE_ID(x) (((x) & 0xFFF) << 0)
4478 #define G_0090EC_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF)
4479 #define C_0090EC_MAX_WAVE_ID 0xFFFFF000
4480 /* CIK */
4481 #define R_0090E8_SPI_PS_MAX_WAVE_ID 0x0090E8
4482 #define S_0090E8_MAX_WAVE_ID(x) (((x) & 0xFFF) << 0)
4483 #define G_0090E8_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF)
4484 #define C_0090E8_MAX_WAVE_ID 0xFFFFF000
4485 /* */
4486 #define R_0090F0_SPI_ARB_PRIORITY 0x0090F0
4487 #define S_0090F0_RING_ORDER_TS0(x) (((x) & 0x07) << 0)
4488 #define G_0090F0_RING_ORDER_TS0(x) (((x) >> 0) & 0x07)
4489 #define C_0090F0_RING_ORDER_TS0 0xFFFFFFF8
4490 #define V_0090F0_X_R0 0x00
4491 #define S_0090F0_RING_ORDER_TS1(x) (((x) & 0x07) << 3)
4492 #define G_0090F0_RING_ORDER_TS1(x) (((x) >> 3) & 0x07)
4493 #define C_0090F0_RING_ORDER_TS1 0xFFFFFFC7
4494 #define S_0090F0_RING_ORDER_TS2(x) (((x) & 0x07) << 6)
4495 #define G_0090F0_RING_ORDER_TS2(x) (((x) >> 6) & 0x07)
4496 #define C_0090F0_RING_ORDER_TS2 0xFFFFFE3F
4497 /* CIK */
4498 #define R_00C700_SPI_ARB_PRIORITY 0x00C700
4499 #define S_00C700_PIPE_ORDER_TS0(x) (((x) & 0x07) << 0)
4500 #define G_00C700_PIPE_ORDER_TS0(x) (((x) >> 0) & 0x07)
4501 #define C_00C700_PIPE_ORDER_TS0 0xFFFFFFF8
4502 #define S_00C700_PIPE_ORDER_TS1(x) (((x) & 0x07) << 3)
4503 #define G_00C700_PIPE_ORDER_TS1(x) (((x) >> 3) & 0x07)
4504 #define C_00C700_PIPE_ORDER_TS1 0xFFFFFFC7
4505 #define S_00C700_PIPE_ORDER_TS2(x) (((x) & 0x07) << 6)
4506 #define G_00C700_PIPE_ORDER_TS2(x) (((x) >> 6) & 0x07)
4507 #define C_00C700_PIPE_ORDER_TS2 0xFFFFFE3F
4508 #define S_00C700_PIPE_ORDER_TS3(x) (((x) & 0x07) << 9)
4509 #define G_00C700_PIPE_ORDER_TS3(x) (((x) >> 9) & 0x07)
4510 #define C_00C700_PIPE_ORDER_TS3 0xFFFFF1FF
4511 #define S_00C700_TS0_DUR_MULT(x) (((x) & 0x03) << 12)
4512 #define G_00C700_TS0_DUR_MULT(x) (((x) >> 12) & 0x03)
4513 #define C_00C700_TS0_DUR_MULT 0xFFFFCFFF
4514 #define S_00C700_TS1_DUR_MULT(x) (((x) & 0x03) << 14)
4515 #define G_00C700_TS1_DUR_MULT(x) (((x) >> 14) & 0x03)
4516 #define C_00C700_TS1_DUR_MULT 0xFFFF3FFF
4517 #define S_00C700_TS2_DUR_MULT(x) (((x) & 0x03) << 16)
4518 #define G_00C700_TS2_DUR_MULT(x) (((x) >> 16) & 0x03)
4519 #define C_00C700_TS2_DUR_MULT 0xFFFCFFFF
4520 #define S_00C700_TS3_DUR_MULT(x) (((x) & 0x03) << 18)
4521 #define G_00C700_TS3_DUR_MULT(x) (((x) >> 18) & 0x03)
4522 #define C_00C700_TS3_DUR_MULT 0xFFF3FFFF
4523 /* */
4524 #define R_0090F4_SPI_ARB_CYCLES_0 0x0090F4 /* moved to 0xC704 on CIK */
4525 #define S_0090F4_TS0_DURATION(x) (((x) & 0xFFFF) << 0)
4526 #define G_0090F4_TS0_DURATION(x) (((x) >> 0) & 0xFFFF)
4527 #define C_0090F4_TS0_DURATION 0xFFFF0000
4528 #define S_0090F4_TS1_DURATION(x) (((x) & 0xFFFF) << 16)
4529 #define G_0090F4_TS1_DURATION(x) (((x) >> 16) & 0xFFFF)
4530 #define C_0090F4_TS1_DURATION 0x0000FFFF
4531 #define R_0090F8_SPI_ARB_CYCLES_1 0x0090F8 /* moved to 0xC708 on CIK */
4532 #define S_0090F8_TS2_DURATION(x) (((x) & 0xFFFF) << 0)
4533 #define G_0090F8_TS2_DURATION(x) (((x) >> 0) & 0xFFFF)
4534 #define C_0090F8_TS2_DURATION 0xFFFF0000
4535 /* CIK */
4536 #define R_008F40_SQ_FLAT_SCRATCH_WORD0 0x008F40
4537 #define S_008F40_SIZE(x) (((x) & 0x7FFFF) << 0)
4538 #define G_008F40_SIZE(x) (((x) >> 0) & 0x7FFFF)
4539 #define C_008F40_SIZE 0xFFF80000
4540 #define R_008F44_SQ_FLAT_SCRATCH_WORD1 0x008F44
4541 #define S_008F44_OFFSET(x) (((x) & 0xFFFFFF) << 0)
4542 #define G_008F44_OFFSET(x) (((x) >> 0) & 0xFFFFFF)
4543 #define C_008F44_OFFSET 0xFF000000
4544 /* */
4545 #define R_030FF8_DB_ZPASS_COUNT_LOW 0x030FF8
4546 #define R_030FFC_DB_ZPASS_COUNT_HI 0x030FFC
4547 #define S_030FFC_COUNT_HI(x) (((x) & 0x7FFFFFFF) << 0)
4548 #define G_030FFC_COUNT_HI(x) (((x) >> 0) & 0x7FFFFFFF)
4549 #define C_030FFC_COUNT_HI 0x80000000
4550 #define R_009100_SPI_CONFIG_CNTL 0x009100
4551 #define S_009100_GPR_WRITE_PRIORITY(x) (((x) & 0x1FFFFF) << 0)
4552 #define G_009100_GPR_WRITE_PRIORITY(x) (((x) >> 0) & 0x1FFFFF)
4553 #define C_009100_GPR_WRITE_PRIORITY 0xFFE00000
4554 #define S_009100_EXP_PRIORITY_ORDER(x) (((x) & 0x07) << 21)
4555 #define G_009100_EXP_PRIORITY_ORDER(x) (((x) >> 21) & 0x07)
4556 #define C_009100_EXP_PRIORITY_ORDER 0xFF1FFFFF
4557 #define S_009100_ENABLE_SQG_TOP_EVENTS(x) (((x) & 0x1) << 24)
4558 #define G_009100_ENABLE_SQG_TOP_EVENTS(x) (((x) >> 24) & 0x1)
4559 #define C_009100_ENABLE_SQG_TOP_EVENTS 0xFEFFFFFF
4560 #define S_009100_ENABLE_SQG_BOP_EVENTS(x) (((x) & 0x1) << 25)
4561 #define G_009100_ENABLE_SQG_BOP_EVENTS(x) (((x) >> 25) & 0x1)
4562 #define C_009100_ENABLE_SQG_BOP_EVENTS 0xFDFFFFFF
4563 #define S_009100_RSRC_MGMT_RESET(x) (((x) & 0x1) << 26)
4564 #define G_009100_RSRC_MGMT_RESET(x) (((x) >> 26) & 0x1)
4565 #define C_009100_RSRC_MGMT_RESET 0xFBFFFFFF
4566 #define R_00913C_SPI_CONFIG_CNTL_1 0x00913C
4567 #define S_00913C_VTX_DONE_DELAY(x) (((x) & 0x0F) << 0)
4568 #define G_00913C_VTX_DONE_DELAY(x) (((x) >> 0) & 0x0F)
4569 #define C_00913C_VTX_DONE_DELAY 0xFFFFFFF0
4570 #define V_00913C_X_DELAY_14_CLKS 0x00
4571 #define V_00913C_X_DELAY_16_CLKS 0x01
4572 #define V_00913C_X_DELAY_18_CLKS 0x02
4573 #define V_00913C_X_DELAY_20_CLKS 0x03
4574 #define V_00913C_X_DELAY_22_CLKS 0x04
4575 #define V_00913C_X_DELAY_24_CLKS 0x05
4576 #define V_00913C_X_DELAY_26_CLKS 0x06
4577 #define V_00913C_X_DELAY_28_CLKS 0x07
4578 #define V_00913C_X_DELAY_30_CLKS 0x08
4579 #define V_00913C_X_DELAY_32_CLKS 0x09
4580 #define V_00913C_X_DELAY_34_CLKS 0x0A
4581 #define V_00913C_X_DELAY_4_CLKS 0x0B
4582 #define V_00913C_X_DELAY_6_CLKS 0x0C
4583 #define V_00913C_X_DELAY_8_CLKS 0x0D
4584 #define V_00913C_X_DELAY_10_CLKS 0x0E
4585 #define V_00913C_X_DELAY_12_CLKS 0x0F
4586 #define S_00913C_INTERP_ONE_PRIM_PER_ROW(x) (((x) & 0x1) << 4)
4587 #define G_00913C_INTERP_ONE_PRIM_PER_ROW(x) (((x) >> 4) & 0x1)
4588 #define C_00913C_INTERP_ONE_PRIM_PER_ROW 0xFFFFFFEF
4589 #define S_00913C_PC_LIMIT_ENABLE(x) (((x) & 0x1) << 6)
4590 #define G_00913C_PC_LIMIT_ENABLE(x) (((x) >> 6) & 0x1)
4591 #define C_00913C_PC_LIMIT_ENABLE 0xFFFFFFBF
4592 #define S_00913C_PC_LIMIT_STRICT(x) (((x) & 0x1) << 7)
4593 #define G_00913C_PC_LIMIT_STRICT(x) (((x) >> 7) & 0x1)
4594 #define C_00913C_PC_LIMIT_STRICT 0xFFFFFF7F
4595 #define S_00913C_PC_LIMIT_SIZE(x) (((x) & 0xFFFF) << 16)
4596 #define G_00913C_PC_LIMIT_SIZE(x) (((x) >> 16) & 0xFFFF)
4597 #define C_00913C_PC_LIMIT_SIZE 0x0000FFFF
4598 #define R_00936C_SPI_RESOURCE_RESERVE_CU_AB_0 0x00936C
4599 #define S_00936C_TYPE_A(x) (((x) & 0x0F) << 0)
4600 #define G_00936C_TYPE_A(x) (((x) >> 0) & 0x0F)
4601 #define C_00936C_TYPE_A 0xFFFFFFF0
4602 #define S_00936C_VGPR_A(x) (((x) & 0x07) << 4)
4603 #define G_00936C_VGPR_A(x) (((x) >> 4) & 0x07)
4604 #define C_00936C_VGPR_A 0xFFFFFF8F
4605 #define S_00936C_SGPR_A(x) (((x) & 0x07) << 7)
4606 #define G_00936C_SGPR_A(x) (((x) >> 7) & 0x07)
4607 #define C_00936C_SGPR_A 0xFFFFFC7F
4608 #define S_00936C_LDS_A(x) (((x) & 0x07) << 10)
4609 #define G_00936C_LDS_A(x) (((x) >> 10) & 0x07)
4610 #define C_00936C_LDS_A 0xFFFFE3FF
4611 #define S_00936C_WAVES_A(x) (((x) & 0x03) << 13)
4612 #define G_00936C_WAVES_A(x) (((x) >> 13) & 0x03)
4613 #define C_00936C_WAVES_A 0xFFFF9FFF
4614 #define S_00936C_EN_A(x) (((x) & 0x1) << 15)
4615 #define G_00936C_EN_A(x) (((x) >> 15) & 0x1)
4616 #define C_00936C_EN_A 0xFFFF7FFF
4617 #define S_00936C_TYPE_B(x) (((x) & 0x0F) << 16)
4618 #define G_00936C_TYPE_B(x) (((x) >> 16) & 0x0F)
4619 #define C_00936C_TYPE_B 0xFFF0FFFF
4620 #define S_00936C_VGPR_B(x) (((x) & 0x07) << 20)
4621 #define G_00936C_VGPR_B(x) (((x) >> 20) & 0x07)
4622 #define C_00936C_VGPR_B 0xFF8FFFFF
4623 #define S_00936C_SGPR_B(x) (((x) & 0x07) << 23)
4624 #define G_00936C_SGPR_B(x) (((x) >> 23) & 0x07)
4625 #define C_00936C_SGPR_B 0xFC7FFFFF
4626 #define S_00936C_LDS_B(x) (((x) & 0x07) << 26)
4627 #define G_00936C_LDS_B(x) (((x) >> 26) & 0x07)
4628 #define C_00936C_LDS_B 0xE3FFFFFF
4629 #define S_00936C_WAVES_B(x) (((x) & 0x03) << 29)
4630 #define G_00936C_WAVES_B(x) (((x) >> 29) & 0x03)
4631 #define C_00936C_WAVES_B 0x9FFFFFFF
4632 #define S_00936C_EN_B(x) (((x) & 0x1) << 31)
4633 #define G_00936C_EN_B(x) (((x) >> 31) & 0x1)
4634 #define C_00936C_EN_B 0x7FFFFFFF
4635 #define R_00950C_TA_CS_BC_BASE_ADDR 0x00950C
4636 /* CIK */
4637 #define R_030E00_TA_CS_BC_BASE_ADDR 0x030E00
4638 #define R_030E04_TA_CS_BC_BASE_ADDR_HI 0x030E04
4639 #define S_030E04_ADDRESS(x) (((x) & 0xFF) << 0)
4640 #define G_030E04_ADDRESS(x) (((x) >> 0) & 0xFF)
4641 #define C_030E04_ADDRESS 0xFFFFFF00
4642 /* */
4643 #define R_009858_DB_SUBTILE_CONTROL 0x009858
4644 #define S_009858_MSAA1_X(x) (((x) & 0x03) << 0)
4645 #define G_009858_MSAA1_X(x) (((x) >> 0) & 0x03)
4646 #define C_009858_MSAA1_X 0xFFFFFFFC
4647 #define S_009858_MSAA1_Y(x) (((x) & 0x03) << 2)
4648 #define G_009858_MSAA1_Y(x) (((x) >> 2) & 0x03)
4649 #define C_009858_MSAA1_Y 0xFFFFFFF3
4650 #define S_009858_MSAA2_X(x) (((x) & 0x03) << 4)
4651 #define G_009858_MSAA2_X(x) (((x) >> 4) & 0x03)
4652 #define C_009858_MSAA2_X 0xFFFFFFCF
4653 #define S_009858_MSAA2_Y(x) (((x) & 0x03) << 6)
4654 #define G_009858_MSAA2_Y(x) (((x) >> 6) & 0x03)
4655 #define C_009858_MSAA2_Y 0xFFFFFF3F
4656 #define S_009858_MSAA4_X(x) (((x) & 0x03) << 8)
4657 #define G_009858_MSAA4_X(x) (((x) >> 8) & 0x03)
4658 #define C_009858_MSAA4_X 0xFFFFFCFF
4659 #define S_009858_MSAA4_Y(x) (((x) & 0x03) << 10)
4660 #define G_009858_MSAA4_Y(x) (((x) >> 10) & 0x03)
4661 #define C_009858_MSAA4_Y 0xFFFFF3FF
4662 #define S_009858_MSAA8_X(x) (((x) & 0x03) << 12)
4663 #define G_009858_MSAA8_X(x) (((x) >> 12) & 0x03)
4664 #define C_009858_MSAA8_X 0xFFFFCFFF
4665 #define S_009858_MSAA8_Y(x) (((x) & 0x03) << 14)
4666 #define G_009858_MSAA8_Y(x) (((x) >> 14) & 0x03)
4667 #define C_009858_MSAA8_Y 0xFFFF3FFF
4668 #define S_009858_MSAA16_X(x) (((x) & 0x03) << 16)
4669 #define G_009858_MSAA16_X(x) (((x) >> 16) & 0x03)
4670 #define C_009858_MSAA16_X 0xFFFCFFFF
4671 #define S_009858_MSAA16_Y(x) (((x) & 0x03) << 18)
4672 #define G_009858_MSAA16_Y(x) (((x) >> 18) & 0x03)
4673 #define C_009858_MSAA16_Y 0xFFF3FFFF
4674 #define R_0098F8_GB_ADDR_CONFIG 0x0098F8
4675 #define S_0098F8_NUM_PIPES(x) (((x) & 0x07) << 0)
4676 #define G_0098F8_NUM_PIPES(x) (((x) >> 0) & 0x07)
4677 #define C_0098F8_NUM_PIPES 0xFFFFFFF8
4678 #define S_0098F8_PIPE_INTERLEAVE_SIZE(x) (((x) & 0x07) << 4)
4679 #define G_0098F8_PIPE_INTERLEAVE_SIZE(x) (((x) >> 4) & 0x07)
4680 #define C_0098F8_PIPE_INTERLEAVE_SIZE 0xFFFFFF8F
4681 #define S_0098F8_BANK_INTERLEAVE_SIZE(x) (((x) & 0x07) << 8)
4682 #define G_0098F8_BANK_INTERLEAVE_SIZE(x) (((x) >> 8) & 0x07)
4683 #define C_0098F8_BANK_INTERLEAVE_SIZE 0xFFFFF8FF
4684 #define S_0098F8_NUM_SHADER_ENGINES(x) (((x) & 0x03) << 12)
4685 #define G_0098F8_NUM_SHADER_ENGINES(x) (((x) >> 12) & 0x03)
4686 #define C_0098F8_NUM_SHADER_ENGINES 0xFFFFCFFF
4687 #define S_0098F8_SHADER_ENGINE_TILE_SIZE(x) (((x) & 0x07) << 16)
4688 #define G_0098F8_SHADER_ENGINE_TILE_SIZE(x) (((x) >> 16) & 0x07)
4689 #define C_0098F8_SHADER_ENGINE_TILE_SIZE 0xFFF8FFFF
4690 #define S_0098F8_NUM_GPUS(x) (((x) & 0x07) << 20)
4691 #define G_0098F8_NUM_GPUS(x) (((x) >> 20) & 0x07)
4692 #define C_0098F8_NUM_GPUS 0xFF8FFFFF
4693 #define S_0098F8_MULTI_GPU_TILE_SIZE(x) (((x) & 0x03) << 24)
4694 #define G_0098F8_MULTI_GPU_TILE_SIZE(x) (((x) >> 24) & 0x03)
4695 #define C_0098F8_MULTI_GPU_TILE_SIZE 0xFCFFFFFF
4696 #define S_0098F8_ROW_SIZE(x) (((x) & 0x03) << 28)
4697 #define G_0098F8_ROW_SIZE(x) (((x) >> 28) & 0x03)
4698 #define C_0098F8_ROW_SIZE 0xCFFFFFFF
4699 #define S_0098F8_NUM_LOWER_PIPES(x) (((x) & 0x1) << 30)
4700 #define G_0098F8_NUM_LOWER_PIPES(x) (((x) >> 30) & 0x1)
4701 #define C_0098F8_NUM_LOWER_PIPES 0xBFFFFFFF
4702 #define R_009910_GB_TILE_MODE0 0x009910
4703 #define S_009910_MICRO_TILE_MODE(x) (((x) & 0x03) << 0)
4704 #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
4705 #define C_009910_MICRO_TILE_MODE 0xFFFFFFFC
4706 #define V_009910_ADDR_SURF_DISPLAY_MICRO_TILING 0x00
4707 #define V_009910_ADDR_SURF_THIN_MICRO_TILING 0x01
4708 #define V_009910_ADDR_SURF_DEPTH_MICRO_TILING 0x02
4709 #define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03
4710 #define S_009910_ARRAY_MODE(x) (((x) & 0x0F) << 2)
4711 #define G_009910_ARRAY_MODE(x) (((x) >> 2) & 0x0F)
4712 #define C_009910_ARRAY_MODE 0xFFFFFFC3
4713 #define V_009910_ARRAY_LINEAR_GENERAL 0x00
4714 #define V_009910_ARRAY_LINEAR_ALIGNED 0x01
4715 #define V_009910_ARRAY_1D_TILED_THIN1 0x02
4716 #define V_009910_ARRAY_1D_TILED_THICK 0x03
4717 #define V_009910_ARRAY_2D_TILED_THIN1 0x04
4718 #define V_009910_ARRAY_2D_TILED_THICK 0x07
4719 #define V_009910_ARRAY_2D_TILED_XTHICK 0x08
4720 #define V_009910_ARRAY_3D_TILED_THIN1 0x0C
4721 #define V_009910_ARRAY_3D_TILED_THICK 0x0D
4722 #define V_009910_ARRAY_3D_TILED_XTHICK 0x0E
4723 #define V_009910_ARRAY_POWER_SAVE 0x0F
4724 #define S_009910_PIPE_CONFIG(x) (((x) & 0x1F) << 6)
4725 #define G_009910_PIPE_CONFIG(x) (((x) >> 6) & 0x1F)
4726 #define C_009910_PIPE_CONFIG 0xFFFFF83F
4727 #define V_009910_ADDR_SURF_P2 0x00
4728 #define V_009910_ADDR_SURF_P2_RESERVED0 0x01
4729 #define V_009910_ADDR_SURF_P2_RESERVED1 0x02
4730 #define V_009910_ADDR_SURF_P2_RESERVED2 0x03
4731 #define V_009910_X_ADDR_SURF_P4_8X16 0x04
4732 #define V_009910_X_ADDR_SURF_P4_16X16 0x05
4733 #define V_009910_X_ADDR_SURF_P4_16X32 0x06
4734 #define V_009910_X_ADDR_SURF_P4_32X32 0x07
4735 #define V_009910_X_ADDR_SURF_P8_16X16_8X16 0x08
4736 #define V_009910_X_ADDR_SURF_P8_16X32_8X16 0x09
4737 #define V_009910_X_ADDR_SURF_P8_32X32_8X16 0x0A
4738 #define V_009910_X_ADDR_SURF_P8_16X32_16X16 0x0B
4739 #define V_009910_X_ADDR_SURF_P8_32X32_16X16 0x0C
4740 #define V_009910_X_ADDR_SURF_P8_32X32_16X32 0x0D
4741 #define V_009910_X_ADDR_SURF_P8_32X64_32X32 0x0E
4742 #define S_009910_TILE_SPLIT(x) (((x) & 0x07) << 11)
4743 #define G_009910_TILE_SPLIT(x) (((x) >> 11) & 0x07)
4744 #define C_009910_TILE_SPLIT 0xFFFFC7FF
4745 #define V_009910_ADDR_SURF_TILE_SPLIT_64B 0x00
4746 #define V_009910_ADDR_SURF_TILE_SPLIT_128B 0x01
4747 #define V_009910_ADDR_SURF_TILE_SPLIT_256B 0x02
4748 #define V_009910_ADDR_SURF_TILE_SPLIT_512B 0x03
4749 #define V_009910_ADDR_SURF_TILE_SPLIT_1KB 0x04
4750 #define V_009910_ADDR_SURF_TILE_SPLIT_2KB 0x05
4751 #define V_009910_ADDR_SURF_TILE_SPLIT_4KB 0x06
4752 #define S_009910_BANK_WIDTH(x) (((x) & 0x03) << 14)
4753 #define G_009910_BANK_WIDTH(x) (((x) >> 14) & 0x03)
4754 #define C_009910_BANK_WIDTH 0xFFFF3FFF
4755 #define V_009910_ADDR_SURF_BANK_WIDTH_1 0x00
4756 #define V_009910_ADDR_SURF_BANK_WIDTH_2 0x01
4757 #define V_009910_ADDR_SURF_BANK_WIDTH_4 0x02
4758 #define V_009910_ADDR_SURF_BANK_WIDTH_8 0x03
4759 #define S_009910_BANK_HEIGHT(x) (((x) & 0x03) << 16)
4760 #define G_009910_BANK_HEIGHT(x) (((x) >> 16) & 0x03)
4761 #define C_009910_BANK_HEIGHT 0xFFFCFFFF
4762 #define V_009910_ADDR_SURF_BANK_HEIGHT_1 0x00
4763 #define V_009910_ADDR_SURF_BANK_HEIGHT_2 0x01
4764 #define V_009910_ADDR_SURF_BANK_HEIGHT_4 0x02
4765 #define V_009910_ADDR_SURF_BANK_HEIGHT_8 0x03
4766 #define S_009910_MACRO_TILE_ASPECT(x) (((x) & 0x03) << 18)
4767 #define G_009910_MACRO_TILE_ASPECT(x) (((x) >> 18) & 0x03)
4768 #define C_009910_MACRO_TILE_ASPECT 0xFFF3FFFF
4769 #define V_009910_ADDR_SURF_MACRO_ASPECT_1 0x00
4770 #define V_009910_ADDR_SURF_MACRO_ASPECT_2 0x01
4771 #define V_009910_ADDR_SURF_MACRO_ASPECT_4 0x02
4772 #define V_009910_ADDR_SURF_MACRO_ASPECT_8 0x03
4773 #define S_009910_NUM_BANKS(x) (((x) & 0x03) << 20)
4774 #define G_009910_NUM_BANKS(x) (((x) >> 20) & 0x03)
4775 #define C_009910_NUM_BANKS 0xFFCFFFFF
4776 #define V_009910_ADDR_SURF_2_BANK 0x00
4777 #define V_009910_ADDR_SURF_4_BANK 0x01
4778 #define V_009910_ADDR_SURF_8_BANK 0x02
4779 #define V_009910_ADDR_SURF_16_BANK 0x03
4780 #define S_009910_MICRO_TILE_MODE_NEW(x) (((x) & 0x07) << 22)
4781 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
4782 #define C_009910_MICRO_TILE_MODE_NEW 0xFE3FFFFF
4783 #define V_009910_ADDR_SURF_DISPLAY_MICRO_TILING 0x00
4784 #define V_009910_ADDR_SURF_THIN_MICRO_TILING 0x01
4785 #define V_009910_ADDR_SURF_DEPTH_MICRO_TILING 0x02
4786 #define V_009910_ADDR_SURF_ROTATED_MICRO_TILING 0x03
4787 #define S_009910_SAMPLE_SPLIT(x) (((x) & 0x03) << 25)
4788 #define G_009910_SAMPLE_SPLIT(x) (((x) >> 25) & 0x03)
4789 #define C_009910_SAMPLE_SPLIT 0xF9FFFFFF
4790 #define R_009914_GB_TILE_MODE1 0x009914
4791 #define R_009918_GB_TILE_MODE2 0x009918
4792 #define R_00991C_GB_TILE_MODE3 0x00991C
4793 #define R_009920_GB_TILE_MODE4 0x009920
4794 #define R_009924_GB_TILE_MODE5 0x009924
4795 #define R_009928_GB_TILE_MODE6 0x009928
4796 #define R_00992C_GB_TILE_MODE7 0x00992C
4797 #define R_009930_GB_TILE_MODE8 0x009930
4798 #define R_009934_GB_TILE_MODE9 0x009934
4799 #define R_009938_GB_TILE_MODE10 0x009938
4800 #define R_00993C_GB_TILE_MODE11 0x00993C
4801 #define R_009940_GB_TILE_MODE12 0x009940
4802 #define R_009944_GB_TILE_MODE13 0x009944
4803 #define R_009948_GB_TILE_MODE14 0x009948
4804 #define R_00994C_GB_TILE_MODE15 0x00994C
4805 #define R_009950_GB_TILE_MODE16 0x009950
4806 #define R_009954_GB_TILE_MODE17 0x009954
4807 #define R_009958_GB_TILE_MODE18 0x009958
4808 #define R_00995C_GB_TILE_MODE19 0x00995C
4809 #define R_009960_GB_TILE_MODE20 0x009960
4810 #define R_009964_GB_TILE_MODE21 0x009964
4811 #define R_009968_GB_TILE_MODE22 0x009968
4812 #define R_00996C_GB_TILE_MODE23 0x00996C
4813 #define R_009970_GB_TILE_MODE24 0x009970
4814 #define R_009974_GB_TILE_MODE25 0x009974
4815 #define R_009978_GB_TILE_MODE26 0x009978
4816 #define R_00997C_GB_TILE_MODE27 0x00997C
4817 #define R_009980_GB_TILE_MODE28 0x009980
4818 #define R_009984_GB_TILE_MODE29 0x009984
4819 #define R_009988_GB_TILE_MODE30 0x009988
4820 #define R_00998C_GB_TILE_MODE31 0x00998C
4821 /* CIK */
4822 #define R_009990_GB_MACROTILE_MODE0 0x009990
4823 #define S_009990_BANK_WIDTH(x) (((x) & 0x03) << 0)
4824 #define G_009990_BANK_WIDTH(x) (((x) >> 0) & 0x03)
4825 #define C_009990_BANK_WIDTH 0xFFFFFFFC
4826 #define S_009990_BANK_HEIGHT(x) (((x) & 0x03) << 2)
4827 #define G_009990_BANK_HEIGHT(x) (((x) >> 2) & 0x03)
4828 #define C_009990_BANK_HEIGHT 0xFFFFFFF3
4829 #define S_009990_MACRO_TILE_ASPECT(x) (((x) & 0x03) << 4)
4830 #define G_009990_MACRO_TILE_ASPECT(x) (((x) >> 4) & 0x03)
4831 #define C_009990_MACRO_TILE_ASPECT 0xFFFFFFCF
4832 #define S_009990_NUM_BANKS(x) (((x) & 0x03) << 6)
4833 #define G_009990_NUM_BANKS(x) (((x) >> 6) & 0x03)
4834 #define C_009990_NUM_BANKS 0xFFFFFF3F
4835 #define R_009994_GB_MACROTILE_MODE1 0x009994
4836 #define R_009998_GB_MACROTILE_MODE2 0x009998
4837 #define R_00999C_GB_MACROTILE_MODE3 0x00999C
4838 #define R_0099A0_GB_MACROTILE_MODE4 0x0099A0
4839 #define R_0099A4_GB_MACROTILE_MODE5 0x0099A4
4840 #define R_0099A8_GB_MACROTILE_MODE6 0x0099A8
4841 #define R_0099AC_GB_MACROTILE_MODE7 0x0099AC
4842 #define R_0099B0_GB_MACROTILE_MODE8 0x0099B0
4843 #define R_0099B4_GB_MACROTILE_MODE9 0x0099B4
4844 #define R_0099B8_GB_MACROTILE_MODE10 0x0099B8
4845 #define R_0099BC_GB_MACROTILE_MODE11 0x0099BC
4846 #define R_0099C0_GB_MACROTILE_MODE12 0x0099C0
4847 #define R_0099C4_GB_MACROTILE_MODE13 0x0099C4
4848 #define R_0099C8_GB_MACROTILE_MODE14 0x0099C8
4849 #define R_0099CC_GB_MACROTILE_MODE15 0x0099CC
4850 /* */
4851 #define R_00B000_SPI_SHADER_TBA_LO_PS 0x00B000
4852 #define R_00B004_SPI_SHADER_TBA_HI_PS 0x00B004
4853 #define S_00B004_MEM_BASE(x) (((x) & 0xFF) << 0)
4854 #define G_00B004_MEM_BASE(x) (((x) >> 0) & 0xFF)
4855 #define C_00B004_MEM_BASE 0xFFFFFF00
4856 #define R_00B008_SPI_SHADER_TMA_LO_PS 0x00B008
4857 #define R_00B00C_SPI_SHADER_TMA_HI_PS 0x00B00C
4858 #define S_00B00C_MEM_BASE(x) (((x) & 0xFF) << 0)
4859 #define G_00B00C_MEM_BASE(x) (((x) >> 0) & 0xFF)
4860 #define C_00B00C_MEM_BASE 0xFFFFFF00
4861 /* CIK */
4862 #define R_00B01C_SPI_SHADER_PGM_RSRC3_PS 0x00B01C
4863 #define S_00B01C_CU_EN(x) (((x) & 0xFFFF) << 0)
4864 #define G_00B01C_CU_EN(x) (((x) >> 0) & 0xFFFF)
4865 #define C_00B01C_CU_EN 0xFFFF0000
4866 #define S_00B01C_WAVE_LIMIT(x) (((x) & 0x3F) << 16)
4867 #define G_00B01C_WAVE_LIMIT(x) (((x) >> 16) & 0x3F)
4868 #define C_00B01C_WAVE_LIMIT 0xFFC0FFFF
4869 #define S_00B01C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22)
4870 #define G_00B01C_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F)
4871 #define C_00B01C_LOCK_LOW_THRESHOLD 0xFC3FFFFF
4872 /* */
4873 #define R_00B020_SPI_SHADER_PGM_LO_PS 0x00B020
4874 #define R_00B024_SPI_SHADER_PGM_HI_PS 0x00B024
4875 #define S_00B024_MEM_BASE(x) (((x) & 0xFF) << 0)
4876 #define G_00B024_MEM_BASE(x) (((x) >> 0) & 0xFF)
4877 #define C_00B024_MEM_BASE 0xFFFFFF00
4878 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
4879 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
4880 #define G_00B028_VGPRS(x) (((x) >> 0) & 0x3F)
4881 #define C_00B028_VGPRS 0xFFFFFFC0
4882 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
4883 #define G_00B028_SGPRS(x) (((x) >> 6) & 0x0F)
4884 #define C_00B028_SGPRS 0xFFFFFC3F
4885 #define S_00B028_PRIORITY(x) (((x) & 0x03) << 10)
4886 #define G_00B028_PRIORITY(x) (((x) >> 10) & 0x03)
4887 #define C_00B028_PRIORITY 0xFFFFF3FF
4888 #define S_00B028_FLOAT_MODE(x) (((x) & 0xFF) << 12)
4889 #define G_00B028_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
4890 #define C_00B028_FLOAT_MODE 0xFFF00FFF
4891 #define S_00B028_PRIV(x) (((x) & 0x1) << 20)
4892 #define G_00B028_PRIV(x) (((x) >> 20) & 0x1)
4893 #define C_00B028_PRIV 0xFFEFFFFF
4894 #define S_00B028_DX10_CLAMP(x) (((x) & 0x1) << 21)
4895 #define G_00B028_DX10_CLAMP(x) (((x) >> 21) & 0x1)
4896 #define C_00B028_DX10_CLAMP 0xFFDFFFFF
4897 #define S_00B028_DEBUG_MODE(x) (((x) & 0x1) << 22)
4898 #define G_00B028_DEBUG_MODE(x) (((x) >> 22) & 0x1)
4899 #define C_00B028_DEBUG_MODE 0xFFBFFFFF
4900 #define S_00B028_IEEE_MODE(x) (((x) & 0x1) << 23)
4901 #define G_00B028_IEEE_MODE(x) (((x) >> 23) & 0x1)
4902 #define C_00B028_IEEE_MODE 0xFF7FFFFF
4903 #define S_00B028_CU_GROUP_DISABLE(x) (((x) & 0x1) << 24)
4904 #define G_00B028_CU_GROUP_DISABLE(x) (((x) >> 24) & 0x1)
4905 #define C_00B028_CU_GROUP_DISABLE 0xFEFFFFFF
4906 /* CIK */
4907 #define S_00B028_CACHE_CTL(x) (((x) & 0x07) << 25)
4908 #define G_00B028_CACHE_CTL(x) (((x) >> 25) & 0x07)
4909 #define C_00B028_CACHE_CTL 0xF1FFFFFF
4910 #define S_00B028_CDBG_USER(x) (((x) & 0x1) << 28)
4911 #define G_00B028_CDBG_USER(x) (((x) >> 28) & 0x1)
4912 #define C_00B028_CDBG_USER 0xEFFFFFFF
4913 /* */
4914 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
4915 #define S_00B02C_SCRATCH_EN(x) (((x) & 0x1) << 0)
4916 #define G_00B02C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
4917 #define C_00B02C_SCRATCH_EN 0xFFFFFFFE
4918 #define S_00B02C_USER_SGPR(x) (((x) & 0x1F) << 1)
4919 #define G_00B02C_USER_SGPR(x) (((x) >> 1) & 0x1F)
4920 #define C_00B02C_USER_SGPR 0xFFFFFFC1
4921 #define S_00B02C_TRAP_PRESENT(x) (((x) & 0x1) << 6)
4922 #define G_00B02C_TRAP_PRESENT(x) (((x) >> 6) & 0x1)
4923 #define C_00B02C_TRAP_PRESENT 0xFFFFFFBF
4924 #define S_00B02C_WAVE_CNT_EN(x) (((x) & 0x1) << 7)
4925 #define G_00B02C_WAVE_CNT_EN(x) (((x) >> 7) & 0x1)
4926 #define C_00B02C_WAVE_CNT_EN 0xFFFFFF7F
4927 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
4928 #define G_00B02C_EXTRA_LDS_SIZE(x) (((x) >> 8) & 0xFF)
4929 #define C_00B02C_EXTRA_LDS_SIZE 0xFFFF00FF
4930 #define S_00B02C_EXCP_EN(x) (((x) & 0x7F) << 16) /* mask is 0x1FF on CIK */
4931 #define G_00B02C_EXCP_EN(x) (((x) >> 16) & 0x7F) /* mask is 0x1FF on CIK */
4932 #define C_00B02C_EXCP_EN 0xFF80FFFF /* mask is 0x1FF on CIK */
4933 #define S_00B02C_EXCP_EN_CIK(x) (((x) & 0x1FF) << 16)
4934 #define G_00B02C_EXCP_EN_CIK(x) (((x) >> 16) & 0x1FF)
4935 #define C_00B02C_EXCP_EN_CIK 0xFE00FFFF
4936 #define R_00B030_SPI_SHADER_USER_DATA_PS_0 0x00B030
4937 #define R_00B034_SPI_SHADER_USER_DATA_PS_1 0x00B034
4938 #define R_00B038_SPI_SHADER_USER_DATA_PS_2 0x00B038
4939 #define R_00B03C_SPI_SHADER_USER_DATA_PS_3 0x00B03C
4940 #define R_00B040_SPI_SHADER_USER_DATA_PS_4 0x00B040
4941 #define R_00B044_SPI_SHADER_USER_DATA_PS_5 0x00B044
4942 #define R_00B048_SPI_SHADER_USER_DATA_PS_6 0x00B048
4943 #define R_00B04C_SPI_SHADER_USER_DATA_PS_7 0x00B04C
4944 #define R_00B050_SPI_SHADER_USER_DATA_PS_8 0x00B050
4945 #define R_00B054_SPI_SHADER_USER_DATA_PS_9 0x00B054
4946 #define R_00B058_SPI_SHADER_USER_DATA_PS_10 0x00B058
4947 #define R_00B05C_SPI_SHADER_USER_DATA_PS_11 0x00B05C
4948 #define R_00B060_SPI_SHADER_USER_DATA_PS_12 0x00B060
4949 #define R_00B064_SPI_SHADER_USER_DATA_PS_13 0x00B064
4950 #define R_00B068_SPI_SHADER_USER_DATA_PS_14 0x00B068
4951 #define R_00B06C_SPI_SHADER_USER_DATA_PS_15 0x00B06C
4952 #define R_00B100_SPI_SHADER_TBA_LO_VS 0x00B100
4953 #define R_00B104_SPI_SHADER_TBA_HI_VS 0x00B104
4954 #define S_00B104_MEM_BASE(x) (((x) & 0xFF) << 0)
4955 #define G_00B104_MEM_BASE(x) (((x) >> 0) & 0xFF)
4956 #define C_00B104_MEM_BASE 0xFFFFFF00
4957 #define R_00B108_SPI_SHADER_TMA_LO_VS 0x00B108
4958 #define R_00B10C_SPI_SHADER_TMA_HI_VS 0x00B10C
4959 #define S_00B10C_MEM_BASE(x) (((x) & 0xFF) << 0)
4960 #define G_00B10C_MEM_BASE(x) (((x) >> 0) & 0xFF)
4961 #define C_00B10C_MEM_BASE 0xFFFFFF00
4962 /* CIK */
4963 #define R_00B118_SPI_SHADER_PGM_RSRC3_VS 0x00B118
4964 #define S_00B118_CU_EN(x) (((x) & 0xFFFF) << 0)
4965 #define G_00B118_CU_EN(x) (((x) >> 0) & 0xFFFF)
4966 #define C_00B118_CU_EN 0xFFFF0000
4967 #define S_00B118_WAVE_LIMIT(x) (((x) & 0x3F) << 16)
4968 #define G_00B118_WAVE_LIMIT(x) (((x) >> 16) & 0x3F)
4969 #define C_00B118_WAVE_LIMIT 0xFFC0FFFF
4970 #define S_00B118_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22)
4971 #define G_00B118_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F)
4972 #define C_00B118_LOCK_LOW_THRESHOLD 0xFC3FFFFF
4973 #define R_00B11C_SPI_SHADER_LATE_ALLOC_VS 0x00B11C
4974 #define S_00B11C_LIMIT(x) (((x) & 0x3F) << 0)
4975 #define G_00B11C_LIMIT(x) (((x) >> 0) & 0x3F)
4976 #define C_00B11C_LIMIT 0xFFFFFFC0
4977 /* */
4978 #define R_00B120_SPI_SHADER_PGM_LO_VS 0x00B120
4979 #define R_00B124_SPI_SHADER_PGM_HI_VS 0x00B124
4980 #define S_00B124_MEM_BASE(x) (((x) & 0xFF) << 0)
4981 #define G_00B124_MEM_BASE(x) (((x) >> 0) & 0xFF)
4982 #define C_00B124_MEM_BASE 0xFFFFFF00
4983 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
4984 #define S_00B128_VGPRS(x) (((x) & 0x3F) << 0)
4985 #define G_00B128_VGPRS(x) (((x) >> 0) & 0x3F)
4986 #define C_00B128_VGPRS 0xFFFFFFC0
4987 #define S_00B128_SGPRS(x) (((x) & 0x0F) << 6)
4988 #define G_00B128_SGPRS(x) (((x) >> 6) & 0x0F)
4989 #define C_00B128_SGPRS 0xFFFFFC3F
4990 #define S_00B128_PRIORITY(x) (((x) & 0x03) << 10)
4991 #define G_00B128_PRIORITY(x) (((x) >> 10) & 0x03)
4992 #define C_00B128_PRIORITY 0xFFFFF3FF
4993 #define S_00B128_FLOAT_MODE(x) (((x) & 0xFF) << 12)
4994 #define G_00B128_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
4995 #define C_00B128_FLOAT_MODE 0xFFF00FFF
4996 #define S_00B128_PRIV(x) (((x) & 0x1) << 20)
4997 #define G_00B128_PRIV(x) (((x) >> 20) & 0x1)
4998 #define C_00B128_PRIV 0xFFEFFFFF
4999 #define S_00B128_DX10_CLAMP(x) (((x) & 0x1) << 21)
5000 #define G_00B128_DX10_CLAMP(x) (((x) >> 21) & 0x1)
5001 #define C_00B128_DX10_CLAMP 0xFFDFFFFF
5002 #define S_00B128_DEBUG_MODE(x) (((x) & 0x1) << 22)
5003 #define G_00B128_DEBUG_MODE(x) (((x) >> 22) & 0x1)
5004 #define C_00B128_DEBUG_MODE 0xFFBFFFFF
5005 #define S_00B128_IEEE_MODE(x) (((x) & 0x1) << 23)
5006 #define G_00B128_IEEE_MODE(x) (((x) >> 23) & 0x1)
5007 #define C_00B128_IEEE_MODE 0xFF7FFFFF
5008 #define S_00B128_VGPR_COMP_CNT(x) (((x) & 0x03) << 24)
5009 #define G_00B128_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03)
5010 #define C_00B128_VGPR_COMP_CNT 0xFCFFFFFF
5011 #define S_00B128_CU_GROUP_ENABLE(x) (((x) & 0x1) << 26)
5012 #define G_00B128_CU_GROUP_ENABLE(x) (((x) >> 26) & 0x1)
5013 #define C_00B128_CU_GROUP_ENABLE 0xFBFFFFFF
5014 /* CIK */
5015 #define S_00B128_CACHE_CTL(x) (((x) & 0x07) << 27)
5016 #define G_00B128_CACHE_CTL(x) (((x) >> 27) & 0x07)
5017 #define C_00B128_CACHE_CTL 0xC7FFFFFF
5018 #define S_00B128_CDBG_USER(x) (((x) & 0x1) << 30)
5019 #define G_00B128_CDBG_USER(x) (((x) >> 30) & 0x1)
5020 #define C_00B128_CDBG_USER 0xBFFFFFFF
5021 /* */
5022 #define R_00B12C_SPI_SHADER_PGM_RSRC2_VS 0x00B12C
5023 #define S_00B12C_SCRATCH_EN(x) (((x) & 0x1) << 0)
5024 #define G_00B12C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
5025 #define C_00B12C_SCRATCH_EN 0xFFFFFFFE
5026 #define S_00B12C_USER_SGPR(x) (((x) & 0x1F) << 1)
5027 #define G_00B12C_USER_SGPR(x) (((x) >> 1) & 0x1F)
5028 #define C_00B12C_USER_SGPR 0xFFFFFFC1
5029 #define S_00B12C_TRAP_PRESENT(x) (((x) & 0x1) << 6)
5030 #define G_00B12C_TRAP_PRESENT(x) (((x) >> 6) & 0x1)
5031 #define C_00B12C_TRAP_PRESENT 0xFFFFFFBF
5032 #define S_00B12C_OC_LDS_EN(x) (((x) & 0x1) << 7)
5033 #define G_00B12C_OC_LDS_EN(x) (((x) >> 7) & 0x1)
5034 #define C_00B12C_OC_LDS_EN 0xFFFFFF7F
5035 #define S_00B12C_SO_BASE0_EN(x) (((x) & 0x1) << 8)
5036 #define G_00B12C_SO_BASE0_EN(x) (((x) >> 8) & 0x1)
5037 #define C_00B12C_SO_BASE0_EN 0xFFFFFEFF
5038 #define S_00B12C_SO_BASE1_EN(x) (((x) & 0x1) << 9)
5039 #define G_00B12C_SO_BASE1_EN(x) (((x) >> 9) & 0x1)
5040 #define C_00B12C_SO_BASE1_EN 0xFFFFFDFF
5041 #define S_00B12C_SO_BASE2_EN(x) (((x) & 0x1) << 10)
5042 #define G_00B12C_SO_BASE2_EN(x) (((x) >> 10) & 0x1)
5043 #define C_00B12C_SO_BASE2_EN 0xFFFFFBFF
5044 #define S_00B12C_SO_BASE3_EN(x) (((x) & 0x1) << 11)
5045 #define G_00B12C_SO_BASE3_EN(x) (((x) >> 11) & 0x1)
5046 #define C_00B12C_SO_BASE3_EN 0xFFFFF7FF
5047 #define S_00B12C_SO_EN(x) (((x) & 0x1) << 12)
5048 #define G_00B12C_SO_EN(x) (((x) >> 12) & 0x1)
5049 #define C_00B12C_SO_EN 0xFFFFEFFF
5050 #define S_00B12C_EXCP_EN(x) (((x) & 0x7F) << 13) /* mask is 0x1FF on CIK */
5051 #define G_00B12C_EXCP_EN(x) (((x) >> 13) & 0x7F) /* mask is 0x1FF on CIK */
5052 #define C_00B12C_EXCP_EN 0xFFF01FFF /* mask is 0x1FF on CIK */
5053 #define S_00B12C_EXCP_EN_CIK(x) (((x) & 0x1FF) << 13)
5054 #define G_00B12C_EXCP_EN_CIK(x) (((x) >> 13) & 0x1FF)
5055 #define C_00B12C_EXCP_EN_CIK 0xFFC01FFF
5056 /* VI */
5057 #define S_00B12C_DISPATCH_DRAW_EN(x) (((x) & 0x1) << 24)
5058 #define G_00B12C_DISPATCH_DRAW_EN(x) (((x) >> 24) & 0x1)
5059 #define C_00B12C_DISPATCH_DRAW_EN 0xFEFFFFFF
5060 /* */
5061 #define R_00B130_SPI_SHADER_USER_DATA_VS_0 0x00B130
5062 #define R_00B134_SPI_SHADER_USER_DATA_VS_1 0x00B134
5063 #define R_00B138_SPI_SHADER_USER_DATA_VS_2 0x00B138
5064 #define R_00B13C_SPI_SHADER_USER_DATA_VS_3 0x00B13C
5065 #define R_00B140_SPI_SHADER_USER_DATA_VS_4 0x00B140
5066 #define R_00B144_SPI_SHADER_USER_DATA_VS_5 0x00B144
5067 #define R_00B148_SPI_SHADER_USER_DATA_VS_6 0x00B148
5068 #define R_00B14C_SPI_SHADER_USER_DATA_VS_7 0x00B14C
5069 #define R_00B150_SPI_SHADER_USER_DATA_VS_8 0x00B150
5070 #define R_00B154_SPI_SHADER_USER_DATA_VS_9 0x00B154
5071 #define R_00B158_SPI_SHADER_USER_DATA_VS_10 0x00B158
5072 #define R_00B15C_SPI_SHADER_USER_DATA_VS_11 0x00B15C
5073 #define R_00B160_SPI_SHADER_USER_DATA_VS_12 0x00B160
5074 #define R_00B164_SPI_SHADER_USER_DATA_VS_13 0x00B164
5075 #define R_00B168_SPI_SHADER_USER_DATA_VS_14 0x00B168
5076 #define R_00B16C_SPI_SHADER_USER_DATA_VS_15 0x00B16C
5077 #define R_00B200_SPI_SHADER_TBA_LO_GS 0x00B200
5078 #define R_00B204_SPI_SHADER_TBA_HI_GS 0x00B204
5079 #define S_00B204_MEM_BASE(x) (((x) & 0xFF) << 0)
5080 #define G_00B204_MEM_BASE(x) (((x) >> 0) & 0xFF)
5081 #define C_00B204_MEM_BASE 0xFFFFFF00
5082 #define R_00B208_SPI_SHADER_TMA_LO_GS 0x00B208
5083 #define R_00B20C_SPI_SHADER_TMA_HI_GS 0x00B20C
5084 #define S_00B20C_MEM_BASE(x) (((x) & 0xFF) << 0)
5085 #define G_00B20C_MEM_BASE(x) (((x) >> 0) & 0xFF)
5086 #define C_00B20C_MEM_BASE 0xFFFFFF00
5087 /* CIK */
5088 #define R_00B21C_SPI_SHADER_PGM_RSRC3_GS 0x00B21C
5089 #define S_00B21C_CU_EN(x) (((x) & 0xFFFF) << 0)
5090 #define G_00B21C_CU_EN(x) (((x) >> 0) & 0xFFFF)
5091 #define C_00B21C_CU_EN 0xFFFF0000
5092 #define S_00B21C_WAVE_LIMIT(x) (((x) & 0x3F) << 16)
5093 #define G_00B21C_WAVE_LIMIT(x) (((x) >> 16) & 0x3F)
5094 #define C_00B21C_WAVE_LIMIT 0xFFC0FFFF
5095 #define S_00B21C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22)
5096 #define G_00B21C_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F)
5097 #define C_00B21C_LOCK_LOW_THRESHOLD 0xFC3FFFFF
5098 /* */
5099 /* VI */
5100 #define S_00B21C_GROUP_FIFO_DEPTH(x) (((x) & 0x3F) << 26)
5101 #define G_00B21C_GROUP_FIFO_DEPTH(x) (((x) >> 26) & 0x3F)
5102 #define C_00B21C_GROUP_FIFO_DEPTH 0x03FFFFFF
5103 /* */
5104 #define R_00B220_SPI_SHADER_PGM_LO_GS 0x00B220
5105 #define R_00B224_SPI_SHADER_PGM_HI_GS 0x00B224
5106 #define S_00B224_MEM_BASE(x) (((x) & 0xFF) << 0)
5107 #define G_00B224_MEM_BASE(x) (((x) >> 0) & 0xFF)
5108 #define C_00B224_MEM_BASE 0xFFFFFF00
5109 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
5110 #define S_00B228_VGPRS(x) (((x) & 0x3F) << 0)
5111 #define G_00B228_VGPRS(x) (((x) >> 0) & 0x3F)
5112 #define C_00B228_VGPRS 0xFFFFFFC0
5113 #define S_00B228_SGPRS(x) (((x) & 0x0F) << 6)
5114 #define G_00B228_SGPRS(x) (((x) >> 6) & 0x0F)
5115 #define C_00B228_SGPRS 0xFFFFFC3F
5116 #define S_00B228_PRIORITY(x) (((x) & 0x03) << 10)
5117 #define G_00B228_PRIORITY(x) (((x) >> 10) & 0x03)
5118 #define C_00B228_PRIORITY 0xFFFFF3FF
5119 #define S_00B228_FLOAT_MODE(x) (((x) & 0xFF) << 12)
5120 #define G_00B228_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
5121 #define C_00B228_FLOAT_MODE 0xFFF00FFF
5122 #define S_00B228_PRIV(x) (((x) & 0x1) << 20)
5123 #define G_00B228_PRIV(x) (((x) >> 20) & 0x1)
5124 #define C_00B228_PRIV 0xFFEFFFFF
5125 #define S_00B228_DX10_CLAMP(x) (((x) & 0x1) << 21)
5126 #define G_00B228_DX10_CLAMP(x) (((x) >> 21) & 0x1)
5127 #define C_00B228_DX10_CLAMP 0xFFDFFFFF
5128 #define S_00B228_DEBUG_MODE(x) (((x) & 0x1) << 22)
5129 #define G_00B228_DEBUG_MODE(x) (((x) >> 22) & 0x1)
5130 #define C_00B228_DEBUG_MODE 0xFFBFFFFF
5131 #define S_00B228_IEEE_MODE(x) (((x) & 0x1) << 23)
5132 #define G_00B228_IEEE_MODE(x) (((x) >> 23) & 0x1)
5133 #define C_00B228_IEEE_MODE 0xFF7FFFFF
5134 #define S_00B228_CU_GROUP_ENABLE(x) (((x) & 0x1) << 24)
5135 #define G_00B228_CU_GROUP_ENABLE(x) (((x) >> 24) & 0x1)
5136 #define C_00B228_CU_GROUP_ENABLE 0xFEFFFFFF
5137 /* CIK */
5138 #define S_00B228_CACHE_CTL(x) (((x) & 0x07) << 25)
5139 #define G_00B228_CACHE_CTL(x) (((x) >> 25) & 0x07)
5140 #define C_00B228_CACHE_CTL 0xF1FFFFFF
5141 #define S_00B228_CDBG_USER(x) (((x) & 0x1) << 28)
5142 #define G_00B228_CDBG_USER(x) (((x) >> 28) & 0x1)
5143 #define C_00B228_CDBG_USER 0xEFFFFFFF
5144 /* */
5145 #define R_00B22C_SPI_SHADER_PGM_RSRC2_GS 0x00B22C
5146 #define S_00B22C_SCRATCH_EN(x) (((x) & 0x1) << 0)
5147 #define G_00B22C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
5148 #define C_00B22C_SCRATCH_EN 0xFFFFFFFE
5149 #define S_00B22C_USER_SGPR(x) (((x) & 0x1F) << 1)
5150 #define G_00B22C_USER_SGPR(x) (((x) >> 1) & 0x1F)
5151 #define C_00B22C_USER_SGPR 0xFFFFFFC1
5152 #define S_00B22C_TRAP_PRESENT(x) (((x) & 0x1) << 6)
5153 #define G_00B22C_TRAP_PRESENT(x) (((x) >> 6) & 0x1)
5154 #define C_00B22C_TRAP_PRESENT 0xFFFFFFBF
5155 #define S_00B22C_EXCP_EN(x) (((x) & 0x7F) << 7) /* mask is 0x1FF on CIK */
5156 #define G_00B22C_EXCP_EN(x) (((x) >> 7) & 0x7F) /* mask is 0x1FF on CIK */
5157 #define C_00B22C_EXCP_EN 0xFFFFC07F /* mask is 0x1FF on CIK */
5158 #define S_00B22C_EXCP_EN_CIK(x) (((x) & 0x1FF) << 7)
5159 #define G_00B22C_EXCP_EN_CIK(x) (((x) >> 7) & 0x1FF)
5160 #define C_00B22C_EXCP_EN_CIK 0xFFFF007F
5161 #define R_00B230_SPI_SHADER_USER_DATA_GS_0 0x00B230
5162 #define R_00B234_SPI_SHADER_USER_DATA_GS_1 0x00B234
5163 #define R_00B238_SPI_SHADER_USER_DATA_GS_2 0x00B238
5164 #define R_00B23C_SPI_SHADER_USER_DATA_GS_3 0x00B23C
5165 #define R_00B240_SPI_SHADER_USER_DATA_GS_4 0x00B240
5166 #define R_00B244_SPI_SHADER_USER_DATA_GS_5 0x00B244
5167 #define R_00B248_SPI_SHADER_USER_DATA_GS_6 0x00B248
5168 #define R_00B24C_SPI_SHADER_USER_DATA_GS_7 0x00B24C
5169 #define R_00B250_SPI_SHADER_USER_DATA_GS_8 0x00B250
5170 #define R_00B254_SPI_SHADER_USER_DATA_GS_9 0x00B254
5171 #define R_00B258_SPI_SHADER_USER_DATA_GS_10 0x00B258
5172 #define R_00B25C_SPI_SHADER_USER_DATA_GS_11 0x00B25C
5173 #define R_00B260_SPI_SHADER_USER_DATA_GS_12 0x00B260
5174 #define R_00B264_SPI_SHADER_USER_DATA_GS_13 0x00B264
5175 #define R_00B268_SPI_SHADER_USER_DATA_GS_14 0x00B268
5176 #define R_00B26C_SPI_SHADER_USER_DATA_GS_15 0x00B26C
5177 #define R_00B300_SPI_SHADER_TBA_LO_ES 0x00B300
5178 #define R_00B304_SPI_SHADER_TBA_HI_ES 0x00B304
5179 #define S_00B304_MEM_BASE(x) (((x) & 0xFF) << 0)
5180 #define G_00B304_MEM_BASE(x) (((x) >> 0) & 0xFF)
5181 #define C_00B304_MEM_BASE 0xFFFFFF00
5182 #define R_00B308_SPI_SHADER_TMA_LO_ES 0x00B308
5183 #define R_00B30C_SPI_SHADER_TMA_HI_ES 0x00B30C
5184 #define S_00B30C_MEM_BASE(x) (((x) & 0xFF) << 0)
5185 #define G_00B30C_MEM_BASE(x) (((x) >> 0) & 0xFF)
5186 #define C_00B30C_MEM_BASE 0xFFFFFF00
5187 /* CIK */
5188 #define R_00B31C_SPI_SHADER_PGM_RSRC3_ES 0x00B31C
5189 #define S_00B31C_CU_EN(x) (((x) & 0xFFFF) << 0)
5190 #define G_00B31C_CU_EN(x) (((x) >> 0) & 0xFFFF)
5191 #define C_00B31C_CU_EN 0xFFFF0000
5192 #define S_00B31C_WAVE_LIMIT(x) (((x) & 0x3F) << 16)
5193 #define G_00B31C_WAVE_LIMIT(x) (((x) >> 16) & 0x3F)
5194 #define C_00B31C_WAVE_LIMIT 0xFFC0FFFF
5195 #define S_00B31C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22)
5196 #define G_00B31C_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F)
5197 #define C_00B31C_LOCK_LOW_THRESHOLD 0xFC3FFFFF
5198 /* */
5199 /* VI */
5200 #define S_00B31C_GROUP_FIFO_DEPTH(x) (((x) & 0x3F) << 26)
5201 #define G_00B31C_GROUP_FIFO_DEPTH(x) (((x) >> 26) & 0x3F)
5202 #define C_00B31C_GROUP_FIFO_DEPTH 0x03FFFFFF
5203 /* */
5204 #define R_00B320_SPI_SHADER_PGM_LO_ES 0x00B320
5205 #define R_00B324_SPI_SHADER_PGM_HI_ES 0x00B324
5206 #define S_00B324_MEM_BASE(x) (((x) & 0xFF) << 0)
5207 #define G_00B324_MEM_BASE(x) (((x) >> 0) & 0xFF)
5208 #define C_00B324_MEM_BASE 0xFFFFFF00
5209 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
5210 #define S_00B328_VGPRS(x) (((x) & 0x3F) << 0)
5211 #define G_00B328_VGPRS(x) (((x) >> 0) & 0x3F)
5212 #define C_00B328_VGPRS 0xFFFFFFC0
5213 #define S_00B328_SGPRS(x) (((x) & 0x0F) << 6)
5214 #define G_00B328_SGPRS(x) (((x) >> 6) & 0x0F)
5215 #define C_00B328_SGPRS 0xFFFFFC3F
5216 #define S_00B328_PRIORITY(x) (((x) & 0x03) << 10)
5217 #define G_00B328_PRIORITY(x) (((x) >> 10) & 0x03)
5218 #define C_00B328_PRIORITY 0xFFFFF3FF
5219 #define S_00B328_FLOAT_MODE(x) (((x) & 0xFF) << 12)
5220 #define G_00B328_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
5221 #define C_00B328_FLOAT_MODE 0xFFF00FFF
5222 #define S_00B328_PRIV(x) (((x) & 0x1) << 20)
5223 #define G_00B328_PRIV(x) (((x) >> 20) & 0x1)
5224 #define C_00B328_PRIV 0xFFEFFFFF
5225 #define S_00B328_DX10_CLAMP(x) (((x) & 0x1) << 21)
5226 #define G_00B328_DX10_CLAMP(x) (((x) >> 21) & 0x1)
5227 #define C_00B328_DX10_CLAMP 0xFFDFFFFF
5228 #define S_00B328_DEBUG_MODE(x) (((x) & 0x1) << 22)
5229 #define G_00B328_DEBUG_MODE(x) (((x) >> 22) & 0x1)
5230 #define C_00B328_DEBUG_MODE 0xFFBFFFFF
5231 #define S_00B328_IEEE_MODE(x) (((x) & 0x1) << 23)
5232 #define G_00B328_IEEE_MODE(x) (((x) >> 23) & 0x1)
5233 #define C_00B328_IEEE_MODE 0xFF7FFFFF
5234 #define S_00B328_VGPR_COMP_CNT(x) (((x) & 0x03) << 24)
5235 #define G_00B328_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03)
5236 #define C_00B328_VGPR_COMP_CNT 0xFCFFFFFF
5237 #define S_00B328_CU_GROUP_ENABLE(x) (((x) & 0x1) << 26)
5238 #define G_00B328_CU_GROUP_ENABLE(x) (((x) >> 26) & 0x1)
5239 #define C_00B328_CU_GROUP_ENABLE 0xFBFFFFFF
5240 /* CIK */
5241 #define S_00B328_CACHE_CTL(x) (((x) & 0x07) << 27)
5242 #define G_00B328_CACHE_CTL(x) (((x) >> 27) & 0x07)
5243 #define C_00B328_CACHE_CTL 0xC7FFFFFF
5244 #define S_00B328_CDBG_USER(x) (((x) & 0x1) << 30)
5245 #define G_00B328_CDBG_USER(x) (((x) >> 30) & 0x1)
5246 #define C_00B328_CDBG_USER 0xBFFFFFFF
5247 /* */
5248 #define R_00B32C_SPI_SHADER_PGM_RSRC2_ES 0x00B32C
5249 #define S_00B32C_SCRATCH_EN(x) (((x) & 0x1) << 0)
5250 #define G_00B32C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
5251 #define C_00B32C_SCRATCH_EN 0xFFFFFFFE
5252 #define S_00B32C_USER_SGPR(x) (((x) & 0x1F) << 1)
5253 #define G_00B32C_USER_SGPR(x) (((x) >> 1) & 0x1F)
5254 #define C_00B32C_USER_SGPR 0xFFFFFFC1
5255 #define S_00B32C_TRAP_PRESENT(x) (((x) & 0x1) << 6)
5256 #define G_00B32C_TRAP_PRESENT(x) (((x) >> 6) & 0x1)
5257 #define C_00B32C_TRAP_PRESENT 0xFFFFFFBF
5258 #define S_00B32C_OC_LDS_EN(x) (((x) & 0x1) << 7)
5259 #define G_00B32C_OC_LDS_EN(x) (((x) >> 7) & 0x1)
5260 #define C_00B32C_OC_LDS_EN 0xFFFFFF7F
5261 #define S_00B32C_EXCP_EN(x) (((x) & 0x7F) << 8) /* mask is 0x1FF on CIK */
5262 #define G_00B32C_EXCP_EN(x) (((x) >> 8) & 0x7F) /* mask is 0x1FF on CIK */
5263 #define C_00B32C_EXCP_EN 0xFFFF80FF /* mask is 0x1FF on CIK */
5264 #define S_00B32C_LDS_SIZE(x) (((x) & 0x1FF) << 20) /* CIK, for on-chip GS */
5265 #define G_00B32C_LDS_SIZE(x) (((x) >> 20) & 0x1FF) /* CIK, for on-chip GS */
5266 #define C_00B32C_LDS_SIZE 0xE00FFFFF /* CIK, for on-chip GS */
5267 #define R_00B330_SPI_SHADER_USER_DATA_ES_0 0x00B330
5268 #define R_00B334_SPI_SHADER_USER_DATA_ES_1 0x00B334
5269 #define R_00B338_SPI_SHADER_USER_DATA_ES_2 0x00B338
5270 #define R_00B33C_SPI_SHADER_USER_DATA_ES_3 0x00B33C
5271 #define R_00B340_SPI_SHADER_USER_DATA_ES_4 0x00B340
5272 #define R_00B344_SPI_SHADER_USER_DATA_ES_5 0x00B344
5273 #define R_00B348_SPI_SHADER_USER_DATA_ES_6 0x00B348
5274 #define R_00B34C_SPI_SHADER_USER_DATA_ES_7 0x00B34C
5275 #define R_00B350_SPI_SHADER_USER_DATA_ES_8 0x00B350
5276 #define R_00B354_SPI_SHADER_USER_DATA_ES_9 0x00B354
5277 #define R_00B358_SPI_SHADER_USER_DATA_ES_10 0x00B358
5278 #define R_00B35C_SPI_SHADER_USER_DATA_ES_11 0x00B35C
5279 #define R_00B360_SPI_SHADER_USER_DATA_ES_12 0x00B360
5280 #define R_00B364_SPI_SHADER_USER_DATA_ES_13 0x00B364
5281 #define R_00B368_SPI_SHADER_USER_DATA_ES_14 0x00B368
5282 #define R_00B36C_SPI_SHADER_USER_DATA_ES_15 0x00B36C
5283 #define R_00B400_SPI_SHADER_TBA_LO_HS 0x00B400
5284 #define R_00B404_SPI_SHADER_TBA_HI_HS 0x00B404
5285 #define S_00B404_MEM_BASE(x) (((x) & 0xFF) << 0)
5286 #define G_00B404_MEM_BASE(x) (((x) >> 0) & 0xFF)
5287 #define C_00B404_MEM_BASE 0xFFFFFF00
5288 #define R_00B408_SPI_SHADER_TMA_LO_HS 0x00B408
5289 #define R_00B40C_SPI_SHADER_TMA_HI_HS 0x00B40C
5290 #define S_00B40C_MEM_BASE(x) (((x) & 0xFF) << 0)
5291 #define G_00B40C_MEM_BASE(x) (((x) >> 0) & 0xFF)
5292 #define C_00B40C_MEM_BASE 0xFFFFFF00
5293 /* CIK */
5294 #define R_00B41C_SPI_SHADER_PGM_RSRC3_HS 0x00B41C
5295 #define S_00B41C_WAVE_LIMIT(x) (((x) & 0x3F) << 0)
5296 #define G_00B41C_WAVE_LIMIT(x) (((x) >> 0) & 0x3F)
5297 #define C_00B41C_WAVE_LIMIT 0xFFFFFFC0
5298 #define S_00B41C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 6)
5299 #define G_00B41C_LOCK_LOW_THRESHOLD(x) (((x) >> 6) & 0x0F)
5300 #define C_00B41C_LOCK_LOW_THRESHOLD 0xFFFFFC3F
5301 /* */
5302 /* VI */
5303 #define S_00B41C_GROUP_FIFO_DEPTH(x) (((x) & 0x3F) << 10)
5304 #define G_00B41C_GROUP_FIFO_DEPTH(x) (((x) >> 10) & 0x3F)
5305 #define C_00B41C_GROUP_FIFO_DEPTH 0xFFFF03FF
5306 /* */
5307 #define R_00B420_SPI_SHADER_PGM_LO_HS 0x00B420
5308 #define R_00B424_SPI_SHADER_PGM_HI_HS 0x00B424
5309 #define S_00B424_MEM_BASE(x) (((x) & 0xFF) << 0)
5310 #define G_00B424_MEM_BASE(x) (((x) >> 0) & 0xFF)
5311 #define C_00B424_MEM_BASE 0xFFFFFF00
5312 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
5313 #define S_00B428_VGPRS(x) (((x) & 0x3F) << 0)
5314 #define G_00B428_VGPRS(x) (((x) >> 0) & 0x3F)
5315 #define C_00B428_VGPRS 0xFFFFFFC0
5316 #define S_00B428_SGPRS(x) (((x) & 0x0F) << 6)
5317 #define G_00B428_SGPRS(x) (((x) >> 6) & 0x0F)
5318 #define C_00B428_SGPRS 0xFFFFFC3F
5319 #define S_00B428_PRIORITY(x) (((x) & 0x03) << 10)
5320 #define G_00B428_PRIORITY(x) (((x) >> 10) & 0x03)
5321 #define C_00B428_PRIORITY 0xFFFFF3FF
5322 #define S_00B428_FLOAT_MODE(x) (((x) & 0xFF) << 12)
5323 #define G_00B428_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
5324 #define C_00B428_FLOAT_MODE 0xFFF00FFF
5325 #define S_00B428_PRIV(x) (((x) & 0x1) << 20)
5326 #define G_00B428_PRIV(x) (((x) >> 20) & 0x1)
5327 #define C_00B428_PRIV 0xFFEFFFFF
5328 #define S_00B428_DX10_CLAMP(x) (((x) & 0x1) << 21)
5329 #define G_00B428_DX10_CLAMP(x) (((x) >> 21) & 0x1)
5330 #define C_00B428_DX10_CLAMP 0xFFDFFFFF
5331 #define S_00B428_DEBUG_MODE(x) (((x) & 0x1) << 22)
5332 #define G_00B428_DEBUG_MODE(x) (((x) >> 22) & 0x1)
5333 #define C_00B428_DEBUG_MODE 0xFFBFFFFF
5334 #define S_00B428_IEEE_MODE(x) (((x) & 0x1) << 23)
5335 #define G_00B428_IEEE_MODE(x) (((x) >> 23) & 0x1)
5336 #define C_00B428_IEEE_MODE 0xFF7FFFFF
5337 /* CIK */
5338 #define S_00B428_CACHE_CTL(x) (((x) & 0x07) << 24)
5339 #define G_00B428_CACHE_CTL(x) (((x) >> 24) & 0x07)
5340 #define C_00B428_CACHE_CTL 0xF8FFFFFF
5341 #define S_00B428_CDBG_USER(x) (((x) & 0x1) << 27)
5342 #define G_00B428_CDBG_USER(x) (((x) >> 27) & 0x1)
5343 #define C_00B428_CDBG_USER 0xF7FFFFFF
5344 /* */
5345 #define R_00B42C_SPI_SHADER_PGM_RSRC2_HS 0x00B42C
5346 #define S_00B42C_SCRATCH_EN(x) (((x) & 0x1) << 0)
5347 #define G_00B42C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
5348 #define C_00B42C_SCRATCH_EN 0xFFFFFFFE
5349 #define S_00B42C_USER_SGPR(x) (((x) & 0x1F) << 1)
5350 #define G_00B42C_USER_SGPR(x) (((x) >> 1) & 0x1F)
5351 #define C_00B42C_USER_SGPR 0xFFFFFFC1
5352 #define S_00B42C_TRAP_PRESENT(x) (((x) & 0x1) << 6)
5353 #define G_00B42C_TRAP_PRESENT(x) (((x) >> 6) & 0x1)
5354 #define C_00B42C_TRAP_PRESENT 0xFFFFFFBF
5355 #define S_00B42C_OC_LDS_EN(x) (((x) & 0x1) << 7)
5356 #define G_00B42C_OC_LDS_EN(x) (((x) >> 7) & 0x1)
5357 #define C_00B42C_OC_LDS_EN 0xFFFFFF7F
5358 #define S_00B42C_TG_SIZE_EN(x) (((x) & 0x1) << 8)
5359 #define G_00B42C_TG_SIZE_EN(x) (((x) >> 8) & 0x1)
5360 #define C_00B42C_TG_SIZE_EN 0xFFFFFEFF
5361 #define S_00B42C_EXCP_EN(x) (((x) & 0x7F) << 9) /* mask is 0x1FF on CIK */
5362 #define G_00B42C_EXCP_EN(x) (((x) >> 9) & 0x7F) /* mask is 0x1FF on CIK */
5363 #define C_00B42C_EXCP_EN 0xFFFF01FF /* mask is 0x1FF on CIK */
5364 #define R_00B430_SPI_SHADER_USER_DATA_HS_0 0x00B430
5365 #define R_00B434_SPI_SHADER_USER_DATA_HS_1 0x00B434
5366 #define R_00B438_SPI_SHADER_USER_DATA_HS_2 0x00B438
5367 #define R_00B43C_SPI_SHADER_USER_DATA_HS_3 0x00B43C
5368 #define R_00B440_SPI_SHADER_USER_DATA_HS_4 0x00B440
5369 #define R_00B444_SPI_SHADER_USER_DATA_HS_5 0x00B444
5370 #define R_00B448_SPI_SHADER_USER_DATA_HS_6 0x00B448
5371 #define R_00B44C_SPI_SHADER_USER_DATA_HS_7 0x00B44C
5372 #define R_00B450_SPI_SHADER_USER_DATA_HS_8 0x00B450
5373 #define R_00B454_SPI_SHADER_USER_DATA_HS_9 0x00B454
5374 #define R_00B458_SPI_SHADER_USER_DATA_HS_10 0x00B458
5375 #define R_00B45C_SPI_SHADER_USER_DATA_HS_11 0x00B45C
5376 #define R_00B460_SPI_SHADER_USER_DATA_HS_12 0x00B460
5377 #define R_00B464_SPI_SHADER_USER_DATA_HS_13 0x00B464
5378 #define R_00B468_SPI_SHADER_USER_DATA_HS_14 0x00B468
5379 #define R_00B46C_SPI_SHADER_USER_DATA_HS_15 0x00B46C
5380 #define R_00B500_SPI_SHADER_TBA_LO_LS 0x00B500
5381 #define R_00B504_SPI_SHADER_TBA_HI_LS 0x00B504
5382 #define S_00B504_MEM_BASE(x) (((x) & 0xFF) << 0)
5383 #define G_00B504_MEM_BASE(x) (((x) >> 0) & 0xFF)
5384 #define C_00B504_MEM_BASE 0xFFFFFF00
5385 #define R_00B508_SPI_SHADER_TMA_LO_LS 0x00B508
5386 #define R_00B50C_SPI_SHADER_TMA_HI_LS 0x00B50C
5387 #define S_00B50C_MEM_BASE(x) (((x) & 0xFF) << 0)
5388 #define G_00B50C_MEM_BASE(x) (((x) >> 0) & 0xFF)
5389 #define C_00B50C_MEM_BASE 0xFFFFFF00
5390 /* CIK */
5391 #define R_00B51C_SPI_SHADER_PGM_RSRC3_LS 0x00B51C
5392 #define S_00B51C_CU_EN(x) (((x) & 0xFFFF) << 0)
5393 #define G_00B51C_CU_EN(x) (((x) >> 0) & 0xFFFF)
5394 #define C_00B51C_CU_EN 0xFFFF0000
5395 #define S_00B51C_WAVE_LIMIT(x) (((x) & 0x3F) << 16)
5396 #define G_00B51C_WAVE_LIMIT(x) (((x) >> 16) & 0x3F)
5397 #define C_00B51C_WAVE_LIMIT 0xFFC0FFFF
5398 #define S_00B51C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22)
5399 #define G_00B51C_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F)
5400 #define C_00B51C_LOCK_LOW_THRESHOLD 0xFC3FFFFF
5401 /* */
5402 /* VI */
5403 #define S_00B51C_GROUP_FIFO_DEPTH(x) (((x) & 0x3F) << 26)
5404 #define G_00B51C_GROUP_FIFO_DEPTH(x) (((x) >> 26) & 0x3F)
5405 #define C_00B51C_GROUP_FIFO_DEPTH 0x03FFFFFF
5406 /* */
5407 #define R_00B520_SPI_SHADER_PGM_LO_LS 0x00B520
5408 #define R_00B524_SPI_SHADER_PGM_HI_LS 0x00B524
5409 #define S_00B524_MEM_BASE(x) (((x) & 0xFF) << 0)
5410 #define G_00B524_MEM_BASE(x) (((x) >> 0) & 0xFF)
5411 #define C_00B524_MEM_BASE 0xFFFFFF00
5412 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
5413 #define S_00B528_VGPRS(x) (((x) & 0x3F) << 0)
5414 #define G_00B528_VGPRS(x) (((x) >> 0) & 0x3F)
5415 #define C_00B528_VGPRS 0xFFFFFFC0
5416 #define S_00B528_SGPRS(x) (((x) & 0x0F) << 6)
5417 #define G_00B528_SGPRS(x) (((x) >> 6) & 0x0F)
5418 #define C_00B528_SGPRS 0xFFFFFC3F
5419 #define S_00B528_PRIORITY(x) (((x) & 0x03) << 10)
5420 #define G_00B528_PRIORITY(x) (((x) >> 10) & 0x03)
5421 #define C_00B528_PRIORITY 0xFFFFF3FF
5422 #define S_00B528_FLOAT_MODE(x) (((x) & 0xFF) << 12)
5423 #define G_00B528_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
5424 #define C_00B528_FLOAT_MODE 0xFFF00FFF
5425 #define S_00B528_PRIV(x) (((x) & 0x1) << 20)
5426 #define G_00B528_PRIV(x) (((x) >> 20) & 0x1)
5427 #define C_00B528_PRIV 0xFFEFFFFF
5428 #define S_00B528_DX10_CLAMP(x) (((x) & 0x1) << 21)
5429 #define G_00B528_DX10_CLAMP(x) (((x) >> 21) & 0x1)
5430 #define C_00B528_DX10_CLAMP 0xFFDFFFFF
5431 #define S_00B528_DEBUG_MODE(x) (((x) & 0x1) << 22)
5432 #define G_00B528_DEBUG_MODE(x) (((x) >> 22) & 0x1)
5433 #define C_00B528_DEBUG_MODE 0xFFBFFFFF
5434 #define S_00B528_IEEE_MODE(x) (((x) & 0x1) << 23)
5435 #define G_00B528_IEEE_MODE(x) (((x) >> 23) & 0x1)
5436 #define C_00B528_IEEE_MODE 0xFF7FFFFF
5437 #define S_00B528_VGPR_COMP_CNT(x) (((x) & 0x03) << 24)
5438 #define G_00B528_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03)
5439 #define C_00B528_VGPR_COMP_CNT 0xFCFFFFFF
5440 /* CIK */
5441 #define S_00B528_CACHE_CTL(x) (((x) & 0x07) << 26)
5442 #define G_00B528_CACHE_CTL(x) (((x) >> 26) & 0x07)
5443 #define C_00B528_CACHE_CTL 0xE3FFFFFF
5444 #define S_00B528_CDBG_USER(x) (((x) & 0x1) << 29)
5445 #define G_00B528_CDBG_USER(x) (((x) >> 29) & 0x1)
5446 #define C_00B528_CDBG_USER 0xDFFFFFFF
5447 /* */
5448 #define R_00B52C_SPI_SHADER_PGM_RSRC2_LS 0x00B52C
5449 #define S_00B52C_SCRATCH_EN(x) (((x) & 0x1) << 0)
5450 #define G_00B52C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
5451 #define C_00B52C_SCRATCH_EN 0xFFFFFFFE
5452 #define S_00B52C_USER_SGPR(x) (((x) & 0x1F) << 1)
5453 #define G_00B52C_USER_SGPR(x) (((x) >> 1) & 0x1F)
5454 #define C_00B52C_USER_SGPR 0xFFFFFFC1
5455 #define S_00B52C_TRAP_PRESENT(x) (((x) & 0x1) << 6)
5456 #define G_00B52C_TRAP_PRESENT(x) (((x) >> 6) & 0x1)
5457 #define C_00B52C_TRAP_PRESENT 0xFFFFFFBF
5458 #define S_00B52C_LDS_SIZE(x) (((x) & 0x1FF) << 7)
5459 #define G_00B52C_LDS_SIZE(x) (((x) >> 7) & 0x1FF)
5460 #define C_00B52C_LDS_SIZE 0xFFFF007F
5461 #define S_00B52C_EXCP_EN(x) (((x) & 0x7F) << 16) /* mask is 0x1FF on CIK */
5462 #define G_00B52C_EXCP_EN(x) (((x) >> 16) & 0x7F) /* mask is 0x1FF on CIK */
5463 #define C_00B52C_EXCP_EN 0xFF80FFFF /* mask is 0x1FF on CIK */
5464 #define R_00B530_SPI_SHADER_USER_DATA_LS_0 0x00B530
5465 #define R_00B534_SPI_SHADER_USER_DATA_LS_1 0x00B534
5466 #define R_00B538_SPI_SHADER_USER_DATA_LS_2 0x00B538
5467 #define R_00B53C_SPI_SHADER_USER_DATA_LS_3 0x00B53C
5468 #define R_00B540_SPI_SHADER_USER_DATA_LS_4 0x00B540
5469 #define R_00B544_SPI_SHADER_USER_DATA_LS_5 0x00B544
5470 #define R_00B548_SPI_SHADER_USER_DATA_LS_6 0x00B548
5471 #define R_00B54C_SPI_SHADER_USER_DATA_LS_7 0x00B54C
5472 #define R_00B550_SPI_SHADER_USER_DATA_LS_8 0x00B550
5473 #define R_00B554_SPI_SHADER_USER_DATA_LS_9 0x00B554
5474 #define R_00B558_SPI_SHADER_USER_DATA_LS_10 0x00B558
5475 #define R_00B55C_SPI_SHADER_USER_DATA_LS_11 0x00B55C
5476 #define R_00B560_SPI_SHADER_USER_DATA_LS_12 0x00B560
5477 #define R_00B564_SPI_SHADER_USER_DATA_LS_13 0x00B564
5478 #define R_00B568_SPI_SHADER_USER_DATA_LS_14 0x00B568
5479 #define R_00B56C_SPI_SHADER_USER_DATA_LS_15 0x00B56C
5480 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
5481 #define S_00B800_COMPUTE_SHADER_EN(x) (((x) & 0x1) << 0)
5482 #define G_00B800_COMPUTE_SHADER_EN(x) (((x) >> 0) & 0x1)
5483 #define C_00B800_COMPUTE_SHADER_EN 0xFFFFFFFE
5484 #define S_00B800_PARTIAL_TG_EN(x) (((x) & 0x1) << 1)
5485 #define G_00B800_PARTIAL_TG_EN(x) (((x) >> 1) & 0x1)
5486 #define C_00B800_PARTIAL_TG_EN 0xFFFFFFFD
5487 #define S_00B800_FORCE_START_AT_000(x) (((x) & 0x1) << 2)
5488 #define G_00B800_FORCE_START_AT_000(x) (((x) >> 2) & 0x1)
5489 #define C_00B800_FORCE_START_AT_000 0xFFFFFFFB
5490 #define S_00B800_ORDERED_APPEND_ENBL(x) (((x) & 0x1) << 3)
5491 #define G_00B800_ORDERED_APPEND_ENBL(x) (((x) >> 3) & 0x1)
5492 #define C_00B800_ORDERED_APPEND_ENBL 0xFFFFFFF7
5493 /* CIK */
5494 #define S_00B800_ORDERED_APPEND_MODE(x) (((x) & 0x1) << 4)
5495 #define G_00B800_ORDERED_APPEND_MODE(x) (((x) >> 4) & 0x1)
5496 #define C_00B800_ORDERED_APPEND_MODE 0xFFFFFFEF
5497 #define S_00B800_USE_THREAD_DIMENSIONS(x) (((x) & 0x1) << 5)
5498 #define G_00B800_USE_THREAD_DIMENSIONS(x) (((x) >> 5) & 0x1)
5499 #define C_00B800_USE_THREAD_DIMENSIONS 0xFFFFFFDF
5500 #define S_00B800_ORDER_MODE(x) (((x) & 0x1) << 6)
5501 #define G_00B800_ORDER_MODE(x) (((x) >> 6) & 0x1)
5502 #define C_00B800_ORDER_MODE 0xFFFFFFBF
5503 #define S_00B800_DISPATCH_CACHE_CNTL(x) (((x) & 0x07) << 7)
5504 #define G_00B800_DISPATCH_CACHE_CNTL(x) (((x) >> 7) & 0x07)
5505 #define C_00B800_DISPATCH_CACHE_CNTL 0xFFFFFC7F
5506 #define S_00B800_SCALAR_L1_INV_VOL(x) (((x) & 0x1) << 10)
5507 #define G_00B800_SCALAR_L1_INV_VOL(x) (((x) >> 10) & 0x1)
5508 #define C_00B800_SCALAR_L1_INV_VOL 0xFFFFFBFF
5509 #define S_00B800_VECTOR_L1_INV_VOL(x) (((x) & 0x1) << 11)
5510 #define G_00B800_VECTOR_L1_INV_VOL(x) (((x) >> 11) & 0x1)
5511 #define C_00B800_VECTOR_L1_INV_VOL 0xFFFFF7FF
5512 #define S_00B800_DATA_ATC(x) (((x) & 0x1) << 12)
5513 #define G_00B800_DATA_ATC(x) (((x) >> 12) & 0x1)
5514 #define C_00B800_DATA_ATC 0xFFFFEFFF
5515 #define S_00B800_RESTORE(x) (((x) & 0x1) << 14)
5516 #define G_00B800_RESTORE(x) (((x) >> 14) & 0x1)
5517 #define C_00B800_RESTORE 0xFFFFBFFF
5518 /* */
5519 #define R_00B804_COMPUTE_DIM_X 0x00B804
5520 #define R_00B808_COMPUTE_DIM_Y 0x00B808
5521 #define R_00B80C_COMPUTE_DIM_Z 0x00B80C
5522 #define R_00B810_COMPUTE_START_X 0x00B810
5523 #define R_00B814_COMPUTE_START_Y 0x00B814
5524 #define R_00B818_COMPUTE_START_Z 0x00B818
5525 #define R_00B81C_COMPUTE_NUM_THREAD_X 0x00B81C
5526 #define S_00B81C_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0)
5527 #define G_00B81C_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF)
5528 #define C_00B81C_NUM_THREAD_FULL 0xFFFF0000
5529 #define S_00B81C_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16)
5530 #define G_00B81C_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF)
5531 #define C_00B81C_NUM_THREAD_PARTIAL 0x0000FFFF
5532 #define R_00B820_COMPUTE_NUM_THREAD_Y 0x00B820
5533 #define S_00B820_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0)
5534 #define G_00B820_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF)
5535 #define C_00B820_NUM_THREAD_FULL 0xFFFF0000
5536 #define S_00B820_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16)
5537 #define G_00B820_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF)
5538 #define C_00B820_NUM_THREAD_PARTIAL 0x0000FFFF
5539 #define R_00B824_COMPUTE_NUM_THREAD_Z 0x00B824
5540 #define S_00B824_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0)
5541 #define G_00B824_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF)
5542 #define C_00B824_NUM_THREAD_FULL 0xFFFF0000
5543 #define S_00B824_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16)
5544 #define G_00B824_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF)
5545 #define C_00B824_NUM_THREAD_PARTIAL 0x0000FFFF
5546 #define R_00B82C_COMPUTE_MAX_WAVE_ID 0x00B82C /* moved to 0xCD20 on CIK */
5547 #define S_00B82C_MAX_WAVE_ID(x) (((x) & 0xFFF) << 0)
5548 #define G_00B82C_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF)
5549 #define C_00B82C_MAX_WAVE_ID 0xFFFFF000
5550 /* CIK */
5551 #define R_00B828_COMPUTE_PIPELINESTAT_ENABLE 0x00B828
5552 #define S_00B828_PIPELINESTAT_ENABLE(x) (((x) & 0x1) << 0)
5553 #define G_00B828_PIPELINESTAT_ENABLE(x) (((x) >> 0) & 0x1)
5554 #define C_00B828_PIPELINESTAT_ENABLE 0xFFFFFFFE
5555 #define R_00B82C_COMPUTE_PERFCOUNT_ENABLE 0x00B82C
5556 #define S_00B82C_PERFCOUNT_ENABLE(x) (((x) & 0x1) << 0)
5557 #define G_00B82C_PERFCOUNT_ENABLE(x) (((x) >> 0) & 0x1)
5558 #define C_00B82C_PERFCOUNT_ENABLE 0xFFFFFFFE
5559 /* */
5560 #define R_00B830_COMPUTE_PGM_LO 0x00B830
5561 #define R_00B834_COMPUTE_PGM_HI 0x00B834
5562 #define S_00B834_DATA(x) (((x) & 0xFF) << 0)
5563 #define G_00B834_DATA(x) (((x) >> 0) & 0xFF)
5564 #define C_00B834_DATA 0xFFFFFF00
5565 /* CIK */
5566 #define S_00B834_INST_ATC(x) (((x) & 0x1) << 8)
5567 #define G_00B834_INST_ATC(x) (((x) >> 8) & 0x1)
5568 #define C_00B834_INST_ATC 0xFFFFFEFF
5569 /* */
5570 #define R_00B838_COMPUTE_TBA_LO 0x00B838
5571 #define R_00B83C_COMPUTE_TBA_HI 0x00B83C
5572 #define S_00B83C_DATA(x) (((x) & 0xFF) << 0)
5573 #define G_00B83C_DATA(x) (((x) >> 0) & 0xFF)
5574 #define C_00B83C_DATA 0xFFFFFF00
5575 #define R_00B840_COMPUTE_TMA_LO 0x00B840
5576 #define R_00B844_COMPUTE_TMA_HI 0x00B844
5577 #define S_00B844_DATA(x) (((x) & 0xFF) << 0)
5578 #define G_00B844_DATA(x) (((x) >> 0) & 0xFF)
5579 #define C_00B844_DATA 0xFFFFFF00
5580 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
5581 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
5582 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
5583 #define C_00B848_VGPRS 0xFFFFFFC0
5584 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
5585 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
5586 #define C_00B848_SGPRS 0xFFFFFC3F
5587 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
5588 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
5589 #define C_00B848_PRIORITY 0xFFFFF3FF
5590 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
5591 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
5592 #define C_00B848_FLOAT_MODE 0xFFF00FFF
5593 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
5594 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
5595 #define C_00B848_PRIV 0xFFEFFFFF
5596 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
5597 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
5598 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
5599 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
5600 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
5601 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
5602 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
5603 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
5604 #define C_00B848_IEEE_MODE 0xFF7FFFFF
5605 /* CIK */
5606 #define S_00B848_BULKY(x) (((x) & 0x1) << 24)
5607 #define G_00B848_BULKY(x) (((x) >> 24) & 0x1)
5608 #define C_00B848_BULKY 0xFEFFFFFF
5609 #define S_00B848_CDBG_USER(x) (((x) & 0x1) << 25)
5610 #define G_00B848_CDBG_USER(x) (((x) >> 25) & 0x1)
5611 #define C_00B848_CDBG_USER 0xFDFFFFFF
5612 /* */
5613 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
5614 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
5615 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
5616 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
5617 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
5618 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
5619 #define C_00B84C_USER_SGPR 0xFFFFFFC1
5620 #define S_00B84C_TRAP_PRESENT(x) (((x) & 0x1) << 6)
5621 #define G_00B84C_TRAP_PRESENT(x) (((x) >> 6) & 0x1)
5622 #define C_00B84C_TRAP_PRESENT 0xFFFFFFBF
5623 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
5624 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
5625 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
5626 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
5627 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
5628 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
5629 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
5630 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
5631 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
5632 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
5633 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
5634 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
5635 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
5636 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
5637 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
5638 /* CIK */
5639 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
5640 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
5641 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
5642 /* */
5643 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
5644 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
5645 #define C_00B84C_LDS_SIZE 0xFF007FFF
5646 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
5647 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
5648 #define C_00B84C_EXCP_EN 0x80FFFFFF
5649 #define R_00B850_COMPUTE_VMID 0x00B850
5650 #define S_00B850_DATA(x) (((x) & 0x0F) << 0)
5651 #define G_00B850_DATA(x) (((x) >> 0) & 0x0F)
5652 #define C_00B850_DATA 0xFFFFFFF0
5653 #define R_00B854_COMPUTE_RESOURCE_LIMITS 0x00B854
5654 #define S_00B854_WAVES_PER_SH(x) (((x) & 0x3F) << 0) /* mask is 0x3FF on CIK */
5655 #define G_00B854_WAVES_PER_SH(x) (((x) >> 0) & 0x3F) /* mask is 0x3FF on CIK */
5656 #define C_00B854_WAVES_PER_SH 0xFFFFFFC0 /* mask is 0x3FF on CIK */
5657 #define S_00B854_TG_PER_CU(x) (((x) & 0x0F) << 12)
5658 #define G_00B854_TG_PER_CU(x) (((x) >> 12) & 0x0F)
5659 #define C_00B854_TG_PER_CU 0xFFFF0FFF
5660 #define S_00B854_LOCK_THRESHOLD(x) (((x) & 0x3F) << 16)
5661 #define G_00B854_LOCK_THRESHOLD(x) (((x) >> 16) & 0x3F)
5662 #define C_00B854_LOCK_THRESHOLD 0xFFC0FFFF
5663 #define S_00B854_SIMD_DEST_CNTL(x) (((x) & 0x1) << 22)
5664 #define G_00B854_SIMD_DEST_CNTL(x) (((x) >> 22) & 0x1)
5665 #define C_00B854_SIMD_DEST_CNTL 0xFFBFFFFF
5666 /* CIK */
5667 #define S_00B854_FORCE_SIMD_DIST(x) (((x) & 0x1) << 23)
5668 #define G_00B854_FORCE_SIMD_DIST(x) (((x) >> 23) & 0x1)
5669 #define C_00B854_FORCE_SIMD_DIST 0xFF7FFFFF
5670 #define S_00B854_CU_GROUP_COUNT(x) (((x) & 0x07) << 24)
5671 #define G_00B854_CU_GROUP_COUNT(x) (((x) >> 24) & 0x07)
5672 #define C_00B854_CU_GROUP_COUNT 0xF8FFFFFF
5673 /* */
5674 #define R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 0x00B858
5675 #define S_00B858_SH0_CU_EN(x) (((x) & 0xFFFF) << 0)
5676 #define G_00B858_SH0_CU_EN(x) (((x) >> 0) & 0xFFFF)
5677 #define C_00B858_SH0_CU_EN 0xFFFF0000
5678 #define S_00B858_SH1_CU_EN(x) (((x) & 0xFFFF) << 16)
5679 #define G_00B858_SH1_CU_EN(x) (((x) >> 16) & 0xFFFF)
5680 #define C_00B858_SH1_CU_EN 0x0000FFFF
5681 #define R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1 0x00B85C
5682 #define S_00B85C_SH0_CU_EN(x) (((x) & 0xFFFF) << 0)
5683 #define G_00B85C_SH0_CU_EN(x) (((x) >> 0) & 0xFFFF)
5684 #define C_00B85C_SH0_CU_EN 0xFFFF0000
5685 #define S_00B85C_SH1_CU_EN(x) (((x) & 0xFFFF) << 16)
5686 #define G_00B85C_SH1_CU_EN(x) (((x) >> 16) & 0xFFFF)
5687 #define C_00B85C_SH1_CU_EN 0x0000FFFF
5688 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
5689 #define S_00B860_WAVES(x) (((x) & 0xFFF) << 0)
5690 #define G_00B860_WAVES(x) (((x) >> 0) & 0xFFF)
5691 #define C_00B860_WAVES 0xFFFFF000
5692 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
5693 #define G_00B860_WAVESIZE(x) (((x) >> 12) & 0x1FFF)
5694 #define C_00B860_WAVESIZE 0xFE000FFF
5695 /* CIK */
5696 #define R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2 0x00B864
5697 #define S_00B864_SH0_CU_EN(x) (((x) & 0xFFFF) << 0)
5698 #define G_00B864_SH0_CU_EN(x) (((x) >> 0) & 0xFFFF)
5699 #define C_00B864_SH0_CU_EN 0xFFFF0000
5700 #define S_00B864_SH1_CU_EN(x) (((x) & 0xFFFF) << 16)
5701 #define G_00B864_SH1_CU_EN(x) (((x) >> 16) & 0xFFFF)
5702 #define C_00B864_SH1_CU_EN 0x0000FFFF
5703 #define R_00B868_COMPUTE_STATIC_THREAD_MGMT_SE3 0x00B868
5704 #define S_00B868_SH0_CU_EN(x) (((x) & 0xFFFF) << 0)
5705 #define G_00B868_SH0_CU_EN(x) (((x) >> 0) & 0xFFFF)
5706 #define C_00B868_SH0_CU_EN 0xFFFF0000
5707 #define S_00B868_SH1_CU_EN(x) (((x) & 0xFFFF) << 16)
5708 #define G_00B868_SH1_CU_EN(x) (((x) >> 16) & 0xFFFF)
5709 #define C_00B868_SH1_CU_EN 0x0000FFFF
5710 #define R_00B86C_COMPUTE_RESTART_X 0x00B86C
5711 #define R_00B870_COMPUTE_RESTART_Y 0x00B870
5712 #define R_00B874_COMPUTE_RESTART_Z 0x00B874
5713 #define R_00B87C_COMPUTE_MISC_RESERVED 0x00B87C
5714 #define S_00B87C_SEND_SEID(x) (((x) & 0x03) << 0)
5715 #define G_00B87C_SEND_SEID(x) (((x) >> 0) & 0x03)
5716 #define C_00B87C_SEND_SEID 0xFFFFFFFC
5717 #define S_00B87C_RESERVED2(x) (((x) & 0x1) << 2)
5718 #define G_00B87C_RESERVED2(x) (((x) >> 2) & 0x1)
5719 #define C_00B87C_RESERVED2 0xFFFFFFFB
5720 #define S_00B87C_RESERVED3(x) (((x) & 0x1) << 3)
5721 #define G_00B87C_RESERVED3(x) (((x) >> 3) & 0x1)
5722 #define C_00B87C_RESERVED3 0xFFFFFFF7
5723 #define S_00B87C_RESERVED4(x) (((x) & 0x1) << 4)
5724 #define G_00B87C_RESERVED4(x) (((x) >> 4) & 0x1)
5725 #define C_00B87C_RESERVED4 0xFFFFFFEF
5726 /* VI */
5727 #define S_00B87C_WAVE_ID_BASE(x) (((x) & 0xFFF) << 5)
5728 #define G_00B87C_WAVE_ID_BASE(x) (((x) >> 5) & 0xFFF)
5729 #define C_00B87C_WAVE_ID_BASE 0xFFFE001F
5730 #define R_00B880_COMPUTE_DISPATCH_ID 0x00B880
5731 #define R_00B884_COMPUTE_THREADGROUP_ID 0x00B884
5732 #define R_00B888_COMPUTE_RELAUNCH 0x00B888
5733 #define S_00B888_PAYLOAD(x) (((x) & 0x3FFFFFFF) << 0)
5734 #define G_00B888_PAYLOAD(x) (((x) >> 0) & 0x3FFFFFFF)
5735 #define C_00B888_PAYLOAD 0xC0000000
5736 #define S_00B888_IS_EVENT(x) (((x) & 0x1) << 30)
5737 #define G_00B888_IS_EVENT(x) (((x) >> 30) & 0x1)
5738 #define C_00B888_IS_EVENT 0xBFFFFFFF
5739 #define S_00B888_IS_STATE(x) (((x) & 0x1) << 31)
5740 #define G_00B888_IS_STATE(x) (((x) >> 31) & 0x1)
5741 #define C_00B888_IS_STATE 0x7FFFFFFF
5742 #define R_00B88C_COMPUTE_WAVE_RESTORE_ADDR_LO 0x00B88C
5743 #define R_00B890_COMPUTE_WAVE_RESTORE_ADDR_HI 0x00B890
5744 #define S_00B890_ADDR(x) (((x) & 0xFFFF) << 0)
5745 #define G_00B890_ADDR(x) (((x) >> 0) & 0xFFFF)
5746 #define C_00B890_ADDR 0xFFFF0000
5747 #define R_00B894_COMPUTE_WAVE_RESTORE_CONTROL 0x00B894
5748 #define S_00B894_ATC(x) (((x) & 0x1) << 0)
5749 #define G_00B894_ATC(x) (((x) >> 0) & 0x1)
5750 #define C_00B894_ATC 0xFFFFFFFE
5751 #define S_00B894_MTYPE(x) (((x) & 0x03) << 1)
5752 #define G_00B894_MTYPE(x) (((x) >> 1) & 0x03)
5753 #define C_00B894_MTYPE 0xFFFFFFF9
5754 /* */
5755 /* */
5756 #define R_00B900_COMPUTE_USER_DATA_0 0x00B900
5757 #define R_00B904_COMPUTE_USER_DATA_1 0x00B904
5758 #define R_00B908_COMPUTE_USER_DATA_2 0x00B908
5759 #define R_00B90C_COMPUTE_USER_DATA_3 0x00B90C
5760 #define R_00B910_COMPUTE_USER_DATA_4 0x00B910
5761 #define R_00B914_COMPUTE_USER_DATA_5 0x00B914
5762 #define R_00B918_COMPUTE_USER_DATA_6 0x00B918
5763 #define R_00B91C_COMPUTE_USER_DATA_7 0x00B91C
5764 #define R_00B920_COMPUTE_USER_DATA_8 0x00B920
5765 #define R_00B924_COMPUTE_USER_DATA_9 0x00B924
5766 #define R_00B928_COMPUTE_USER_DATA_10 0x00B928
5767 #define R_00B92C_COMPUTE_USER_DATA_11 0x00B92C
5768 #define R_00B930_COMPUTE_USER_DATA_12 0x00B930
5769 #define R_00B934_COMPUTE_USER_DATA_13 0x00B934
5770 #define R_00B938_COMPUTE_USER_DATA_14 0x00B938
5771 #define R_00B93C_COMPUTE_USER_DATA_15 0x00B93C
5772 #define R_00B9FC_COMPUTE_NOWHERE 0x00B9FC
5773 #define R_028000_DB_RENDER_CONTROL 0x028000
5774 #define S_028000_DEPTH_CLEAR_ENABLE(x) (((x) & 0x1) << 0)
5775 #define G_028000_DEPTH_CLEAR_ENABLE(x) (((x) >> 0) & 0x1)
5776 #define C_028000_DEPTH_CLEAR_ENABLE 0xFFFFFFFE
5777 #define S_028000_STENCIL_CLEAR_ENABLE(x) (((x) & 0x1) << 1)
5778 #define G_028000_STENCIL_CLEAR_ENABLE(x) (((x) >> 1) & 0x1)
5779 #define C_028000_STENCIL_CLEAR_ENABLE 0xFFFFFFFD
5780 #define S_028000_DEPTH_COPY(x) (((x) & 0x1) << 2)
5781 #define G_028000_DEPTH_COPY(x) (((x) >> 2) & 0x1)
5782 #define C_028000_DEPTH_COPY 0xFFFFFFFB
5783 #define S_028000_STENCIL_COPY(x) (((x) & 0x1) << 3)
5784 #define G_028000_STENCIL_COPY(x) (((x) >> 3) & 0x1)
5785 #define C_028000_STENCIL_COPY 0xFFFFFFF7
5786 #define S_028000_RESUMMARIZE_ENABLE(x) (((x) & 0x1) << 4)
5787 #define G_028000_RESUMMARIZE_ENABLE(x) (((x) >> 4) & 0x1)
5788 #define C_028000_RESUMMARIZE_ENABLE 0xFFFFFFEF
5789 #define S_028000_STENCIL_COMPRESS_DISABLE(x) (((x) & 0x1) << 5)
5790 #define G_028000_STENCIL_COMPRESS_DISABLE(x) (((x) >> 5) & 0x1)
5791 #define C_028000_STENCIL_COMPRESS_DISABLE 0xFFFFFFDF
5792 #define S_028000_DEPTH_COMPRESS_DISABLE(x) (((x) & 0x1) << 6)
5793 #define G_028000_DEPTH_COMPRESS_DISABLE(x) (((x) >> 6) & 0x1)
5794 #define C_028000_DEPTH_COMPRESS_DISABLE 0xFFFFFFBF
5795 #define S_028000_COPY_CENTROID(x) (((x) & 0x1) << 7)
5796 #define G_028000_COPY_CENTROID(x) (((x) >> 7) & 0x1)
5797 #define C_028000_COPY_CENTROID 0xFFFFFF7F
5798 #define S_028000_COPY_SAMPLE(x) (((x) & 0x0F) << 8)
5799 #define G_028000_COPY_SAMPLE(x) (((x) >> 8) & 0x0F)
5800 #define C_028000_COPY_SAMPLE 0xFFFFF0FF
5801 /* VI */
5802 #define S_028000_DECOMPRESS_ENABLE(x) (((x) & 0x1) << 12)
5803 #define G_028000_DECOMPRESS_ENABLE(x) (((x) >> 12) & 0x1)
5804 #define C_028000_DECOMPRESS_ENABLE 0xFFFFEFFF
5805 /* */
5806 #define R_028004_DB_COUNT_CONTROL 0x028004
5807 #define S_028004_ZPASS_INCREMENT_DISABLE(x) (((x) & 0x1) << 0)
5808 #define G_028004_ZPASS_INCREMENT_DISABLE(x) (((x) >> 0) & 0x1)
5809 #define C_028004_ZPASS_INCREMENT_DISABLE 0xFFFFFFFE
5810 #define S_028004_PERFECT_ZPASS_COUNTS(x) (((x) & 0x1) << 1)
5811 #define G_028004_PERFECT_ZPASS_COUNTS(x) (((x) >> 1) & 0x1)
5812 #define C_028004_PERFECT_ZPASS_COUNTS 0xFFFFFFFD
5813 #define S_028004_SAMPLE_RATE(x) (((x) & 0x07) << 4)
5814 #define G_028004_SAMPLE_RATE(x) (((x) >> 4) & 0x07)
5815 #define C_028004_SAMPLE_RATE 0xFFFFFF8F
5816 /* CIK */
5817 #define S_028004_ZPASS_ENABLE(x) (((x) & 0x0F) << 8)
5818 #define G_028004_ZPASS_ENABLE(x) (((x) >> 8) & 0x0F)
5819 #define C_028004_ZPASS_ENABLE 0xFFFFF0FF
5820 #define S_028004_ZFAIL_ENABLE(x) (((x) & 0x0F) << 12)
5821 #define G_028004_ZFAIL_ENABLE(x) (((x) >> 12) & 0x0F)
5822 #define C_028004_ZFAIL_ENABLE 0xFFFF0FFF
5823 #define S_028004_SFAIL_ENABLE(x) (((x) & 0x0F) << 16)
5824 #define G_028004_SFAIL_ENABLE(x) (((x) >> 16) & 0x0F)
5825 #define C_028004_SFAIL_ENABLE 0xFFF0FFFF
5826 #define S_028004_DBFAIL_ENABLE(x) (((x) & 0x0F) << 20)
5827 #define G_028004_DBFAIL_ENABLE(x) (((x) >> 20) & 0x0F)
5828 #define C_028004_DBFAIL_ENABLE 0xFF0FFFFF
5829 #define S_028004_SLICE_EVEN_ENABLE(x) (((x) & 0x0F) << 24)
5830 #define G_028004_SLICE_EVEN_ENABLE(x) (((x) >> 24) & 0x0F)
5831 #define C_028004_SLICE_EVEN_ENABLE 0xF0FFFFFF
5832 #define S_028004_SLICE_ODD_ENABLE(x) (((x) & 0x0F) << 28)
5833 #define G_028004_SLICE_ODD_ENABLE(x) (((x) >> 28) & 0x0F)
5834 #define C_028004_SLICE_ODD_ENABLE 0x0FFFFFFF
5835 /* */
5836 #define R_028008_DB_DEPTH_VIEW 0x028008
5837 #define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0)
5838 #define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF)
5839 #define C_028008_SLICE_START 0xFFFFF800
5840 #define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13)
5841 #define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
5842 #define C_028008_SLICE_MAX 0xFF001FFF
5843 #define S_028008_Z_READ_ONLY(x) (((x) & 0x1) << 24)
5844 #define G_028008_Z_READ_ONLY(x) (((x) >> 24) & 0x1)
5845 #define C_028008_Z_READ_ONLY 0xFEFFFFFF
5846 #define S_028008_STENCIL_READ_ONLY(x) (((x) & 0x1) << 25)
5847 #define G_028008_STENCIL_READ_ONLY(x) (((x) >> 25) & 0x1)
5848 #define C_028008_STENCIL_READ_ONLY 0xFDFFFFFF
5849 #define R_02800C_DB_RENDER_OVERRIDE 0x02800C
5850 #define S_02800C_FORCE_HIZ_ENABLE(x) (((x) & 0x03) << 0)
5851 #define G_02800C_FORCE_HIZ_ENABLE(x) (((x) >> 0) & 0x03)
5852 #define C_02800C_FORCE_HIZ_ENABLE 0xFFFFFFFC
5853 #define V_02800C_FORCE_OFF 0x00
5854 #define V_02800C_FORCE_ENABLE 0x01
5855 #define V_02800C_FORCE_DISABLE 0x02
5856 #define V_02800C_FORCE_RESERVED 0x03
5857 #define S_02800C_FORCE_HIS_ENABLE0(x) (((x) & 0x03) << 2)
5858 #define G_02800C_FORCE_HIS_ENABLE0(x) (((x) >> 2) & 0x03)
5859 #define C_02800C_FORCE_HIS_ENABLE0 0xFFFFFFF3
5860 #define V_02800C_FORCE_OFF 0x00
5861 #define V_02800C_FORCE_ENABLE 0x01
5862 #define V_02800C_FORCE_DISABLE 0x02
5863 #define V_02800C_FORCE_RESERVED 0x03
5864 #define S_02800C_FORCE_HIS_ENABLE1(x) (((x) & 0x03) << 4)
5865 #define G_02800C_FORCE_HIS_ENABLE1(x) (((x) >> 4) & 0x03)
5866 #define C_02800C_FORCE_HIS_ENABLE1 0xFFFFFFCF
5867 #define V_02800C_FORCE_OFF 0x00
5868 #define V_02800C_FORCE_ENABLE 0x01
5869 #define V_02800C_FORCE_DISABLE 0x02
5870 #define V_02800C_FORCE_RESERVED 0x03
5871 #define S_02800C_FORCE_SHADER_Z_ORDER(x) (((x) & 0x1) << 6)
5872 #define G_02800C_FORCE_SHADER_Z_ORDER(x) (((x) >> 6) & 0x1)
5873 #define C_02800C_FORCE_SHADER_Z_ORDER 0xFFFFFFBF
5874 #define S_02800C_FAST_Z_DISABLE(x) (((x) & 0x1) << 7)
5875 #define G_02800C_FAST_Z_DISABLE(x) (((x) >> 7) & 0x1)
5876 #define C_02800C_FAST_Z_DISABLE 0xFFFFFF7F
5877 #define S_02800C_FAST_STENCIL_DISABLE(x) (((x) & 0x1) << 8)
5878 #define G_02800C_FAST_STENCIL_DISABLE(x) (((x) >> 8) & 0x1)
5879 #define C_02800C_FAST_STENCIL_DISABLE 0xFFFFFEFF
5880 #define S_02800C_NOOP_CULL_DISABLE(x) (((x) & 0x1) << 9)
5881 #define G_02800C_NOOP_CULL_DISABLE(x) (((x) >> 9) & 0x1)
5882 #define C_02800C_NOOP_CULL_DISABLE 0xFFFFFDFF
5883 #define S_02800C_FORCE_COLOR_KILL(x) (((x) & 0x1) << 10)
5884 #define G_02800C_FORCE_COLOR_KILL(x) (((x) >> 10) & 0x1)
5885 #define C_02800C_FORCE_COLOR_KILL 0xFFFFFBFF
5886 #define S_02800C_FORCE_Z_READ(x) (((x) & 0x1) << 11)
5887 #define G_02800C_FORCE_Z_READ(x) (((x) >> 11) & 0x1)
5888 #define C_02800C_FORCE_Z_READ 0xFFFFF7FF
5889 #define S_02800C_FORCE_STENCIL_READ(x) (((x) & 0x1) << 12)
5890 #define G_02800C_FORCE_STENCIL_READ(x) (((x) >> 12) & 0x1)
5891 #define C_02800C_FORCE_STENCIL_READ 0xFFFFEFFF
5892 #define S_02800C_FORCE_FULL_Z_RANGE(x) (((x) & 0x03) << 13)
5893 #define G_02800C_FORCE_FULL_Z_RANGE(x) (((x) >> 13) & 0x03)
5894 #define C_02800C_FORCE_FULL_Z_RANGE 0xFFFF9FFF
5895 #define V_02800C_FORCE_OFF 0x00
5896 #define V_02800C_FORCE_ENABLE 0x01
5897 #define V_02800C_FORCE_DISABLE 0x02
5898 #define V_02800C_FORCE_RESERVED 0x03
5899 #define S_02800C_FORCE_QC_SMASK_CONFLICT(x) (((x) & 0x1) << 15)
5900 #define G_02800C_FORCE_QC_SMASK_CONFLICT(x) (((x) >> 15) & 0x1)
5901 #define C_02800C_FORCE_QC_SMASK_CONFLICT 0xFFFF7FFF
5902 #define S_02800C_DISABLE_VIEWPORT_CLAMP(x) (((x) & 0x1) << 16)
5903 #define G_02800C_DISABLE_VIEWPORT_CLAMP(x) (((x) >> 16) & 0x1)
5904 #define C_02800C_DISABLE_VIEWPORT_CLAMP 0xFFFEFFFF
5905 #define S_02800C_IGNORE_SC_ZRANGE(x) (((x) & 0x1) << 17)
5906 #define G_02800C_IGNORE_SC_ZRANGE(x) (((x) >> 17) & 0x1)
5907 #define C_02800C_IGNORE_SC_ZRANGE 0xFFFDFFFF
5908 #define S_02800C_DISABLE_FULLY_COVERED(x) (((x) & 0x1) << 18)
5909 #define G_02800C_DISABLE_FULLY_COVERED(x) (((x) >> 18) & 0x1)
5910 #define C_02800C_DISABLE_FULLY_COVERED 0xFFFBFFFF
5911 #define S_02800C_FORCE_Z_LIMIT_SUMM(x) (((x) & 0x03) << 19)
5912 #define G_02800C_FORCE_Z_LIMIT_SUMM(x) (((x) >> 19) & 0x03)
5913 #define C_02800C_FORCE_Z_LIMIT_SUMM 0xFFE7FFFF
5914 #define V_02800C_FORCE_SUMM_OFF 0x00
5915 #define V_02800C_FORCE_SUMM_MINZ 0x01
5916 #define V_02800C_FORCE_SUMM_MAXZ 0x02
5917 #define V_02800C_FORCE_SUMM_BOTH 0x03
5918 #define S_02800C_MAX_TILES_IN_DTT(x) (((x) & 0x1F) << 21)
5919 #define G_02800C_MAX_TILES_IN_DTT(x) (((x) >> 21) & 0x1F)
5920 #define C_02800C_MAX_TILES_IN_DTT 0xFC1FFFFF
5921 #define S_02800C_DISABLE_TILE_RATE_TILES(x) (((x) & 0x1) << 26)
5922 #define G_02800C_DISABLE_TILE_RATE_TILES(x) (((x) >> 26) & 0x1)
5923 #define C_02800C_DISABLE_TILE_RATE_TILES 0xFBFFFFFF
5924 #define S_02800C_FORCE_Z_DIRTY(x) (((x) & 0x1) << 27)
5925 #define G_02800C_FORCE_Z_DIRTY(x) (((x) >> 27) & 0x1)
5926 #define C_02800C_FORCE_Z_DIRTY 0xF7FFFFFF
5927 #define S_02800C_FORCE_STENCIL_DIRTY(x) (((x) & 0x1) << 28)
5928 #define G_02800C_FORCE_STENCIL_DIRTY(x) (((x) >> 28) & 0x1)
5929 #define C_02800C_FORCE_STENCIL_DIRTY 0xEFFFFFFF
5930 #define S_02800C_FORCE_Z_VALID(x) (((x) & 0x1) << 29)
5931 #define G_02800C_FORCE_Z_VALID(x) (((x) >> 29) & 0x1)
5932 #define C_02800C_FORCE_Z_VALID 0xDFFFFFFF
5933 #define S_02800C_FORCE_STENCIL_VALID(x) (((x) & 0x1) << 30)
5934 #define G_02800C_FORCE_STENCIL_VALID(x) (((x) >> 30) & 0x1)
5935 #define C_02800C_FORCE_STENCIL_VALID 0xBFFFFFFF
5936 #define S_02800C_PRESERVE_COMPRESSION(x) (((x) & 0x1) << 31)
5937 #define G_02800C_PRESERVE_COMPRESSION(x) (((x) >> 31) & 0x1)
5938 #define C_02800C_PRESERVE_COMPRESSION 0x7FFFFFFF
5939 #define R_028010_DB_RENDER_OVERRIDE2 0x028010
5940 #define S_028010_PARTIAL_SQUAD_LAUNCH_CONTROL(x) (((x) & 0x03) << 0)
5941 #define G_028010_PARTIAL_SQUAD_LAUNCH_CONTROL(x) (((x) >> 0) & 0x03)
5942 #define C_028010_PARTIAL_SQUAD_LAUNCH_CONTROL 0xFFFFFFFC
5943 #define V_028010_PSLC_AUTO 0x00
5944 #define V_028010_PSLC_ON_HANG_ONLY 0x01
5945 #define V_028010_PSLC_ASAP 0x02
5946 #define V_028010_PSLC_COUNTDOWN 0x03
5947 #define S_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN(x) (((x) & 0x07) << 2)
5948 #define G_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN(x) (((x) >> 2) & 0x07)
5949 #define C_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN 0xFFFFFFE3
5950 #define S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(x) (((x) & 0x1) << 5)
5951 #define G_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(x) (((x) >> 5) & 0x1)
5952 #define C_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION 0xFFFFFFDF
5953 #define S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(x) (((x) & 0x1) << 6)
5954 #define G_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(x) (((x) >> 6) & 0x1)
5955 #define C_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION 0xFFFFFFBF
5956 #define S_028010_DISABLE_COLOR_ON_VALIDATION(x) (((x) & 0x1) << 7)
5957 #define G_028010_DISABLE_COLOR_ON_VALIDATION(x) (((x) >> 7) & 0x1)
5958 #define C_028010_DISABLE_COLOR_ON_VALIDATION 0xFFFFFF7F
5959 #define S_028010_DECOMPRESS_Z_ON_FLUSH(x) (((x) & 0x1) << 8)
5960 #define G_028010_DECOMPRESS_Z_ON_FLUSH(x) (((x) >> 8) & 0x1)
5961 #define C_028010_DECOMPRESS_Z_ON_FLUSH 0xFFFFFEFF
5962 #define S_028010_DISABLE_REG_SNOOP(x) (((x) & 0x1) << 9)
5963 #define G_028010_DISABLE_REG_SNOOP(x) (((x) >> 9) & 0x1)
5964 #define C_028010_DISABLE_REG_SNOOP 0xFFFFFDFF
5965 #define S_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE(x) (((x) & 0x1) << 10)
5966 #define G_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE(x) (((x) >> 10) & 0x1)
5967 #define C_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE 0xFFFFFBFF
5968 /* CIK */
5969 #define S_028010_SEPARATE_HIZS_FUNC_ENABLE(x) (((x) & 0x1) << 11)
5970 #define G_028010_SEPARATE_HIZS_FUNC_ENABLE(x) (((x) >> 11) & 0x1)
5971 #define C_028010_SEPARATE_HIZS_FUNC_ENABLE 0xFFFFF7FF
5972 #define S_028010_HIZ_ZFUNC(x) (((x) & 0x07) << 12)
5973 #define G_028010_HIZ_ZFUNC(x) (((x) >> 12) & 0x07)
5974 #define C_028010_HIZ_ZFUNC 0xFFFF8FFF
5975 #define S_028010_HIS_SFUNC_FF(x) (((x) & 0x07) << 15)
5976 #define G_028010_HIS_SFUNC_FF(x) (((x) >> 15) & 0x07)
5977 #define C_028010_HIS_SFUNC_FF 0xFFFC7FFF
5978 #define S_028010_HIS_SFUNC_BF(x) (((x) & 0x07) << 18)
5979 #define G_028010_HIS_SFUNC_BF(x) (((x) >> 18) & 0x07)
5980 #define C_028010_HIS_SFUNC_BF 0xFFE3FFFF
5981 #define S_028010_PRESERVE_ZRANGE(x) (((x) & 0x1) << 21)
5982 #define G_028010_PRESERVE_ZRANGE(x) (((x) >> 21) & 0x1)
5983 #define C_028010_PRESERVE_ZRANGE 0xFFDFFFFF
5984 #define S_028010_PRESERVE_SRESULTS(x) (((x) & 0x1) << 22)
5985 #define G_028010_PRESERVE_SRESULTS(x) (((x) >> 22) & 0x1)
5986 #define C_028010_PRESERVE_SRESULTS 0xFFBFFFFF
5987 #define S_028010_DISABLE_FAST_PASS(x) (((x) & 0x1) << 23)
5988 #define G_028010_DISABLE_FAST_PASS(x) (((x) >> 23) & 0x1)
5989 #define C_028010_DISABLE_FAST_PASS 0xFF7FFFFF
5990 /* */
5991 #define R_028014_DB_HTILE_DATA_BASE 0x028014
5992 #define R_028020_DB_DEPTH_BOUNDS_MIN 0x028020
5993 #define R_028024_DB_DEPTH_BOUNDS_MAX 0x028024
5994 #define R_028028_DB_STENCIL_CLEAR 0x028028
5995 #define S_028028_CLEAR(x) (((x) & 0xFF) << 0)
5996 #define G_028028_CLEAR(x) (((x) >> 0) & 0xFF)
5997 #define C_028028_CLEAR 0xFFFFFF00
5998 #define R_02802C_DB_DEPTH_CLEAR 0x02802C
5999 #define R_028030_PA_SC_SCREEN_SCISSOR_TL 0x028030
6000 #define S_028030_TL_X(x) (((x) & 0xFFFF) << 0)
6001 #define G_028030_TL_X(x) (((x) >> 0) & 0xFFFF)
6002 #define C_028030_TL_X 0xFFFF0000
6003 #define S_028030_TL_Y(x) (((x) & 0xFFFF) << 16)
6004 #define G_028030_TL_Y(x) (((x) >> 16) & 0xFFFF)
6005 #define C_028030_TL_Y 0x0000FFFF
6006 #define R_028034_PA_SC_SCREEN_SCISSOR_BR 0x028034
6007 #define S_028034_BR_X(x) (((x) & 0xFFFF) << 0)
6008 #define G_028034_BR_X(x) (((x) >> 0) & 0xFFFF)
6009 #define C_028034_BR_X 0xFFFF0000
6010 #define S_028034_BR_Y(x) (((x) & 0xFFFF) << 16)
6011 #define G_028034_BR_Y(x) (((x) >> 16) & 0xFFFF)
6012 #define C_028034_BR_Y 0x0000FFFF
6013 #define R_02803C_DB_DEPTH_INFO 0x02803C
6014 #define S_02803C_ADDR5_SWIZZLE_MASK(x) (((x) & 0x0F) << 0)
6015 #define G_02803C_ADDR5_SWIZZLE_MASK(x) (((x) >> 0) & 0x0F)
6016 #define C_02803C_ADDR5_SWIZZLE_MASK 0xFFFFFFF0
6017 /* CIK */
6018 #define S_02803C_ARRAY_MODE(x) (((x) & 0x0F) << 4)
6019 #define G_02803C_ARRAY_MODE(x) (((x) >> 4) & 0x0F)
6020 #define C_02803C_ARRAY_MODE 0xFFFFFF0F
6021 #define V_02803C_ARRAY_LINEAR_GENERAL 0x00
6022 #define V_02803C_ARRAY_LINEAR_ALIGNED 0x01
6023 #define V_02803C_ARRAY_1D_TILED_THIN1 0x02
6024 #define V_02803C_ARRAY_2D_TILED_THIN1 0x04
6025 #define V_02803C_ARRAY_PRT_TILED_THIN1 0x05
6026 #define V_02803C_ARRAY_PRT_2D_TILED_THIN1 0x06
6027 #define S_02803C_PIPE_CONFIG(x) (((x) & 0x1F) << 8)
6028 #define G_02803C_PIPE_CONFIG(x) (((x) >> 8) & 0x1F)
6029 #define C_02803C_PIPE_CONFIG 0xFFFFE0FF
6030 #define V_02803C_ADDR_SURF_P2 0x00
6031 #define V_02803C_X_ADDR_SURF_P4_8X16 0x04
6032 #define V_02803C_X_ADDR_SURF_P4_16X16 0x05
6033 #define V_02803C_X_ADDR_SURF_P4_16X32 0x06
6034 #define V_02803C_X_ADDR_SURF_P4_32X32 0x07
6035 #define V_02803C_X_ADDR_SURF_P8_16X16_8X16 0x08
6036 #define V_02803C_X_ADDR_SURF_P8_16X32_8X16 0x09
6037 #define V_02803C_X_ADDR_SURF_P8_32X32_8X16 0x0A
6038 #define V_02803C_X_ADDR_SURF_P8_16X32_16X16 0x0B
6039 #define V_02803C_X_ADDR_SURF_P8_32X32_16X16 0x0C
6040 #define V_02803C_X_ADDR_SURF_P8_32X32_16X32 0x0D
6041 #define V_02803C_X_ADDR_SURF_P8_32X64_32X32 0x0E
6042 #define V_02803C_X_ADDR_SURF_P16_32X32_8X16 0x10
6043 #define V_02803C_X_ADDR_SURF_P16_32X32_16X16 0x11
6044 #define S_02803C_BANK_WIDTH(x) (((x) & 0x03) << 13)
6045 #define G_02803C_BANK_WIDTH(x) (((x) >> 13) & 0x03)
6046 #define C_02803C_BANK_WIDTH 0xFFFF9FFF
6047 #define V_02803C_ADDR_SURF_BANK_WIDTH_1 0x00
6048 #define V_02803C_ADDR_SURF_BANK_WIDTH_2 0x01
6049 #define V_02803C_ADDR_SURF_BANK_WIDTH_4 0x02
6050 #define V_02803C_ADDR_SURF_BANK_WIDTH_8 0x03
6051 #define S_02803C_BANK_HEIGHT(x) (((x) & 0x03) << 15)
6052 #define G_02803C_BANK_HEIGHT(x) (((x) >> 15) & 0x03)
6053 #define C_02803C_BANK_HEIGHT 0xFFFE7FFF
6054 #define V_02803C_ADDR_SURF_BANK_HEIGHT_1 0x00
6055 #define V_02803C_ADDR_SURF_BANK_HEIGHT_2 0x01
6056 #define V_02803C_ADDR_SURF_BANK_HEIGHT_4 0x02
6057 #define V_02803C_ADDR_SURF_BANK_HEIGHT_8 0x03
6058 #define S_02803C_MACRO_TILE_ASPECT(x) (((x) & 0x03) << 17)
6059 #define G_02803C_MACRO_TILE_ASPECT(x) (((x) >> 17) & 0x03)
6060 #define C_02803C_MACRO_TILE_ASPECT 0xFFF9FFFF
6061 #define V_02803C_ADDR_SURF_MACRO_ASPECT_1 0x00
6062 #define V_02803C_ADDR_SURF_MACRO_ASPECT_2 0x01
6063 #define V_02803C_ADDR_SURF_MACRO_ASPECT_4 0x02
6064 #define V_02803C_ADDR_SURF_MACRO_ASPECT_8 0x03
6065 #define S_02803C_NUM_BANKS(x) (((x) & 0x03) << 19)
6066 #define G_02803C_NUM_BANKS(x) (((x) >> 19) & 0x03)
6067 #define C_02803C_NUM_BANKS 0xFFE7FFFF
6068 #define V_02803C_ADDR_SURF_2_BANK 0x00
6069 #define V_02803C_ADDR_SURF_4_BANK 0x01
6070 #define V_02803C_ADDR_SURF_8_BANK 0x02
6071 #define V_02803C_ADDR_SURF_16_BANK 0x03
6072 /* */
6073 #define R_028040_DB_Z_INFO 0x028040
6074 #define S_028040_FORMAT(x) (((x) & 0x03) << 0)
6075 #define G_028040_FORMAT(x) (((x) >> 0) & 0x03)
6076 #define C_028040_FORMAT 0xFFFFFFFC
6077 #define V_028040_Z_INVALID 0x00
6078 #define V_028040_Z_16 0x01
6079 #define V_028040_Z_24 0x02 /* deprecated */
6080 #define V_028040_Z_32_FLOAT 0x03
6081 #define S_028040_NUM_SAMPLES(x) (((x) & 0x03) << 2)
6082 #define G_028040_NUM_SAMPLES(x) (((x) >> 2) & 0x03)
6083 #define C_028040_NUM_SAMPLES 0xFFFFFFF3
6084 /* CIK */
6085 #define S_028040_TILE_SPLIT(x) (((x) & 0x07) << 13)
6086 #define G_028040_TILE_SPLIT(x) (((x) >> 13) & 0x07)
6087 #define C_028040_TILE_SPLIT 0xFFFF1FFF
6088 #define V_028040_ADDR_SURF_TILE_SPLIT_64B 0x00
6089 #define V_028040_ADDR_SURF_TILE_SPLIT_128B 0x01
6090 #define V_028040_ADDR_SURF_TILE_SPLIT_256B 0x02
6091 #define V_028040_ADDR_SURF_TILE_SPLIT_512B 0x03
6092 #define V_028040_ADDR_SURF_TILE_SPLIT_1KB 0x04
6093 #define V_028040_ADDR_SURF_TILE_SPLIT_2KB 0x05
6094 #define V_028040_ADDR_SURF_TILE_SPLIT_4KB 0x06
6095 /* */
6096 #define S_028040_TILE_MODE_INDEX(x) (((x) & 0x07) << 20) /* not on CIK */
6097 #define G_028040_TILE_MODE_INDEX(x) (((x) >> 20) & 0x07) /* not on CIK */
6098 #define C_028040_TILE_MODE_INDEX 0xFF8FFFFF /* not on CIK */
6099 /* VI */
6100 #define S_028040_DECOMPRESS_ON_N_ZPLANES(x) (((x) & 0x0F) << 23)
6101 #define G_028040_DECOMPRESS_ON_N_ZPLANES(x) (((x) >> 23) & 0x0F)
6102 #define C_028040_DECOMPRESS_ON_N_ZPLANES 0xF87FFFFF
6103 /* */
6104 #define S_028040_ALLOW_EXPCLEAR(x) (((x) & 0x1) << 27)
6105 #define G_028040_ALLOW_EXPCLEAR(x) (((x) >> 27) & 0x1)
6106 #define C_028040_ALLOW_EXPCLEAR 0xF7FFFFFF
6107 #define S_028040_READ_SIZE(x) (((x) & 0x1) << 28)
6108 #define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1)
6109 #define C_028040_READ_SIZE 0xEFFFFFFF
6110 #define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29)
6111 #define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1)
6112 #define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF
6113 /* VI */
6114 #define S_028040_CLEAR_DISALLOWED(x) (((x) & 0x1) << 30)
6115 #define G_028040_CLEAR_DISALLOWED(x) (((x) >> 30) & 0x1)
6116 #define C_028040_CLEAR_DISALLOWED 0xBFFFFFFF
6117 /* */
6118 #define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
6119 #define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
6120 #define C_028040_ZRANGE_PRECISION 0x7FFFFFFF
6121 #define R_028044_DB_STENCIL_INFO 0x028044
6122 #define S_028044_FORMAT(x) (((x) & 0x1) << 0)
6123 #define G_028044_FORMAT(x) (((x) >> 0) & 0x1)
6124 #define C_028044_FORMAT 0xFFFFFFFE
6125 #define V_028044_STENCIL_INVALID 0x00
6126 #define V_028044_STENCIL_8 0x01
6127 /* CIK */
6128 #define S_028044_TILE_SPLIT(x) (((x) & 0x07) << 13)
6129 #define G_028044_TILE_SPLIT(x) (((x) >> 13) & 0x07)
6130 #define C_028044_TILE_SPLIT 0xFFFF1FFF
6131 #define V_028044_ADDR_SURF_TILE_SPLIT_64B 0x00
6132 #define V_028044_ADDR_SURF_TILE_SPLIT_128B 0x01
6133 #define V_028044_ADDR_SURF_TILE_SPLIT_256B 0x02
6134 #define V_028044_ADDR_SURF_TILE_SPLIT_512B 0x03
6135 #define V_028044_ADDR_SURF_TILE_SPLIT_1KB 0x04
6136 #define V_028044_ADDR_SURF_TILE_SPLIT_2KB 0x05
6137 #define V_028044_ADDR_SURF_TILE_SPLIT_4KB 0x06
6138 /* */
6139 #define S_028044_TILE_MODE_INDEX(x) (((x) & 0x07) << 20) /* not on CIK */
6140 #define G_028044_TILE_MODE_INDEX(x) (((x) >> 20) & 0x07) /* not on CIK */
6141 #define C_028044_TILE_MODE_INDEX 0xFF8FFFFF /* not on CIK */
6142 #define S_028044_ALLOW_EXPCLEAR(x) (((x) & 0x1) << 27)
6143 #define G_028044_ALLOW_EXPCLEAR(x) (((x) >> 27) & 0x1)
6144 #define C_028044_ALLOW_EXPCLEAR 0xF7FFFFFF
6145 #define S_028044_TILE_STENCIL_DISABLE(x) (((x) & 0x1) << 29)
6146 #define G_028044_TILE_STENCIL_DISABLE(x) (((x) >> 29) & 0x1)
6147 #define C_028044_TILE_STENCIL_DISABLE 0xDFFFFFFF
6148 /* VI */
6149 #define S_028044_CLEAR_DISALLOWED(x) (((x) & 0x1) << 30)
6150 #define G_028044_CLEAR_DISALLOWED(x) (((x) >> 30) & 0x1)
6151 #define C_028044_CLEAR_DISALLOWED 0xBFFFFFFF
6152 /* */
6153 #define R_028048_DB_Z_READ_BASE 0x028048
6154 #define R_02804C_DB_STENCIL_READ_BASE 0x02804C
6155 #define R_028050_DB_Z_WRITE_BASE 0x028050
6156 #define R_028054_DB_STENCIL_WRITE_BASE 0x028054
6157 #define R_028058_DB_DEPTH_SIZE 0x028058
6158 #define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0)
6159 #define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF)
6160 #define C_028058_PITCH_TILE_MAX 0xFFFFF800
6161 #define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11)
6162 #define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF)
6163 #define C_028058_HEIGHT_TILE_MAX 0xFFC007FF
6164 #define R_02805C_DB_DEPTH_SLICE 0x02805C
6165 #define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0)
6166 #define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF)
6167 #define C_02805C_SLICE_TILE_MAX 0xFFC00000
6168 #define R_028080_TA_BC_BASE_ADDR 0x028080
6169 /* CIK */
6170 #define R_028084_TA_BC_BASE_ADDR_HI 0x028084
6171 #define S_028084_ADDRESS(x) (((x) & 0xFF) << 0)
6172 #define G_028084_ADDRESS(x) (((x) >> 0) & 0xFF)
6173 #define C_028084_ADDRESS 0xFFFFFF00
6174 #define R_0281E8_COHER_DEST_BASE_HI_0 0x0281E8
6175 #define R_0281EC_COHER_DEST_BASE_HI_1 0x0281EC
6176 #define R_0281F0_COHER_DEST_BASE_HI_2 0x0281F0
6177 #define R_0281F4_COHER_DEST_BASE_HI_3 0x0281F4
6178 /* */
6179 #define R_0281F8_COHER_DEST_BASE_2 0x0281F8
6180 #define R_0281FC_COHER_DEST_BASE_3 0x0281FC
6181 #define R_028200_PA_SC_WINDOW_OFFSET 0x028200
6182 #define S_028200_WINDOW_X_OFFSET(x) (((x) & 0xFFFF) << 0)
6183 #define G_028200_WINDOW_X_OFFSET(x) (((x) >> 0) & 0xFFFF)
6184 #define C_028200_WINDOW_X_OFFSET 0xFFFF0000
6185 #define S_028200_WINDOW_Y_OFFSET(x) (((x) & 0xFFFF) << 16)
6186 #define G_028200_WINDOW_Y_OFFSET(x) (((x) >> 16) & 0xFFFF)
6187 #define C_028200_WINDOW_Y_OFFSET 0x0000FFFF
6188 #define R_028204_PA_SC_WINDOW_SCISSOR_TL 0x028204
6189 #define S_028204_TL_X(x) (((x) & 0x7FFF) << 0)
6190 #define G_028204_TL_X(x) (((x) >> 0) & 0x7FFF)
6191 #define C_028204_TL_X 0xFFFF8000
6192 #define S_028204_TL_Y(x) (((x) & 0x7FFF) << 16)
6193 #define G_028204_TL_Y(x) (((x) >> 16) & 0x7FFF)
6194 #define C_028204_TL_Y 0x8000FFFF
6195 #define S_028204_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31)
6196 #define G_028204_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1)
6197 #define C_028204_WINDOW_OFFSET_DISABLE 0x7FFFFFFF
6198 #define R_028208_PA_SC_WINDOW_SCISSOR_BR 0x028208
6199 #define S_028208_BR_X(x) (((x) & 0x7FFF) << 0)
6200 #define G_028208_BR_X(x) (((x) >> 0) & 0x7FFF)
6201 #define C_028208_BR_X 0xFFFF8000
6202 #define S_028208_BR_Y(x) (((x) & 0x7FFF) << 16)
6203 #define G_028208_BR_Y(x) (((x) >> 16) & 0x7FFF)
6204 #define C_028208_BR_Y 0x8000FFFF
6205 #define R_02820C_PA_SC_CLIPRECT_RULE 0x02820C
6206 #define S_02820C_CLIP_RULE(x) (((x) & 0xFFFF) << 0)
6207 #define G_02820C_CLIP_RULE(x) (((x) >> 0) & 0xFFFF)
6208 #define C_02820C_CLIP_RULE 0xFFFF0000
6209 #define R_028210_PA_SC_CLIPRECT_0_TL 0x028210
6210 #define S_028210_TL_X(x) (((x) & 0x7FFF) << 0)
6211 #define G_028210_TL_X(x) (((x) >> 0) & 0x7FFF)
6212 #define C_028210_TL_X 0xFFFF8000
6213 #define S_028210_TL_Y(x) (((x) & 0x7FFF) << 16)
6214 #define G_028210_TL_Y(x) (((x) >> 16) & 0x7FFF)
6215 #define C_028210_TL_Y 0x8000FFFF
6216 #define R_028214_PA_SC_CLIPRECT_0_BR 0x028214
6217 #define S_028214_BR_X(x) (((x) & 0x7FFF) << 0)
6218 #define G_028214_BR_X(x) (((x) >> 0) & 0x7FFF)
6219 #define C_028214_BR_X 0xFFFF8000
6220 #define S_028214_BR_Y(x) (((x) & 0x7FFF) << 16)
6221 #define G_028214_BR_Y(x) (((x) >> 16) & 0x7FFF)
6222 #define C_028214_BR_Y 0x8000FFFF
6223 #define R_028218_PA_SC_CLIPRECT_1_TL 0x028218
6224 #define R_02821C_PA_SC_CLIPRECT_1_BR 0x02821C
6225 #define R_028220_PA_SC_CLIPRECT_2_TL 0x028220
6226 #define R_028224_PA_SC_CLIPRECT_2_BR 0x028224
6227 #define R_028228_PA_SC_CLIPRECT_3_TL 0x028228
6228 #define R_02822C_PA_SC_CLIPRECT_3_BR 0x02822C
6229 #define R_028230_PA_SC_EDGERULE 0x028230
6230 #define S_028230_ER_TRI(x) (((x) & 0x0F) << 0)
6231 #define G_028230_ER_TRI(x) (((x) >> 0) & 0x0F)
6232 #define C_028230_ER_TRI 0xFFFFFFF0
6233 #define S_028230_ER_POINT(x) (((x) & 0x0F) << 4)
6234 #define G_028230_ER_POINT(x) (((x) >> 4) & 0x0F)
6235 #define C_028230_ER_POINT 0xFFFFFF0F
6236 #define S_028230_ER_RECT(x) (((x) & 0x0F) << 8)
6237 #define G_028230_ER_RECT(x) (((x) >> 8) & 0x0F)
6238 #define C_028230_ER_RECT 0xFFFFF0FF
6239 #define S_028230_ER_LINE_LR(x) (((x) & 0x3F) << 12)
6240 #define G_028230_ER_LINE_LR(x) (((x) >> 12) & 0x3F)
6241 #define C_028230_ER_LINE_LR 0xFFFC0FFF
6242 #define S_028230_ER_LINE_RL(x) (((x) & 0x3F) << 18)
6243 #define G_028230_ER_LINE_RL(x) (((x) >> 18) & 0x3F)
6244 #define C_028230_ER_LINE_RL 0xFF03FFFF
6245 #define S_028230_ER_LINE_TB(x) (((x) & 0x0F) << 24)
6246 #define G_028230_ER_LINE_TB(x) (((x) >> 24) & 0x0F)
6247 #define C_028230_ER_LINE_TB 0xF0FFFFFF
6248 #define S_028230_ER_LINE_BT(x) (((x) & 0x0F) << 28)
6249 #define G_028230_ER_LINE_BT(x) (((x) >> 28) & 0x0F)
6250 #define C_028230_ER_LINE_BT 0x0FFFFFFF
6251 #define R_028234_PA_SU_HARDWARE_SCREEN_OFFSET 0x028234
6252 #define S_028234_HW_SCREEN_OFFSET_X(x) (((x) & 0x1FF) << 0)
6253 #define G_028234_HW_SCREEN_OFFSET_X(x) (((x) >> 0) & 0x1FF)
6254 #define C_028234_HW_SCREEN_OFFSET_X 0xFFFFFE00
6255 #define S_028234_HW_SCREEN_OFFSET_Y(x) (((x) & 0x1FF) << 16)
6256 #define G_028234_HW_SCREEN_OFFSET_Y(x) (((x) >> 16) & 0x1FF)
6257 #define C_028234_HW_SCREEN_OFFSET_Y 0xFE00FFFF
6258 #define R_028238_CB_TARGET_MASK 0x028238
6259 #define S_028238_TARGET0_ENABLE(x) (((x) & 0x0F) << 0)
6260 #define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0x0F)
6261 #define C_028238_TARGET0_ENABLE 0xFFFFFFF0
6262 #define S_028238_TARGET1_ENABLE(x) (((x) & 0x0F) << 4)
6263 #define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0x0F)
6264 #define C_028238_TARGET1_ENABLE 0xFFFFFF0F
6265 #define S_028238_TARGET2_ENABLE(x) (((x) & 0x0F) << 8)
6266 #define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0x0F)
6267 #define C_028238_TARGET2_ENABLE 0xFFFFF0FF
6268 #define S_028238_TARGET3_ENABLE(x) (((x) & 0x0F) << 12)
6269 #define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0x0F)
6270 #define C_028238_TARGET3_ENABLE 0xFFFF0FFF
6271 #define S_028238_TARGET4_ENABLE(x) (((x) & 0x0F) << 16)
6272 #define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0x0F)
6273 #define C_028238_TARGET4_ENABLE 0xFFF0FFFF
6274 #define S_028238_TARGET5_ENABLE(x) (((x) & 0x0F) << 20)
6275 #define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0x0F)
6276 #define C_028238_TARGET5_ENABLE 0xFF0FFFFF
6277 #define S_028238_TARGET6_ENABLE(x) (((x) & 0x0F) << 24)
6278 #define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0x0F)
6279 #define C_028238_TARGET6_ENABLE 0xF0FFFFFF
6280 #define S_028238_TARGET7_ENABLE(x) (((x) & 0x0F) << 28)
6281 #define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0x0F)
6282 #define C_028238_TARGET7_ENABLE 0x0FFFFFFF
6283 #define R_02823C_CB_SHADER_MASK 0x02823C
6284 #define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0x0F) << 0)
6285 #define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0x0F)
6286 #define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0
6287 #define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0x0F) << 4)
6288 #define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0x0F)
6289 #define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F
6290 #define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0x0F) << 8)
6291 #define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0x0F)
6292 #define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF
6293 #define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0x0F) << 12)
6294 #define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0x0F)
6295 #define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF
6296 #define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0x0F) << 16)
6297 #define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0x0F)
6298 #define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF
6299 #define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0x0F) << 20)
6300 #define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0x0F)
6301 #define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF
6302 #define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0x0F) << 24)
6303 #define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0x0F)
6304 #define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF
6305 #define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0x0F) << 28)
6306 #define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0x0F)
6307 #define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF
6308 #define R_028240_PA_SC_GENERIC_SCISSOR_TL 0x028240
6309 #define S_028240_TL_X(x) (((x) & 0x7FFF) << 0)
6310 #define G_028240_TL_X(x) (((x) >> 0) & 0x7FFF)
6311 #define C_028240_TL_X 0xFFFF8000
6312 #define S_028240_TL_Y(x) (((x) & 0x7FFF) << 16)
6313 #define G_028240_TL_Y(x) (((x) >> 16) & 0x7FFF)
6314 #define C_028240_TL_Y 0x8000FFFF
6315 #define S_028240_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31)
6316 #define G_028240_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1)
6317 #define C_028240_WINDOW_OFFSET_DISABLE 0x7FFFFFFF
6318 #define R_028244_PA_SC_GENERIC_SCISSOR_BR 0x028244
6319 #define S_028244_BR_X(x) (((x) & 0x7FFF) << 0)
6320 #define G_028244_BR_X(x) (((x) >> 0) & 0x7FFF)
6321 #define C_028244_BR_X 0xFFFF8000
6322 #define S_028244_BR_Y(x) (((x) & 0x7FFF) << 16)
6323 #define G_028244_BR_Y(x) (((x) >> 16) & 0x7FFF)
6324 #define C_028244_BR_Y 0x8000FFFF
6325 #define R_028248_COHER_DEST_BASE_0 0x028248
6326 #define R_02824C_COHER_DEST_BASE_1 0x02824C
6327 #define R_028250_PA_SC_VPORT_SCISSOR_0_TL 0x028250
6328 #define S_028250_TL_X(x) (((x) & 0x7FFF) << 0)
6329 #define G_028250_TL_X(x) (((x) >> 0) & 0x7FFF)
6330 #define C_028250_TL_X 0xFFFF8000
6331 #define S_028250_TL_Y(x) (((x) & 0x7FFF) << 16)
6332 #define G_028250_TL_Y(x) (((x) >> 16) & 0x7FFF)
6333 #define C_028250_TL_Y 0x8000FFFF
6334 #define S_028250_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31)
6335 #define G_028250_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1)
6336 #define C_028250_WINDOW_OFFSET_DISABLE 0x7FFFFFFF
6337 #define R_028254_PA_SC_VPORT_SCISSOR_0_BR 0x028254
6338 #define S_028254_BR_X(x) (((x) & 0x7FFF) << 0)
6339 #define G_028254_BR_X(x) (((x) >> 0) & 0x7FFF)
6340 #define C_028254_BR_X 0xFFFF8000
6341 #define S_028254_BR_Y(x) (((x) & 0x7FFF) << 16)
6342 #define G_028254_BR_Y(x) (((x) >> 16) & 0x7FFF)
6343 #define C_028254_BR_Y 0x8000FFFF
6344 #define R_028258_PA_SC_VPORT_SCISSOR_1_TL 0x028258
6345 #define R_02825C_PA_SC_VPORT_SCISSOR_1_BR 0x02825C
6346 #define R_028260_PA_SC_VPORT_SCISSOR_2_TL 0x028260
6347 #define R_028264_PA_SC_VPORT_SCISSOR_2_BR 0x028264
6348 #define R_028268_PA_SC_VPORT_SCISSOR_3_TL 0x028268
6349 #define R_02826C_PA_SC_VPORT_SCISSOR_3_BR 0x02826C
6350 #define R_028270_PA_SC_VPORT_SCISSOR_4_TL 0x028270
6351 #define R_028274_PA_SC_VPORT_SCISSOR_4_BR 0x028274
6352 #define R_028278_PA_SC_VPORT_SCISSOR_5_TL 0x028278
6353 #define R_02827C_PA_SC_VPORT_SCISSOR_5_BR 0x02827C
6354 #define R_028280_PA_SC_VPORT_SCISSOR_6_TL 0x028280
6355 #define R_028284_PA_SC_VPORT_SCISSOR_6_BR 0x028284
6356 #define R_028288_PA_SC_VPORT_SCISSOR_7_TL 0x028288
6357 #define R_02828C_PA_SC_VPORT_SCISSOR_7_BR 0x02828C
6358 #define R_028290_PA_SC_VPORT_SCISSOR_8_TL 0x028290
6359 #define R_028294_PA_SC_VPORT_SCISSOR_8_BR 0x028294
6360 #define R_028298_PA_SC_VPORT_SCISSOR_9_TL 0x028298
6361 #define R_02829C_PA_SC_VPORT_SCISSOR_9_BR 0x02829C
6362 #define R_0282A0_PA_SC_VPORT_SCISSOR_10_TL 0x0282A0
6363 #define R_0282A4_PA_SC_VPORT_SCISSOR_10_BR 0x0282A4
6364 #define R_0282A8_PA_SC_VPORT_SCISSOR_11_TL 0x0282A8
6365 #define R_0282AC_PA_SC_VPORT_SCISSOR_11_BR 0x0282AC
6366 #define R_0282B0_PA_SC_VPORT_SCISSOR_12_TL 0x0282B0
6367 #define R_0282B4_PA_SC_VPORT_SCISSOR_12_BR 0x0282B4
6368 #define R_0282B8_PA_SC_VPORT_SCISSOR_13_TL 0x0282B8
6369 #define R_0282BC_PA_SC_VPORT_SCISSOR_13_BR 0x0282BC
6370 #define R_0282C0_PA_SC_VPORT_SCISSOR_14_TL 0x0282C0
6371 #define R_0282C4_PA_SC_VPORT_SCISSOR_14_BR 0x0282C4
6372 #define R_0282C8_PA_SC_VPORT_SCISSOR_15_TL 0x0282C8
6373 #define R_0282CC_PA_SC_VPORT_SCISSOR_15_BR 0x0282CC
6374 #define R_0282D0_PA_SC_VPORT_ZMIN_0 0x0282D0
6375 #define R_0282D4_PA_SC_VPORT_ZMAX_0 0x0282D4
6376 #define R_0282D8_PA_SC_VPORT_ZMIN_1 0x0282D8
6377 #define R_0282DC_PA_SC_VPORT_ZMAX_1 0x0282DC
6378 #define R_0282E0_PA_SC_VPORT_ZMIN_2 0x0282E0
6379 #define R_0282E4_PA_SC_VPORT_ZMAX_2 0x0282E4
6380 #define R_0282E8_PA_SC_VPORT_ZMIN_3 0x0282E8
6381 #define R_0282EC_PA_SC_VPORT_ZMAX_3 0x0282EC
6382 #define R_0282F0_PA_SC_VPORT_ZMIN_4 0x0282F0
6383 #define R_0282F4_PA_SC_VPORT_ZMAX_4 0x0282F4
6384 #define R_0282F8_PA_SC_VPORT_ZMIN_5 0x0282F8
6385 #define R_0282FC_PA_SC_VPORT_ZMAX_5 0x0282FC
6386 #define R_028300_PA_SC_VPORT_ZMIN_6 0x028300
6387 #define R_028304_PA_SC_VPORT_ZMAX_6 0x028304
6388 #define R_028308_PA_SC_VPORT_ZMIN_7 0x028308
6389 #define R_02830C_PA_SC_VPORT_ZMAX_7 0x02830C
6390 #define R_028310_PA_SC_VPORT_ZMIN_8 0x028310
6391 #define R_028314_PA_SC_VPORT_ZMAX_8 0x028314
6392 #define R_028318_PA_SC_VPORT_ZMIN_9 0x028318
6393 #define R_02831C_PA_SC_VPORT_ZMAX_9 0x02831C
6394 #define R_028320_PA_SC_VPORT_ZMIN_10 0x028320
6395 #define R_028324_PA_SC_VPORT_ZMAX_10 0x028324
6396 #define R_028328_PA_SC_VPORT_ZMIN_11 0x028328
6397 #define R_02832C_PA_SC_VPORT_ZMAX_11 0x02832C
6398 #define R_028330_PA_SC_VPORT_ZMIN_12 0x028330
6399 #define R_028334_PA_SC_VPORT_ZMAX_12 0x028334
6400 #define R_028338_PA_SC_VPORT_ZMIN_13 0x028338
6401 #define R_02833C_PA_SC_VPORT_ZMAX_13 0x02833C
6402 #define R_028340_PA_SC_VPORT_ZMIN_14 0x028340
6403 #define R_028344_PA_SC_VPORT_ZMAX_14 0x028344
6404 #define R_028348_PA_SC_VPORT_ZMIN_15 0x028348
6405 #define R_02834C_PA_SC_VPORT_ZMAX_15 0x02834C
6406 #define R_028350_PA_SC_RASTER_CONFIG 0x028350
6407 #define S_028350_RB_MAP_PKR0(x) (((x) & 0x03) << 0)
6408 #define G_028350_RB_MAP_PKR0(x) (((x) >> 0) & 0x03)
6409 #define C_028350_RB_MAP_PKR0 0xFFFFFFFC
6410 #define V_028350_RASTER_CONFIG_RB_MAP_0 0x00
6411 #define V_028350_RASTER_CONFIG_RB_MAP_1 0x01
6412 #define V_028350_RASTER_CONFIG_RB_MAP_2 0x02
6413 #define V_028350_RASTER_CONFIG_RB_MAP_3 0x03
6414 #define S_028350_RB_MAP_PKR1(x) (((x) & 0x03) << 2)
6415 #define G_028350_RB_MAP_PKR1(x) (((x) >> 2) & 0x03)
6416 #define C_028350_RB_MAP_PKR1 0xFFFFFFF3
6417 #define V_028350_RASTER_CONFIG_RB_MAP_0 0x00
6418 #define V_028350_RASTER_CONFIG_RB_MAP_1 0x01
6419 #define V_028350_RASTER_CONFIG_RB_MAP_2 0x02
6420 #define V_028350_RASTER_CONFIG_RB_MAP_3 0x03
6421 #define S_028350_RB_XSEL2(x) (((x) & 0x03) << 4)
6422 #define G_028350_RB_XSEL2(x) (((x) >> 4) & 0x03)
6423 #define C_028350_RB_XSEL2 0xFFFFFFCF
6424 #define V_028350_RASTER_CONFIG_RB_XSEL2_0 0x00
6425 #define V_028350_RASTER_CONFIG_RB_XSEL2_1 0x01
6426 #define V_028350_RASTER_CONFIG_RB_XSEL2_2 0x02
6427 #define V_028350_RASTER_CONFIG_RB_XSEL2_3 0x03
6428 #define S_028350_RB_XSEL(x) (((x) & 0x1) << 6)
6429 #define G_028350_RB_XSEL(x) (((x) >> 6) & 0x1)
6430 #define C_028350_RB_XSEL 0xFFFFFFBF
6431 #define S_028350_RB_YSEL(x) (((x) & 0x1) << 7)
6432 #define G_028350_RB_YSEL(x) (((x) >> 7) & 0x1)
6433 #define C_028350_RB_YSEL 0xFFFFFF7F
6434 #define S_028350_PKR_MAP(x) (((x) & 0x03) << 8)
6435 #define G_028350_PKR_MAP(x) (((x) >> 8) & 0x03)
6436 #define C_028350_PKR_MAP 0xFFFFFCFF
6437 #define V_028350_RASTER_CONFIG_PKR_MAP_0 0x00
6438 #define V_028350_RASTER_CONFIG_PKR_MAP_1 0x01
6439 #define V_028350_RASTER_CONFIG_PKR_MAP_2 0x02
6440 #define V_028350_RASTER_CONFIG_PKR_MAP_3 0x03
6441 #define S_028350_PKR_XSEL(x) (((x) & 0x03) << 10)
6442 #define G_028350_PKR_XSEL(x) (((x) >> 10) & 0x03)
6443 #define C_028350_PKR_XSEL 0xFFFFF3FF
6444 #define V_028350_RASTER_CONFIG_PKR_XSEL_0 0x00
6445 #define V_028350_RASTER_CONFIG_PKR_XSEL_1 0x01
6446 #define V_028350_RASTER_CONFIG_PKR_XSEL_2 0x02
6447 #define V_028350_RASTER_CONFIG_PKR_XSEL_3 0x03
6448 #define S_028350_PKR_YSEL(x) (((x) & 0x03) << 12)
6449 #define G_028350_PKR_YSEL(x) (((x) >> 12) & 0x03)
6450 #define C_028350_PKR_YSEL 0xFFFFCFFF
6451 #define V_028350_RASTER_CONFIG_PKR_YSEL_0 0x00
6452 #define V_028350_RASTER_CONFIG_PKR_YSEL_1 0x01
6453 #define V_028350_RASTER_CONFIG_PKR_YSEL_2 0x02
6454 #define V_028350_RASTER_CONFIG_PKR_YSEL_3 0x03
6455 #define S_028350_PKR_XSEL2(x) (((x) & 0x03) << 14)
6456 #define G_028350_PKR_XSEL2(x) (((x) >> 14) & 0x03)
6457 #define C_028350_PKR_XSEL2 0xFFFF3FFF
6458 #define V_028350_RASTER_CONFIG_PKR_XSEL2_0 0x00
6459 #define V_028350_RASTER_CONFIG_PKR_XSEL2_1 0x01
6460 #define V_028350_RASTER_CONFIG_PKR_XSEL2_2 0x02
6461 #define V_028350_RASTER_CONFIG_PKR_XSEL2_3 0x03
6462 #define S_028350_SC_MAP(x) (((x) & 0x03) << 16)
6463 #define G_028350_SC_MAP(x) (((x) >> 16) & 0x03)
6464 #define C_028350_SC_MAP 0xFFFCFFFF
6465 #define V_028350_RASTER_CONFIG_SC_MAP_0 0x00
6466 #define V_028350_RASTER_CONFIG_SC_MAP_1 0x01
6467 #define V_028350_RASTER_CONFIG_SC_MAP_2 0x02
6468 #define V_028350_RASTER_CONFIG_SC_MAP_3 0x03
6469 #define S_028350_SC_XSEL(x) (((x) & 0x03) << 18)
6470 #define G_028350_SC_XSEL(x) (((x) >> 18) & 0x03)
6471 #define C_028350_SC_XSEL 0xFFF3FFFF
6472 #define V_028350_RASTER_CONFIG_SC_XSEL_8_WIDE_TILE 0x00
6473 #define V_028350_RASTER_CONFIG_SC_XSEL_16_WIDE_TILE 0x01
6474 #define V_028350_RASTER_CONFIG_SC_XSEL_32_WIDE_TILE 0x02
6475 #define V_028350_RASTER_CONFIG_SC_XSEL_64_WIDE_TILE 0x03
6476 #define S_028350_SC_YSEL(x) (((x) & 0x03) << 20)
6477 #define G_028350_SC_YSEL(x) (((x) >> 20) & 0x03)
6478 #define C_028350_SC_YSEL 0xFFCFFFFF
6479 #define V_028350_RASTER_CONFIG_SC_YSEL_8_WIDE_TILE 0x00
6480 #define V_028350_RASTER_CONFIG_SC_YSEL_16_WIDE_TILE 0x01
6481 #define V_028350_RASTER_CONFIG_SC_YSEL_32_WIDE_TILE 0x02
6482 #define V_028350_RASTER_CONFIG_SC_YSEL_64_WIDE_TILE 0x03
6483 #define S_028350_SE_MAP(x) (((x) & 0x03) << 24)
6484 #define G_028350_SE_MAP(x) (((x) >> 24) & 0x03)
6485 #define C_028350_SE_MAP 0xFCFFFFFF
6486 #define V_028350_RASTER_CONFIG_SE_MAP_0 0x00
6487 #define V_028350_RASTER_CONFIG_SE_MAP_1 0x01
6488 #define V_028350_RASTER_CONFIG_SE_MAP_2 0x02
6489 #define V_028350_RASTER_CONFIG_SE_MAP_3 0x03
6490 #define S_028350_SE_XSEL(x) (((x) & 0x03) << 26)
6491 #define G_028350_SE_XSEL(x) (((x) >> 26) & 0x03)
6492 #define C_028350_SE_XSEL 0xF3FFFFFF
6493 #define V_028350_RASTER_CONFIG_SE_XSEL_8_WIDE_TILE 0x00
6494 #define V_028350_RASTER_CONFIG_SE_XSEL_16_WIDE_TILE 0x01
6495 #define V_028350_RASTER_CONFIG_SE_XSEL_32_WIDE_TILE 0x02
6496 #define V_028350_RASTER_CONFIG_SE_XSEL_64_WIDE_TILE 0x03
6497 #define S_028350_SE_YSEL(x) (((x) & 0x03) << 28)
6498 #define G_028350_SE_YSEL(x) (((x) >> 28) & 0x03)
6499 #define C_028350_SE_YSEL 0xCFFFFFFF
6500 #define V_028350_RASTER_CONFIG_SE_YSEL_8_WIDE_TILE 0x00
6501 #define V_028350_RASTER_CONFIG_SE_YSEL_16_WIDE_TILE 0x01
6502 #define V_028350_RASTER_CONFIG_SE_YSEL_32_WIDE_TILE 0x02
6503 #define V_028350_RASTER_CONFIG_SE_YSEL_64_WIDE_TILE 0x03
6504 /* CIK */
6505 #define R_028354_PA_SC_RASTER_CONFIG_1 0x028354
6506 #define S_028354_SE_PAIR_MAP(x) (((x) & 0x03) << 0)
6507 #define G_028354_SE_PAIR_MAP(x) (((x) >> 0) & 0x03)
6508 #define C_028354_SE_PAIR_MAP 0xFFFFFFFC
6509 #define V_028354_RASTER_CONFIG_SE_PAIR_MAP_0 0x00
6510 #define V_028354_RASTER_CONFIG_SE_PAIR_MAP_1 0x01
6511 #define V_028354_RASTER_CONFIG_SE_PAIR_MAP_2 0x02
6512 #define V_028354_RASTER_CONFIG_SE_PAIR_MAP_3 0x03
6513 #define S_028354_SE_PAIR_XSEL(x) (((x) & 0x03) << 2)
6514 #define G_028354_SE_PAIR_XSEL(x) (((x) >> 2) & 0x03)
6515 #define C_028354_SE_PAIR_XSEL 0xFFFFFFF3
6516 #define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE 0x00
6517 #define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE 0x01
6518 #define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE 0x02
6519 #define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE 0x03
6520 #define S_028354_SE_PAIR_YSEL(x) (((x) & 0x03) << 4)
6521 #define G_028354_SE_PAIR_YSEL(x) (((x) >> 4) & 0x03)
6522 #define C_028354_SE_PAIR_YSEL 0xFFFFFFCF
6523 #define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE 0x00
6524 #define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE 0x01
6525 #define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE 0x02
6526 #define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE 0x03
6527 #define R_028358_PA_SC_SCREEN_EXTENT_CONTROL 0x028358
6528 #define S_028358_SLICE_EVEN_ENABLE(x) (((x) & 0x03) << 0)
6529 #define G_028358_SLICE_EVEN_ENABLE(x) (((x) >> 0) & 0x03)
6530 #define C_028358_SLICE_EVEN_ENABLE 0xFFFFFFFC
6531 #define S_028358_SLICE_ODD_ENABLE(x) (((x) & 0x03) << 2)
6532 #define G_028358_SLICE_ODD_ENABLE(x) (((x) >> 2) & 0x03)
6533 #define C_028358_SLICE_ODD_ENABLE 0xFFFFFFF3
6534 /* */
6535 #define R_028400_VGT_MAX_VTX_INDX 0x028400
6536 #define R_028404_VGT_MIN_VTX_INDX 0x028404
6537 #define R_028408_VGT_INDX_OFFSET 0x028408
6538 #define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX 0x02840C
6539 #define R_028414_CB_BLEND_RED 0x028414
6540 #define R_028418_CB_BLEND_GREEN 0x028418
6541 #define R_02841C_CB_BLEND_BLUE 0x02841C
6542 #define R_028420_CB_BLEND_ALPHA 0x028420
6543 /* VI */
6544 #define R_028424_CB_DCC_CONTROL 0x028424
6545 #define S_028424_OVERWRITE_COMBINER_DISABLE(x) (((x) & 0x1) << 0)
6546 #define G_028424_OVERWRITE_COMBINER_DISABLE(x) (((x) >> 0) & 0x1)
6547 #define C_028424_OVERWRITE_COMBINER_DISABLE 0xFFFFFFFE
6548 #define S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(x) (((x) & 0x1) << 1)
6549 #define G_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(x) (((x) >> 1) & 0x1)
6550 #define C_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE 0xFFFFFFFD
6551 #define S_028424_OVERWRITE_COMBINER_WATERMARK(x) (((x) & 0x1F) << 2)
6552 #define G_028424_OVERWRITE_COMBINER_WATERMARK(x) (((x) >> 2) & 0x1F)
6553 #define C_028424_OVERWRITE_COMBINER_WATERMARK 0xFFFFFF83
6554 /* */
6555 #define R_02842C_DB_STENCIL_CONTROL 0x02842C
6556 #define S_02842C_STENCILFAIL(x) (((x) & 0x0F) << 0)
6557 #define G_02842C_STENCILFAIL(x) (((x) >> 0) & 0x0F)
6558 #define C_02842C_STENCILFAIL 0xFFFFFFF0
6559 #define V_02842C_STENCIL_KEEP 0x00
6560 #define V_02842C_STENCIL_ZERO 0x01
6561 #define V_02842C_STENCIL_ONES 0x02
6562 #define V_02842C_STENCIL_REPLACE_TEST 0x03
6563 #define V_02842C_STENCIL_REPLACE_OP 0x04
6564 #define V_02842C_STENCIL_ADD_CLAMP 0x05
6565 #define V_02842C_STENCIL_SUB_CLAMP 0x06
6566 #define V_02842C_STENCIL_INVERT 0x07
6567 #define V_02842C_STENCIL_ADD_WRAP 0x08
6568 #define V_02842C_STENCIL_SUB_WRAP 0x09
6569 #define V_02842C_STENCIL_AND 0x0A
6570 #define V_02842C_STENCIL_OR 0x0B
6571 #define V_02842C_STENCIL_XOR 0x0C
6572 #define V_02842C_STENCIL_NAND 0x0D
6573 #define V_02842C_STENCIL_NOR 0x0E
6574 #define V_02842C_STENCIL_XNOR 0x0F
6575 #define S_02842C_STENCILZPASS(x) (((x) & 0x0F) << 4)
6576 #define G_02842C_STENCILZPASS(x) (((x) >> 4) & 0x0F)
6577 #define C_02842C_STENCILZPASS 0xFFFFFF0F
6578 #define V_02842C_STENCIL_KEEP 0x00
6579 #define V_02842C_STENCIL_ZERO 0x01
6580 #define V_02842C_STENCIL_ONES 0x02
6581 #define V_02842C_STENCIL_REPLACE_TEST 0x03
6582 #define V_02842C_STENCIL_REPLACE_OP 0x04
6583 #define V_02842C_STENCIL_ADD_CLAMP 0x05
6584 #define V_02842C_STENCIL_SUB_CLAMP 0x06
6585 #define V_02842C_STENCIL_INVERT 0x07
6586 #define V_02842C_STENCIL_ADD_WRAP 0x08
6587 #define V_02842C_STENCIL_SUB_WRAP 0x09
6588 #define V_02842C_STENCIL_AND 0x0A
6589 #define V_02842C_STENCIL_OR 0x0B
6590 #define V_02842C_STENCIL_XOR 0x0C
6591 #define V_02842C_STENCIL_NAND 0x0D
6592 #define V_02842C_STENCIL_NOR 0x0E
6593 #define V_02842C_STENCIL_XNOR 0x0F
6594 #define S_02842C_STENCILZFAIL(x) (((x) & 0x0F) << 8)
6595 #define G_02842C_STENCILZFAIL(x) (((x) >> 8) & 0x0F)
6596 #define C_02842C_STENCILZFAIL 0xFFFFF0FF
6597 #define V_02842C_STENCIL_KEEP 0x00
6598 #define V_02842C_STENCIL_ZERO 0x01
6599 #define V_02842C_STENCIL_ONES 0x02
6600 #define V_02842C_STENCIL_REPLACE_TEST 0x03
6601 #define V_02842C_STENCIL_REPLACE_OP 0x04
6602 #define V_02842C_STENCIL_ADD_CLAMP 0x05
6603 #define V_02842C_STENCIL_SUB_CLAMP 0x06
6604 #define V_02842C_STENCIL_INVERT 0x07
6605 #define V_02842C_STENCIL_ADD_WRAP 0x08
6606 #define V_02842C_STENCIL_SUB_WRAP 0x09
6607 #define V_02842C_STENCIL_AND 0x0A
6608 #define V_02842C_STENCIL_OR 0x0B
6609 #define V_02842C_STENCIL_XOR 0x0C
6610 #define V_02842C_STENCIL_NAND 0x0D
6611 #define V_02842C_STENCIL_NOR 0x0E
6612 #define V_02842C_STENCIL_XNOR 0x0F
6613 #define S_02842C_STENCILFAIL_BF(x) (((x) & 0x0F) << 12)
6614 #define G_02842C_STENCILFAIL_BF(x) (((x) >> 12) & 0x0F)
6615 #define C_02842C_STENCILFAIL_BF 0xFFFF0FFF
6616 #define V_02842C_STENCIL_KEEP 0x00
6617 #define V_02842C_STENCIL_ZERO 0x01
6618 #define V_02842C_STENCIL_ONES 0x02
6619 #define V_02842C_STENCIL_REPLACE_TEST 0x03
6620 #define V_02842C_STENCIL_REPLACE_OP 0x04
6621 #define V_02842C_STENCIL_ADD_CLAMP 0x05
6622 #define V_02842C_STENCIL_SUB_CLAMP 0x06
6623 #define V_02842C_STENCIL_INVERT 0x07
6624 #define V_02842C_STENCIL_ADD_WRAP 0x08
6625 #define V_02842C_STENCIL_SUB_WRAP 0x09
6626 #define V_02842C_STENCIL_AND 0x0A
6627 #define V_02842C_STENCIL_OR 0x0B
6628 #define V_02842C_STENCIL_XOR 0x0C
6629 #define V_02842C_STENCIL_NAND 0x0D
6630 #define V_02842C_STENCIL_NOR 0x0E
6631 #define V_02842C_STENCIL_XNOR 0x0F
6632 #define S_02842C_STENCILZPASS_BF(x) (((x) & 0x0F) << 16)
6633 #define G_02842C_STENCILZPASS_BF(x) (((x) >> 16) & 0x0F)
6634 #define C_02842C_STENCILZPASS_BF 0xFFF0FFFF
6635 #define V_02842C_STENCIL_KEEP 0x00
6636 #define V_02842C_STENCIL_ZERO 0x01
6637 #define V_02842C_STENCIL_ONES 0x02
6638 #define V_02842C_STENCIL_REPLACE_TEST 0x03
6639 #define V_02842C_STENCIL_REPLACE_OP 0x04
6640 #define V_02842C_STENCIL_ADD_CLAMP 0x05
6641 #define V_02842C_STENCIL_SUB_CLAMP 0x06
6642 #define V_02842C_STENCIL_INVERT 0x07
6643 #define V_02842C_STENCIL_ADD_WRAP 0x08
6644 #define V_02842C_STENCIL_SUB_WRAP 0x09
6645 #define V_02842C_STENCIL_AND 0x0A
6646 #define V_02842C_STENCIL_OR 0x0B
6647 #define V_02842C_STENCIL_XOR 0x0C
6648 #define V_02842C_STENCIL_NAND 0x0D
6649 #define V_02842C_STENCIL_NOR 0x0E
6650 #define V_02842C_STENCIL_XNOR 0x0F
6651 #define S_02842C_STENCILZFAIL_BF(x) (((x) & 0x0F) << 20)
6652 #define G_02842C_STENCILZFAIL_BF(x) (((x) >> 20) & 0x0F)
6653 #define C_02842C_STENCILZFAIL_BF 0xFF0FFFFF
6654 #define V_02842C_STENCIL_KEEP 0x00
6655 #define V_02842C_STENCIL_ZERO 0x01
6656 #define V_02842C_STENCIL_ONES 0x02
6657 #define V_02842C_STENCIL_REPLACE_TEST 0x03
6658 #define V_02842C_STENCIL_REPLACE_OP 0x04
6659 #define V_02842C_STENCIL_ADD_CLAMP 0x05
6660 #define V_02842C_STENCIL_SUB_CLAMP 0x06
6661 #define V_02842C_STENCIL_INVERT 0x07
6662 #define V_02842C_STENCIL_ADD_WRAP 0x08
6663 #define V_02842C_STENCIL_SUB_WRAP 0x09
6664 #define V_02842C_STENCIL_AND 0x0A
6665 #define V_02842C_STENCIL_OR 0x0B
6666 #define V_02842C_STENCIL_XOR 0x0C
6667 #define V_02842C_STENCIL_NAND 0x0D
6668 #define V_02842C_STENCIL_NOR 0x0E
6669 #define V_02842C_STENCIL_XNOR 0x0F
6670 #define R_028430_DB_STENCILREFMASK 0x028430
6671 #define S_028430_STENCILTESTVAL(x) (((x) & 0xFF) << 0)
6672 #define G_028430_STENCILTESTVAL(x) (((x) >> 0) & 0xFF)
6673 #define C_028430_STENCILTESTVAL 0xFFFFFF00
6674 #define S_028430_STENCILMASK(x) (((x) & 0xFF) << 8)
6675 #define G_028430_STENCILMASK(x) (((x) >> 8) & 0xFF)
6676 #define C_028430_STENCILMASK 0xFFFF00FF
6677 #define S_028430_STENCILWRITEMASK(x) (((x) & 0xFF) << 16)
6678 #define G_028430_STENCILWRITEMASK(x) (((x) >> 16) & 0xFF)
6679 #define C_028430_STENCILWRITEMASK 0xFF00FFFF
6680 #define S_028430_STENCILOPVAL(x) (((x) & 0xFF) << 24)
6681 #define G_028430_STENCILOPVAL(x) (((x) >> 24) & 0xFF)
6682 #define C_028430_STENCILOPVAL 0x00FFFFFF
6683 #define R_028434_DB_STENCILREFMASK_BF 0x028434
6684 #define S_028434_STENCILTESTVAL_BF(x) (((x) & 0xFF) << 0)
6685 #define G_028434_STENCILTESTVAL_BF(x) (((x) >> 0) & 0xFF)
6686 #define C_028434_STENCILTESTVAL_BF 0xFFFFFF00
6687 #define S_028434_STENCILMASK_BF(x) (((x) & 0xFF) << 8)
6688 #define G_028434_STENCILMASK_BF(x) (((x) >> 8) & 0xFF)
6689 #define C_028434_STENCILMASK_BF 0xFFFF00FF
6690 #define S_028434_STENCILWRITEMASK_BF(x) (((x) & 0xFF) << 16)
6691 #define G_028434_STENCILWRITEMASK_BF(x) (((x) >> 16) & 0xFF)
6692 #define C_028434_STENCILWRITEMASK_BF 0xFF00FFFF
6693 #define S_028434_STENCILOPVAL_BF(x) (((x) & 0xFF) << 24)
6694 #define G_028434_STENCILOPVAL_BF(x) (((x) >> 24) & 0xFF)
6695 #define C_028434_STENCILOPVAL_BF 0x00FFFFFF
6696 #define R_02843C_PA_CL_VPORT_XSCALE 0x02843C
6697 #define R_028440_PA_CL_VPORT_XOFFSET 0x028440
6698 #define R_028444_PA_CL_VPORT_YSCALE 0x028444
6699 #define R_028448_PA_CL_VPORT_YOFFSET 0x028448
6700 #define R_02844C_PA_CL_VPORT_ZSCALE 0x02844C
6701 #define R_028450_PA_CL_VPORT_ZOFFSET 0x028450
6702 #define R_028454_PA_CL_VPORT_XSCALE_1 0x028454
6703 #define R_028458_PA_CL_VPORT_XOFFSET_1 0x028458
6704 #define R_02845C_PA_CL_VPORT_YSCALE_1 0x02845C
6705 #define R_028460_PA_CL_VPORT_YOFFSET_1 0x028460
6706 #define R_028464_PA_CL_VPORT_ZSCALE_1 0x028464
6707 #define R_028468_PA_CL_VPORT_ZOFFSET_1 0x028468
6708 #define R_02846C_PA_CL_VPORT_XSCALE_2 0x02846C
6709 #define R_028470_PA_CL_VPORT_XOFFSET_2 0x028470
6710 #define R_028474_PA_CL_VPORT_YSCALE_2 0x028474
6711 #define R_028478_PA_CL_VPORT_YOFFSET_2 0x028478
6712 #define R_02847C_PA_CL_VPORT_ZSCALE_2 0x02847C
6713 #define R_028480_PA_CL_VPORT_ZOFFSET_2 0x028480
6714 #define R_028484_PA_CL_VPORT_XSCALE_3 0x028484
6715 #define R_028488_PA_CL_VPORT_XOFFSET_3 0x028488
6716 #define R_02848C_PA_CL_VPORT_YSCALE_3 0x02848C
6717 #define R_028490_PA_CL_VPORT_YOFFSET_3 0x028490
6718 #define R_028494_PA_CL_VPORT_ZSCALE_3 0x028494
6719 #define R_028498_PA_CL_VPORT_ZOFFSET_3 0x028498
6720 #define R_02849C_PA_CL_VPORT_XSCALE_4 0x02849C
6721 #define R_0284A0_PA_CL_VPORT_XOFFSET_4 0x0284A0
6722 #define R_0284A4_PA_CL_VPORT_YSCALE_4 0x0284A4
6723 #define R_0284A8_PA_CL_VPORT_YOFFSET_4 0x0284A8
6724 #define R_0284AC_PA_CL_VPORT_ZSCALE_4 0x0284AC
6725 #define R_0284B0_PA_CL_VPORT_ZOFFSET_4 0x0284B0
6726 #define R_0284B4_PA_CL_VPORT_XSCALE_5 0x0284B4
6727 #define R_0284B8_PA_CL_VPORT_XOFFSET_5 0x0284B8
6728 #define R_0284BC_PA_CL_VPORT_YSCALE_5 0x0284BC
6729 #define R_0284C0_PA_CL_VPORT_YOFFSET_5 0x0284C0
6730 #define R_0284C4_PA_CL_VPORT_ZSCALE_5 0x0284C4
6731 #define R_0284C8_PA_CL_VPORT_ZOFFSET_5 0x0284C8
6732 #define R_0284CC_PA_CL_VPORT_XSCALE_6 0x0284CC
6733 #define R_0284D0_PA_CL_VPORT_XOFFSET_6 0x0284D0
6734 #define R_0284D4_PA_CL_VPORT_YSCALE_6 0x0284D4
6735 #define R_0284D8_PA_CL_VPORT_YOFFSET_6 0x0284D8
6736 #define R_0284DC_PA_CL_VPORT_ZSCALE_6 0x0284DC
6737 #define R_0284E0_PA_CL_VPORT_ZOFFSET_6 0x0284E0
6738 #define R_0284E4_PA_CL_VPORT_XSCALE_7 0x0284E4
6739 #define R_0284E8_PA_CL_VPORT_XOFFSET_7 0x0284E8
6740 #define R_0284EC_PA_CL_VPORT_YSCALE_7 0x0284EC
6741 #define R_0284F0_PA_CL_VPORT_YOFFSET_7 0x0284F0
6742 #define R_0284F4_PA_CL_VPORT_ZSCALE_7 0x0284F4
6743 #define R_0284F8_PA_CL_VPORT_ZOFFSET_7 0x0284F8
6744 #define R_0284FC_PA_CL_VPORT_XSCALE_8 0x0284FC
6745 #define R_028500_PA_CL_VPORT_XOFFSET_8 0x028500
6746 #define R_028504_PA_CL_VPORT_YSCALE_8 0x028504
6747 #define R_028508_PA_CL_VPORT_YOFFSET_8 0x028508
6748 #define R_02850C_PA_CL_VPORT_ZSCALE_8 0x02850C
6749 #define R_028510_PA_CL_VPORT_ZOFFSET_8 0x028510
6750 #define R_028514_PA_CL_VPORT_XSCALE_9 0x028514
6751 #define R_028518_PA_CL_VPORT_XOFFSET_9 0x028518
6752 #define R_02851C_PA_CL_VPORT_YSCALE_9 0x02851C
6753 #define R_028520_PA_CL_VPORT_YOFFSET_9 0x028520
6754 #define R_028524_PA_CL_VPORT_ZSCALE_9 0x028524
6755 #define R_028528_PA_CL_VPORT_ZOFFSET_9 0x028528
6756 #define R_02852C_PA_CL_VPORT_XSCALE_10 0x02852C
6757 #define R_028530_PA_CL_VPORT_XOFFSET_10 0x028530
6758 #define R_028534_PA_CL_VPORT_YSCALE_10 0x028534
6759 #define R_028538_PA_CL_VPORT_YOFFSET_10 0x028538
6760 #define R_02853C_PA_CL_VPORT_ZSCALE_10 0x02853C
6761 #define R_028540_PA_CL_VPORT_ZOFFSET_10 0x028540
6762 #define R_028544_PA_CL_VPORT_XSCALE_11 0x028544
6763 #define R_028548_PA_CL_VPORT_XOFFSET_11 0x028548
6764 #define R_02854C_PA_CL_VPORT_YSCALE_11 0x02854C
6765 #define R_028550_PA_CL_VPORT_YOFFSET_11 0x028550
6766 #define R_028554_PA_CL_VPORT_ZSCALE_11 0x028554
6767 #define R_028558_PA_CL_VPORT_ZOFFSET_11 0x028558
6768 #define R_02855C_PA_CL_VPORT_XSCALE_12 0x02855C
6769 #define R_028560_PA_CL_VPORT_XOFFSET_12 0x028560
6770 #define R_028564_PA_CL_VPORT_YSCALE_12 0x028564
6771 #define R_028568_PA_CL_VPORT_YOFFSET_12 0x028568
6772 #define R_02856C_PA_CL_VPORT_ZSCALE_12 0x02856C
6773 #define R_028570_PA_CL_VPORT_ZOFFSET_12 0x028570
6774 #define R_028574_PA_CL_VPORT_XSCALE_13 0x028574
6775 #define R_028578_PA_CL_VPORT_XOFFSET_13 0x028578
6776 #define R_02857C_PA_CL_VPORT_YSCALE_13 0x02857C
6777 #define R_028580_PA_CL_VPORT_YOFFSET_13 0x028580
6778 #define R_028584_PA_CL_VPORT_ZSCALE_13 0x028584
6779 #define R_028588_PA_CL_VPORT_ZOFFSET_13 0x028588
6780 #define R_02858C_PA_CL_VPORT_XSCALE_14 0x02858C
6781 #define R_028590_PA_CL_VPORT_XOFFSET_14 0x028590
6782 #define R_028594_PA_CL_VPORT_YSCALE_14 0x028594
6783 #define R_028598_PA_CL_VPORT_YOFFSET_14 0x028598
6784 #define R_02859C_PA_CL_VPORT_ZSCALE_14 0x02859C
6785 #define R_0285A0_PA_CL_VPORT_ZOFFSET_14 0x0285A0
6786 #define R_0285A4_PA_CL_VPORT_XSCALE_15 0x0285A4
6787 #define R_0285A8_PA_CL_VPORT_XOFFSET_15 0x0285A8
6788 #define R_0285AC_PA_CL_VPORT_YSCALE_15 0x0285AC
6789 #define R_0285B0_PA_CL_VPORT_YOFFSET_15 0x0285B0
6790 #define R_0285B4_PA_CL_VPORT_ZSCALE_15 0x0285B4
6791 #define R_0285B8_PA_CL_VPORT_ZOFFSET_15 0x0285B8
6792 #define R_0285BC_PA_CL_UCP_0_X 0x0285BC
6793 #define R_0285C0_PA_CL_UCP_0_Y 0x0285C0
6794 #define R_0285C4_PA_CL_UCP_0_Z 0x0285C4
6795 #define R_0285C8_PA_CL_UCP_0_W 0x0285C8
6796 #define R_0285CC_PA_CL_UCP_1_X 0x0285CC
6797 #define R_0285D0_PA_CL_UCP_1_Y 0x0285D0
6798 #define R_0285D4_PA_CL_UCP_1_Z 0x0285D4
6799 #define R_0285D8_PA_CL_UCP_1_W 0x0285D8
6800 #define R_0285DC_PA_CL_UCP_2_X 0x0285DC
6801 #define R_0285E0_PA_CL_UCP_2_Y 0x0285E0
6802 #define R_0285E4_PA_CL_UCP_2_Z 0x0285E4
6803 #define R_0285E8_PA_CL_UCP_2_W 0x0285E8
6804 #define R_0285EC_PA_CL_UCP_3_X 0x0285EC
6805 #define R_0285F0_PA_CL_UCP_3_Y 0x0285F0
6806 #define R_0285F4_PA_CL_UCP_3_Z 0x0285F4
6807 #define R_0285F8_PA_CL_UCP_3_W 0x0285F8
6808 #define R_0285FC_PA_CL_UCP_4_X 0x0285FC
6809 #define R_028600_PA_CL_UCP_4_Y 0x028600
6810 #define R_028604_PA_CL_UCP_4_Z 0x028604
6811 #define R_028608_PA_CL_UCP_4_W 0x028608
6812 #define R_02860C_PA_CL_UCP_5_X 0x02860C
6813 #define R_028610_PA_CL_UCP_5_Y 0x028610
6814 #define R_028614_PA_CL_UCP_5_Z 0x028614
6815 #define R_028618_PA_CL_UCP_5_W 0x028618
6816 #define R_028644_SPI_PS_INPUT_CNTL_0 0x028644
6817 #define S_028644_OFFSET(x) (((x) & 0x3F) << 0)
6818 #define G_028644_OFFSET(x) (((x) >> 0) & 0x3F)
6819 #define C_028644_OFFSET 0xFFFFFFC0
6820 #define S_028644_DEFAULT_VAL(x) (((x) & 0x03) << 8)
6821 #define G_028644_DEFAULT_VAL(x) (((x) >> 8) & 0x03)
6822 #define C_028644_DEFAULT_VAL 0xFFFFFCFF
6823 #define V_028644_X_0_0F 0x00
6824 #define S_028644_FLAT_SHADE(x) (((x) & 0x1) << 10)
6825 #define G_028644_FLAT_SHADE(x) (((x) >> 10) & 0x1)
6826 #define C_028644_FLAT_SHADE 0xFFFFFBFF
6827 #define S_028644_CYL_WRAP(x) (((x) & 0x0F) << 13)
6828 #define G_028644_CYL_WRAP(x) (((x) >> 13) & 0x0F)
6829 #define C_028644_CYL_WRAP 0xFFFE1FFF
6830 #define S_028644_PT_SPRITE_TEX(x) (((x) & 0x1) << 17)
6831 #define G_028644_PT_SPRITE_TEX(x) (((x) >> 17) & 0x1)
6832 #define C_028644_PT_SPRITE_TEX 0xFFFDFFFF
6833 /* CIK */
6834 #define S_028644_DUP(x) (((x) & 0x1) << 18)
6835 #define G_028644_DUP(x) (((x) >> 18) & 0x1)
6836 #define C_028644_DUP 0xFFFBFFFF
6837 /* */
6838 /* VI */
6839 #define S_028644_FP16_INTERP_MODE(x) (((x) & 0x1) << 19)
6840 #define G_028644_FP16_INTERP_MODE(x) (((x) >> 19) & 0x1)
6841 #define C_028644_FP16_INTERP_MODE 0xFFF7FFFF
6842 #define S_028644_USE_DEFAULT_ATTR1(x) (((x) & 0x1) << 20)
6843 #define G_028644_USE_DEFAULT_ATTR1(x) (((x) >> 20) & 0x1)
6844 #define C_028644_USE_DEFAULT_ATTR1 0xFFEFFFFF
6845 #define S_028644_DEFAULT_VAL_ATTR1(x) (((x) & 0x03) << 21)
6846 #define G_028644_DEFAULT_VAL_ATTR1(x) (((x) >> 21) & 0x03)
6847 #define C_028644_DEFAULT_VAL_ATTR1 0xFF9FFFFF
6848 #define S_028644_PT_SPRITE_TEX_ATTR1(x) (((x) & 0x1) << 23)
6849 #define G_028644_PT_SPRITE_TEX_ATTR1(x) (((x) >> 23) & 0x1)
6850 #define C_028644_PT_SPRITE_TEX_ATTR1 0xFF7FFFFF
6851 #define S_028644_ATTR0_VALID(x) (((x) & 0x1) << 24)
6852 #define G_028644_ATTR0_VALID(x) (((x) >> 24) & 0x1)
6853 #define C_028644_ATTR0_VALID 0xFEFFFFFF
6854 #define S_028644_ATTR1_VALID(x) (((x) & 0x1) << 25)
6855 #define G_028644_ATTR1_VALID(x) (((x) >> 25) & 0x1)
6856 #define C_028644_ATTR1_VALID 0xFDFFFFFF
6857 /* */
6858 #define R_028648_SPI_PS_INPUT_CNTL_1 0x028648
6859 #define R_02864C_SPI_PS_INPUT_CNTL_2 0x02864C
6860 #define R_028650_SPI_PS_INPUT_CNTL_3 0x028650
6861 #define R_028654_SPI_PS_INPUT_CNTL_4 0x028654
6862 #define R_028658_SPI_PS_INPUT_CNTL_5 0x028658
6863 #define R_02865C_SPI_PS_INPUT_CNTL_6 0x02865C
6864 #define R_028660_SPI_PS_INPUT_CNTL_7 0x028660
6865 #define R_028664_SPI_PS_INPUT_CNTL_8 0x028664
6866 #define R_028668_SPI_PS_INPUT_CNTL_9 0x028668
6867 #define R_02866C_SPI_PS_INPUT_CNTL_10 0x02866C
6868 #define R_028670_SPI_PS_INPUT_CNTL_11 0x028670
6869 #define R_028674_SPI_PS_INPUT_CNTL_12 0x028674
6870 #define R_028678_SPI_PS_INPUT_CNTL_13 0x028678
6871 #define R_02867C_SPI_PS_INPUT_CNTL_14 0x02867C
6872 #define R_028680_SPI_PS_INPUT_CNTL_15 0x028680
6873 #define R_028684_SPI_PS_INPUT_CNTL_16 0x028684
6874 #define R_028688_SPI_PS_INPUT_CNTL_17 0x028688
6875 #define R_02868C_SPI_PS_INPUT_CNTL_18 0x02868C
6876 #define R_028690_SPI_PS_INPUT_CNTL_19 0x028690
6877 #define R_028694_SPI_PS_INPUT_CNTL_20 0x028694
6878 #define R_028698_SPI_PS_INPUT_CNTL_21 0x028698
6879 #define R_02869C_SPI_PS_INPUT_CNTL_22 0x02869C
6880 #define R_0286A0_SPI_PS_INPUT_CNTL_23 0x0286A0
6881 #define R_0286A4_SPI_PS_INPUT_CNTL_24 0x0286A4
6882 #define R_0286A8_SPI_PS_INPUT_CNTL_25 0x0286A8
6883 #define R_0286AC_SPI_PS_INPUT_CNTL_26 0x0286AC
6884 #define R_0286B0_SPI_PS_INPUT_CNTL_27 0x0286B0
6885 #define R_0286B4_SPI_PS_INPUT_CNTL_28 0x0286B4
6886 #define R_0286B8_SPI_PS_INPUT_CNTL_29 0x0286B8
6887 #define R_0286BC_SPI_PS_INPUT_CNTL_30 0x0286BC
6888 #define R_0286C0_SPI_PS_INPUT_CNTL_31 0x0286C0
6889 #define R_0286C4_SPI_VS_OUT_CONFIG 0x0286C4
6890 #define S_0286C4_VS_EXPORT_COUNT(x) (((x) & 0x1F) << 1)
6891 #define G_0286C4_VS_EXPORT_COUNT(x) (((x) >> 1) & 0x1F)
6892 #define C_0286C4_VS_EXPORT_COUNT 0xFFFFFFC1
6893 #define S_0286C4_VS_HALF_PACK(x) (((x) & 0x1) << 6)
6894 #define G_0286C4_VS_HALF_PACK(x) (((x) >> 6) & 0x1)
6895 #define C_0286C4_VS_HALF_PACK 0xFFFFFFBF
6896 #define S_0286C4_VS_EXPORTS_FOG(x) (((x) & 0x1) << 7) /* not on CIK */
6897 #define G_0286C4_VS_EXPORTS_FOG(x) (((x) >> 7) & 0x1) /* not on CIK */
6898 #define C_0286C4_VS_EXPORTS_FOG 0xFFFFFF7F /* not on CIK */
6899 #define S_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) & 0x1F) << 8) /* not on CIK */
6900 #define G_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) >> 8) & 0x1F) /* not on CIK */
6901 #define C_0286C4_VS_OUT_FOG_VEC_ADDR 0xFFFFE0FF /* not on CIK */
6902 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
6903 #define S_0286CC_PERSP_SAMPLE_ENA(x) (((x) & 0x1) << 0)
6904 #define G_0286CC_PERSP_SAMPLE_ENA(x) (((x) >> 0) & 0x1)
6905 #define C_0286CC_PERSP_SAMPLE_ENA 0xFFFFFFFE
6906 #define S_0286CC_PERSP_CENTER_ENA(x) (((x) & 0x1) << 1)
6907 #define G_0286CC_PERSP_CENTER_ENA(x) (((x) >> 1) & 0x1)
6908 #define C_0286CC_PERSP_CENTER_ENA 0xFFFFFFFD
6909 #define S_0286CC_PERSP_CENTROID_ENA(x) (((x) & 0x1) << 2)
6910 #define G_0286CC_PERSP_CENTROID_ENA(x) (((x) >> 2) & 0x1)
6911 #define C_0286CC_PERSP_CENTROID_ENA 0xFFFFFFFB
6912 #define S_0286CC_PERSP_PULL_MODEL_ENA(x) (((x) & 0x1) << 3)
6913 #define G_0286CC_PERSP_PULL_MODEL_ENA(x) (((x) >> 3) & 0x1)
6914 #define C_0286CC_PERSP_PULL_MODEL_ENA 0xFFFFFFF7
6915 #define S_0286CC_LINEAR_SAMPLE_ENA(x) (((x) & 0x1) << 4)
6916 #define G_0286CC_LINEAR_SAMPLE_ENA(x) (((x) >> 4) & 0x1)
6917 #define C_0286CC_LINEAR_SAMPLE_ENA 0xFFFFFFEF
6918 #define S_0286CC_LINEAR_CENTER_ENA(x) (((x) & 0x1) << 5)
6919 #define G_0286CC_LINEAR_CENTER_ENA(x) (((x) >> 5) & 0x1)
6920 #define C_0286CC_LINEAR_CENTER_ENA 0xFFFFFFDF
6921 #define S_0286CC_LINEAR_CENTROID_ENA(x) (((x) & 0x1) << 6)
6922 #define G_0286CC_LINEAR_CENTROID_ENA(x) (((x) >> 6) & 0x1)
6923 #define C_0286CC_LINEAR_CENTROID_ENA 0xFFFFFFBF
6924 #define S_0286CC_LINE_STIPPLE_TEX_ENA(x) (((x) & 0x1) << 7)
6925 #define G_0286CC_LINE_STIPPLE_TEX_ENA(x) (((x) >> 7) & 0x1)
6926 #define C_0286CC_LINE_STIPPLE_TEX_ENA 0xFFFFFF7F
6927 #define S_0286CC_POS_X_FLOAT_ENA(x) (((x) & 0x1) << 8)
6928 #define G_0286CC_POS_X_FLOAT_ENA(x) (((x) >> 8) & 0x1)
6929 #define C_0286CC_POS_X_FLOAT_ENA 0xFFFFFEFF
6930 #define S_0286CC_POS_Y_FLOAT_ENA(x) (((x) & 0x1) << 9)
6931 #define G_0286CC_POS_Y_FLOAT_ENA(x) (((x) >> 9) & 0x1)
6932 #define C_0286CC_POS_Y_FLOAT_ENA 0xFFFFFDFF
6933 #define S_0286CC_POS_Z_FLOAT_ENA(x) (((x) & 0x1) << 10)
6934 #define G_0286CC_POS_Z_FLOAT_ENA(x) (((x) >> 10) & 0x1)
6935 #define C_0286CC_POS_Z_FLOAT_ENA 0xFFFFFBFF
6936 #define S_0286CC_POS_W_FLOAT_ENA(x) (((x) & 0x1) << 11)
6937 #define G_0286CC_POS_W_FLOAT_ENA(x) (((x) >> 11) & 0x1)
6938 #define C_0286CC_POS_W_FLOAT_ENA 0xFFFFF7FF
6939 #define S_0286CC_FRONT_FACE_ENA(x) (((x) & 0x1) << 12)
6940 #define G_0286CC_FRONT_FACE_ENA(x) (((x) >> 12) & 0x1)
6941 #define C_0286CC_FRONT_FACE_ENA 0xFFFFEFFF
6942 #define S_0286CC_ANCILLARY_ENA(x) (((x) & 0x1) << 13)
6943 #define G_0286CC_ANCILLARY_ENA(x) (((x) >> 13) & 0x1)
6944 #define C_0286CC_ANCILLARY_ENA 0xFFFFDFFF
6945 #define S_0286CC_SAMPLE_COVERAGE_ENA(x) (((x) & 0x1) << 14)
6946 #define G_0286CC_SAMPLE_COVERAGE_ENA(x) (((x) >> 14) & 0x1)
6947 #define C_0286CC_SAMPLE_COVERAGE_ENA 0xFFFFBFFF
6948 #define S_0286CC_POS_FIXED_PT_ENA(x) (((x) & 0x1) << 15)
6949 #define G_0286CC_POS_FIXED_PT_ENA(x) (((x) >> 15) & 0x1)
6950 #define C_0286CC_POS_FIXED_PT_ENA 0xFFFF7FFF
6951 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
6952 #define S_0286D0_PERSP_SAMPLE_ENA(x) (((x) & 0x1) << 0)
6953 #define G_0286D0_PERSP_SAMPLE_ENA(x) (((x) >> 0) & 0x1)
6954 #define C_0286D0_PERSP_SAMPLE_ENA 0xFFFFFFFE
6955 #define S_0286D0_PERSP_CENTER_ENA(x) (((x) & 0x1) << 1)
6956 #define G_0286D0_PERSP_CENTER_ENA(x) (((x) >> 1) & 0x1)
6957 #define C_0286D0_PERSP_CENTER_ENA 0xFFFFFFFD
6958 #define S_0286D0_PERSP_CENTROID_ENA(x) (((x) & 0x1) << 2)
6959 #define G_0286D0_PERSP_CENTROID_ENA(x) (((x) >> 2) & 0x1)
6960 #define C_0286D0_PERSP_CENTROID_ENA 0xFFFFFFFB
6961 #define S_0286D0_PERSP_PULL_MODEL_ENA(x) (((x) & 0x1) << 3)
6962 #define G_0286D0_PERSP_PULL_MODEL_ENA(x) (((x) >> 3) & 0x1)
6963 #define C_0286D0_PERSP_PULL_MODEL_ENA 0xFFFFFFF7
6964 #define S_0286D0_LINEAR_SAMPLE_ENA(x) (((x) & 0x1) << 4)
6965 #define G_0286D0_LINEAR_SAMPLE_ENA(x) (((x) >> 4) & 0x1)
6966 #define C_0286D0_LINEAR_SAMPLE_ENA 0xFFFFFFEF
6967 #define S_0286D0_LINEAR_CENTER_ENA(x) (((x) & 0x1) << 5)
6968 #define G_0286D0_LINEAR_CENTER_ENA(x) (((x) >> 5) & 0x1)
6969 #define C_0286D0_LINEAR_CENTER_ENA 0xFFFFFFDF
6970 #define S_0286D0_LINEAR_CENTROID_ENA(x) (((x) & 0x1) << 6)
6971 #define G_0286D0_LINEAR_CENTROID_ENA(x) (((x) >> 6) & 0x1)
6972 #define C_0286D0_LINEAR_CENTROID_ENA 0xFFFFFFBF
6973 #define S_0286D0_LINE_STIPPLE_TEX_ENA(x) (((x) & 0x1) << 7)
6974 #define G_0286D0_LINE_STIPPLE_TEX_ENA(x) (((x) >> 7) & 0x1)
6975 #define C_0286D0_LINE_STIPPLE_TEX_ENA 0xFFFFFF7F
6976 #define S_0286D0_POS_X_FLOAT_ENA(x) (((x) & 0x1) << 8)
6977 #define G_0286D0_POS_X_FLOAT_ENA(x) (((x) >> 8) & 0x1)
6978 #define C_0286D0_POS_X_FLOAT_ENA 0xFFFFFEFF
6979 #define S_0286D0_POS_Y_FLOAT_ENA(x) (((x) & 0x1) << 9)
6980 #define G_0286D0_POS_Y_FLOAT_ENA(x) (((x) >> 9) & 0x1)
6981 #define C_0286D0_POS_Y_FLOAT_ENA 0xFFFFFDFF
6982 #define S_0286D0_POS_Z_FLOAT_ENA(x) (((x) & 0x1) << 10)
6983 #define G_0286D0_POS_Z_FLOAT_ENA(x) (((x) >> 10) & 0x1)
6984 #define C_0286D0_POS_Z_FLOAT_ENA 0xFFFFFBFF
6985 #define S_0286D0_POS_W_FLOAT_ENA(x) (((x) & 0x1) << 11)
6986 #define G_0286D0_POS_W_FLOAT_ENA(x) (((x) >> 11) & 0x1)
6987 #define C_0286D0_POS_W_FLOAT_ENA 0xFFFFF7FF
6988 #define S_0286D0_FRONT_FACE_ENA(x) (((x) & 0x1) << 12)
6989 #define G_0286D0_FRONT_FACE_ENA(x) (((x) >> 12) & 0x1)
6990 #define C_0286D0_FRONT_FACE_ENA 0xFFFFEFFF
6991 #define S_0286D0_ANCILLARY_ENA(x) (((x) & 0x1) << 13)
6992 #define G_0286D0_ANCILLARY_ENA(x) (((x) >> 13) & 0x1)
6993 #define C_0286D0_ANCILLARY_ENA 0xFFFFDFFF
6994 #define S_0286D0_SAMPLE_COVERAGE_ENA(x) (((x) & 0x1) << 14)
6995 #define G_0286D0_SAMPLE_COVERAGE_ENA(x) (((x) >> 14) & 0x1)
6996 #define C_0286D0_SAMPLE_COVERAGE_ENA 0xFFFFBFFF
6997 #define S_0286D0_POS_FIXED_PT_ENA(x) (((x) & 0x1) << 15)
6998 #define G_0286D0_POS_FIXED_PT_ENA(x) (((x) >> 15) & 0x1)
6999 #define C_0286D0_POS_FIXED_PT_ENA 0xFFFF7FFF
7000 #define R_0286D4_SPI_INTERP_CONTROL_0 0x0286D4
7001 #define S_0286D4_FLAT_SHADE_ENA(x) (((x) & 0x1) << 0)
7002 #define G_0286D4_FLAT_SHADE_ENA(x) (((x) >> 0) & 0x1)
7003 #define C_0286D4_FLAT_SHADE_ENA 0xFFFFFFFE
7004 #define S_0286D4_PNT_SPRITE_ENA(x) (((x) & 0x1) << 1)
7005 #define G_0286D4_PNT_SPRITE_ENA(x) (((x) >> 1) & 0x1)
7006 #define C_0286D4_PNT_SPRITE_ENA 0xFFFFFFFD
7007 #define S_0286D4_PNT_SPRITE_OVRD_X(x) (((x) & 0x07) << 2)
7008 #define G_0286D4_PNT_SPRITE_OVRD_X(x) (((x) >> 2) & 0x07)
7009 #define C_0286D4_PNT_SPRITE_OVRD_X 0xFFFFFFE3
7010 #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00
7011 #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01
7012 #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02
7013 #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03
7014 #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04
7015 #define S_0286D4_PNT_SPRITE_OVRD_Y(x) (((x) & 0x07) << 5)
7016 #define G_0286D4_PNT_SPRITE_OVRD_Y(x) (((x) >> 5) & 0x07)
7017 #define C_0286D4_PNT_SPRITE_OVRD_Y 0xFFFFFF1F
7018 #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00
7019 #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01
7020 #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02
7021 #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03
7022 #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04
7023 #define S_0286D4_PNT_SPRITE_OVRD_Z(x) (((x) & 0x07) << 8)
7024 #define G_0286D4_PNT_SPRITE_OVRD_Z(x) (((x) >> 8) & 0x07)
7025 #define C_0286D4_PNT_SPRITE_OVRD_Z 0xFFFFF8FF
7026 #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00
7027 #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01
7028 #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02
7029 #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03
7030 #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04
7031 #define S_0286D4_PNT_SPRITE_OVRD_W(x) (((x) & 0x07) << 11)
7032 #define G_0286D4_PNT_SPRITE_OVRD_W(x) (((x) >> 11) & 0x07)
7033 #define C_0286D4_PNT_SPRITE_OVRD_W 0xFFFFC7FF
7034 #define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00
7035 #define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01
7036 #define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02
7037 #define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03
7038 #define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04
7039 #define S_0286D4_PNT_SPRITE_TOP_1(x) (((x) & 0x1) << 14)
7040 #define G_0286D4_PNT_SPRITE_TOP_1(x) (((x) >> 14) & 0x1)
7041 #define C_0286D4_PNT_SPRITE_TOP_1 0xFFFFBFFF
7042 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
7043 #define S_0286D8_NUM_INTERP(x) (((x) & 0x3F) << 0)
7044 #define G_0286D8_NUM_INTERP(x) (((x) >> 0) & 0x3F)
7045 #define C_0286D8_NUM_INTERP 0xFFFFFFC0
7046 #define S_0286D8_PARAM_GEN(x) (((x) & 0x1) << 6)
7047 #define G_0286D8_PARAM_GEN(x) (((x) >> 6) & 0x1)
7048 #define C_0286D8_PARAM_GEN 0xFFFFFFBF
7049 #define S_0286D8_FOG_ADDR(x) (((x) & 0x7F) << 7) /* not on CIK */
7050 #define G_0286D8_FOG_ADDR(x) (((x) >> 7) & 0x7F) /* not on CIK */
7051 #define C_0286D8_FOG_ADDR 0xFFFFC07F /* not on CIK */
7052 #define S_0286D8_BC_OPTIMIZE_DISABLE(x) (((x) & 0x1) << 14)
7053 #define G_0286D8_BC_OPTIMIZE_DISABLE(x) (((x) >> 14) & 0x1)
7054 #define C_0286D8_BC_OPTIMIZE_DISABLE 0xFFFFBFFF
7055 #define S_0286D8_PASS_FOG_THROUGH_PS(x) (((x) & 0x1) << 15) /* not on CIK */
7056 #define G_0286D8_PASS_FOG_THROUGH_PS(x) (((x) >> 15) & 0x1) /* not on CIK */
7057 #define C_0286D8_PASS_FOG_THROUGH_PS 0xFFFF7FFF /* not on CIK */
7058 #define R_0286E0_SPI_BARYC_CNTL 0x0286E0
7059 #define S_0286E0_PERSP_CENTER_CNTL(x) (((x) & 0x1) << 0)
7060 #define G_0286E0_PERSP_CENTER_CNTL(x) (((x) >> 0) & 0x1)
7061 #define C_0286E0_PERSP_CENTER_CNTL 0xFFFFFFFE
7062 #define S_0286E0_PERSP_CENTROID_CNTL(x) (((x) & 0x1) << 4)
7063 #define G_0286E0_PERSP_CENTROID_CNTL(x) (((x) >> 4) & 0x1)
7064 #define C_0286E0_PERSP_CENTROID_CNTL 0xFFFFFFEF
7065 #define S_0286E0_LINEAR_CENTER_CNTL(x) (((x) & 0x1) << 8)
7066 #define G_0286E0_LINEAR_CENTER_CNTL(x) (((x) >> 8) & 0x1)
7067 #define C_0286E0_LINEAR_CENTER_CNTL 0xFFFFFEFF
7068 #define S_0286E0_LINEAR_CENTROID_CNTL(x) (((x) & 0x1) << 12)
7069 #define G_0286E0_LINEAR_CENTROID_CNTL(x) (((x) >> 12) & 0x1)
7070 #define C_0286E0_LINEAR_CENTROID_CNTL 0xFFFFEFFF
7071 #define S_0286E0_POS_FLOAT_LOCATION(x) (((x) & 0x03) << 16)
7072 #define G_0286E0_POS_FLOAT_LOCATION(x) (((x) >> 16) & 0x03)
7073 #define C_0286E0_POS_FLOAT_LOCATION 0xFFFCFFFF
7074 #define V_0286E0_X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT 0x00
7075 #define S_0286E0_POS_FLOAT_ULC(x) (((x) & 0x1) << 20)
7076 #define G_0286E0_POS_FLOAT_ULC(x) (((x) >> 20) & 0x1)
7077 #define C_0286E0_POS_FLOAT_ULC 0xFFEFFFFF
7078 #define S_0286E0_FRONT_FACE_ALL_BITS(x) (((x) & 0x1) << 24)
7079 #define G_0286E0_FRONT_FACE_ALL_BITS(x) (((x) >> 24) & 0x1)
7080 #define C_0286E0_FRONT_FACE_ALL_BITS 0xFEFFFFFF
7081 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
7082 #define S_0286E8_WAVES(x) (((x) & 0xFFF) << 0)
7083 #define G_0286E8_WAVES(x) (((x) >> 0) & 0xFFF)
7084 #define C_0286E8_WAVES 0xFFFFF000
7085 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
7086 #define G_0286E8_WAVESIZE(x) (((x) >> 12) & 0x1FFF)
7087 #define C_0286E8_WAVESIZE 0xFE000FFF
7088 #define R_028704_SPI_WAVE_MGMT_1 0x028704 /* not on CIK */
7089 #define S_028704_NUM_PS_WAVES(x) (((x) & 0x3F) << 0)
7090 #define G_028704_NUM_PS_WAVES(x) (((x) >> 0) & 0x3F)
7091 #define C_028704_NUM_PS_WAVES 0xFFFFFFC0
7092 #define S_028704_NUM_VS_WAVES(x) (((x) & 0x3F) << 6)
7093 #define G_028704_NUM_VS_WAVES(x) (((x) >> 6) & 0x3F)
7094 #define C_028704_NUM_VS_WAVES 0xFFFFF03F
7095 #define S_028704_NUM_GS_WAVES(x) (((x) & 0x3F) << 12)
7096 #define G_028704_NUM_GS_WAVES(x) (((x) >> 12) & 0x3F)
7097 #define C_028704_NUM_GS_WAVES 0xFFFC0FFF
7098 #define S_028704_NUM_ES_WAVES(x) (((x) & 0x3F) << 18)
7099 #define G_028704_NUM_ES_WAVES(x) (((x) >> 18) & 0x3F)
7100 #define C_028704_NUM_ES_WAVES 0xFF03FFFF
7101 #define S_028704_NUM_HS_WAVES(x) (((x) & 0x3F) << 24)
7102 #define G_028704_NUM_HS_WAVES(x) (((x) >> 24) & 0x3F)
7103 #define C_028704_NUM_HS_WAVES 0xC0FFFFFF
7104 #define R_028708_SPI_WAVE_MGMT_2 0x028708 /* not on CIK */
7105 #define S_028708_NUM_LS_WAVES(x) (((x) & 0x3F) << 0)
7106 #define G_028708_NUM_LS_WAVES(x) (((x) >> 0) & 0x3F)
7107 #define C_028708_NUM_LS_WAVES 0xFFFFFFC0
7108 #define R_02870C_SPI_SHADER_POS_FORMAT 0x02870C
7109 #define S_02870C_POS0_EXPORT_FORMAT(x) (((x) & 0x0F) << 0)
7110 #define G_02870C_POS0_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F)
7111 #define C_02870C_POS0_EXPORT_FORMAT 0xFFFFFFF0
7112 #define V_02870C_SPI_SHADER_NONE 0x00
7113 #define V_02870C_SPI_SHADER_1COMP 0x01
7114 #define V_02870C_SPI_SHADER_2COMP 0x02
7115 #define V_02870C_SPI_SHADER_4COMPRESS 0x03
7116 #define V_02870C_SPI_SHADER_4COMP 0x04
7117 #define S_02870C_POS1_EXPORT_FORMAT(x) (((x) & 0x0F) << 4)
7118 #define G_02870C_POS1_EXPORT_FORMAT(x) (((x) >> 4) & 0x0F)
7119 #define C_02870C_POS1_EXPORT_FORMAT 0xFFFFFF0F
7120 #define V_02870C_SPI_SHADER_NONE 0x00
7121 #define V_02870C_SPI_SHADER_1COMP 0x01
7122 #define V_02870C_SPI_SHADER_2COMP 0x02
7123 #define V_02870C_SPI_SHADER_4COMPRESS 0x03
7124 #define V_02870C_SPI_SHADER_4COMP 0x04
7125 #define S_02870C_POS2_EXPORT_FORMAT(x) (((x) & 0x0F) << 8)
7126 #define G_02870C_POS2_EXPORT_FORMAT(x) (((x) >> 8) & 0x0F)
7127 #define C_02870C_POS2_EXPORT_FORMAT 0xFFFFF0FF
7128 #define V_02870C_SPI_SHADER_NONE 0x00
7129 #define V_02870C_SPI_SHADER_1COMP 0x01
7130 #define V_02870C_SPI_SHADER_2COMP 0x02
7131 #define V_02870C_SPI_SHADER_4COMPRESS 0x03
7132 #define V_02870C_SPI_SHADER_4COMP 0x04
7133 #define S_02870C_POS3_EXPORT_FORMAT(x) (((x) & 0x0F) << 12)
7134 #define G_02870C_POS3_EXPORT_FORMAT(x) (((x) >> 12) & 0x0F)
7135 #define C_02870C_POS3_EXPORT_FORMAT 0xFFFF0FFF
7136 #define V_02870C_SPI_SHADER_NONE 0x00
7137 #define V_02870C_SPI_SHADER_1COMP 0x01
7138 #define V_02870C_SPI_SHADER_2COMP 0x02
7139 #define V_02870C_SPI_SHADER_4COMPRESS 0x03
7140 #define V_02870C_SPI_SHADER_4COMP 0x04
7141 #define R_028710_SPI_SHADER_Z_FORMAT 0x028710
7142 #define S_028710_Z_EXPORT_FORMAT(x) (((x) & 0x0F) << 0)
7143 #define G_028710_Z_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F)
7144 #define C_028710_Z_EXPORT_FORMAT 0xFFFFFFF0
7145 #define V_028710_SPI_SHADER_ZERO 0x00
7146 #define V_028710_SPI_SHADER_32_R 0x01
7147 #define V_028710_SPI_SHADER_32_GR 0x02
7148 #define V_028710_SPI_SHADER_32_AR 0x03
7149 #define V_028710_SPI_SHADER_FP16_ABGR 0x04
7150 #define V_028710_SPI_SHADER_UNORM16_ABGR 0x05
7151 #define V_028710_SPI_SHADER_SNORM16_ABGR 0x06
7152 #define V_028710_SPI_SHADER_UINT16_ABGR 0x07
7153 #define V_028710_SPI_SHADER_SINT16_ABGR 0x08
7154 #define V_028710_SPI_SHADER_32_ABGR 0x09
7155 #define R_028714_SPI_SHADER_COL_FORMAT 0x028714
7156 #define S_028714_COL0_EXPORT_FORMAT(x) (((x) & 0x0F) << 0)
7157 #define G_028714_COL0_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F)
7158 #define C_028714_COL0_EXPORT_FORMAT 0xFFFFFFF0
7159 #define V_028714_SPI_SHADER_ZERO 0x00
7160 #define V_028714_SPI_SHADER_32_R 0x01
7161 #define V_028714_SPI_SHADER_32_GR 0x02
7162 #define V_028714_SPI_SHADER_32_AR 0x03
7163 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
7164 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
7165 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
7166 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
7167 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
7168 #define V_028714_SPI_SHADER_32_ABGR 0x09
7169 #define S_028714_COL1_EXPORT_FORMAT(x) (((x) & 0x0F) << 4)
7170 #define G_028714_COL1_EXPORT_FORMAT(x) (((x) >> 4) & 0x0F)
7171 #define C_028714_COL1_EXPORT_FORMAT 0xFFFFFF0F
7172 #define V_028714_SPI_SHADER_ZERO 0x00
7173 #define V_028714_SPI_SHADER_32_R 0x01
7174 #define V_028714_SPI_SHADER_32_GR 0x02
7175 #define V_028714_SPI_SHADER_32_AR 0x03
7176 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
7177 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
7178 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
7179 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
7180 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
7181 #define V_028714_SPI_SHADER_32_ABGR 0x09
7182 #define S_028714_COL2_EXPORT_FORMAT(x) (((x) & 0x0F) << 8)
7183 #define G_028714_COL2_EXPORT_FORMAT(x) (((x) >> 8) & 0x0F)
7184 #define C_028714_COL2_EXPORT_FORMAT 0xFFFFF0FF
7185 #define V_028714_SPI_SHADER_ZERO 0x00
7186 #define V_028714_SPI_SHADER_32_R 0x01
7187 #define V_028714_SPI_SHADER_32_GR 0x02
7188 #define V_028714_SPI_SHADER_32_AR 0x03
7189 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
7190 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
7191 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
7192 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
7193 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
7194 #define V_028714_SPI_SHADER_32_ABGR 0x09
7195 #define S_028714_COL3_EXPORT_FORMAT(x) (((x) & 0x0F) << 12)
7196 #define G_028714_COL3_EXPORT_FORMAT(x) (((x) >> 12) & 0x0F)
7197 #define C_028714_COL3_EXPORT_FORMAT 0xFFFF0FFF
7198 #define V_028714_SPI_SHADER_ZERO 0x00
7199 #define V_028714_SPI_SHADER_32_R 0x01
7200 #define V_028714_SPI_SHADER_32_GR 0x02
7201 #define V_028714_SPI_SHADER_32_AR 0x03
7202 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
7203 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
7204 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
7205 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
7206 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
7207 #define V_028714_SPI_SHADER_32_ABGR 0x09
7208 #define S_028714_COL4_EXPORT_FORMAT(x) (((x) & 0x0F) << 16)
7209 #define G_028714_COL4_EXPORT_FORMAT(x) (((x) >> 16) & 0x0F)
7210 #define C_028714_COL4_EXPORT_FORMAT 0xFFF0FFFF
7211 #define V_028714_SPI_SHADER_ZERO 0x00
7212 #define V_028714_SPI_SHADER_32_R 0x01
7213 #define V_028714_SPI_SHADER_32_GR 0x02
7214 #define V_028714_SPI_SHADER_32_AR 0x03
7215 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
7216 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
7217 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
7218 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
7219 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
7220 #define V_028714_SPI_SHADER_32_ABGR 0x09
7221 #define S_028714_COL5_EXPORT_FORMAT(x) (((x) & 0x0F) << 20)
7222 #define G_028714_COL5_EXPORT_FORMAT(x) (((x) >> 20) & 0x0F)
7223 #define C_028714_COL5_EXPORT_FORMAT 0xFF0FFFFF
7224 #define V_028714_SPI_SHADER_ZERO 0x00
7225 #define V_028714_SPI_SHADER_32_R 0x01
7226 #define V_028714_SPI_SHADER_32_GR 0x02
7227 #define V_028714_SPI_SHADER_32_AR 0x03
7228 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
7229 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
7230 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
7231 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
7232 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
7233 #define V_028714_SPI_SHADER_32_ABGR 0x09
7234 #define S_028714_COL6_EXPORT_FORMAT(x) (((x) & 0x0F) << 24)
7235 #define G_028714_COL6_EXPORT_FORMAT(x) (((x) >> 24) & 0x0F)
7236 #define C_028714_COL6_EXPORT_FORMAT 0xF0FFFFFF
7237 #define V_028714_SPI_SHADER_ZERO 0x00
7238 #define V_028714_SPI_SHADER_32_R 0x01
7239 #define V_028714_SPI_SHADER_32_GR 0x02
7240 #define V_028714_SPI_SHADER_32_AR 0x03
7241 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
7242 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
7243 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
7244 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
7245 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
7246 #define V_028714_SPI_SHADER_32_ABGR 0x09
7247 #define S_028714_COL7_EXPORT_FORMAT(x) (((x) & 0x0F) << 28)
7248 #define G_028714_COL7_EXPORT_FORMAT(x) (((x) >> 28) & 0x0F)
7249 #define C_028714_COL7_EXPORT_FORMAT 0x0FFFFFFF
7250 #define V_028714_SPI_SHADER_ZERO 0x00
7251 #define V_028714_SPI_SHADER_32_R 0x01
7252 #define V_028714_SPI_SHADER_32_GR 0x02
7253 #define V_028714_SPI_SHADER_32_AR 0x03
7254 #define V_028714_SPI_SHADER_FP16_ABGR 0x04
7255 #define V_028714_SPI_SHADER_UNORM16_ABGR 0x05
7256 #define V_028714_SPI_SHADER_SNORM16_ABGR 0x06
7257 #define V_028714_SPI_SHADER_UINT16_ABGR 0x07
7258 #define V_028714_SPI_SHADER_SINT16_ABGR 0x08
7259 #define V_028714_SPI_SHADER_32_ABGR 0x09
7260 #define R_028780_CB_BLEND0_CONTROL 0x028780
7261 #define S_028780_COLOR_SRCBLEND(x) (((x) & 0x1F) << 0)
7262 #define G_028780_COLOR_SRCBLEND(x) (((x) >> 0) & 0x1F)
7263 #define C_028780_COLOR_SRCBLEND 0xFFFFFFE0
7264 #define V_028780_BLEND_ZERO 0x00
7265 #define V_028780_BLEND_ONE 0x01
7266 #define V_028780_BLEND_SRC_COLOR 0x02
7267 #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03
7268 #define V_028780_BLEND_SRC_ALPHA 0x04
7269 #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05
7270 #define V_028780_BLEND_DST_ALPHA 0x06
7271 #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07
7272 #define V_028780_BLEND_DST_COLOR 0x08
7273 #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09
7274 #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A
7275 #define V_028780_BLEND_CONSTANT_COLOR 0x0D
7276 #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E
7277 #define V_028780_BLEND_SRC1_COLOR 0x0F
7278 #define V_028780_BLEND_INV_SRC1_COLOR 0x10
7279 #define V_028780_BLEND_SRC1_ALPHA 0x11
7280 #define V_028780_BLEND_INV_SRC1_ALPHA 0x12
7281 #define V_028780_BLEND_CONSTANT_ALPHA 0x13
7282 #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
7283 #define S_028780_COLOR_COMB_FCN(x) (((x) & 0x07) << 5)
7284 #define G_028780_COLOR_COMB_FCN(x) (((x) >> 5) & 0x07)
7285 #define C_028780_COLOR_COMB_FCN 0xFFFFFF1F
7286 #define V_028780_COMB_DST_PLUS_SRC 0x00
7287 #define V_028780_COMB_SRC_MINUS_DST 0x01
7288 #define V_028780_COMB_MIN_DST_SRC 0x02
7289 #define V_028780_COMB_MAX_DST_SRC 0x03
7290 #define V_028780_COMB_DST_MINUS_SRC 0x04
7291 #define S_028780_COLOR_DESTBLEND(x) (((x) & 0x1F) << 8)
7292 #define G_028780_COLOR_DESTBLEND(x) (((x) >> 8) & 0x1F)
7293 #define C_028780_COLOR_DESTBLEND 0xFFFFE0FF
7294 #define V_028780_BLEND_ZERO 0x00
7295 #define V_028780_BLEND_ONE 0x01
7296 #define V_028780_BLEND_SRC_COLOR 0x02
7297 #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03
7298 #define V_028780_BLEND_SRC_ALPHA 0x04
7299 #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05
7300 #define V_028780_BLEND_DST_ALPHA 0x06
7301 #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07
7302 #define V_028780_BLEND_DST_COLOR 0x08
7303 #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09
7304 #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A
7305 #define V_028780_BLEND_CONSTANT_COLOR 0x0D
7306 #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E
7307 #define V_028780_BLEND_SRC1_COLOR 0x0F
7308 #define V_028780_BLEND_INV_SRC1_COLOR 0x10
7309 #define V_028780_BLEND_SRC1_ALPHA 0x11
7310 #define V_028780_BLEND_INV_SRC1_ALPHA 0x12
7311 #define V_028780_BLEND_CONSTANT_ALPHA 0x13
7312 #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
7313 #define S_028780_ALPHA_SRCBLEND(x) (((x) & 0x1F) << 16)
7314 #define G_028780_ALPHA_SRCBLEND(x) (((x) >> 16) & 0x1F)
7315 #define C_028780_ALPHA_SRCBLEND 0xFFE0FFFF
7316 #define V_028780_BLEND_ZERO 0x00
7317 #define V_028780_BLEND_ONE 0x01
7318 #define V_028780_BLEND_SRC_COLOR 0x02
7319 #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03
7320 #define V_028780_BLEND_SRC_ALPHA 0x04
7321 #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05
7322 #define V_028780_BLEND_DST_ALPHA 0x06
7323 #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07
7324 #define V_028780_BLEND_DST_COLOR 0x08
7325 #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09
7326 #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A
7327 #define V_028780_BLEND_CONSTANT_COLOR 0x0D
7328 #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E
7329 #define V_028780_BLEND_SRC1_COLOR 0x0F
7330 #define V_028780_BLEND_INV_SRC1_COLOR 0x10
7331 #define V_028780_BLEND_SRC1_ALPHA 0x11
7332 #define V_028780_BLEND_INV_SRC1_ALPHA 0x12
7333 #define V_028780_BLEND_CONSTANT_ALPHA 0x13
7334 #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
7335 #define S_028780_ALPHA_COMB_FCN(x) (((x) & 0x07) << 21)
7336 #define G_028780_ALPHA_COMB_FCN(x) (((x) >> 21) & 0x07)
7337 #define C_028780_ALPHA_COMB_FCN 0xFF1FFFFF
7338 #define V_028780_COMB_DST_PLUS_SRC 0x00
7339 #define V_028780_COMB_SRC_MINUS_DST 0x01
7340 #define V_028780_COMB_MIN_DST_SRC 0x02
7341 #define V_028780_COMB_MAX_DST_SRC 0x03
7342 #define V_028780_COMB_DST_MINUS_SRC 0x04
7343 #define S_028780_ALPHA_DESTBLEND(x) (((x) & 0x1F) << 24)
7344 #define G_028780_ALPHA_DESTBLEND(x) (((x) >> 24) & 0x1F)
7345 #define C_028780_ALPHA_DESTBLEND 0xE0FFFFFF
7346 #define V_028780_BLEND_ZERO 0x00
7347 #define V_028780_BLEND_ONE 0x01
7348 #define V_028780_BLEND_SRC_COLOR 0x02
7349 #define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03
7350 #define V_028780_BLEND_SRC_ALPHA 0x04
7351 #define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05
7352 #define V_028780_BLEND_DST_ALPHA 0x06
7353 #define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07
7354 #define V_028780_BLEND_DST_COLOR 0x08
7355 #define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09
7356 #define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A
7357 #define V_028780_BLEND_CONSTANT_COLOR 0x0D
7358 #define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E
7359 #define V_028780_BLEND_SRC1_COLOR 0x0F
7360 #define V_028780_BLEND_INV_SRC1_COLOR 0x10
7361 #define V_028780_BLEND_SRC1_ALPHA 0x11
7362 #define V_028780_BLEND_INV_SRC1_ALPHA 0x12
7363 #define V_028780_BLEND_CONSTANT_ALPHA 0x13
7364 #define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14
7365 #define S_028780_SEPARATE_ALPHA_BLEND(x) (((x) & 0x1) << 29)
7366 #define G_028780_SEPARATE_ALPHA_BLEND(x) (((x) >> 29) & 0x1)
7367 #define C_028780_SEPARATE_ALPHA_BLEND 0xDFFFFFFF
7368 #define S_028780_ENABLE(x) (((x) & 0x1) << 30)
7369 #define G_028780_ENABLE(x) (((x) >> 30) & 0x1)
7370 #define C_028780_ENABLE 0xBFFFFFFF
7371 #define S_028780_DISABLE_ROP3(x) (((x) & 0x1) << 31)
7372 #define G_028780_DISABLE_ROP3(x) (((x) >> 31) & 0x1)
7373 #define C_028780_DISABLE_ROP3 0x7FFFFFFF
7374 #define R_028784_CB_BLEND1_CONTROL 0x028784
7375 #define R_028788_CB_BLEND2_CONTROL 0x028788
7376 #define R_02878C_CB_BLEND3_CONTROL 0x02878C
7377 #define R_028790_CB_BLEND4_CONTROL 0x028790
7378 #define R_028794_CB_BLEND5_CONTROL 0x028794
7379 #define R_028798_CB_BLEND6_CONTROL 0x028798
7380 #define R_02879C_CB_BLEND7_CONTROL 0x02879C
7381 #define R_0287CC_CS_COPY_STATE 0x0287CC
7382 #define S_0287CC_SRC_STATE_ID(x) (((x) & 0x07) << 0)
7383 #define G_0287CC_SRC_STATE_ID(x) (((x) >> 0) & 0x07)
7384 #define C_0287CC_SRC_STATE_ID 0xFFFFFFF8
7385 #define R_0287D4_PA_CL_POINT_X_RAD 0x0287D4
7386 #define R_0287D8_PA_CL_POINT_Y_RAD 0x0287D8
7387 #define R_0287DC_PA_CL_POINT_SIZE 0x0287DC
7388 #define R_0287E0_PA_CL_POINT_CULL_RAD 0x0287E0
7389 #define R_0287E4_VGT_DMA_BASE_HI 0x0287E4
7390 #define S_0287E4_BASE_ADDR(x) (((x) & 0xFF) << 0)
7391 #define G_0287E4_BASE_ADDR(x) (((x) >> 0) & 0xFF)
7392 #define C_0287E4_BASE_ADDR 0xFFFFFF00
7393 #define R_0287E8_VGT_DMA_BASE 0x0287E8
7394 #define R_0287F0_VGT_DRAW_INITIATOR 0x0287F0
7395 #define S_0287F0_SOURCE_SELECT(x) (((x) & 0x03) << 0)
7396 #define G_0287F0_SOURCE_SELECT(x) (((x) >> 0) & 0x03)
7397 #define C_0287F0_SOURCE_SELECT 0xFFFFFFFC
7398 #define V_0287F0_DI_SRC_SEL_DMA 0x00
7399 #define V_0287F0_DI_SRC_SEL_IMMEDIATE 0x01 /* not on CIK */
7400 #define V_0287F0_DI_SRC_SEL_AUTO_INDEX 0x02
7401 #define V_0287F0_DI_SRC_SEL_RESERVED 0x03
7402 #define S_0287F0_MAJOR_MODE(x) (((x) & 0x03) << 2)
7403 #define G_0287F0_MAJOR_MODE(x) (((x) >> 2) & 0x03)
7404 #define C_0287F0_MAJOR_MODE 0xFFFFFFF3
7405 #define V_0287F0_DI_MAJOR_MODE_0 0x00
7406 #define V_0287F0_DI_MAJOR_MODE_1 0x01
7407 #define S_0287F0_NOT_EOP(x) (((x) & 0x1) << 5)
7408 #define G_0287F0_NOT_EOP(x) (((x) >> 5) & 0x1)
7409 #define C_0287F0_NOT_EOP 0xFFFFFFDF
7410 #define S_0287F0_USE_OPAQUE(x) (((x) & 0x1) << 6)
7411 #define G_0287F0_USE_OPAQUE(x) (((x) >> 6) & 0x1)
7412 #define C_0287F0_USE_OPAQUE 0xFFFFFFBF
7413 #define R_0287F4_VGT_IMMED_DATA 0x0287F4 /* not on CIK */
7414 #define R_0287F8_VGT_EVENT_ADDRESS_REG 0x0287F8
7415 #define S_0287F8_ADDRESS_LOW(x) (((x) & 0xFFFFFFF) << 0)
7416 #define G_0287F8_ADDRESS_LOW(x) (((x) >> 0) & 0xFFFFFFF)
7417 #define C_0287F8_ADDRESS_LOW 0xF0000000
7418 #define R_028800_DB_DEPTH_CONTROL 0x028800
7419 #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)
7420 #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)
7421 #define C_028800_STENCIL_ENABLE 0xFFFFFFFE
7422 #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)
7423 #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)
7424 #define C_028800_Z_ENABLE 0xFFFFFFFD
7425 #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)
7426 #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)
7427 #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB
7428 #define S_028800_DEPTH_BOUNDS_ENABLE(x) (((x) & 0x1) << 3)
7429 #define G_028800_DEPTH_BOUNDS_ENABLE(x) (((x) >> 3) & 0x1)
7430 #define C_028800_DEPTH_BOUNDS_ENABLE 0xFFFFFFF7
7431 #define S_028800_ZFUNC(x) (((x) & 0x07) << 4)
7432 #define G_028800_ZFUNC(x) (((x) >> 4) & 0x07)
7433 #define C_028800_ZFUNC 0xFFFFFF8F
7434 #define V_028800_FRAG_NEVER 0x00
7435 #define V_028800_FRAG_LESS 0x01
7436 #define V_028800_FRAG_EQUAL 0x02
7437 #define V_028800_FRAG_LEQUAL 0x03
7438 #define V_028800_FRAG_GREATER 0x04
7439 #define V_028800_FRAG_NOTEQUAL 0x05
7440 #define V_028800_FRAG_GEQUAL 0x06
7441 #define V_028800_FRAG_ALWAYS 0x07
7442 #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)
7443 #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)
7444 #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F
7445 #define S_028800_STENCILFUNC(x) (((x) & 0x07) << 8)
7446 #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x07)
7447 #define C_028800_STENCILFUNC 0xFFFFF8FF
7448 #define V_028800_REF_NEVER 0x00
7449 #define V_028800_REF_LESS 0x01
7450 #define V_028800_REF_EQUAL 0x02
7451 #define V_028800_REF_LEQUAL 0x03
7452 #define V_028800_REF_GREATER 0x04
7453 #define V_028800_REF_NOTEQUAL 0x05
7454 #define V_028800_REF_GEQUAL 0x06
7455 #define V_028800_REF_ALWAYS 0x07
7456 #define S_028800_STENCILFUNC_BF(x) (((x) & 0x07) << 20)
7457 #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x07)
7458 #define C_028800_STENCILFUNC_BF 0xFF8FFFFF
7459 #define V_028800_REF_NEVER 0x00
7460 #define V_028800_REF_LESS 0x01
7461 #define V_028800_REF_EQUAL 0x02
7462 #define V_028800_REF_LEQUAL 0x03
7463 #define V_028800_REF_GREATER 0x04
7464 #define V_028800_REF_NOTEQUAL 0x05
7465 #define V_028800_REF_GEQUAL 0x06
7466 #define V_028800_REF_ALWAYS 0x07
7467 #define S_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL(x) (((x) & 0x1) << 30)
7468 #define G_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL(x) (((x) >> 30) & 0x1)
7469 #define C_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL 0xBFFFFFFF
7470 #define S_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS(x) (((x) & 0x1) << 31)
7471 #define G_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS(x) (((x) >> 31) & 0x1)
7472 #define C_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS 0x7FFFFFFF
7473 #define R_028804_DB_EQAA 0x028804
7474 #define S_028804_MAX_ANCHOR_SAMPLES(x) (((x) & 0x7) << 0)
7475 #define G_028804_MAX_ANCHOR_SAMPLES(x) (((x) >> 0) & 0x07)
7476 #define C_028804_MAX_ANCHOR_SAMPLES 0xFFFFFFF8
7477 #define S_028804_PS_ITER_SAMPLES(x) (((x) & 0x7) << 4)
7478 #define G_028804_PS_ITER_SAMPLES(x) (((x) >> 4) & 0x07)
7479 #define C_028804_PS_ITER_SAMPLES 0xFFFFFF8F
7480 #define S_028804_MASK_EXPORT_NUM_SAMPLES(x) (((x) & 0x7) << 8)
7481 #define G_028804_MASK_EXPORT_NUM_SAMPLES(x) (((x) >> 8) & 0x07)
7482 #define C_028804_MASK_EXPORT_NUM_SAMPLES 0xFFFFF8FF
7483 #define S_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((x) & 0x7) << 12)
7484 #define G_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((x) >> 12) & 0x07)
7485 #define C_028804_ALPHA_TO_MASK_NUM_SAMPLES 0xFFFF8FFF
7486 #define S_028804_HIGH_QUALITY_INTERSECTIONS(x) (((x) & 0x1) << 16)
7487 #define G_028804_HIGH_QUALITY_INTERSECTIONS(x) (((x) >> 16) & 0x1)
7488 #define C_028804_HIGH_QUALITY_INTERSECTIONS 0xFFFEFFFF
7489 #define S_028804_INCOHERENT_EQAA_READS(x) (((x) & 0x1) << 17)
7490 #define G_028804_INCOHERENT_EQAA_READS(x) (((x) >> 17) & 0x1)
7491 #define C_028804_INCOHERENT_EQAA_READS 0xFFFDFFFF
7492 #define S_028804_INTERPOLATE_COMP_Z(x) (((x) & 0x1) << 18)
7493 #define G_028804_INTERPOLATE_COMP_Z(x) (((x) >> 18) & 0x1)
7494 #define C_028804_INTERPOLATE_COMP_Z 0xFFFBFFFF
7495 #define S_028804_INTERPOLATE_SRC_Z(x) (((x) & 0x1) << 19)
7496 #define G_028804_INTERPOLATE_SRC_Z(x) (((x) >> 19) & 0x1)
7497 #define C_028804_INTERPOLATE_SRC_Z 0xFFF7FFFF
7498 #define S_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((x) & 0x1) << 20)
7499 #define G_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((x) >> 20) & 0x1)
7500 #define C_028804_STATIC_ANCHOR_ASSOCIATIONS 0xFFEFFFFF
7501 #define S_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((x) & 0x1) << 21)
7502 #define G_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((x) >> 21) & 0x1)
7503 #define C_028804_ALPHA_TO_MASK_EQAA_DISABLE 0xFFDFFFFF
7504 #define S_028804_OVERRASTERIZATION_AMOUNT(x) (((x) & 0x07) << 24)
7505 #define G_028804_OVERRASTERIZATION_AMOUNT(x) (((x) >> 24) & 0x07)
7506 #define C_028804_OVERRASTERIZATION_AMOUNT 0xF8FFFFFF
7507 #define S_028804_ENABLE_POSTZ_OVERRASTERIZATION(x) (((x) & 0x1) << 27)
7508 #define G_028804_ENABLE_POSTZ_OVERRASTERIZATION(x) (((x) >> 27) & 0x1)
7509 #define C_028804_ENABLE_POSTZ_OVERRASTERIZATION 0xF7FFFFFF
7510 #define R_028808_CB_COLOR_CONTROL 0x028808
7511 #define S_028808_DEGAMMA_ENABLE(x) (((x) & 0x1) << 3)
7512 #define G_028808_DEGAMMA_ENABLE(x) (((x) >> 3) & 0x1)
7513 #define C_028808_DEGAMMA_ENABLE 0xFFFFFFF7
7514 #define S_028808_MODE(x) (((x) & 0x07) << 4)
7515 #define G_028808_MODE(x) (((x) >> 4) & 0x07)
7516 #define C_028808_MODE 0xFFFFFF8F
7517 #define V_028808_CB_DISABLE 0x00
7518 #define V_028808_CB_NORMAL 0x01
7519 #define V_028808_CB_ELIMINATE_FAST_CLEAR 0x02
7520 #define V_028808_CB_RESOLVE 0x03
7521 #define V_028808_CB_FMASK_DECOMPRESS 0x05
7522 #define S_028808_ROP3(x) (((x) & 0xFF) << 16)
7523 #define G_028808_ROP3(x) (((x) >> 16) & 0xFF)
7524 #define C_028808_ROP3 0xFF00FFFF
7525 #define V_028808_X_0X00 0x00
7526 #define V_028808_X_0X05 0x05
7527 #define V_028808_X_0X0A 0x0A
7528 #define V_028808_X_0X0F 0x0F
7529 #define V_028808_X_0X11 0x11
7530 #define V_028808_X_0X22 0x22
7531 #define V_028808_X_0X33 0x33
7532 #define V_028808_X_0X44 0x44
7533 #define V_028808_X_0X50 0x50
7534 #define V_028808_X_0X55 0x55
7535 #define V_028808_X_0X5A 0x5A
7536 #define V_028808_X_0X5F 0x5F
7537 #define V_028808_X_0X66 0x66
7538 #define V_028808_X_0X77 0x77
7539 #define V_028808_X_0X88 0x88
7540 #define V_028808_X_0X99 0x99
7541 #define V_028808_X_0XA0 0xA0
7542 #define V_028808_X_0XA5 0xA5
7543 #define V_028808_X_0XAA 0xAA
7544 #define V_028808_X_0XAF 0xAF
7545 #define V_028808_X_0XBB 0xBB
7546 #define V_028808_X_0XCC 0xCC
7547 #define V_028808_X_0XDD 0xDD
7548 #define V_028808_X_0XEE 0xEE
7549 #define V_028808_X_0XF0 0xF0
7550 #define V_028808_X_0XF5 0xF5
7551 #define V_028808_X_0XFA 0xFA
7552 #define V_028808_X_0XFF 0xFF
7553 #define R_02880C_DB_SHADER_CONTROL 0x02880C
7554 #define S_02880C_Z_EXPORT_ENABLE(x) (((x) & 0x1) << 0)
7555 #define G_02880C_Z_EXPORT_ENABLE(x) (((x) >> 0) & 0x1)
7556 #define C_02880C_Z_EXPORT_ENABLE 0xFFFFFFFE
7557 #define S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(x) (((x) & 0x1) << 1)
7558 #define G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(x) (((x) >> 1) & 0x1)
7559 #define C_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE 0xFFFFFFFD
7560 #define S_02880C_STENCIL_OP_VAL_EXPORT_ENABLE(x) (((x) & 0x1) << 2)
7561 #define G_02880C_STENCIL_OP_VAL_EXPORT_ENABLE(x) (((x) >> 2) & 0x1)
7562 #define C_02880C_STENCIL_OP_VAL_EXPORT_ENABLE 0xFFFFFFFB
7563 #define S_02880C_Z_ORDER(x) (((x) & 0x03) << 4)
7564 #define G_02880C_Z_ORDER(x) (((x) >> 4) & 0x03)
7565 #define C_02880C_Z_ORDER 0xFFFFFFCF
7566 #define V_02880C_LATE_Z 0x00
7567 #define V_02880C_EARLY_Z_THEN_LATE_Z 0x01
7568 #define V_02880C_RE_Z 0x02
7569 #define V_02880C_EARLY_Z_THEN_RE_Z 0x03
7570 #define S_02880C_KILL_ENABLE(x) (((x) & 0x1) << 6)
7571 #define G_02880C_KILL_ENABLE(x) (((x) >> 6) & 0x1)
7572 #define C_02880C_KILL_ENABLE 0xFFFFFFBF
7573 #define S_02880C_COVERAGE_TO_MASK_ENABLE(x) (((x) & 0x1) << 7)
7574 #define G_02880C_COVERAGE_TO_MASK_ENABLE(x) (((x) >> 7) & 0x1)
7575 #define C_02880C_COVERAGE_TO_MASK_ENABLE 0xFFFFFF7F
7576 #define S_02880C_MASK_EXPORT_ENABLE(x) (((x) & 0x1) << 8)
7577 #define G_02880C_MASK_EXPORT_ENABLE(x) (((x) >> 8) & 0x1)
7578 #define C_02880C_MASK_EXPORT_ENABLE 0xFFFFFEFF
7579 #define S_02880C_EXEC_ON_HIER_FAIL(x) (((x) & 0x1) << 9)
7580 #define G_02880C_EXEC_ON_HIER_FAIL(x) (((x) >> 9) & 0x1)
7581 #define C_02880C_EXEC_ON_HIER_FAIL 0xFFFFFDFF
7582 #define S_02880C_EXEC_ON_NOOP(x) (((x) & 0x1) << 10)
7583 #define G_02880C_EXEC_ON_NOOP(x) (((x) >> 10) & 0x1)
7584 #define C_02880C_EXEC_ON_NOOP 0xFFFFFBFF
7585 #define S_02880C_ALPHA_TO_MASK_DISABLE(x) (((x) & 0x1) << 11)
7586 #define G_02880C_ALPHA_TO_MASK_DISABLE(x) (((x) >> 11) & 0x1)
7587 #define C_02880C_ALPHA_TO_MASK_DISABLE 0xFFFFF7FF
7588 #define S_02880C_DEPTH_BEFORE_SHADER(x) (((x) & 0x1) << 12)
7589 #define G_02880C_DEPTH_BEFORE_SHADER(x) (((x) >> 12) & 0x1)
7590 #define C_02880C_DEPTH_BEFORE_SHADER 0xFFFFEFFF
7591 /* CIK */
7592 #define S_02880C_CONSERVATIVE_Z_EXPORT(x) (((x) & 0x03) << 13)
7593 #define G_02880C_CONSERVATIVE_Z_EXPORT(x) (((x) >> 13) & 0x03)
7594 #define C_02880C_CONSERVATIVE_Z_EXPORT 0xFFFF9FFF
7595 #define V_02880C_EXPORT_ANY_Z 0
7596 #define V_02880C_EXPORT_LESS_THAN_Z 1
7597 #define V_02880C_EXPORT_GREATER_THAN_Z 2
7598 #define V_02880C_EXPORT_RESERVED 3
7599 /* */
7600 #define R_028810_PA_CL_CLIP_CNTL 0x028810
7601 #define S_028810_UCP_ENA_0(x) (((x) & 0x1) << 0)
7602 #define G_028810_UCP_ENA_0(x) (((x) >> 0) & 0x1)
7603 #define C_028810_UCP_ENA_0 0xFFFFFFFE
7604 #define S_028810_UCP_ENA_1(x) (((x) & 0x1) << 1)
7605 #define G_028810_UCP_ENA_1(x) (((x) >> 1) & 0x1)
7606 #define C_028810_UCP_ENA_1 0xFFFFFFFD
7607 #define S_028810_UCP_ENA_2(x) (((x) & 0x1) << 2)
7608 #define G_028810_UCP_ENA_2(x) (((x) >> 2) & 0x1)
7609 #define C_028810_UCP_ENA_2 0xFFFFFFFB
7610 #define S_028810_UCP_ENA_3(x) (((x) & 0x1) << 3)
7611 #define G_028810_UCP_ENA_3(x) (((x) >> 3) & 0x1)
7612 #define C_028810_UCP_ENA_3 0xFFFFFFF7
7613 #define S_028810_UCP_ENA_4(x) (((x) & 0x1) << 4)
7614 #define G_028810_UCP_ENA_4(x) (((x) >> 4) & 0x1)
7615 #define C_028810_UCP_ENA_4 0xFFFFFFEF
7616 #define S_028810_UCP_ENA_5(x) (((x) & 0x1) << 5)
7617 #define G_028810_UCP_ENA_5(x) (((x) >> 5) & 0x1)
7618 #define C_028810_UCP_ENA_5 0xFFFFFFDF
7619 #define S_028810_PS_UCP_Y_SCALE_NEG(x) (((x) & 0x1) << 13)
7620 #define G_028810_PS_UCP_Y_SCALE_NEG(x) (((x) >> 13) & 0x1)
7621 #define C_028810_PS_UCP_Y_SCALE_NEG 0xFFFFDFFF
7622 #define S_028810_PS_UCP_MODE(x) (((x) & 0x03) << 14)
7623 #define G_028810_PS_UCP_MODE(x) (((x) >> 14) & 0x03)
7624 #define C_028810_PS_UCP_MODE 0xFFFF3FFF
7625 #define S_028810_CLIP_DISABLE(x) (((x) & 0x1) << 16)
7626 #define G_028810_CLIP_DISABLE(x) (((x) >> 16) & 0x1)
7627 #define C_028810_CLIP_DISABLE 0xFFFEFFFF
7628 #define S_028810_UCP_CULL_ONLY_ENA(x) (((x) & 0x1) << 17)
7629 #define G_028810_UCP_CULL_ONLY_ENA(x) (((x) >> 17) & 0x1)
7630 #define C_028810_UCP_CULL_ONLY_ENA 0xFFFDFFFF
7631 #define S_028810_BOUNDARY_EDGE_FLAG_ENA(x) (((x) & 0x1) << 18)
7632 #define G_028810_BOUNDARY_EDGE_FLAG_ENA(x) (((x) >> 18) & 0x1)
7633 #define C_028810_BOUNDARY_EDGE_FLAG_ENA 0xFFFBFFFF
7634 #define S_028810_DX_CLIP_SPACE_DEF(x) (((x) & 0x1) << 19)
7635 #define G_028810_DX_CLIP_SPACE_DEF(x) (((x) >> 19) & 0x1)
7636 #define C_028810_DX_CLIP_SPACE_DEF 0xFFF7FFFF
7637 #define S_028810_DIS_CLIP_ERR_DETECT(x) (((x) & 0x1) << 20)
7638 #define G_028810_DIS_CLIP_ERR_DETECT(x) (((x) >> 20) & 0x1)
7639 #define C_028810_DIS_CLIP_ERR_DETECT 0xFFEFFFFF
7640 #define S_028810_VTX_KILL_OR(x) (((x) & 0x1) << 21)
7641 #define G_028810_VTX_KILL_OR(x) (((x) >> 21) & 0x1)
7642 #define C_028810_VTX_KILL_OR 0xFFDFFFFF
7643 #define S_028810_DX_RASTERIZATION_KILL(x) (((x) & 0x1) << 22)
7644 #define G_028810_DX_RASTERIZATION_KILL(x) (((x) >> 22) & 0x1)
7645 #define C_028810_DX_RASTERIZATION_KILL 0xFFBFFFFF
7646 #define S_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) & 0x1) << 24)
7647 #define G_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) >> 24) & 0x1)
7648 #define C_028810_DX_LINEAR_ATTR_CLIP_ENA 0xFEFFFFFF
7649 #define S_028810_VTE_VPORT_PROVOKE_DISABLE(x) (((x) & 0x1) << 25)
7650 #define G_028810_VTE_VPORT_PROVOKE_DISABLE(x) (((x) >> 25) & 0x1)
7651 #define C_028810_VTE_VPORT_PROVOKE_DISABLE 0xFDFFFFFF
7652 #define S_028810_ZCLIP_NEAR_DISABLE(x) (((x) & 0x1) << 26)
7653 #define G_028810_ZCLIP_NEAR_DISABLE(x) (((x) >> 26) & 0x1)
7654 #define C_028810_ZCLIP_NEAR_DISABLE 0xFBFFFFFF
7655 #define S_028810_ZCLIP_FAR_DISABLE(x) (((x) & 0x1) << 27)
7656 #define G_028810_ZCLIP_FAR_DISABLE(x) (((x) >> 27) & 0x1)
7657 #define C_028810_ZCLIP_FAR_DISABLE 0xF7FFFFFF
7658 #define R_028814_PA_SU_SC_MODE_CNTL 0x028814
7659 #define S_028814_CULL_FRONT(x) (((x) & 0x1) << 0)
7660 #define G_028814_CULL_FRONT(x) (((x) >> 0) & 0x1)
7661 #define C_028814_CULL_FRONT 0xFFFFFFFE
7662 #define S_028814_CULL_BACK(x) (((x) & 0x1) << 1)
7663 #define G_028814_CULL_BACK(x) (((x) >> 1) & 0x1)
7664 #define C_028814_CULL_BACK 0xFFFFFFFD
7665 #define S_028814_FACE(x) (((x) & 0x1) << 2)
7666 #define G_028814_FACE(x) (((x) >> 2) & 0x1)
7667 #define C_028814_FACE 0xFFFFFFFB
7668 #define S_028814_POLY_MODE(x) (((x) & 0x03) << 3)
7669 #define G_028814_POLY_MODE(x) (((x) >> 3) & 0x03)
7670 #define C_028814_POLY_MODE 0xFFFFFFE7
7671 #define V_028814_X_DISABLE_POLY_MODE 0x00
7672 #define V_028814_X_DUAL_MODE 0x01
7673 #define S_028814_POLYMODE_FRONT_PTYPE(x) (((x) & 0x07) << 5)
7674 #define G_028814_POLYMODE_FRONT_PTYPE(x) (((x) >> 5) & 0x07)
7675 #define C_028814_POLYMODE_FRONT_PTYPE 0xFFFFFF1F
7676 #define V_028814_X_DRAW_POINTS 0x00
7677 #define V_028814_X_DRAW_LINES 0x01
7678 #define V_028814_X_DRAW_TRIANGLES 0x02
7679 #define S_028814_POLYMODE_BACK_PTYPE(x) (((x) & 0x07) << 8)
7680 #define G_028814_POLYMODE_BACK_PTYPE(x) (((x) >> 8) & 0x07)
7681 #define C_028814_POLYMODE_BACK_PTYPE 0xFFFFF8FF
7682 #define V_028814_X_DRAW_POINTS 0x00
7683 #define V_028814_X_DRAW_LINES 0x01
7684 #define V_028814_X_DRAW_TRIANGLES 0x02
7685 #define S_028814_POLY_OFFSET_FRONT_ENABLE(x) (((x) & 0x1) << 11)
7686 #define G_028814_POLY_OFFSET_FRONT_ENABLE(x) (((x) >> 11) & 0x1)
7687 #define C_028814_POLY_OFFSET_FRONT_ENABLE 0xFFFFF7FF
7688 #define S_028814_POLY_OFFSET_BACK_ENABLE(x) (((x) & 0x1) << 12)
7689 #define G_028814_POLY_OFFSET_BACK_ENABLE(x) (((x) >> 12) & 0x1)
7690 #define C_028814_POLY_OFFSET_BACK_ENABLE 0xFFFFEFFF
7691 #define S_028814_POLY_OFFSET_PARA_ENABLE(x) (((x) & 0x1) << 13)
7692 #define G_028814_POLY_OFFSET_PARA_ENABLE(x) (((x) >> 13) & 0x1)
7693 #define C_028814_POLY_OFFSET_PARA_ENABLE 0xFFFFDFFF
7694 #define S_028814_VTX_WINDOW_OFFSET_ENABLE(x) (((x) & 0x1) << 16)
7695 #define G_028814_VTX_WINDOW_OFFSET_ENABLE(x) (((x) >> 16) & 0x1)
7696 #define C_028814_VTX_WINDOW_OFFSET_ENABLE 0xFFFEFFFF
7697 #define S_028814_PROVOKING_VTX_LAST(x) (((x) & 0x1) << 19)
7698 #define G_028814_PROVOKING_VTX_LAST(x) (((x) >> 19) & 0x1)
7699 #define C_028814_PROVOKING_VTX_LAST 0xFFF7FFFF
7700 #define S_028814_PERSP_CORR_DIS(x) (((x) & 0x1) << 20)
7701 #define G_028814_PERSP_CORR_DIS(x) (((x) >> 20) & 0x1)
7702 #define C_028814_PERSP_CORR_DIS 0xFFEFFFFF
7703 #define S_028814_MULTI_PRIM_IB_ENA(x) (((x) & 0x1) << 21)
7704 #define G_028814_MULTI_PRIM_IB_ENA(x) (((x) >> 21) & 0x1)
7705 #define C_028814_MULTI_PRIM_IB_ENA 0xFFDFFFFF
7706 #define R_028818_PA_CL_VTE_CNTL 0x028818
7707 #define S_028818_VPORT_X_SCALE_ENA(x) (((x) & 0x1) << 0)
7708 #define G_028818_VPORT_X_SCALE_ENA(x) (((x) >> 0) & 0x1)
7709 #define C_028818_VPORT_X_SCALE_ENA 0xFFFFFFFE
7710 #define S_028818_VPORT_X_OFFSET_ENA(x) (((x) & 0x1) << 1)
7711 #define G_028818_VPORT_X_OFFSET_ENA(x) (((x) >> 1) & 0x1)
7712 #define C_028818_VPORT_X_OFFSET_ENA 0xFFFFFFFD
7713 #define S_028818_VPORT_Y_SCALE_ENA(x) (((x) & 0x1) << 2)
7714 #define G_028818_VPORT_Y_SCALE_ENA(x) (((x) >> 2) & 0x1)
7715 #define C_028818_VPORT_Y_SCALE_ENA 0xFFFFFFFB
7716 #define S_028818_VPORT_Y_OFFSET_ENA(x) (((x) & 0x1) << 3)
7717 #define G_028818_VPORT_Y_OFFSET_ENA(x) (((x) >> 3) & 0x1)
7718 #define C_028818_VPORT_Y_OFFSET_ENA 0xFFFFFFF7
7719 #define S_028818_VPORT_Z_SCALE_ENA(x) (((x) & 0x1) << 4)
7720 #define G_028818_VPORT_Z_SCALE_ENA(x) (((x) >> 4) & 0x1)
7721 #define C_028818_VPORT_Z_SCALE_ENA 0xFFFFFFEF
7722 #define S_028818_VPORT_Z_OFFSET_ENA(x) (((x) & 0x1) << 5)
7723 #define G_028818_VPORT_Z_OFFSET_ENA(x) (((x) >> 5) & 0x1)
7724 #define C_028818_VPORT_Z_OFFSET_ENA 0xFFFFFFDF
7725 #define S_028818_VTX_XY_FMT(x) (((x) & 0x1) << 8)
7726 #define G_028818_VTX_XY_FMT(x) (((x) >> 8) & 0x1)
7727 #define C_028818_VTX_XY_FMT 0xFFFFFEFF
7728 #define S_028818_VTX_Z_FMT(x) (((x) & 0x1) << 9)
7729 #define G_028818_VTX_Z_FMT(x) (((x) >> 9) & 0x1)
7730 #define C_028818_VTX_Z_FMT 0xFFFFFDFF
7731 #define S_028818_VTX_W0_FMT(x) (((x) & 0x1) << 10)
7732 #define G_028818_VTX_W0_FMT(x) (((x) >> 10) & 0x1)
7733 #define C_028818_VTX_W0_FMT 0xFFFFFBFF
7734 #define R_02881C_PA_CL_VS_OUT_CNTL 0x02881C
7735 #define S_02881C_CLIP_DIST_ENA_0(x) (((x) & 0x1) << 0)
7736 #define G_02881C_CLIP_DIST_ENA_0(x) (((x) >> 0) & 0x1)
7737 #define C_02881C_CLIP_DIST_ENA_0 0xFFFFFFFE
7738 #define S_02881C_CLIP_DIST_ENA_1(x) (((x) & 0x1) << 1)
7739 #define G_02881C_CLIP_DIST_ENA_1(x) (((x) >> 1) & 0x1)
7740 #define C_02881C_CLIP_DIST_ENA_1 0xFFFFFFFD
7741 #define S_02881C_CLIP_DIST_ENA_2(x) (((x) & 0x1) << 2)
7742 #define G_02881C_CLIP_DIST_ENA_2(x) (((x) >> 2) & 0x1)
7743 #define C_02881C_CLIP_DIST_ENA_2 0xFFFFFFFB
7744 #define S_02881C_CLIP_DIST_ENA_3(x) (((x) & 0x1) << 3)
7745 #define G_02881C_CLIP_DIST_ENA_3(x) (((x) >> 3) & 0x1)
7746 #define C_02881C_CLIP_DIST_ENA_3 0xFFFFFFF7
7747 #define S_02881C_CLIP_DIST_ENA_4(x) (((x) & 0x1) << 4)
7748 #define G_02881C_CLIP_DIST_ENA_4(x) (((x) >> 4) & 0x1)
7749 #define C_02881C_CLIP_DIST_ENA_4 0xFFFFFFEF
7750 #define S_02881C_CLIP_DIST_ENA_5(x) (((x) & 0x1) << 5)
7751 #define G_02881C_CLIP_DIST_ENA_5(x) (((x) >> 5) & 0x1)
7752 #define C_02881C_CLIP_DIST_ENA_5 0xFFFFFFDF
7753 #define S_02881C_CLIP_DIST_ENA_6(x) (((x) & 0x1) << 6)
7754 #define G_02881C_CLIP_DIST_ENA_6(x) (((x) >> 6) & 0x1)
7755 #define C_02881C_CLIP_DIST_ENA_6 0xFFFFFFBF
7756 #define S_02881C_CLIP_DIST_ENA_7(x) (((x) & 0x1) << 7)
7757 #define G_02881C_CLIP_DIST_ENA_7(x) (((x) >> 7) & 0x1)
7758 #define C_02881C_CLIP_DIST_ENA_7 0xFFFFFF7F
7759 #define S_02881C_CULL_DIST_ENA_0(x) (((x) & 0x1) << 8)
7760 #define G_02881C_CULL_DIST_ENA_0(x) (((x) >> 8) & 0x1)
7761 #define C_02881C_CULL_DIST_ENA_0 0xFFFFFEFF
7762 #define S_02881C_CULL_DIST_ENA_1(x) (((x) & 0x1) << 9)
7763 #define G_02881C_CULL_DIST_ENA_1(x) (((x) >> 9) & 0x1)
7764 #define C_02881C_CULL_DIST_ENA_1 0xFFFFFDFF
7765 #define S_02881C_CULL_DIST_ENA_2(x) (((x) & 0x1) << 10)
7766 #define G_02881C_CULL_DIST_ENA_2(x) (((x) >> 10) & 0x1)
7767 #define C_02881C_CULL_DIST_ENA_2 0xFFFFFBFF
7768 #define S_02881C_CULL_DIST_ENA_3(x) (((x) & 0x1) << 11)
7769 #define G_02881C_CULL_DIST_ENA_3(x) (((x) >> 11) & 0x1)
7770 #define C_02881C_CULL_DIST_ENA_3 0xFFFFF7FF
7771 #define S_02881C_CULL_DIST_ENA_4(x) (((x) & 0x1) << 12)
7772 #define G_02881C_CULL_DIST_ENA_4(x) (((x) >> 12) & 0x1)
7773 #define C_02881C_CULL_DIST_ENA_4 0xFFFFEFFF
7774 #define S_02881C_CULL_DIST_ENA_5(x) (((x) & 0x1) << 13)
7775 #define G_02881C_CULL_DIST_ENA_5(x) (((x) >> 13) & 0x1)
7776 #define C_02881C_CULL_DIST_ENA_5 0xFFFFDFFF
7777 #define S_02881C_CULL_DIST_ENA_6(x) (((x) & 0x1) << 14)
7778 #define G_02881C_CULL_DIST_ENA_6(x) (((x) >> 14) & 0x1)
7779 #define C_02881C_CULL_DIST_ENA_6 0xFFFFBFFF
7780 #define S_02881C_CULL_DIST_ENA_7(x) (((x) & 0x1) << 15)
7781 #define G_02881C_CULL_DIST_ENA_7(x) (((x) >> 15) & 0x1)
7782 #define C_02881C_CULL_DIST_ENA_7 0xFFFF7FFF
7783 #define S_02881C_USE_VTX_POINT_SIZE(x) (((x) & 0x1) << 16)
7784 #define G_02881C_USE_VTX_POINT_SIZE(x) (((x) >> 16) & 0x1)
7785 #define C_02881C_USE_VTX_POINT_SIZE 0xFFFEFFFF
7786 #define S_02881C_USE_VTX_EDGE_FLAG(x) (((x) & 0x1) << 17)
7787 #define G_02881C_USE_VTX_EDGE_FLAG(x) (((x) >> 17) & 0x1)
7788 #define C_02881C_USE_VTX_EDGE_FLAG 0xFFFDFFFF
7789 #define S_02881C_USE_VTX_RENDER_TARGET_INDX(x) (((x) & 0x1) << 18)
7790 #define G_02881C_USE_VTX_RENDER_TARGET_INDX(x) (((x) >> 18) & 0x1)
7791 #define C_02881C_USE_VTX_RENDER_TARGET_INDX 0xFFFBFFFF
7792 #define S_02881C_USE_VTX_VIEWPORT_INDX(x) (((x) & 0x1) << 19)
7793 #define G_02881C_USE_VTX_VIEWPORT_INDX(x) (((x) >> 19) & 0x1)
7794 #define C_02881C_USE_VTX_VIEWPORT_INDX 0xFFF7FFFF
7795 #define S_02881C_USE_VTX_KILL_FLAG(x) (((x) & 0x1) << 20)
7796 #define G_02881C_USE_VTX_KILL_FLAG(x) (((x) >> 20) & 0x1)
7797 #define C_02881C_USE_VTX_KILL_FLAG 0xFFEFFFFF
7798 #define S_02881C_VS_OUT_MISC_VEC_ENA(x) (((x) & 0x1) << 21)
7799 #define G_02881C_VS_OUT_MISC_VEC_ENA(x) (((x) >> 21) & 0x1)
7800 #define C_02881C_VS_OUT_MISC_VEC_ENA 0xFFDFFFFF
7801 #define S_02881C_VS_OUT_CCDIST0_VEC_ENA(x) (((x) & 0x1) << 22)
7802 #define G_02881C_VS_OUT_CCDIST0_VEC_ENA(x) (((x) >> 22) & 0x1)
7803 #define C_02881C_VS_OUT_CCDIST0_VEC_ENA 0xFFBFFFFF
7804 #define S_02881C_VS_OUT_CCDIST1_VEC_ENA(x) (((x) & 0x1) << 23)
7805 #define G_02881C_VS_OUT_CCDIST1_VEC_ENA(x) (((x) >> 23) & 0x1)
7806 #define C_02881C_VS_OUT_CCDIST1_VEC_ENA 0xFF7FFFFF
7807 #define S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(x) (((x) & 0x1) << 24)
7808 #define G_02881C_VS_OUT_MISC_SIDE_BUS_ENA(x) (((x) >> 24) & 0x1)
7809 #define C_02881C_VS_OUT_MISC_SIDE_BUS_ENA 0xFEFFFFFF
7810 #define S_02881C_USE_VTX_GS_CUT_FLAG(x) (((x) & 0x1) << 25)
7811 #define G_02881C_USE_VTX_GS_CUT_FLAG(x) (((x) >> 25) & 0x1)
7812 #define C_02881C_USE_VTX_GS_CUT_FLAG 0xFDFFFFFF
7813 /* VI */
7814 #define S_02881C_USE_VTX_LINE_WIDTH(x) (((x) & 0x1) << 26)
7815 #define G_02881C_USE_VTX_LINE_WIDTH(x) (((x) >> 26) & 0x1)
7816 #define C_02881C_USE_VTX_LINE_WIDTH 0xFBFFFFFF
7817 /* */
7818 #define R_028820_PA_CL_NANINF_CNTL 0x028820
7819 #define S_028820_VTE_XY_INF_DISCARD(x) (((x) & 0x1) << 0)
7820 #define G_028820_VTE_XY_INF_DISCARD(x) (((x) >> 0) & 0x1)
7821 #define C_028820_VTE_XY_INF_DISCARD 0xFFFFFFFE
7822 #define S_028820_VTE_Z_INF_DISCARD(x) (((x) & 0x1) << 1)
7823 #define G_028820_VTE_Z_INF_DISCARD(x) (((x) >> 1) & 0x1)
7824 #define C_028820_VTE_Z_INF_DISCARD 0xFFFFFFFD
7825 #define S_028820_VTE_W_INF_DISCARD(x) (((x) & 0x1) << 2)
7826 #define G_028820_VTE_W_INF_DISCARD(x) (((x) >> 2) & 0x1)
7827 #define C_028820_VTE_W_INF_DISCARD 0xFFFFFFFB
7828 #define S_028820_VTE_0XNANINF_IS_0(x) (((x) & 0x1) << 3)
7829 #define G_028820_VTE_0XNANINF_IS_0(x) (((x) >> 3) & 0x1)
7830 #define C_028820_VTE_0XNANINF_IS_0 0xFFFFFFF7
7831 #define S_028820_VTE_XY_NAN_RETAIN(x) (((x) & 0x1) << 4)
7832 #define G_028820_VTE_XY_NAN_RETAIN(x) (((x) >> 4) & 0x1)
7833 #define C_028820_VTE_XY_NAN_RETAIN 0xFFFFFFEF
7834 #define S_028820_VTE_Z_NAN_RETAIN(x) (((x) & 0x1) << 5)
7835 #define G_028820_VTE_Z_NAN_RETAIN(x) (((x) >> 5) & 0x1)
7836 #define C_028820_VTE_Z_NAN_RETAIN 0xFFFFFFDF
7837 #define S_028820_VTE_W_NAN_RETAIN(x) (((x) & 0x1) << 6)
7838 #define G_028820_VTE_W_NAN_RETAIN(x) (((x) >> 6) & 0x1)
7839 #define C_028820_VTE_W_NAN_RETAIN 0xFFFFFFBF
7840 #define S_028820_VTE_W_RECIP_NAN_IS_0(x) (((x) & 0x1) << 7)
7841 #define G_028820_VTE_W_RECIP_NAN_IS_0(x) (((x) >> 7) & 0x1)
7842 #define C_028820_VTE_W_RECIP_NAN_IS_0 0xFFFFFF7F
7843 #define S_028820_VS_XY_NAN_TO_INF(x) (((x) & 0x1) << 8)
7844 #define G_028820_VS_XY_NAN_TO_INF(x) (((x) >> 8) & 0x1)
7845 #define C_028820_VS_XY_NAN_TO_INF 0xFFFFFEFF
7846 #define S_028820_VS_XY_INF_RETAIN(x) (((x) & 0x1) << 9)
7847 #define G_028820_VS_XY_INF_RETAIN(x) (((x) >> 9) & 0x1)
7848 #define C_028820_VS_XY_INF_RETAIN 0xFFFFFDFF
7849 #define S_028820_VS_Z_NAN_TO_INF(x) (((x) & 0x1) << 10)
7850 #define G_028820_VS_Z_NAN_TO_INF(x) (((x) >> 10) & 0x1)
7851 #define C_028820_VS_Z_NAN_TO_INF 0xFFFFFBFF
7852 #define S_028820_VS_Z_INF_RETAIN(x) (((x) & 0x1) << 11)
7853 #define G_028820_VS_Z_INF_RETAIN(x) (((x) >> 11) & 0x1)
7854 #define C_028820_VS_Z_INF_RETAIN 0xFFFFF7FF
7855 #define S_028820_VS_W_NAN_TO_INF(x) (((x) & 0x1) << 12)
7856 #define G_028820_VS_W_NAN_TO_INF(x) (((x) >> 12) & 0x1)
7857 #define C_028820_VS_W_NAN_TO_INF 0xFFFFEFFF
7858 #define S_028820_VS_W_INF_RETAIN(x) (((x) & 0x1) << 13)
7859 #define G_028820_VS_W_INF_RETAIN(x) (((x) >> 13) & 0x1)
7860 #define C_028820_VS_W_INF_RETAIN 0xFFFFDFFF
7861 #define S_028820_VS_CLIP_DIST_INF_DISCARD(x) (((x) & 0x1) << 14)
7862 #define G_028820_VS_CLIP_DIST_INF_DISCARD(x) (((x) >> 14) & 0x1)
7863 #define C_028820_VS_CLIP_DIST_INF_DISCARD 0xFFFFBFFF
7864 #define S_028820_VTE_NO_OUTPUT_NEG_0(x) (((x) & 0x1) << 20)
7865 #define G_028820_VTE_NO_OUTPUT_NEG_0(x) (((x) >> 20) & 0x1)
7866 #define C_028820_VTE_NO_OUTPUT_NEG_0 0xFFEFFFFF
7867 #define R_028824_PA_SU_LINE_STIPPLE_CNTL 0x028824
7868 #define S_028824_LINE_STIPPLE_RESET(x) (((x) & 0x03) << 0)
7869 #define G_028824_LINE_STIPPLE_RESET(x) (((x) >> 0) & 0x03)
7870 #define C_028824_LINE_STIPPLE_RESET 0xFFFFFFFC
7871 #define S_028824_EXPAND_FULL_LENGTH(x) (((x) & 0x1) << 2)
7872 #define G_028824_EXPAND_FULL_LENGTH(x) (((x) >> 2) & 0x1)
7873 #define C_028824_EXPAND_FULL_LENGTH 0xFFFFFFFB
7874 #define S_028824_FRACTIONAL_ACCUM(x) (((x) & 0x1) << 3)
7875 #define G_028824_FRACTIONAL_ACCUM(x) (((x) >> 3) & 0x1)
7876 #define C_028824_FRACTIONAL_ACCUM 0xFFFFFFF7
7877 #define S_028824_DIAMOND_ADJUST(x) (((x) & 0x1) << 4)
7878 #define G_028824_DIAMOND_ADJUST(x) (((x) >> 4) & 0x1)
7879 #define C_028824_DIAMOND_ADJUST 0xFFFFFFEF
7880 #define R_028828_PA_SU_LINE_STIPPLE_SCALE 0x028828
7881 #define R_02882C_PA_SU_PRIM_FILTER_CNTL 0x02882C
7882 #define S_02882C_TRIANGLE_FILTER_DISABLE(x) (((x) & 0x1) << 0)
7883 #define G_02882C_TRIANGLE_FILTER_DISABLE(x) (((x) >> 0) & 0x1)
7884 #define C_02882C_TRIANGLE_FILTER_DISABLE 0xFFFFFFFE
7885 #define S_02882C_LINE_FILTER_DISABLE(x) (((x) & 0x1) << 1)
7886 #define G_02882C_LINE_FILTER_DISABLE(x) (((x) >> 1) & 0x1)
7887 #define C_02882C_LINE_FILTER_DISABLE 0xFFFFFFFD
7888 #define S_02882C_POINT_FILTER_DISABLE(x) (((x) & 0x1) << 2)
7889 #define G_02882C_POINT_FILTER_DISABLE(x) (((x) >> 2) & 0x1)
7890 #define C_02882C_POINT_FILTER_DISABLE 0xFFFFFFFB
7891 #define S_02882C_RECTANGLE_FILTER_DISABLE(x) (((x) & 0x1) << 3)
7892 #define G_02882C_RECTANGLE_FILTER_DISABLE(x) (((x) >> 3) & 0x1)
7893 #define C_02882C_RECTANGLE_FILTER_DISABLE 0xFFFFFFF7
7894 #define S_02882C_TRIANGLE_EXPAND_ENA(x) (((x) & 0x1) << 4)
7895 #define G_02882C_TRIANGLE_EXPAND_ENA(x) (((x) >> 4) & 0x1)
7896 #define C_02882C_TRIANGLE_EXPAND_ENA 0xFFFFFFEF
7897 #define S_02882C_LINE_EXPAND_ENA(x) (((x) & 0x1) << 5)
7898 #define G_02882C_LINE_EXPAND_ENA(x) (((x) >> 5) & 0x1)
7899 #define C_02882C_LINE_EXPAND_ENA 0xFFFFFFDF
7900 #define S_02882C_POINT_EXPAND_ENA(x) (((x) & 0x1) << 6)
7901 #define G_02882C_POINT_EXPAND_ENA(x) (((x) >> 6) & 0x1)
7902 #define C_02882C_POINT_EXPAND_ENA 0xFFFFFFBF
7903 #define S_02882C_RECTANGLE_EXPAND_ENA(x) (((x) & 0x1) << 7)
7904 #define G_02882C_RECTANGLE_EXPAND_ENA(x) (((x) >> 7) & 0x1)
7905 #define C_02882C_RECTANGLE_EXPAND_ENA 0xFFFFFF7F
7906 #define S_02882C_PRIM_EXPAND_CONSTANT(x) (((x) & 0xFF) << 8)
7907 #define G_02882C_PRIM_EXPAND_CONSTANT(x) (((x) >> 8) & 0xFF)
7908 #define C_02882C_PRIM_EXPAND_CONSTANT 0xFFFF00FF
7909 /* CIK */
7910 #define S_02882C_XMAX_RIGHT_EXCLUSION(x) (((x) & 0x1) << 30)
7911 #define G_02882C_XMAX_RIGHT_EXCLUSION(x) (((x) >> 30) & 0x1)
7912 #define C_02882C_XMAX_RIGHT_EXCLUSION 0xBFFFFFFF
7913 #define S_02882C_YMAX_BOTTOM_EXCLUSION(x) (((x) & 0x1) << 31)
7914 #define G_02882C_YMAX_BOTTOM_EXCLUSION(x) (((x) >> 31) & 0x1)
7915 #define C_02882C_YMAX_BOTTOM_EXCLUSION 0x7FFFFFFF
7916 /* */
7917 #define R_028A00_PA_SU_POINT_SIZE 0x028A00
7918 #define S_028A00_HEIGHT(x) (((x) & 0xFFFF) << 0)
7919 #define G_028A00_HEIGHT(x) (((x) >> 0) & 0xFFFF)
7920 #define C_028A00_HEIGHT 0xFFFF0000
7921 #define S_028A00_WIDTH(x) (((x) & 0xFFFF) << 16)
7922 #define G_028A00_WIDTH(x) (((x) >> 16) & 0xFFFF)
7923 #define C_028A00_WIDTH 0x0000FFFF
7924 #define R_028A04_PA_SU_POINT_MINMAX 0x028A04
7925 #define S_028A04_MIN_SIZE(x) (((x) & 0xFFFF) << 0)
7926 #define G_028A04_MIN_SIZE(x) (((x) >> 0) & 0xFFFF)
7927 #define C_028A04_MIN_SIZE 0xFFFF0000
7928 #define S_028A04_MAX_SIZE(x) (((x) & 0xFFFF) << 16)
7929 #define G_028A04_MAX_SIZE(x) (((x) >> 16) & 0xFFFF)
7930 #define C_028A04_MAX_SIZE 0x0000FFFF
7931 #define R_028A08_PA_SU_LINE_CNTL 0x028A08
7932 #define S_028A08_WIDTH(x) (((x) & 0xFFFF) << 0)
7933 #define G_028A08_WIDTH(x) (((x) >> 0) & 0xFFFF)
7934 #define C_028A08_WIDTH 0xFFFF0000
7935 #define R_028A0C_PA_SC_LINE_STIPPLE 0x028A0C
7936 #define S_028A0C_LINE_PATTERN(x) (((x) & 0xFFFF) << 0)
7937 #define G_028A0C_LINE_PATTERN(x) (((x) >> 0) & 0xFFFF)
7938 #define C_028A0C_LINE_PATTERN 0xFFFF0000
7939 #define S_028A0C_REPEAT_COUNT(x) (((x) & 0xFF) << 16)
7940 #define G_028A0C_REPEAT_COUNT(x) (((x) >> 16) & 0xFF)
7941 #define C_028A0C_REPEAT_COUNT 0xFF00FFFF
7942 #define S_028A0C_PATTERN_BIT_ORDER(x) (((x) & 0x1) << 28)
7943 #define G_028A0C_PATTERN_BIT_ORDER(x) (((x) >> 28) & 0x1)
7944 #define C_028A0C_PATTERN_BIT_ORDER 0xEFFFFFFF
7945 #define S_028A0C_AUTO_RESET_CNTL(x) (((x) & 0x03) << 29)
7946 #define G_028A0C_AUTO_RESET_CNTL(x) (((x) >> 29) & 0x03)
7947 #define C_028A0C_AUTO_RESET_CNTL 0x9FFFFFFF
7948 #define R_028A10_VGT_OUTPUT_PATH_CNTL 0x028A10
7949 #define S_028A10_PATH_SELECT(x) (((x) & 0x07) << 0)
7950 #define G_028A10_PATH_SELECT(x) (((x) >> 0) & 0x07)
7951 #define C_028A10_PATH_SELECT 0xFFFFFFF8
7952 #define V_028A10_VGT_OUTPATH_VTX_REUSE 0x00
7953 #define V_028A10_VGT_OUTPATH_TESS_EN 0x01
7954 #define V_028A10_VGT_OUTPATH_PASSTHRU 0x02
7955 #define V_028A10_VGT_OUTPATH_GS_BLOCK 0x03
7956 #define V_028A10_VGT_OUTPATH_HS_BLOCK 0x04
7957 #define R_028A14_VGT_HOS_CNTL 0x028A14
7958 #define S_028A14_TESS_MODE(x) (((x) & 0x03) << 0)
7959 #define G_028A14_TESS_MODE(x) (((x) >> 0) & 0x03)
7960 #define C_028A14_TESS_MODE 0xFFFFFFFC
7961 #define R_028A18_VGT_HOS_MAX_TESS_LEVEL 0x028A18
7962 #define R_028A1C_VGT_HOS_MIN_TESS_LEVEL 0x028A1C
7963 #define R_028A20_VGT_HOS_REUSE_DEPTH 0x028A20
7964 #define S_028A20_REUSE_DEPTH(x) (((x) & 0xFF) << 0)
7965 #define G_028A20_REUSE_DEPTH(x) (((x) >> 0) & 0xFF)
7966 #define C_028A20_REUSE_DEPTH 0xFFFFFF00
7967 #define R_028A24_VGT_GROUP_PRIM_TYPE 0x028A24
7968 #define S_028A24_PRIM_TYPE(x) (((x) & 0x1F) << 0)
7969 #define G_028A24_PRIM_TYPE(x) (((x) >> 0) & 0x1F)
7970 #define C_028A24_PRIM_TYPE 0xFFFFFFE0
7971 #define V_028A24_VGT_GRP_3D_POINT 0x00
7972 #define V_028A24_VGT_GRP_3D_LINE 0x01
7973 #define V_028A24_VGT_GRP_3D_TRI 0x02
7974 #define V_028A24_VGT_GRP_3D_RECT 0x03
7975 #define V_028A24_VGT_GRP_3D_QUAD 0x04
7976 #define V_028A24_VGT_GRP_2D_COPY_RECT_V0 0x05
7977 #define V_028A24_VGT_GRP_2D_COPY_RECT_V1 0x06
7978 #define V_028A24_VGT_GRP_2D_COPY_RECT_V2 0x07
7979 #define V_028A24_VGT_GRP_2D_COPY_RECT_V3 0x08
7980 #define V_028A24_VGT_GRP_2D_FILL_RECT 0x09
7981 #define V_028A24_VGT_GRP_2D_LINE 0x0A
7982 #define V_028A24_VGT_GRP_2D_TRI 0x0B
7983 #define V_028A24_VGT_GRP_PRIM_INDEX_LINE 0x0C
7984 #define V_028A24_VGT_GRP_PRIM_INDEX_TRI 0x0D
7985 #define V_028A24_VGT_GRP_PRIM_INDEX_QUAD 0x0E
7986 #define V_028A24_VGT_GRP_3D_LINE_ADJ 0x0F
7987 #define V_028A24_VGT_GRP_3D_TRI_ADJ 0x10
7988 #define V_028A24_VGT_GRP_3D_PATCH 0x11
7989 #define S_028A24_RETAIN_ORDER(x) (((x) & 0x1) << 14)
7990 #define G_028A24_RETAIN_ORDER(x) (((x) >> 14) & 0x1)
7991 #define C_028A24_RETAIN_ORDER 0xFFFFBFFF
7992 #define S_028A24_RETAIN_QUADS(x) (((x) & 0x1) << 15)
7993 #define G_028A24_RETAIN_QUADS(x) (((x) >> 15) & 0x1)
7994 #define C_028A24_RETAIN_QUADS 0xFFFF7FFF
7995 #define S_028A24_PRIM_ORDER(x) (((x) & 0x07) << 16)
7996 #define G_028A24_PRIM_ORDER(x) (((x) >> 16) & 0x07)
7997 #define C_028A24_PRIM_ORDER 0xFFF8FFFF
7998 #define V_028A24_VGT_GRP_LIST 0x00
7999 #define V_028A24_VGT_GRP_STRIP 0x01
8000 #define V_028A24_VGT_GRP_FAN 0x02
8001 #define V_028A24_VGT_GRP_LOOP 0x03
8002 #define V_028A24_VGT_GRP_POLYGON 0x04
8003 #define R_028A28_VGT_GROUP_FIRST_DECR 0x028A28
8004 #define S_028A28_FIRST_DECR(x) (((x) & 0x0F) << 0)
8005 #define G_028A28_FIRST_DECR(x) (((x) >> 0) & 0x0F)
8006 #define C_028A28_FIRST_DECR 0xFFFFFFF0
8007 #define R_028A2C_VGT_GROUP_DECR 0x028A2C
8008 #define S_028A2C_DECR(x) (((x) & 0x0F) << 0)
8009 #define G_028A2C_DECR(x) (((x) >> 0) & 0x0F)
8010 #define C_028A2C_DECR 0xFFFFFFF0
8011 #define R_028A30_VGT_GROUP_VECT_0_CNTL 0x028A30
8012 #define S_028A30_COMP_X_EN(x) (((x) & 0x1) << 0)
8013 #define G_028A30_COMP_X_EN(x) (((x) >> 0) & 0x1)
8014 #define C_028A30_COMP_X_EN 0xFFFFFFFE
8015 #define S_028A30_COMP_Y_EN(x) (((x) & 0x1) << 1)
8016 #define G_028A30_COMP_Y_EN(x) (((x) >> 1) & 0x1)
8017 #define C_028A30_COMP_Y_EN 0xFFFFFFFD
8018 #define S_028A30_COMP_Z_EN(x) (((x) & 0x1) << 2)
8019 #define G_028A30_COMP_Z_EN(x) (((x) >> 2) & 0x1)
8020 #define C_028A30_COMP_Z_EN 0xFFFFFFFB
8021 #define S_028A30_COMP_W_EN(x) (((x) & 0x1) << 3)
8022 #define G_028A30_COMP_W_EN(x) (((x) >> 3) & 0x1)
8023 #define C_028A30_COMP_W_EN 0xFFFFFFF7
8024 #define S_028A30_STRIDE(x) (((x) & 0xFF) << 8)
8025 #define G_028A30_STRIDE(x) (((x) >> 8) & 0xFF)
8026 #define C_028A30_STRIDE 0xFFFF00FF
8027 #define S_028A30_SHIFT(x) (((x) & 0xFF) << 16)
8028 #define G_028A30_SHIFT(x) (((x) >> 16) & 0xFF)
8029 #define C_028A30_SHIFT 0xFF00FFFF
8030 #define R_028A34_VGT_GROUP_VECT_1_CNTL 0x028A34
8031 #define S_028A34_COMP_X_EN(x) (((x) & 0x1) << 0)
8032 #define G_028A34_COMP_X_EN(x) (((x) >> 0) & 0x1)
8033 #define C_028A34_COMP_X_EN 0xFFFFFFFE
8034 #define S_028A34_COMP_Y_EN(x) (((x) & 0x1) << 1)
8035 #define G_028A34_COMP_Y_EN(x) (((x) >> 1) & 0x1)
8036 #define C_028A34_COMP_Y_EN 0xFFFFFFFD
8037 #define S_028A34_COMP_Z_EN(x) (((x) & 0x1) << 2)
8038 #define G_028A34_COMP_Z_EN(x) (((x) >> 2) & 0x1)
8039 #define C_028A34_COMP_Z_EN 0xFFFFFFFB
8040 #define S_028A34_COMP_W_EN(x) (((x) & 0x1) << 3)
8041 #define G_028A34_COMP_W_EN(x) (((x) >> 3) & 0x1)
8042 #define C_028A34_COMP_W_EN 0xFFFFFFF7
8043 #define S_028A34_STRIDE(x) (((x) & 0xFF) << 8)
8044 #define G_028A34_STRIDE(x) (((x) >> 8) & 0xFF)
8045 #define C_028A34_STRIDE 0xFFFF00FF
8046 #define S_028A34_SHIFT(x) (((x) & 0xFF) << 16)
8047 #define G_028A34_SHIFT(x) (((x) >> 16) & 0xFF)
8048 #define C_028A34_SHIFT 0xFF00FFFF
8049 #define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL 0x028A38
8050 #define S_028A38_X_CONV(x) (((x) & 0x0F) << 0)
8051 #define G_028A38_X_CONV(x) (((x) >> 0) & 0x0F)
8052 #define C_028A38_X_CONV 0xFFFFFFF0
8053 #define V_028A38_VGT_GRP_INDEX_16 0x00
8054 #define V_028A38_VGT_GRP_INDEX_32 0x01
8055 #define V_028A38_VGT_GRP_UINT_16 0x02
8056 #define V_028A38_VGT_GRP_UINT_32 0x03
8057 #define V_028A38_VGT_GRP_SINT_16 0x04
8058 #define V_028A38_VGT_GRP_SINT_32 0x05
8059 #define V_028A38_VGT_GRP_FLOAT_32 0x06
8060 #define V_028A38_VGT_GRP_AUTO_PRIM 0x07
8061 #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
8062 #define S_028A38_X_OFFSET(x) (((x) & 0x0F) << 4)
8063 #define G_028A38_X_OFFSET(x) (((x) >> 4) & 0x0F)
8064 #define C_028A38_X_OFFSET 0xFFFFFF0F
8065 #define S_028A38_Y_CONV(x) (((x) & 0x0F) << 8)
8066 #define G_028A38_Y_CONV(x) (((x) >> 8) & 0x0F)
8067 #define C_028A38_Y_CONV 0xFFFFF0FF
8068 #define V_028A38_VGT_GRP_INDEX_16 0x00
8069 #define V_028A38_VGT_GRP_INDEX_32 0x01
8070 #define V_028A38_VGT_GRP_UINT_16 0x02
8071 #define V_028A38_VGT_GRP_UINT_32 0x03
8072 #define V_028A38_VGT_GRP_SINT_16 0x04
8073 #define V_028A38_VGT_GRP_SINT_32 0x05
8074 #define V_028A38_VGT_GRP_FLOAT_32 0x06
8075 #define V_028A38_VGT_GRP_AUTO_PRIM 0x07
8076 #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
8077 #define S_028A38_Y_OFFSET(x) (((x) & 0x0F) << 12)
8078 #define G_028A38_Y_OFFSET(x) (((x) >> 12) & 0x0F)
8079 #define C_028A38_Y_OFFSET 0xFFFF0FFF
8080 #define S_028A38_Z_CONV(x) (((x) & 0x0F) << 16)
8081 #define G_028A38_Z_CONV(x) (((x) >> 16) & 0x0F)
8082 #define C_028A38_Z_CONV 0xFFF0FFFF
8083 #define V_028A38_VGT_GRP_INDEX_16 0x00
8084 #define V_028A38_VGT_GRP_INDEX_32 0x01
8085 #define V_028A38_VGT_GRP_UINT_16 0x02
8086 #define V_028A38_VGT_GRP_UINT_32 0x03
8087 #define V_028A38_VGT_GRP_SINT_16 0x04
8088 #define V_028A38_VGT_GRP_SINT_32 0x05
8089 #define V_028A38_VGT_GRP_FLOAT_32 0x06
8090 #define V_028A38_VGT_GRP_AUTO_PRIM 0x07
8091 #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
8092 #define S_028A38_Z_OFFSET(x) (((x) & 0x0F) << 20)
8093 #define G_028A38_Z_OFFSET(x) (((x) >> 20) & 0x0F)
8094 #define C_028A38_Z_OFFSET 0xFF0FFFFF
8095 #define S_028A38_W_CONV(x) (((x) & 0x0F) << 24)
8096 #define G_028A38_W_CONV(x) (((x) >> 24) & 0x0F)
8097 #define C_028A38_W_CONV 0xF0FFFFFF
8098 #define V_028A38_VGT_GRP_INDEX_16 0x00
8099 #define V_028A38_VGT_GRP_INDEX_32 0x01
8100 #define V_028A38_VGT_GRP_UINT_16 0x02
8101 #define V_028A38_VGT_GRP_UINT_32 0x03
8102 #define V_028A38_VGT_GRP_SINT_16 0x04
8103 #define V_028A38_VGT_GRP_SINT_32 0x05
8104 #define V_028A38_VGT_GRP_FLOAT_32 0x06
8105 #define V_028A38_VGT_GRP_AUTO_PRIM 0x07
8106 #define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
8107 #define S_028A38_W_OFFSET(x) (((x) & 0x0F) << 28)
8108 #define G_028A38_W_OFFSET(x) (((x) >> 28) & 0x0F)
8109 #define C_028A38_W_OFFSET 0x0FFFFFFF
8110 #define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL 0x028A3C
8111 #define S_028A3C_X_CONV(x) (((x) & 0x0F) << 0)
8112 #define G_028A3C_X_CONV(x) (((x) >> 0) & 0x0F)
8113 #define C_028A3C_X_CONV 0xFFFFFFF0
8114 #define V_028A3C_VGT_GRP_INDEX_16 0x00
8115 #define V_028A3C_VGT_GRP_INDEX_32 0x01
8116 #define V_028A3C_VGT_GRP_UINT_16 0x02
8117 #define V_028A3C_VGT_GRP_UINT_32 0x03
8118 #define V_028A3C_VGT_GRP_SINT_16 0x04
8119 #define V_028A3C_VGT_GRP_SINT_32 0x05
8120 #define V_028A3C_VGT_GRP_FLOAT_32 0x06
8121 #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07
8122 #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
8123 #define S_028A3C_X_OFFSET(x) (((x) & 0x0F) << 4)
8124 #define G_028A3C_X_OFFSET(x) (((x) >> 4) & 0x0F)
8125 #define C_028A3C_X_OFFSET 0xFFFFFF0F
8126 #define S_028A3C_Y_CONV(x) (((x) & 0x0F) << 8)
8127 #define G_028A3C_Y_CONV(x) (((x) >> 8) & 0x0F)
8128 #define C_028A3C_Y_CONV 0xFFFFF0FF
8129 #define V_028A3C_VGT_GRP_INDEX_16 0x00
8130 #define V_028A3C_VGT_GRP_INDEX_32 0x01
8131 #define V_028A3C_VGT_GRP_UINT_16 0x02
8132 #define V_028A3C_VGT_GRP_UINT_32 0x03
8133 #define V_028A3C_VGT_GRP_SINT_16 0x04
8134 #define V_028A3C_VGT_GRP_SINT_32 0x05
8135 #define V_028A3C_VGT_GRP_FLOAT_32 0x06
8136 #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07
8137 #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
8138 #define S_028A3C_Y_OFFSET(x) (((x) & 0x0F) << 12)
8139 #define G_028A3C_Y_OFFSET(x) (((x) >> 12) & 0x0F)
8140 #define C_028A3C_Y_OFFSET 0xFFFF0FFF
8141 #define S_028A3C_Z_CONV(x) (((x) & 0x0F) << 16)
8142 #define G_028A3C_Z_CONV(x) (((x) >> 16) & 0x0F)
8143 #define C_028A3C_Z_CONV 0xFFF0FFFF
8144 #define V_028A3C_VGT_GRP_INDEX_16 0x00
8145 #define V_028A3C_VGT_GRP_INDEX_32 0x01
8146 #define V_028A3C_VGT_GRP_UINT_16 0x02
8147 #define V_028A3C_VGT_GRP_UINT_32 0x03
8148 #define V_028A3C_VGT_GRP_SINT_16 0x04
8149 #define V_028A3C_VGT_GRP_SINT_32 0x05
8150 #define V_028A3C_VGT_GRP_FLOAT_32 0x06
8151 #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07
8152 #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
8153 #define S_028A3C_Z_OFFSET(x) (((x) & 0x0F) << 20)
8154 #define G_028A3C_Z_OFFSET(x) (((x) >> 20) & 0x0F)
8155 #define C_028A3C_Z_OFFSET 0xFF0FFFFF
8156 #define S_028A3C_W_CONV(x) (((x) & 0x0F) << 24)
8157 #define G_028A3C_W_CONV(x) (((x) >> 24) & 0x0F)
8158 #define C_028A3C_W_CONV 0xF0FFFFFF
8159 #define V_028A3C_VGT_GRP_INDEX_16 0x00
8160 #define V_028A3C_VGT_GRP_INDEX_32 0x01
8161 #define V_028A3C_VGT_GRP_UINT_16 0x02
8162 #define V_028A3C_VGT_GRP_UINT_32 0x03
8163 #define V_028A3C_VGT_GRP_SINT_16 0x04
8164 #define V_028A3C_VGT_GRP_SINT_32 0x05
8165 #define V_028A3C_VGT_GRP_FLOAT_32 0x06
8166 #define V_028A3C_VGT_GRP_AUTO_PRIM 0x07
8167 #define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08
8168 #define S_028A3C_W_OFFSET(x) (((x) & 0x0F) << 28)
8169 #define G_028A3C_W_OFFSET(x) (((x) >> 28) & 0x0F)
8170 #define C_028A3C_W_OFFSET 0x0FFFFFFF
8171 #define R_028A40_VGT_GS_MODE 0x028A40
8172 #define S_028A40_MODE(x) (((x) & 0x07) << 0)
8173 #define G_028A40_MODE(x) (((x) >> 0) & 0x07)
8174 #define C_028A40_MODE 0xFFFFFFF8
8175 #define V_028A40_GS_OFF 0x00
8176 #define V_028A40_GS_SCENARIO_A 0x01
8177 #define V_028A40_GS_SCENARIO_B 0x02
8178 #define V_028A40_GS_SCENARIO_G 0x03
8179 #define V_028A40_GS_SCENARIO_C 0x04
8180 #define V_028A40_SPRITE_EN 0x05
8181 #define S_028A40_CUT_MODE(x) (((x) & 0x03) << 4)
8182 #define G_028A40_CUT_MODE(x) (((x) >> 4) & 0x03)
8183 #define C_028A40_CUT_MODE 0xFFFFFFCF
8184 #define V_028A40_GS_CUT_1024 0x00
8185 #define V_028A40_GS_CUT_512 0x01
8186 #define V_028A40_GS_CUT_256 0x02
8187 #define V_028A40_GS_CUT_128 0x03
8188 #define S_028A40_GS_C_PACK_EN(x) (((x) & 0x1) << 11)
8189 #define G_028A40_GS_C_PACK_EN(x) (((x) >> 11) & 0x1)
8190 #define C_028A40_GS_C_PACK_EN 0xFFFFF7FF
8191 #define S_028A40_ES_PASSTHRU(x) (((x) & 0x1) << 13)
8192 #define G_028A40_ES_PASSTHRU(x) (((x) >> 13) & 0x1)
8193 #define C_028A40_ES_PASSTHRU 0xFFFFDFFF
8194 #define S_028A40_COMPUTE_MODE(x) (((x) & 0x1) << 14)
8195 #define G_028A40_COMPUTE_MODE(x) (((x) >> 14) & 0x1)
8196 #define C_028A40_COMPUTE_MODE 0xFFFFBFFF
8197 #define S_028A40_FAST_COMPUTE_MODE(x) (((x) & 0x1) << 15)
8198 #define G_028A40_FAST_COMPUTE_MODE(x) (((x) >> 15) & 0x1)
8199 #define C_028A40_FAST_COMPUTE_MODE 0xFFFF7FFF
8200 #define S_028A40_ELEMENT_INFO_EN(x) (((x) & 0x1) << 16)
8201 #define G_028A40_ELEMENT_INFO_EN(x) (((x) >> 16) & 0x1)
8202 #define C_028A40_ELEMENT_INFO_EN 0xFFFEFFFF
8203 #define S_028A40_PARTIAL_THD_AT_EOI(x) (((x) & 0x1) << 17)
8204 #define G_028A40_PARTIAL_THD_AT_EOI(x) (((x) >> 17) & 0x1)
8205 #define C_028A40_PARTIAL_THD_AT_EOI 0xFFFDFFFF
8206 #define S_028A40_SUPPRESS_CUTS(x) (((x) & 0x1) << 18)
8207 #define G_028A40_SUPPRESS_CUTS(x) (((x) >> 18) & 0x1)
8208 #define C_028A40_SUPPRESS_CUTS 0xFFFBFFFF
8209 #define S_028A40_ES_WRITE_OPTIMIZE(x) (((x) & 0x1) << 19)
8210 #define G_028A40_ES_WRITE_OPTIMIZE(x) (((x) >> 19) & 0x1)
8211 #define C_028A40_ES_WRITE_OPTIMIZE 0xFFF7FFFF
8212 #define S_028A40_GS_WRITE_OPTIMIZE(x) (((x) & 0x1) << 20)
8213 #define G_028A40_GS_WRITE_OPTIMIZE(x) (((x) >> 20) & 0x1)
8214 #define C_028A40_GS_WRITE_OPTIMIZE 0xFFEFFFFF
8215 /* CIK */
8216 #define S_028A40_ONCHIP(x) (((x) & 0x03) << 21)
8217 #define G_028A40_ONCHIP(x) (((x) >> 21) & 0x03)
8218 #define C_028A40_ONCHIP 0xFF9FFFFF
8219 #define V_028A40_X_0_OFFCHIP_GS 0x00
8220 #define V_028A40_X_3_ES_AND_GS_ARE_ONCHIP 0x03
8221 #define R_028A44_VGT_GS_ONCHIP_CNTL 0x028A44
8222 #define S_028A44_ES_VERTS_PER_SUBGRP(x) (((x) & 0x7FF) << 0)
8223 #define G_028A44_ES_VERTS_PER_SUBGRP(x) (((x) >> 0) & 0x7FF)
8224 #define C_028A44_ES_VERTS_PER_SUBGRP 0xFFFFF800
8225 #define S_028A44_GS_PRIMS_PER_SUBGRP(x) (((x) & 0x7FF) << 11)
8226 #define G_028A44_GS_PRIMS_PER_SUBGRP(x) (((x) >> 11) & 0x7FF)
8227 #define C_028A44_GS_PRIMS_PER_SUBGRP 0xFFC007FF
8228 /* */
8229 #define R_028A48_PA_SC_MODE_CNTL_0 0x028A48
8230 #define S_028A48_MSAA_ENABLE(x) (((x) & 0x1) << 0)
8231 #define G_028A48_MSAA_ENABLE(x) (((x) >> 0) & 0x1)
8232 #define C_028A48_MSAA_ENABLE 0xFFFFFFFE
8233 #define S_028A48_VPORT_SCISSOR_ENABLE(x) (((x) & 0x1) << 1)
8234 #define G_028A48_VPORT_SCISSOR_ENABLE(x) (((x) >> 1) & 0x1)
8235 #define C_028A48_VPORT_SCISSOR_ENABLE 0xFFFFFFFD
8236 #define S_028A48_LINE_STIPPLE_ENABLE(x) (((x) & 0x1) << 2)
8237 #define G_028A48_LINE_STIPPLE_ENABLE(x) (((x) >> 2) & 0x1)
8238 #define C_028A48_LINE_STIPPLE_ENABLE 0xFFFFFFFB
8239 #define S_028A48_SEND_UNLIT_STILES_TO_PKR(x) (((x) & 0x1) << 3)
8240 #define G_028A48_SEND_UNLIT_STILES_TO_PKR(x) (((x) >> 3) & 0x1)
8241 #define C_028A48_SEND_UNLIT_STILES_TO_PKR 0xFFFFFFF7
8242 #define R_028A4C_PA_SC_MODE_CNTL_1 0x028A4C
8243 #define S_028A4C_WALK_SIZE(x) (((x) & 0x1) << 0)
8244 #define G_028A4C_WALK_SIZE(x) (((x) >> 0) & 0x1)
8245 #define C_028A4C_WALK_SIZE 0xFFFFFFFE
8246 #define S_028A4C_WALK_ALIGNMENT(x) (((x) & 0x1) << 1)
8247 #define G_028A4C_WALK_ALIGNMENT(x) (((x) >> 1) & 0x1)
8248 #define C_028A4C_WALK_ALIGNMENT 0xFFFFFFFD
8249 #define S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) & 0x1) << 2)
8250 #define G_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) >> 2) & 0x1)
8251 #define C_028A4C_WALK_ALIGN8_PRIM_FITS_ST 0xFFFFFFFB
8252 #define S_028A4C_WALK_FENCE_ENABLE(x) (((x) & 0x1) << 3)
8253 #define G_028A4C_WALK_FENCE_ENABLE(x) (((x) >> 3) & 0x1)
8254 #define C_028A4C_WALK_FENCE_ENABLE 0xFFFFFFF7
8255 #define S_028A4C_WALK_FENCE_SIZE(x) (((x) & 0x07) << 4)
8256 #define G_028A4C_WALK_FENCE_SIZE(x) (((x) >> 4) & 0x07)
8257 #define C_028A4C_WALK_FENCE_SIZE 0xFFFFFF8F
8258 #define S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(x) (((x) & 0x1) << 7)
8259 #define G_028A4C_SUPERTILE_WALK_ORDER_ENABLE(x) (((x) >> 7) & 0x1)
8260 #define C_028A4C_SUPERTILE_WALK_ORDER_ENABLE 0xFFFFFF7F
8261 #define S_028A4C_TILE_WALK_ORDER_ENABLE(x) (((x) & 0x1) << 8)
8262 #define G_028A4C_TILE_WALK_ORDER_ENABLE(x) (((x) >> 8) & 0x1)
8263 #define C_028A4C_TILE_WALK_ORDER_ENABLE 0xFFFFFEFF
8264 #define S_028A4C_TILE_COVER_DISABLE(x) (((x) & 0x1) << 9)
8265 #define G_028A4C_TILE_COVER_DISABLE(x) (((x) >> 9) & 0x1)
8266 #define C_028A4C_TILE_COVER_DISABLE 0xFFFFFDFF
8267 #define S_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) & 0x1) << 10)
8268 #define G_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) >> 10) & 0x1)
8269 #define C_028A4C_TILE_COVER_NO_SCISSOR 0xFFFFFBFF
8270 #define S_028A4C_ZMM_LINE_EXTENT(x) (((x) & 0x1) << 11)
8271 #define G_028A4C_ZMM_LINE_EXTENT(x) (((x) >> 11) & 0x1)
8272 #define C_028A4C_ZMM_LINE_EXTENT 0xFFFFF7FF
8273 #define S_028A4C_ZMM_LINE_OFFSET(x) (((x) & 0x1) << 12)
8274 #define G_028A4C_ZMM_LINE_OFFSET(x) (((x) >> 12) & 0x1)
8275 #define C_028A4C_ZMM_LINE_OFFSET 0xFFFFEFFF
8276 #define S_028A4C_ZMM_RECT_EXTENT(x) (((x) & 0x1) << 13)
8277 #define G_028A4C_ZMM_RECT_EXTENT(x) (((x) >> 13) & 0x1)
8278 #define C_028A4C_ZMM_RECT_EXTENT 0xFFFFDFFF
8279 #define S_028A4C_KILL_PIX_POST_HI_Z(x) (((x) & 0x1) << 14)
8280 #define G_028A4C_KILL_PIX_POST_HI_Z(x) (((x) >> 14) & 0x1)
8281 #define C_028A4C_KILL_PIX_POST_HI_Z 0xFFFFBFFF
8282 #define S_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) & 0x1) << 15)
8283 #define G_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) >> 15) & 0x1)
8284 #define C_028A4C_KILL_PIX_POST_DETAIL_MASK 0xFFFF7FFF
8285 #define S_028A4C_PS_ITER_SAMPLE(x) (((x) & 0x1) << 16)
8286 #define G_028A4C_PS_ITER_SAMPLE(x) (((x) >> 16) & 0x1)
8287 #define C_028A4C_PS_ITER_SAMPLE 0xFFFEFFFF
8288 #define S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(x) (((x) & 0x1) << 17)
8289 #define G_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(x) (((x) >> 17) & 0x1)
8290 #define C_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE 0xFFFDFFFF
8291 #define S_028A4C_MULTI_GPU_SUPERTILE_ENABLE(x) (((x) & 0x1) << 18)
8292 #define G_028A4C_MULTI_GPU_SUPERTILE_ENABLE(x) (((x) >> 18) & 0x1)
8293 #define C_028A4C_MULTI_GPU_SUPERTILE_ENABLE 0xFFFBFFFF
8294 #define S_028A4C_GPU_ID_OVERRIDE_ENABLE(x) (((x) & 0x1) << 19)
8295 #define G_028A4C_GPU_ID_OVERRIDE_ENABLE(x) (((x) >> 19) & 0x1)
8296 #define C_028A4C_GPU_ID_OVERRIDE_ENABLE 0xFFF7FFFF
8297 #define S_028A4C_GPU_ID_OVERRIDE(x) (((x) & 0x0F) << 20)
8298 #define G_028A4C_GPU_ID_OVERRIDE(x) (((x) >> 20) & 0x0F)
8299 #define C_028A4C_GPU_ID_OVERRIDE 0xFF0FFFFF
8300 #define S_028A4C_MULTI_GPU_PRIM_DISCARD_ENABLE(x) (((x) & 0x1) << 24)
8301 #define G_028A4C_MULTI_GPU_PRIM_DISCARD_ENABLE(x) (((x) >> 24) & 0x1)
8302 #define C_028A4C_MULTI_GPU_PRIM_DISCARD_ENABLE 0xFEFFFFFF
8303 #define S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) & 0x1) << 25)
8304 #define G_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) >> 25) & 0x1)
8305 #define C_028A4C_FORCE_EOV_CNTDWN_ENABLE 0xFDFFFFFF
8306 #define S_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) & 0x1) << 26)
8307 #define G_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) >> 26) & 0x1)
8308 #define C_028A4C_FORCE_EOV_REZ_ENABLE 0xFBFFFFFF
8309 #define S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(x) (((x) & 0x1) << 27)
8310 #define G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(x) (((x) >> 27) & 0x1)
8311 #define C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE 0xF7FFFFFF
8312 #define S_028A4C_OUT_OF_ORDER_WATER_MARK(x) (((x) & 0x07) << 28)
8313 #define G_028A4C_OUT_OF_ORDER_WATER_MARK(x) (((x) >> 28) & 0x07)
8314 #define C_028A4C_OUT_OF_ORDER_WATER_MARK 0x8FFFFFFF
8315 #define R_028A50_VGT_ENHANCE 0x028A50
8316 #define R_028A54_VGT_GS_PER_ES 0x028A54
8317 #define S_028A54_GS_PER_ES(x) (((x) & 0x7FF) << 0)
8318 #define G_028A54_GS_PER_ES(x) (((x) >> 0) & 0x7FF)
8319 #define C_028A54_GS_PER_ES 0xFFFFF800
8320 #define R_028A58_VGT_ES_PER_GS 0x028A58
8321 #define S_028A58_ES_PER_GS(x) (((x) & 0x7FF) << 0)
8322 #define G_028A58_ES_PER_GS(x) (((x) >> 0) & 0x7FF)
8323 #define C_028A58_ES_PER_GS 0xFFFFF800
8324 #define R_028A5C_VGT_GS_PER_VS 0x028A5C
8325 #define S_028A5C_GS_PER_VS(x) (((x) & 0x0F) << 0)
8326 #define G_028A5C_GS_PER_VS(x) (((x) >> 0) & 0x0F)
8327 #define C_028A5C_GS_PER_VS 0xFFFFFFF0
8328 #define R_028A60_VGT_GSVS_RING_OFFSET_1 0x028A60
8329 #define S_028A60_OFFSET(x) (((x) & 0x7FFF) << 0)
8330 #define G_028A60_OFFSET(x) (((x) >> 0) & 0x7FFF)
8331 #define C_028A60_OFFSET 0xFFFF8000
8332 #define R_028A64_VGT_GSVS_RING_OFFSET_2 0x028A64
8333 #define S_028A64_OFFSET(x) (((x) & 0x7FFF) << 0)
8334 #define G_028A64_OFFSET(x) (((x) >> 0) & 0x7FFF)
8335 #define C_028A64_OFFSET 0xFFFF8000
8336 #define R_028A68_VGT_GSVS_RING_OFFSET_3 0x028A68
8337 #define S_028A68_OFFSET(x) (((x) & 0x7FFF) << 0)
8338 #define G_028A68_OFFSET(x) (((x) >> 0) & 0x7FFF)
8339 #define C_028A68_OFFSET 0xFFFF8000
8340 #define R_028A6C_VGT_GS_OUT_PRIM_TYPE 0x028A6C
8341 #define S_028A6C_OUTPRIM_TYPE(x) (((x) & 0x3F) << 0)
8342 #define G_028A6C_OUTPRIM_TYPE(x) (((x) >> 0) & 0x3F)
8343 #define C_028A6C_OUTPRIM_TYPE 0xFFFFFFC0
8344 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
8345 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
8346 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
8347 #define S_028A6C_OUTPRIM_TYPE_1(x) (((x) & 0x3F) << 8)
8348 #define G_028A6C_OUTPRIM_TYPE_1(x) (((x) >> 8) & 0x3F)
8349 #define C_028A6C_OUTPRIM_TYPE_1 0xFFFFC0FF
8350 #define S_028A6C_OUTPRIM_TYPE_2(x) (((x) & 0x3F) << 16)
8351 #define G_028A6C_OUTPRIM_TYPE_2(x) (((x) >> 16) & 0x3F)
8352 #define C_028A6C_OUTPRIM_TYPE_2 0xFFC0FFFF
8353 #define S_028A6C_OUTPRIM_TYPE_3(x) (((x) & 0x3F) << 22)
8354 #define G_028A6C_OUTPRIM_TYPE_3(x) (((x) >> 22) & 0x3F)
8355 #define C_028A6C_OUTPRIM_TYPE_3 0xF03FFFFF
8356 #define S_028A6C_UNIQUE_TYPE_PER_STREAM(x) (((x) & 0x1) << 31)
8357 #define G_028A6C_UNIQUE_TYPE_PER_STREAM(x) (((x) >> 31) & 0x1)
8358 #define C_028A6C_UNIQUE_TYPE_PER_STREAM 0x7FFFFFFF
8359 #define R_028A70_IA_ENHANCE 0x028A70
8360 #define R_028A74_VGT_DMA_SIZE 0x028A74
8361 #define R_028A78_VGT_DMA_MAX_SIZE 0x028A78
8362 #define R_028A7C_VGT_DMA_INDEX_TYPE 0x028A7C
8363 #define S_028A7C_INDEX_TYPE(x) (((x) & 0x03) << 0)
8364 #define G_028A7C_INDEX_TYPE(x) (((x) >> 0) & 0x03)
8365 #define C_028A7C_INDEX_TYPE 0xFFFFFFFC
8366 #define V_028A7C_VGT_INDEX_16 0x00
8367 #define V_028A7C_VGT_INDEX_32 0x01
8368 #define V_028A7C_VGT_INDEX_8 0x02 /* VI */
8369 #define S_028A7C_SWAP_MODE(x) (((x) & 0x03) << 2)
8370 #define G_028A7C_SWAP_MODE(x) (((x) >> 2) & 0x03)
8371 #define C_028A7C_SWAP_MODE 0xFFFFFFF3
8372 #define V_028A7C_VGT_DMA_SWAP_NONE 0x00
8373 #define V_028A7C_VGT_DMA_SWAP_16_BIT 0x01
8374 #define V_028A7C_VGT_DMA_SWAP_32_BIT 0x02
8375 #define V_028A7C_VGT_DMA_SWAP_WORD 0x03
8376 /* CIK */
8377 #define S_028A7C_BUF_TYPE(x) (((x) & 0x03) << 4)
8378 #define G_028A7C_BUF_TYPE(x) (((x) >> 4) & 0x03)
8379 #define C_028A7C_BUF_TYPE 0xFFFFFFCF
8380 #define V_028A7C_VGT_DMA_BUF_MEM 0x00
8381 #define V_028A7C_VGT_DMA_BUF_RING 0x01
8382 #define V_028A7C_VGT_DMA_BUF_SETUP 0x02
8383 #define S_028A7C_RDREQ_POLICY(x) (((x) & 0x03) << 6)
8384 #define G_028A7C_RDREQ_POLICY(x) (((x) >> 6) & 0x03)
8385 #define C_028A7C_RDREQ_POLICY 0xFFFFFF3F
8386 #define V_028A7C_VGT_POLICY_LRU 0x00
8387 #define V_028A7C_VGT_POLICY_STREAM 0x01
8388 #define S_028A7C_ATC(x) (((x) & 0x1) << 8)
8389 #define G_028A7C_ATC(x) (((x) >> 8) & 0x1)
8390 #define C_028A7C_ATC 0xFFFFFEFF
8391 #define S_028A7C_NOT_EOP(x) (((x) & 0x1) << 9)
8392 #define G_028A7C_NOT_EOP(x) (((x) >> 9) & 0x1)
8393 #define C_028A7C_NOT_EOP 0xFFFFFDFF
8394 #define S_028A7C_REQ_PATH(x) (((x) & 0x1) << 10)
8395 #define G_028A7C_REQ_PATH(x) (((x) >> 10) & 0x1)
8396 #define C_028A7C_REQ_PATH 0xFFFFFBFF
8397 /* */
8398 /* VI */
8399 #define S_028A7C_MTYPE(x) (((x) & 0x03) << 11)
8400 #define G_028A7C_MTYPE(x) (((x) >> 11) & 0x03)
8401 #define C_028A7C_MTYPE 0xFFFFE7FF
8402 /* */
8403 #define R_028A80_WD_ENHANCE 0x028A80
8404 #define R_028A84_VGT_PRIMITIVEID_EN 0x028A84
8405 #define S_028A84_PRIMITIVEID_EN(x) (((x) & 0x1) << 0)
8406 #define G_028A84_PRIMITIVEID_EN(x) (((x) >> 0) & 0x1)
8407 #define C_028A84_PRIMITIVEID_EN 0xFFFFFFFE
8408 #define S_028A84_DISABLE_RESET_ON_EOI(x) (((x) & 0x1) << 1) /* not on CIK */
8409 #define G_028A84_DISABLE_RESET_ON_EOI(x) (((x) >> 1) & 0x1) /* not on CIK */
8410 #define C_028A84_DISABLE_RESET_ON_EOI 0xFFFFFFFD /* not on CIK */
8411 #define R_028A88_VGT_DMA_NUM_INSTANCES 0x028A88
8412 #define R_028A8C_VGT_PRIMITIVEID_RESET 0x028A8C
8413 #define R_028A90_VGT_EVENT_INITIATOR 0x028A90
8414 #define S_028A90_EVENT_TYPE(x) (((x) & 0x3F) << 0)
8415 #define G_028A90_EVENT_TYPE(x) (((x) >> 0) & 0x3F)
8416 #define C_028A90_EVENT_TYPE 0xFFFFFFC0
8417 #define V_028A90_SAMPLE_STREAMOUTSTATS1 0x01
8418 #define V_028A90_SAMPLE_STREAMOUTSTATS2 0x02
8419 #define V_028A90_SAMPLE_STREAMOUTSTATS3 0x03
8420 #define V_028A90_CACHE_FLUSH_TS 0x04
8421 #define V_028A90_CONTEXT_DONE 0x05
8422 #define V_028A90_CACHE_FLUSH 0x06
8423 #define V_028A90_CS_PARTIAL_FLUSH 0x07
8424 #define V_028A90_VGT_STREAMOUT_SYNC 0x08
8425 #define V_028A90_VGT_STREAMOUT_RESET 0x0A
8426 #define V_028A90_END_OF_PIPE_INCR_DE 0x0B
8427 #define V_028A90_END_OF_PIPE_IB_END 0x0C
8428 #define V_028A90_RST_PIX_CNT 0x0D
8429 #define V_028A90_VS_PARTIAL_FLUSH 0x0F
8430 #define V_028A90_PS_PARTIAL_FLUSH 0x10
8431 #define V_028A90_FLUSH_HS_OUTPUT 0x11
8432 #define V_028A90_FLUSH_LS_OUTPUT 0x12
8433 #define V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT 0x14
8434 #define V_028A90_ZPASS_DONE 0x15 /* not on CIK */
8435 #define V_028A90_CACHE_FLUSH_AND_INV_EVENT 0x16
8436 #define V_028A90_PERFCOUNTER_START 0x17
8437 #define V_028A90_PERFCOUNTER_STOP 0x18
8438 #define V_028A90_PIPELINESTAT_START 0x19
8439 #define V_028A90_PIPELINESTAT_STOP 0x1A
8440 #define V_028A90_PERFCOUNTER_SAMPLE 0x1B
8441 #define V_028A90_FLUSH_ES_OUTPUT 0x1C
8442 #define V_028A90_FLUSH_GS_OUTPUT 0x1D
8443 #define V_028A90_SAMPLE_PIPELINESTAT 0x1E
8444 #define V_028A90_SO_VGTSTREAMOUT_FLUSH 0x1F
8445 #define V_028A90_SAMPLE_STREAMOUTSTATS 0x20
8446 #define V_028A90_RESET_VTX_CNT 0x21
8447 #define V_028A90_BLOCK_CONTEXT_DONE 0x22
8448 #define V_028A90_CS_CONTEXT_DONE 0x23
8449 #define V_028A90_VGT_FLUSH 0x24
8450 #define V_028A90_SC_SEND_DB_VPZ 0x27
8451 #define V_028A90_BOTTOM_OF_PIPE_TS 0x28
8452 #define V_028A90_DB_CACHE_FLUSH_AND_INV 0x2A
8453 #define V_028A90_FLUSH_AND_INV_DB_DATA_TS 0x2B
8454 #define V_028A90_FLUSH_AND_INV_DB_META 0x2C
8455 #define V_028A90_FLUSH_AND_INV_CB_DATA_TS 0x2D
8456 #define V_028A90_FLUSH_AND_INV_CB_META 0x2E
8457 #define V_028A90_CS_DONE 0x2F
8458 #define V_028A90_PS_DONE 0x30
8459 #define V_028A90_FLUSH_AND_INV_CB_PIXEL_DATA 0x31
8460 #define V_028A90_THREAD_TRACE_START 0x33
8461 #define V_028A90_THREAD_TRACE_STOP 0x34
8462 #define V_028A90_THREAD_TRACE_MARKER 0x35
8463 #define V_028A90_THREAD_TRACE_FLUSH 0x36
8464 #define V_028A90_THREAD_TRACE_FINISH 0x37
8465 /* CIK */
8466 #define V_028A90_PIXEL_PIPE_STAT_CONTROL 0x38
8467 #define V_028A90_PIXEL_PIPE_STAT_DUMP 0x39
8468 #define V_028A90_PIXEL_PIPE_STAT_RESET 0x40
8469 /* */
8470 #define S_028A90_ADDRESS_HI(x) (((x) & 0x1FF) << 18)
8471 #define G_028A90_ADDRESS_HI(x) (((x) >> 18) & 0x1FF)
8472 #define C_028A90_ADDRESS_HI 0xF803FFFF
8473 #define S_028A90_EXTENDED_EVENT(x) (((x) & 0x1) << 27)
8474 #define G_028A90_EXTENDED_EVENT(x) (((x) >> 27) & 0x1)
8475 #define C_028A90_EXTENDED_EVENT 0xF7FFFFFF
8476 #define R_028A94_VGT_MULTI_PRIM_IB_RESET_EN 0x028A94
8477 #define S_028A94_RESET_EN(x) (((x) & 0x1) << 0)
8478 #define G_028A94_RESET_EN(x) (((x) >> 0) & 0x1)
8479 #define C_028A94_RESET_EN 0xFFFFFFFE
8480 #define R_028AA0_VGT_INSTANCE_STEP_RATE_0 0x028AA0
8481 #define R_028AA4_VGT_INSTANCE_STEP_RATE_1 0x028AA4
8482 #define R_028AA8_IA_MULTI_VGT_PARAM 0x028AA8
8483 #define S_028AA8_PRIMGROUP_SIZE(x) (((x) & 0xFFFF) << 0)
8484 #define G_028AA8_PRIMGROUP_SIZE(x) (((x) >> 0) & 0xFFFF)
8485 #define C_028AA8_PRIMGROUP_SIZE 0xFFFF0000
8486 #define S_028AA8_PARTIAL_VS_WAVE_ON(x) (((x) & 0x1) << 16)
8487 #define G_028AA8_PARTIAL_VS_WAVE_ON(x) (((x) >> 16) & 0x1)
8488 #define C_028AA8_PARTIAL_VS_WAVE_ON 0xFFFEFFFF
8489 #define S_028AA8_SWITCH_ON_EOP(x) (((x) & 0x1) << 17)
8490 #define G_028AA8_SWITCH_ON_EOP(x) (((x) >> 17) & 0x1)
8491 #define C_028AA8_SWITCH_ON_EOP 0xFFFDFFFF
8492 #define S_028AA8_PARTIAL_ES_WAVE_ON(x) (((x) & 0x1) << 18)
8493 #define G_028AA8_PARTIAL_ES_WAVE_ON(x) (((x) >> 18) & 0x1)
8494 #define C_028AA8_PARTIAL_ES_WAVE_ON 0xFFFBFFFF
8495 #define S_028AA8_SWITCH_ON_EOI(x) (((x) & 0x1) << 19)
8496 #define G_028AA8_SWITCH_ON_EOI(x) (((x) >> 19) & 0x1)
8497 #define C_028AA8_SWITCH_ON_EOI 0xFFF7FFFF
8498 /* CIK */
8499 #define S_028AA8_WD_SWITCH_ON_EOP(x) (((x) & 0x1) << 20)
8500 #define G_028AA8_WD_SWITCH_ON_EOP(x) (((x) >> 20) & 0x1)
8501 #define C_028AA8_WD_SWITCH_ON_EOP 0xFFEFFFFF
8502 /* VI */
8503 #define S_028AA8_MAX_PRIMGRP_IN_WAVE(x) (((x) & 0x0F) << 28)
8504 #define G_028AA8_MAX_PRIMGRP_IN_WAVE(x) (((x) >> 28) & 0x0F)
8505 #define C_028AA8_MAX_PRIMGRP_IN_WAVE 0x0FFFFFFF
8506 /* */
8507 #define R_028AAC_VGT_ESGS_RING_ITEMSIZE 0x028AAC
8508 #define S_028AAC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
8509 #define G_028AAC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
8510 #define C_028AAC_ITEMSIZE 0xFFFF8000
8511 #define R_028AB0_VGT_GSVS_RING_ITEMSIZE 0x028AB0
8512 #define S_028AB0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
8513 #define G_028AB0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
8514 #define C_028AB0_ITEMSIZE 0xFFFF8000
8515 #define R_028AB4_VGT_REUSE_OFF 0x028AB4
8516 #define S_028AB4_REUSE_OFF(x) (((x) & 0x1) << 0)
8517 #define G_028AB4_REUSE_OFF(x) (((x) >> 0) & 0x1)
8518 #define C_028AB4_REUSE_OFF 0xFFFFFFFE
8519 #define R_028AB8_VGT_VTX_CNT_EN 0x028AB8
8520 #define S_028AB8_VTX_CNT_EN(x) (((x) & 0x1) << 0)
8521 #define G_028AB8_VTX_CNT_EN(x) (((x) >> 0) & 0x1)
8522 #define C_028AB8_VTX_CNT_EN 0xFFFFFFFE
8523 #define R_028ABC_DB_HTILE_SURFACE 0x028ABC
8524 #define S_028ABC_LINEAR(x) (((x) & 0x1) << 0)
8525 #define G_028ABC_LINEAR(x) (((x) >> 0) & 0x1)
8526 #define C_028ABC_LINEAR 0xFFFFFFFE
8527 #define S_028ABC_FULL_CACHE(x) (((x) & 0x1) << 1)
8528 #define G_028ABC_FULL_CACHE(x) (((x) >> 1) & 0x1)
8529 #define C_028ABC_FULL_CACHE 0xFFFFFFFD
8530 #define S_028ABC_HTILE_USES_PRELOAD_WIN(x) (((x) & 0x1) << 2)
8531 #define G_028ABC_HTILE_USES_PRELOAD_WIN(x) (((x) >> 2) & 0x1)
8532 #define C_028ABC_HTILE_USES_PRELOAD_WIN 0xFFFFFFFB
8533 #define S_028ABC_PRELOAD(x) (((x) & 0x1) << 3)
8534 #define G_028ABC_PRELOAD(x) (((x) >> 3) & 0x1)
8535 #define C_028ABC_PRELOAD 0xFFFFFFF7
8536 #define S_028ABC_PREFETCH_WIDTH(x) (((x) & 0x3F) << 4)
8537 #define G_028ABC_PREFETCH_WIDTH(x) (((x) >> 4) & 0x3F)
8538 #define C_028ABC_PREFETCH_WIDTH 0xFFFFFC0F
8539 #define S_028ABC_PREFETCH_HEIGHT(x) (((x) & 0x3F) << 10)
8540 #define G_028ABC_PREFETCH_HEIGHT(x) (((x) >> 10) & 0x3F)
8541 #define C_028ABC_PREFETCH_HEIGHT 0xFFFF03FF
8542 #define S_028ABC_DST_OUTSIDE_ZERO_TO_ONE(x) (((x) & 0x1) << 16)
8543 #define G_028ABC_DST_OUTSIDE_ZERO_TO_ONE(x) (((x) >> 16) & 0x1)
8544 #define C_028ABC_DST_OUTSIDE_ZERO_TO_ONE 0xFFFEFFFF
8545 /* VI */
8546 #define S_028ABC_TC_COMPATIBLE(x) (((x) & 0x1) << 17)
8547 #define G_028ABC_TC_COMPATIBLE(x) (((x) >> 17) & 0x1)
8548 #define C_028ABC_TC_COMPATIBLE 0xFFFDFFFF
8549 /* */
8550 #define R_028AC0_DB_SRESULTS_COMPARE_STATE0 0x028AC0
8551 #define S_028AC0_COMPAREFUNC0(x) (((x) & 0x07) << 0)
8552 #define G_028AC0_COMPAREFUNC0(x) (((x) >> 0) & 0x07)
8553 #define C_028AC0_COMPAREFUNC0 0xFFFFFFF8
8554 #define V_028AC0_REF_NEVER 0x00
8555 #define V_028AC0_REF_LESS 0x01
8556 #define V_028AC0_REF_EQUAL 0x02
8557 #define V_028AC0_REF_LEQUAL 0x03
8558 #define V_028AC0_REF_GREATER 0x04
8559 #define V_028AC0_REF_NOTEQUAL 0x05
8560 #define V_028AC0_REF_GEQUAL 0x06
8561 #define V_028AC0_REF_ALWAYS 0x07
8562 #define S_028AC0_COMPAREVALUE0(x) (((x) & 0xFF) << 4)
8563 #define G_028AC0_COMPAREVALUE0(x) (((x) >> 4) & 0xFF)
8564 #define C_028AC0_COMPAREVALUE0 0xFFFFF00F
8565 #define S_028AC0_COMPAREMASK0(x) (((x) & 0xFF) << 12)
8566 #define G_028AC0_COMPAREMASK0(x) (((x) >> 12) & 0xFF)
8567 #define C_028AC0_COMPAREMASK0 0xFFF00FFF
8568 #define S_028AC0_ENABLE0(x) (((x) & 0x1) << 24)
8569 #define G_028AC0_ENABLE0(x) (((x) >> 24) & 0x1)
8570 #define C_028AC0_ENABLE0 0xFEFFFFFF
8571 #define R_028AC4_DB_SRESULTS_COMPARE_STATE1 0x028AC4
8572 #define S_028AC4_COMPAREFUNC1(x) (((x) & 0x07) << 0)
8573 #define G_028AC4_COMPAREFUNC1(x) (((x) >> 0) & 0x07)
8574 #define C_028AC4_COMPAREFUNC1 0xFFFFFFF8
8575 #define V_028AC4_REF_NEVER 0x00
8576 #define V_028AC4_REF_LESS 0x01
8577 #define V_028AC4_REF_EQUAL 0x02
8578 #define V_028AC4_REF_LEQUAL 0x03
8579 #define V_028AC4_REF_GREATER 0x04
8580 #define V_028AC4_REF_NOTEQUAL 0x05
8581 #define V_028AC4_REF_GEQUAL 0x06
8582 #define V_028AC4_REF_ALWAYS 0x07
8583 #define S_028AC4_COMPAREVALUE1(x) (((x) & 0xFF) << 4)
8584 #define G_028AC4_COMPAREVALUE1(x) (((x) >> 4) & 0xFF)
8585 #define C_028AC4_COMPAREVALUE1 0xFFFFF00F
8586 #define S_028AC4_COMPAREMASK1(x) (((x) & 0xFF) << 12)
8587 #define G_028AC4_COMPAREMASK1(x) (((x) >> 12) & 0xFF)
8588 #define C_028AC4_COMPAREMASK1 0xFFF00FFF
8589 #define S_028AC4_ENABLE1(x) (((x) & 0x1) << 24)
8590 #define G_028AC4_ENABLE1(x) (((x) >> 24) & 0x1)
8591 #define C_028AC4_ENABLE1 0xFEFFFFFF
8592 #define R_028AC8_DB_PRELOAD_CONTROL 0x028AC8
8593 #define S_028AC8_START_X(x) (((x) & 0xFF) << 0)
8594 #define G_028AC8_START_X(x) (((x) >> 0) & 0xFF)
8595 #define C_028AC8_START_X 0xFFFFFF00
8596 #define S_028AC8_START_Y(x) (((x) & 0xFF) << 8)
8597 #define G_028AC8_START_Y(x) (((x) >> 8) & 0xFF)
8598 #define C_028AC8_START_Y 0xFFFF00FF
8599 #define S_028AC8_MAX_X(x) (((x) & 0xFF) << 16)
8600 #define G_028AC8_MAX_X(x) (((x) >> 16) & 0xFF)
8601 #define C_028AC8_MAX_X 0xFF00FFFF
8602 #define S_028AC8_MAX_Y(x) (((x) & 0xFF) << 24)
8603 #define G_028AC8_MAX_Y(x) (((x) >> 24) & 0xFF)
8604 #define C_028AC8_MAX_Y 0x00FFFFFF
8605 #define R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 0x028AD0
8606 #define R_028AD4_VGT_STRMOUT_VTX_STRIDE_0 0x028AD4
8607 #define S_028AD4_STRIDE(x) (((x) & 0x3FF) << 0)
8608 #define G_028AD4_STRIDE(x) (((x) >> 0) & 0x3FF)
8609 #define C_028AD4_STRIDE 0xFFFFFC00
8610 #define R_028ADC_VGT_STRMOUT_BUFFER_OFFSET_0 0x028ADC
8611 #define R_028AE0_VGT_STRMOUT_BUFFER_SIZE_1 0x028AE0
8612 #define R_028AE4_VGT_STRMOUT_VTX_STRIDE_1 0x028AE4
8613 #define S_028AE4_STRIDE(x) (((x) & 0x3FF) << 0)
8614 #define G_028AE4_STRIDE(x) (((x) >> 0) & 0x3FF)
8615 #define C_028AE4_STRIDE 0xFFFFFC00
8616 #define R_028AEC_VGT_STRMOUT_BUFFER_OFFSET_1 0x028AEC
8617 #define R_028AF0_VGT_STRMOUT_BUFFER_SIZE_2 0x028AF0
8618 #define R_028AF4_VGT_STRMOUT_VTX_STRIDE_2 0x028AF4
8619 #define S_028AF4_STRIDE(x) (((x) & 0x3FF) << 0)
8620 #define G_028AF4_STRIDE(x) (((x) >> 0) & 0x3FF)
8621 #define C_028AF4_STRIDE 0xFFFFFC00
8622 #define R_028AFC_VGT_STRMOUT_BUFFER_OFFSET_2 0x028AFC
8623 #define R_028B00_VGT_STRMOUT_BUFFER_SIZE_3 0x028B00
8624 #define R_028B04_VGT_STRMOUT_VTX_STRIDE_3 0x028B04
8625 #define S_028B04_STRIDE(x) (((x) & 0x3FF) << 0)
8626 #define G_028B04_STRIDE(x) (((x) >> 0) & 0x3FF)
8627 #define C_028B04_STRIDE 0xFFFFFC00
8628 #define R_028B0C_VGT_STRMOUT_BUFFER_OFFSET_3 0x028B0C
8629 #define R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x028B28
8630 #define R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x028B2C
8631 #define R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x028B30
8632 #define S_028B30_VERTEX_STRIDE(x) (((x) & 0x1FF) << 0)
8633 #define G_028B30_VERTEX_STRIDE(x) (((x) >> 0) & 0x1FF)
8634 #define C_028B30_VERTEX_STRIDE 0xFFFFFE00
8635 #define R_028B38_VGT_GS_MAX_VERT_OUT 0x028B38
8636 #define S_028B38_MAX_VERT_OUT(x) (((x) & 0x7FF) << 0)
8637 #define G_028B38_MAX_VERT_OUT(x) (((x) >> 0) & 0x7FF)
8638 #define C_028B38_MAX_VERT_OUT 0xFFFFF800
8639 /* VI */
8640 #define R_028B50_VGT_TESS_DISTRIBUTION 0x028B50
8641 #define S_028B50_ACCUM_ISOLINE(x) (((x) & 0xFF) << 0)
8642 #define G_028B50_ACCUM_ISOLINE(x) (((x) >> 0) & 0xFF)
8643 #define C_028B50_ACCUM_ISOLINE 0xFFFFFF00
8644 #define S_028B50_ACCUM_TRI(x) (((x) & 0xFF) << 8)
8645 #define G_028B50_ACCUM_TRI(x) (((x) >> 8) & 0xFF)
8646 #define C_028B50_ACCUM_TRI 0xFFFF00FF
8647 #define S_028B50_ACCUM_QUAD(x) (((x) & 0xFF) << 16)
8648 #define G_028B50_ACCUM_QUAD(x) (((x) >> 16) & 0xFF)
8649 #define C_028B50_ACCUM_QUAD 0xFF00FFFF
8650 #define S_028B50_DONUT_SPLIT(x) (((x) & 0xFF) << 24)
8651 #define G_028B50_DONUT_SPLIT(x) (((x) >> 24) & 0xFF)
8652 #define C_028B50_DONUT_SPLIT 0x00FFFFFF
8653 /* */
8654 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
8655 #define S_028B54_LS_EN(x) (((x) & 0x03) << 0)
8656 #define G_028B54_LS_EN(x) (((x) >> 0) & 0x03)
8657 #define C_028B54_LS_EN 0xFFFFFFFC
8658 #define V_028B54_LS_STAGE_OFF 0x00
8659 #define V_028B54_LS_STAGE_ON 0x01
8660 #define V_028B54_CS_STAGE_ON 0x02
8661 #define S_028B54_HS_EN(x) (((x) & 0x1) << 2)
8662 #define G_028B54_HS_EN(x) (((x) >> 2) & 0x1)
8663 #define C_028B54_HS_EN 0xFFFFFFFB
8664 #define S_028B54_ES_EN(x) (((x) & 0x03) << 3)
8665 #define G_028B54_ES_EN(x) (((x) >> 3) & 0x03)
8666 #define C_028B54_ES_EN 0xFFFFFFE7
8667 #define V_028B54_ES_STAGE_OFF 0x00
8668 #define V_028B54_ES_STAGE_DS 0x01
8669 #define V_028B54_ES_STAGE_REAL 0x02
8670 #define S_028B54_GS_EN(x) (((x) & 0x1) << 5)
8671 #define G_028B54_GS_EN(x) (((x) >> 5) & 0x1)
8672 #define C_028B54_GS_EN 0xFFFFFFDF
8673 #define S_028B54_VS_EN(x) (((x) & 0x03) << 6)
8674 #define G_028B54_VS_EN(x) (((x) >> 6) & 0x03)
8675 #define C_028B54_VS_EN 0xFFFFFF3F
8676 #define V_028B54_VS_STAGE_REAL 0x00
8677 #define V_028B54_VS_STAGE_DS 0x01
8678 #define V_028B54_VS_STAGE_COPY_SHADER 0x02
8679 #define S_028B54_DYNAMIC_HS(x) (((x) & 0x1) << 8)
8680 #define G_028B54_DYNAMIC_HS(x) (((x) >> 8) & 0x1)
8681 #define C_028B54_DYNAMIC_HS 0xFFFFFEFF
8682 /* VI */
8683 #define S_028B54_DISPATCH_DRAW_EN(x) (((x) & 0x1) << 9)
8684 #define G_028B54_DISPATCH_DRAW_EN(x) (((x) >> 9) & 0x1)
8685 #define C_028B54_DISPATCH_DRAW_EN 0xFFFFFDFF
8686 #define S_028B54_DIS_DEALLOC_ACCUM_0(x) (((x) & 0x1) << 10)
8687 #define G_028B54_DIS_DEALLOC_ACCUM_0(x) (((x) >> 10) & 0x1)
8688 #define C_028B54_DIS_DEALLOC_ACCUM_0 0xFFFFFBFF
8689 #define S_028B54_DIS_DEALLOC_ACCUM_1(x) (((x) & 0x1) << 11)
8690 #define G_028B54_DIS_DEALLOC_ACCUM_1(x) (((x) >> 11) & 0x1)
8691 #define C_028B54_DIS_DEALLOC_ACCUM_1 0xFFFFF7FF
8692 #define S_028B54_VS_WAVE_ID_EN(x) (((x) & 0x1) << 12)
8693 #define G_028B54_VS_WAVE_ID_EN(x) (((x) >> 12) & 0x1)
8694 #define C_028B54_VS_WAVE_ID_EN 0xFFFFEFFF
8695 /* */
8696 #define R_028B58_VGT_LS_HS_CONFIG 0x028B58
8697 #define S_028B58_NUM_PATCHES(x) (((x) & 0xFF) << 0)
8698 #define G_028B58_NUM_PATCHES(x) (((x) >> 0) & 0xFF)
8699 #define C_028B58_NUM_PATCHES 0xFFFFFF00
8700 #define S_028B58_HS_NUM_INPUT_CP(x) (((x) & 0x3F) << 8)
8701 #define G_028B58_HS_NUM_INPUT_CP(x) (((x) >> 8) & 0x3F)
8702 #define C_028B58_HS_NUM_INPUT_CP 0xFFFFC0FF
8703 #define S_028B58_HS_NUM_OUTPUT_CP(x) (((x) & 0x3F) << 14)
8704 #define G_028B58_HS_NUM_OUTPUT_CP(x) (((x) >> 14) & 0x3F)
8705 #define C_028B58_HS_NUM_OUTPUT_CP 0xFFF03FFF
8706 #define R_028B5C_VGT_GS_VERT_ITEMSIZE 0x028B5C
8707 #define S_028B5C_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
8708 #define G_028B5C_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
8709 #define C_028B5C_ITEMSIZE 0xFFFF8000
8710 #define R_028B60_VGT_GS_VERT_ITEMSIZE_1 0x028B60
8711 #define S_028B60_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
8712 #define G_028B60_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
8713 #define C_028B60_ITEMSIZE 0xFFFF8000
8714 #define R_028B64_VGT_GS_VERT_ITEMSIZE_2 0x028B64
8715 #define S_028B64_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
8716 #define G_028B64_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
8717 #define C_028B64_ITEMSIZE 0xFFFF8000
8718 #define R_028B68_VGT_GS_VERT_ITEMSIZE_3 0x028B68
8719 #define S_028B68_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
8720 #define G_028B68_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
8721 #define C_028B68_ITEMSIZE 0xFFFF8000
8722 #define R_028B6C_VGT_TF_PARAM 0x028B6C
8723 #define S_028B6C_TYPE(x) (((x) & 0x03) << 0)
8724 #define G_028B6C_TYPE(x) (((x) >> 0) & 0x03)
8725 #define C_028B6C_TYPE 0xFFFFFFFC
8726 #define V_028B6C_TESS_ISOLINE 0x00
8727 #define V_028B6C_TESS_TRIANGLE 0x01
8728 #define V_028B6C_TESS_QUAD 0x02
8729 #define S_028B6C_PARTITIONING(x) (((x) & 0x07) << 2)
8730 #define G_028B6C_PARTITIONING(x) (((x) >> 2) & 0x07)
8731 #define C_028B6C_PARTITIONING 0xFFFFFFE3
8732 #define V_028B6C_PART_INTEGER 0x00
8733 #define V_028B6C_PART_POW2 0x01
8734 #define V_028B6C_PART_FRAC_ODD 0x02
8735 #define V_028B6C_PART_FRAC_EVEN 0x03
8736 #define S_028B6C_TOPOLOGY(x) (((x) & 0x07) << 5)
8737 #define G_028B6C_TOPOLOGY(x) (((x) >> 5) & 0x07)
8738 #define C_028B6C_TOPOLOGY 0xFFFFFF1F
8739 #define V_028B6C_OUTPUT_POINT 0x00
8740 #define V_028B6C_OUTPUT_LINE 0x01
8741 #define V_028B6C_OUTPUT_TRIANGLE_CW 0x02
8742 #define V_028B6C_OUTPUT_TRIANGLE_CCW 0x03
8743 #define S_028B6C_RESERVED_REDUC_AXIS(x) (((x) & 0x1) << 8) /* not on CIK */
8744 #define G_028B6C_RESERVED_REDUC_AXIS(x) (((x) >> 8) & 0x1) /* not on CIK */
8745 #define C_028B6C_RESERVED_REDUC_AXIS 0xFFFFFEFF /* not on CIK */
8746 #define S_028B6C_DEPRECATED(x) (((x) & 0x1) << 9)
8747 #define G_028B6C_DEPRECATED(x) (((x) >> 9) & 0x1)
8748 #define C_028B6C_DEPRECATED 0xFFFFFDFF
8749 #define S_028B6C_NUM_DS_WAVES_PER_SIMD(x) (((x) & 0x0F) << 10)
8750 #define G_028B6C_NUM_DS_WAVES_PER_SIMD(x) (((x) >> 10) & 0x0F)
8751 #define C_028B6C_NUM_DS_WAVES_PER_SIMD 0xFFFFC3FF
8752 #define S_028B6C_DISABLE_DONUTS(x) (((x) & 0x1) << 14)
8753 #define G_028B6C_DISABLE_DONUTS(x) (((x) >> 14) & 0x1)
8754 #define C_028B6C_DISABLE_DONUTS 0xFFFFBFFF
8755 /* CIK */
8756 #define S_028B6C_RDREQ_POLICY(x) (((x) & 0x03) << 15)
8757 #define G_028B6C_RDREQ_POLICY(x) (((x) >> 15) & 0x03)
8758 #define C_028B6C_RDREQ_POLICY 0xFFFE7FFF
8759 #define V_028B6C_VGT_POLICY_LRU 0x00
8760 #define V_028B6C_VGT_POLICY_STREAM 0x01
8761 #define V_028B6C_VGT_POLICY_BYPASS 0x02
8762 /* */
8763 /* VI */
8764 #define S_028B6C_DISTRIBUTION_MODE(x) (((x) & 0x03) << 17)
8765 #define G_028B6C_DISTRIBUTION_MODE(x) (((x) >> 17) & 0x03)
8766 #define C_028B6C_DISTRIBUTION_MODE 0xFFF9FFFF
8767 #define S_028B6C_MTYPE(x) (((x) & 0x03) << 19)
8768 #define G_028B6C_MTYPE(x) (((x) >> 19) & 0x03)
8769 #define C_028B6C_MTYPE 0xFFE7FFFF
8770 /* */
8771 #define R_028B70_DB_ALPHA_TO_MASK 0x028B70
8772 #define S_028B70_ALPHA_TO_MASK_ENABLE(x) (((x) & 0x1) << 0)
8773 #define G_028B70_ALPHA_TO_MASK_ENABLE(x) (((x) >> 0) & 0x1)
8774 #define C_028B70_ALPHA_TO_MASK_ENABLE 0xFFFFFFFE
8775 #define S_028B70_ALPHA_TO_MASK_OFFSET0(x) (((x) & 0x03) << 8)
8776 #define G_028B70_ALPHA_TO_MASK_OFFSET0(x) (((x) >> 8) & 0x03)
8777 #define C_028B70_ALPHA_TO_MASK_OFFSET0 0xFFFFFCFF
8778 #define S_028B70_ALPHA_TO_MASK_OFFSET1(x) (((x) & 0x03) << 10)
8779 #define G_028B70_ALPHA_TO_MASK_OFFSET1(x) (((x) >> 10) & 0x03)
8780 #define C_028B70_ALPHA_TO_MASK_OFFSET1 0xFFFFF3FF
8781 #define S_028B70_ALPHA_TO_MASK_OFFSET2(x) (((x) & 0x03) << 12)
8782 #define G_028B70_ALPHA_TO_MASK_OFFSET2(x) (((x) >> 12) & 0x03)
8783 #define C_028B70_ALPHA_TO_MASK_OFFSET2 0xFFFFCFFF
8784 #define S_028B70_ALPHA_TO_MASK_OFFSET3(x) (((x) & 0x03) << 14)
8785 #define G_028B70_ALPHA_TO_MASK_OFFSET3(x) (((x) >> 14) & 0x03)
8786 #define C_028B70_ALPHA_TO_MASK_OFFSET3 0xFFFF3FFF
8787 #define S_028B70_OFFSET_ROUND(x) (((x) & 0x1) << 16)
8788 #define G_028B70_OFFSET_ROUND(x) (((x) >> 16) & 0x1)
8789 #define C_028B70_OFFSET_ROUND 0xFFFEFFFF
8790 /* CIK */
8791 #define R_028B74_VGT_DISPATCH_DRAW_INDEX 0x028B74
8792 /* */
8793 #define R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL 0x028B78
8794 #define S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) & 0xFF) << 0)
8795 #define G_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) >> 0) & 0xFF)
8796 #define C_028B78_POLY_OFFSET_NEG_NUM_DB_BITS 0xFFFFFF00
8797 #define S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x) (((x) & 0x1) << 8)
8798 #define G_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x) (((x) >> 8) & 0x1)
8799 #define C_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT 0xFFFFFEFF
8800 #define R_028B7C_PA_SU_POLY_OFFSET_CLAMP 0x028B7C
8801 #define R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE 0x028B80
8802 #define R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x028B84
8803 #define R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE 0x028B88
8804 #define R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET 0x028B8C
8805 #define R_028B90_VGT_GS_INSTANCE_CNT 0x028B90
8806 #define S_028B90_ENABLE(x) (((x) & 0x1) << 0)
8807 #define G_028B90_ENABLE(x) (((x) >> 0) & 0x1)
8808 #define C_028B90_ENABLE 0xFFFFFFFE
8809 #define S_028B90_CNT(x) (((x) & 0x7F) << 2)
8810 #define G_028B90_CNT(x) (((x) >> 2) & 0x7F)
8811 #define C_028B90_CNT 0xFFFFFE03
8812 #define R_028B94_VGT_STRMOUT_CONFIG 0x028B94
8813 #define S_028B94_STREAMOUT_0_EN(x) (((x) & 0x1) << 0)
8814 #define G_028B94_STREAMOUT_0_EN(x) (((x) >> 0) & 0x1)
8815 #define C_028B94_STREAMOUT_0_EN 0xFFFFFFFE
8816 #define S_028B94_STREAMOUT_1_EN(x) (((x) & 0x1) << 1)
8817 #define G_028B94_STREAMOUT_1_EN(x) (((x) >> 1) & 0x1)
8818 #define C_028B94_STREAMOUT_1_EN 0xFFFFFFFD
8819 #define S_028B94_STREAMOUT_2_EN(x) (((x) & 0x1) << 2)
8820 #define G_028B94_STREAMOUT_2_EN(x) (((x) >> 2) & 0x1)
8821 #define C_028B94_STREAMOUT_2_EN 0xFFFFFFFB
8822 #define S_028B94_STREAMOUT_3_EN(x) (((x) & 0x1) << 3)
8823 #define G_028B94_STREAMOUT_3_EN(x) (((x) >> 3) & 0x1)
8824 #define C_028B94_STREAMOUT_3_EN 0xFFFFFFF7
8825 #define S_028B94_RAST_STREAM(x) (((x) & 0x07) << 4)
8826 #define G_028B94_RAST_STREAM(x) (((x) >> 4) & 0x07)
8827 #define C_028B94_RAST_STREAM 0xFFFFFF8F
8828 #define S_028B94_RAST_STREAM_MASK(x) (((x) & 0x0F) << 8)
8829 #define G_028B94_RAST_STREAM_MASK(x) (((x) >> 8) & 0x0F)
8830 #define C_028B94_RAST_STREAM_MASK 0xFFFFF0FF
8831 #define S_028B94_USE_RAST_STREAM_MASK(x) (((x) & 0x1) << 31)
8832 #define G_028B94_USE_RAST_STREAM_MASK(x) (((x) >> 31) & 0x1)
8833 #define C_028B94_USE_RAST_STREAM_MASK 0x7FFFFFFF
8834 #define R_028B98_VGT_STRMOUT_BUFFER_CONFIG 0x028B98
8835 #define S_028B98_STREAM_0_BUFFER_EN(x) (((x) & 0x0F) << 0)
8836 #define G_028B98_STREAM_0_BUFFER_EN(x) (((x) >> 0) & 0x0F)
8837 #define C_028B98_STREAM_0_BUFFER_EN 0xFFFFFFF0
8838 #define S_028B98_STREAM_1_BUFFER_EN(x) (((x) & 0x0F) << 4)
8839 #define G_028B98_STREAM_1_BUFFER_EN(x) (((x) >> 4) & 0x0F)
8840 #define C_028B98_STREAM_1_BUFFER_EN 0xFFFFFF0F
8841 #define S_028B98_STREAM_2_BUFFER_EN(x) (((x) & 0x0F) << 8)
8842 #define G_028B98_STREAM_2_BUFFER_EN(x) (((x) >> 8) & 0x0F)
8843 #define C_028B98_STREAM_2_BUFFER_EN 0xFFFFF0FF
8844 #define S_028B98_STREAM_3_BUFFER_EN(x) (((x) & 0x0F) << 12)
8845 #define G_028B98_STREAM_3_BUFFER_EN(x) (((x) >> 12) & 0x0F)
8846 #define C_028B98_STREAM_3_BUFFER_EN 0xFFFF0FFF
8847 #define R_028BD4_PA_SC_CENTROID_PRIORITY_0 0x028BD4
8848 #define S_028BD4_DISTANCE_0(x) (((x) & 0x0F) << 0)
8849 #define G_028BD4_DISTANCE_0(x) (((x) >> 0) & 0x0F)
8850 #define C_028BD4_DISTANCE_0 0xFFFFFFF0
8851 #define S_028BD4_DISTANCE_1(x) (((x) & 0x0F) << 4)
8852 #define G_028BD4_DISTANCE_1(x) (((x) >> 4) & 0x0F)
8853 #define C_028BD4_DISTANCE_1 0xFFFFFF0F
8854 #define S_028BD4_DISTANCE_2(x) (((x) & 0x0F) << 8)
8855 #define G_028BD4_DISTANCE_2(x) (((x) >> 8) & 0x0F)
8856 #define C_028BD4_DISTANCE_2 0xFFFFF0FF
8857 #define S_028BD4_DISTANCE_3(x) (((x) & 0x0F) << 12)
8858 #define G_028BD4_DISTANCE_3(x) (((x) >> 12) & 0x0F)
8859 #define C_028BD4_DISTANCE_3 0xFFFF0FFF
8860 #define S_028BD4_DISTANCE_4(x) (((x) & 0x0F) << 16)
8861 #define G_028BD4_DISTANCE_4(x) (((x) >> 16) & 0x0F)
8862 #define C_028BD4_DISTANCE_4 0xFFF0FFFF
8863 #define S_028BD4_DISTANCE_5(x) (((x) & 0x0F) << 20)
8864 #define G_028BD4_DISTANCE_5(x) (((x) >> 20) & 0x0F)
8865 #define C_028BD4_DISTANCE_5 0xFF0FFFFF
8866 #define S_028BD4_DISTANCE_6(x) (((x) & 0x0F) << 24)
8867 #define G_028BD4_DISTANCE_6(x) (((x) >> 24) & 0x0F)
8868 #define C_028BD4_DISTANCE_6 0xF0FFFFFF
8869 #define S_028BD4_DISTANCE_7(x) (((x) & 0x0F) << 28)
8870 #define G_028BD4_DISTANCE_7(x) (((x) >> 28) & 0x0F)
8871 #define C_028BD4_DISTANCE_7 0x0FFFFFFF
8872 #define R_028BD8_PA_SC_CENTROID_PRIORITY_1 0x028BD8
8873 #define S_028BD8_DISTANCE_8(x) (((x) & 0x0F) << 0)
8874 #define G_028BD8_DISTANCE_8(x) (((x) >> 0) & 0x0F)
8875 #define C_028BD8_DISTANCE_8 0xFFFFFFF0
8876 #define S_028BD8_DISTANCE_9(x) (((x) & 0x0F) << 4)
8877 #define G_028BD8_DISTANCE_9(x) (((x) >> 4) & 0x0F)
8878 #define C_028BD8_DISTANCE_9 0xFFFFFF0F
8879 #define S_028BD8_DISTANCE_10(x) (((x) & 0x0F) << 8)
8880 #define G_028BD8_DISTANCE_10(x) (((x) >> 8) & 0x0F)
8881 #define C_028BD8_DISTANCE_10 0xFFFFF0FF
8882 #define S_028BD8_DISTANCE_11(x) (((x) & 0x0F) << 12)
8883 #define G_028BD8_DISTANCE_11(x) (((x) >> 12) & 0x0F)
8884 #define C_028BD8_DISTANCE_11 0xFFFF0FFF
8885 #define S_028BD8_DISTANCE_12(x) (((x) & 0x0F) << 16)
8886 #define G_028BD8_DISTANCE_12(x) (((x) >> 16) & 0x0F)
8887 #define C_028BD8_DISTANCE_12 0xFFF0FFFF
8888 #define S_028BD8_DISTANCE_13(x) (((x) & 0x0F) << 20)
8889 #define G_028BD8_DISTANCE_13(x) (((x) >> 20) & 0x0F)
8890 #define C_028BD8_DISTANCE_13 0xFF0FFFFF
8891 #define S_028BD8_DISTANCE_14(x) (((x) & 0x0F) << 24)
8892 #define G_028BD8_DISTANCE_14(x) (((x) >> 24) & 0x0F)
8893 #define C_028BD8_DISTANCE_14 0xF0FFFFFF
8894 #define S_028BD8_DISTANCE_15(x) (((x) & 0x0F) << 28)
8895 #define G_028BD8_DISTANCE_15(x) (((x) >> 28) & 0x0F)
8896 #define C_028BD8_DISTANCE_15 0x0FFFFFFF
8897 #define R_028BDC_PA_SC_LINE_CNTL 0x028BDC
8898 #define S_028BDC_EXPAND_LINE_WIDTH(x) (((x) & 0x1) << 9)
8899 #define G_028BDC_EXPAND_LINE_WIDTH(x) (((x) >> 9) & 0x1)
8900 #define C_028BDC_EXPAND_LINE_WIDTH 0xFFFFFDFF
8901 #define S_028BDC_LAST_PIXEL(x) (((x) & 0x1) << 10)
8902 #define G_028BDC_LAST_PIXEL(x) (((x) >> 10) & 0x1)
8903 #define C_028BDC_LAST_PIXEL 0xFFFFFBFF
8904 #define S_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) & 0x1) << 11)
8905 #define G_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) >> 11) & 0x1)
8906 #define C_028BDC_PERPENDICULAR_ENDCAP_ENA 0xFFFFF7FF
8907 #define S_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) & 0x1) << 12)
8908 #define G_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) >> 12) & 0x1)
8909 #define C_028BDC_DX10_DIAMOND_TEST_ENA 0xFFFFEFFF
8910 #define R_028BE0_PA_SC_AA_CONFIG 0x028BE0
8911 #define S_028BE0_MSAA_NUM_SAMPLES(x) (((x) & 0x7) << 0)
8912 #define G_028BE0_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x07)
8913 #define C_028BE0_MSAA_NUM_SAMPLES 0xFFFFFFF8
8914 #define S_028BE0_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4)
8915 #define G_028BE0_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1)
8916 #define C_028BE0_AA_MASK_CENTROID_DTMN 0xFFFFFFEF
8917 #define S_028BE0_MAX_SAMPLE_DIST(x) (((x) & 0xf) << 13)
8918 #define G_028BE0_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0x0F)
8919 #define C_028BE0_MAX_SAMPLE_DIST 0xFFFE1FFF
8920 #define S_028BE0_MSAA_EXPOSED_SAMPLES(x) (((x) & 0x7) << 20)
8921 #define G_028BE0_MSAA_EXPOSED_SAMPLES(x) (((x) >> 20) & 0x07)
8922 #define C_028BE0_MSAA_EXPOSED_SAMPLES 0xFF8FFFFF
8923 #define S_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((x) & 0x3) << 24)
8924 #define G_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((x) >> 24) & 0x03)
8925 #define C_028BE0_DETAIL_TO_EXPOSED_MODE 0xFCFFFFFF
8926 #define R_028BE4_PA_SU_VTX_CNTL 0x028BE4
8927 #define S_028BE4_PIX_CENTER(x) (((x) & 0x1) << 0)
8928 #define G_028BE4_PIX_CENTER(x) (((x) >> 0) & 0x1)
8929 #define C_028BE4_PIX_CENTER 0xFFFFFFFE
8930 #define S_028BE4_ROUND_MODE(x) (((x) & 0x03) << 1)
8931 #define G_028BE4_ROUND_MODE(x) (((x) >> 1) & 0x03)
8932 #define C_028BE4_ROUND_MODE 0xFFFFFFF9
8933 #define V_028BE4_X_TRUNCATE 0x00
8934 #define V_028BE4_X_ROUND 0x01
8935 #define V_028BE4_X_ROUND_TO_EVEN 0x02
8936 #define V_028BE4_X_ROUND_TO_ODD 0x03
8937 #define S_028BE4_QUANT_MODE(x) (((x) & 0x07) << 3)
8938 #define G_028BE4_QUANT_MODE(x) (((x) >> 3) & 0x07)
8939 #define C_028BE4_QUANT_MODE 0xFFFFFFC7
8940 #define V_028BE4_X_16_8_FIXED_POINT_1_16TH 0x00
8941 #define V_028BE4_X_16_8_FIXED_POINT_1_8TH 0x01
8942 #define V_028BE4_X_16_8_FIXED_POINT_1_4TH 0x02
8943 #define V_028BE4_X_16_8_FIXED_POINT_1_2 0x03
8944 #define V_028BE4_X_16_8_FIXED_POINT_1 0x04
8945 #define V_028BE4_X_16_8_FIXED_POINT_1_256TH 0x05
8946 #define V_028BE4_X_14_10_FIXED_POINT_1_1024TH 0x06
8947 #define V_028BE4_X_12_12_FIXED_POINT_1_4096TH 0x07
8948 #define R_028BE8_PA_CL_GB_VERT_CLIP_ADJ 0x028BE8
8949 #define R_028BEC_PA_CL_GB_VERT_DISC_ADJ 0x028BEC
8950 #define R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ 0x028BF0
8951 #define R_028BF4_PA_CL_GB_HORZ_DISC_ADJ 0x028BF4
8952 #define R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x028BF8
8953 #define S_028BF8_S0_X(x) (((x) & 0x0F) << 0)
8954 #define G_028BF8_S0_X(x) (((x) >> 0) & 0x0F)
8955 #define C_028BF8_S0_X 0xFFFFFFF0
8956 #define S_028BF8_S0_Y(x) (((x) & 0x0F) << 4)
8957 #define G_028BF8_S0_Y(x) (((x) >> 4) & 0x0F)
8958 #define C_028BF8_S0_Y 0xFFFFFF0F
8959 #define S_028BF8_S1_X(x) (((x) & 0x0F) << 8)
8960 #define G_028BF8_S1_X(x) (((x) >> 8) & 0x0F)
8961 #define C_028BF8_S1_X 0xFFFFF0FF
8962 #define S_028BF8_S1_Y(x) (((x) & 0x0F) << 12)
8963 #define G_028BF8_S1_Y(x) (((x) >> 12) & 0x0F)
8964 #define C_028BF8_S1_Y 0xFFFF0FFF
8965 #define S_028BF8_S2_X(x) (((x) & 0x0F) << 16)
8966 #define G_028BF8_S2_X(x) (((x) >> 16) & 0x0F)
8967 #define C_028BF8_S2_X 0xFFF0FFFF
8968 #define S_028BF8_S2_Y(x) (((x) & 0x0F) << 20)
8969 #define G_028BF8_S2_Y(x) (((x) >> 20) & 0x0F)
8970 #define C_028BF8_S2_Y 0xFF0FFFFF
8971 #define S_028BF8_S3_X(x) (((x) & 0x0F) << 24)
8972 #define G_028BF8_S3_X(x) (((x) >> 24) & 0x0F)
8973 #define C_028BF8_S3_X 0xF0FFFFFF
8974 #define S_028BF8_S3_Y(x) (((x) & 0x0F) << 28)
8975 #define G_028BF8_S3_Y(x) (((x) >> 28) & 0x0F)
8976 #define C_028BF8_S3_Y 0x0FFFFFFF
8977 #define R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x028BFC
8978 #define S_028BFC_S4_X(x) (((x) & 0x0F) << 0)
8979 #define G_028BFC_S4_X(x) (((x) >> 0) & 0x0F)
8980 #define C_028BFC_S4_X 0xFFFFFFF0
8981 #define S_028BFC_S4_Y(x) (((x) & 0x0F) << 4)
8982 #define G_028BFC_S4_Y(x) (((x) >> 4) & 0x0F)
8983 #define C_028BFC_S4_Y 0xFFFFFF0F
8984 #define S_028BFC_S5_X(x) (((x) & 0x0F) << 8)
8985 #define G_028BFC_S5_X(x) (((x) >> 8) & 0x0F)
8986 #define C_028BFC_S5_X 0xFFFFF0FF
8987 #define S_028BFC_S5_Y(x) (((x) & 0x0F) << 12)
8988 #define G_028BFC_S5_Y(x) (((x) >> 12) & 0x0F)
8989 #define C_028BFC_S5_Y 0xFFFF0FFF
8990 #define S_028BFC_S6_X(x) (((x) & 0x0F) << 16)
8991 #define G_028BFC_S6_X(x) (((x) >> 16) & 0x0F)
8992 #define C_028BFC_S6_X 0xFFF0FFFF
8993 #define S_028BFC_S6_Y(x) (((x) & 0x0F) << 20)
8994 #define G_028BFC_S6_Y(x) (((x) >> 20) & 0x0F)
8995 #define C_028BFC_S6_Y 0xFF0FFFFF
8996 #define S_028BFC_S7_X(x) (((x) & 0x0F) << 24)
8997 #define G_028BFC_S7_X(x) (((x) >> 24) & 0x0F)
8998 #define C_028BFC_S7_X 0xF0FFFFFF
8999 #define S_028BFC_S7_Y(x) (((x) & 0x0F) << 28)
9000 #define G_028BFC_S7_Y(x) (((x) >> 28) & 0x0F)
9001 #define C_028BFC_S7_Y 0x0FFFFFFF
9002 #define R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x028C00
9003 #define S_028C00_S8_X(x) (((x) & 0x0F) << 0)
9004 #define G_028C00_S8_X(x) (((x) >> 0) & 0x0F)
9005 #define C_028C00_S8_X 0xFFFFFFF0
9006 #define S_028C00_S8_Y(x) (((x) & 0x0F) << 4)
9007 #define G_028C00_S8_Y(x) (((x) >> 4) & 0x0F)
9008 #define C_028C00_S8_Y 0xFFFFFF0F
9009 #define S_028C00_S9_X(x) (((x) & 0x0F) << 8)
9010 #define G_028C00_S9_X(x) (((x) >> 8) & 0x0F)
9011 #define C_028C00_S9_X 0xFFFFF0FF
9012 #define S_028C00_S9_Y(x) (((x) & 0x0F) << 12)
9013 #define G_028C00_S9_Y(x) (((x) >> 12) & 0x0F)
9014 #define C_028C00_S9_Y 0xFFFF0FFF
9015 #define S_028C00_S10_X(x) (((x) & 0x0F) << 16)
9016 #define G_028C00_S10_X(x) (((x) >> 16) & 0x0F)
9017 #define C_028C00_S10_X 0xFFF0FFFF
9018 #define S_028C00_S10_Y(x) (((x) & 0x0F) << 20)
9019 #define G_028C00_S10_Y(x) (((x) >> 20) & 0x0F)
9020 #define C_028C00_S10_Y 0xFF0FFFFF
9021 #define S_028C00_S11_X(x) (((x) & 0x0F) << 24)
9022 #define G_028C00_S11_X(x) (((x) >> 24) & 0x0F)
9023 #define C_028C00_S11_X 0xF0FFFFFF
9024 #define S_028C00_S11_Y(x) (((x) & 0x0F) << 28)
9025 #define G_028C00_S11_Y(x) (((x) >> 28) & 0x0F)
9026 #define C_028C00_S11_Y 0x0FFFFFFF
9027 #define R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x028C04
9028 #define S_028C04_S12_X(x) (((x) & 0x0F) << 0)
9029 #define G_028C04_S12_X(x) (((x) >> 0) & 0x0F)
9030 #define C_028C04_S12_X 0xFFFFFFF0
9031 #define S_028C04_S12_Y(x) (((x) & 0x0F) << 4)
9032 #define G_028C04_S12_Y(x) (((x) >> 4) & 0x0F)
9033 #define C_028C04_S12_Y 0xFFFFFF0F
9034 #define S_028C04_S13_X(x) (((x) & 0x0F) << 8)
9035 #define G_028C04_S13_X(x) (((x) >> 8) & 0x0F)
9036 #define C_028C04_S13_X 0xFFFFF0FF
9037 #define S_028C04_S13_Y(x) (((x) & 0x0F) << 12)
9038 #define G_028C04_S13_Y(x) (((x) >> 12) & 0x0F)
9039 #define C_028C04_S13_Y 0xFFFF0FFF
9040 #define S_028C04_S14_X(x) (((x) & 0x0F) << 16)
9041 #define G_028C04_S14_X(x) (((x) >> 16) & 0x0F)
9042 #define C_028C04_S14_X 0xFFF0FFFF
9043 #define S_028C04_S14_Y(x) (((x) & 0x0F) << 20)
9044 #define G_028C04_S14_Y(x) (((x) >> 20) & 0x0F)
9045 #define C_028C04_S14_Y 0xFF0FFFFF
9046 #define S_028C04_S15_X(x) (((x) & 0x0F) << 24)
9047 #define G_028C04_S15_X(x) (((x) >> 24) & 0x0F)
9048 #define C_028C04_S15_X 0xF0FFFFFF
9049 #define S_028C04_S15_Y(x) (((x) & 0x0F) << 28)
9050 #define G_028C04_S15_Y(x) (((x) >> 28) & 0x0F)
9051 #define C_028C04_S15_Y 0x0FFFFFFF
9052 #define R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x028C08
9053 #define S_028C08_S0_X(x) (((x) & 0x0F) << 0)
9054 #define G_028C08_S0_X(x) (((x) >> 0) & 0x0F)
9055 #define C_028C08_S0_X 0xFFFFFFF0
9056 #define S_028C08_S0_Y(x) (((x) & 0x0F) << 4)
9057 #define G_028C08_S0_Y(x) (((x) >> 4) & 0x0F)
9058 #define C_028C08_S0_Y 0xFFFFFF0F
9059 #define S_028C08_S1_X(x) (((x) & 0x0F) << 8)
9060 #define G_028C08_S1_X(x) (((x) >> 8) & 0x0F)
9061 #define C_028C08_S1_X 0xFFFFF0FF
9062 #define S_028C08_S1_Y(x) (((x) & 0x0F) << 12)
9063 #define G_028C08_S1_Y(x) (((x) >> 12) & 0x0F)
9064 #define C_028C08_S1_Y 0xFFFF0FFF
9065 #define S_028C08_S2_X(x) (((x) & 0x0F) << 16)
9066 #define G_028C08_S2_X(x) (((x) >> 16) & 0x0F)
9067 #define C_028C08_S2_X 0xFFF0FFFF
9068 #define S_028C08_S2_Y(x) (((x) & 0x0F) << 20)
9069 #define G_028C08_S2_Y(x) (((x) >> 20) & 0x0F)
9070 #define C_028C08_S2_Y 0xFF0FFFFF
9071 #define S_028C08_S3_X(x) (((x) & 0x0F) << 24)
9072 #define G_028C08_S3_X(x) (((x) >> 24) & 0x0F)
9073 #define C_028C08_S3_X 0xF0FFFFFF
9074 #define S_028C08_S3_Y(x) (((x) & 0x0F) << 28)
9075 #define G_028C08_S3_Y(x) (((x) >> 28) & 0x0F)
9076 #define C_028C08_S3_Y 0x0FFFFFFF
9077 #define R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x028C0C
9078 #define S_028C0C_S4_X(x) (((x) & 0x0F) << 0)
9079 #define G_028C0C_S4_X(x) (((x) >> 0) & 0x0F)
9080 #define C_028C0C_S4_X 0xFFFFFFF0
9081 #define S_028C0C_S4_Y(x) (((x) & 0x0F) << 4)
9082 #define G_028C0C_S4_Y(x) (((x) >> 4) & 0x0F)
9083 #define C_028C0C_S4_Y 0xFFFFFF0F
9084 #define S_028C0C_S5_X(x) (((x) & 0x0F) << 8)
9085 #define G_028C0C_S5_X(x) (((x) >> 8) & 0x0F)
9086 #define C_028C0C_S5_X 0xFFFFF0FF
9087 #define S_028C0C_S5_Y(x) (((x) & 0x0F) << 12)
9088 #define G_028C0C_S5_Y(x) (((x) >> 12) & 0x0F)
9089 #define C_028C0C_S5_Y 0xFFFF0FFF
9090 #define S_028C0C_S6_X(x) (((x) & 0x0F) << 16)
9091 #define G_028C0C_S6_X(x) (((x) >> 16) & 0x0F)
9092 #define C_028C0C_S6_X 0xFFF0FFFF
9093 #define S_028C0C_S6_Y(x) (((x) & 0x0F) << 20)
9094 #define G_028C0C_S6_Y(x) (((x) >> 20) & 0x0F)
9095 #define C_028C0C_S6_Y 0xFF0FFFFF
9096 #define S_028C0C_S7_X(x) (((x) & 0x0F) << 24)
9097 #define G_028C0C_S7_X(x) (((x) >> 24) & 0x0F)
9098 #define C_028C0C_S7_X 0xF0FFFFFF
9099 #define S_028C0C_S7_Y(x) (((x) & 0x0F) << 28)
9100 #define G_028C0C_S7_Y(x) (((x) >> 28) & 0x0F)
9101 #define C_028C0C_S7_Y 0x0FFFFFFF
9102 #define R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x028C10
9103 #define S_028C10_S8_X(x) (((x) & 0x0F) << 0)
9104 #define G_028C10_S8_X(x) (((x) >> 0) & 0x0F)
9105 #define C_028C10_S8_X 0xFFFFFFF0
9106 #define S_028C10_S8_Y(x) (((x) & 0x0F) << 4)
9107 #define G_028C10_S8_Y(x) (((x) >> 4) & 0x0F)
9108 #define C_028C10_S8_Y 0xFFFFFF0F
9109 #define S_028C10_S9_X(x) (((x) & 0x0F) << 8)
9110 #define G_028C10_S9_X(x) (((x) >> 8) & 0x0F)
9111 #define C_028C10_S9_X 0xFFFFF0FF
9112 #define S_028C10_S9_Y(x) (((x) & 0x0F) << 12)
9113 #define G_028C10_S9_Y(x) (((x) >> 12) & 0x0F)
9114 #define C_028C10_S9_Y 0xFFFF0FFF
9115 #define S_028C10_S10_X(x) (((x) & 0x0F) << 16)
9116 #define G_028C10_S10_X(x) (((x) >> 16) & 0x0F)
9117 #define C_028C10_S10_X 0xFFF0FFFF
9118 #define S_028C10_S10_Y(x) (((x) & 0x0F) << 20)
9119 #define G_028C10_S10_Y(x) (((x) >> 20) & 0x0F)
9120 #define C_028C10_S10_Y 0xFF0FFFFF
9121 #define S_028C10_S11_X(x) (((x) & 0x0F) << 24)
9122 #define G_028C10_S11_X(x) (((x) >> 24) & 0x0F)
9123 #define C_028C10_S11_X 0xF0FFFFFF
9124 #define S_028C10_S11_Y(x) (((x) & 0x0F) << 28)
9125 #define G_028C10_S11_Y(x) (((x) >> 28) & 0x0F)
9126 #define C_028C10_S11_Y 0x0FFFFFFF
9127 #define R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x028C14
9128 #define S_028C14_S12_X(x) (((x) & 0x0F) << 0)
9129 #define G_028C14_S12_X(x) (((x) >> 0) & 0x0F)
9130 #define C_028C14_S12_X 0xFFFFFFF0
9131 #define S_028C14_S12_Y(x) (((x) & 0x0F) << 4)
9132 #define G_028C14_S12_Y(x) (((x) >> 4) & 0x0F)
9133 #define C_028C14_S12_Y 0xFFFFFF0F
9134 #define S_028C14_S13_X(x) (((x) & 0x0F) << 8)
9135 #define G_028C14_S13_X(x) (((x) >> 8) & 0x0F)
9136 #define C_028C14_S13_X 0xFFFFF0FF
9137 #define S_028C14_S13_Y(x) (((x) & 0x0F) << 12)
9138 #define G_028C14_S13_Y(x) (((x) >> 12) & 0x0F)
9139 #define C_028C14_S13_Y 0xFFFF0FFF
9140 #define S_028C14_S14_X(x) (((x) & 0x0F) << 16)
9141 #define G_028C14_S14_X(x) (((x) >> 16) & 0x0F)
9142 #define C_028C14_S14_X 0xFFF0FFFF
9143 #define S_028C14_S14_Y(x) (((x) & 0x0F) << 20)
9144 #define G_028C14_S14_Y(x) (((x) >> 20) & 0x0F)
9145 #define C_028C14_S14_Y 0xFF0FFFFF
9146 #define S_028C14_S15_X(x) (((x) & 0x0F) << 24)
9147 #define G_028C14_S15_X(x) (((x) >> 24) & 0x0F)
9148 #define C_028C14_S15_X 0xF0FFFFFF
9149 #define S_028C14_S15_Y(x) (((x) & 0x0F) << 28)
9150 #define G_028C14_S15_Y(x) (((x) >> 28) & 0x0F)
9151 #define C_028C14_S15_Y 0x0FFFFFFF
9152 #define R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x028C18
9153 #define S_028C18_S0_X(x) (((x) & 0x0F) << 0)
9154 #define G_028C18_S0_X(x) (((x) >> 0) & 0x0F)
9155 #define C_028C18_S0_X 0xFFFFFFF0
9156 #define S_028C18_S0_Y(x) (((x) & 0x0F) << 4)
9157 #define G_028C18_S0_Y(x) (((x) >> 4) & 0x0F)
9158 #define C_028C18_S0_Y 0xFFFFFF0F
9159 #define S_028C18_S1_X(x) (((x) & 0x0F) << 8)
9160 #define G_028C18_S1_X(x) (((x) >> 8) & 0x0F)
9161 #define C_028C18_S1_X 0xFFFFF0FF
9162 #define S_028C18_S1_Y(x) (((x) & 0x0F) << 12)
9163 #define G_028C18_S1_Y(x) (((x) >> 12) & 0x0F)
9164 #define C_028C18_S1_Y 0xFFFF0FFF
9165 #define S_028C18_S2_X(x) (((x) & 0x0F) << 16)
9166 #define G_028C18_S2_X(x) (((x) >> 16) & 0x0F)
9167 #define C_028C18_S2_X 0xFFF0FFFF
9168 #define S_028C18_S2_Y(x) (((x) & 0x0F) << 20)
9169 #define G_028C18_S2_Y(x) (((x) >> 20) & 0x0F)
9170 #define C_028C18_S2_Y 0xFF0FFFFF
9171 #define S_028C18_S3_X(x) (((x) & 0x0F) << 24)
9172 #define G_028C18_S3_X(x) (((x) >> 24) & 0x0F)
9173 #define C_028C18_S3_X 0xF0FFFFFF
9174 #define S_028C18_S3_Y(x) (((x) & 0x0F) << 28)
9175 #define G_028C18_S3_Y(x) (((x) >> 28) & 0x0F)
9176 #define C_028C18_S3_Y 0x0FFFFFFF
9177 #define R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x028C1C
9178 #define S_028C1C_S4_X(x) (((x) & 0x0F) << 0)
9179 #define G_028C1C_S4_X(x) (((x) >> 0) & 0x0F)
9180 #define C_028C1C_S4_X 0xFFFFFFF0
9181 #define S_028C1C_S4_Y(x) (((x) & 0x0F) << 4)
9182 #define G_028C1C_S4_Y(x) (((x) >> 4) & 0x0F)
9183 #define C_028C1C_S4_Y 0xFFFFFF0F
9184 #define S_028C1C_S5_X(x) (((x) & 0x0F) << 8)
9185 #define G_028C1C_S5_X(x) (((x) >> 8) & 0x0F)
9186 #define C_028C1C_S5_X 0xFFFFF0FF
9187 #define S_028C1C_S5_Y(x) (((x) & 0x0F) << 12)
9188 #define G_028C1C_S5_Y(x) (((x) >> 12) & 0x0F)
9189 #define C_028C1C_S5_Y 0xFFFF0FFF
9190 #define S_028C1C_S6_X(x) (((x) & 0x0F) << 16)
9191 #define G_028C1C_S6_X(x) (((x) >> 16) & 0x0F)
9192 #define C_028C1C_S6_X 0xFFF0FFFF
9193 #define S_028C1C_S6_Y(x) (((x) & 0x0F) << 20)
9194 #define G_028C1C_S6_Y(x) (((x) >> 20) & 0x0F)
9195 #define C_028C1C_S6_Y 0xFF0FFFFF
9196 #define S_028C1C_S7_X(x) (((x) & 0x0F) << 24)
9197 #define G_028C1C_S7_X(x) (((x) >> 24) & 0x0F)
9198 #define C_028C1C_S7_X 0xF0FFFFFF
9199 #define S_028C1C_S7_Y(x) (((x) & 0x0F) << 28)
9200 #define G_028C1C_S7_Y(x) (((x) >> 28) & 0x0F)
9201 #define C_028C1C_S7_Y 0x0FFFFFFF
9202 #define R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x028C20
9203 #define S_028C20_S8_X(x) (((x) & 0x0F) << 0)
9204 #define G_028C20_S8_X(x) (((x) >> 0) & 0x0F)
9205 #define C_028C20_S8_X 0xFFFFFFF0
9206 #define S_028C20_S8_Y(x) (((x) & 0x0F) << 4)
9207 #define G_028C20_S8_Y(x) (((x) >> 4) & 0x0F)
9208 #define C_028C20_S8_Y 0xFFFFFF0F
9209 #define S_028C20_S9_X(x) (((x) & 0x0F) << 8)
9210 #define G_028C20_S9_X(x) (((x) >> 8) & 0x0F)
9211 #define C_028C20_S9_X 0xFFFFF0FF
9212 #define S_028C20_S9_Y(x) (((x) & 0x0F) << 12)
9213 #define G_028C20_S9_Y(x) (((x) >> 12) & 0x0F)
9214 #define C_028C20_S9_Y 0xFFFF0FFF
9215 #define S_028C20_S10_X(x) (((x) & 0x0F) << 16)
9216 #define G_028C20_S10_X(x) (((x) >> 16) & 0x0F)
9217 #define C_028C20_S10_X 0xFFF0FFFF
9218 #define S_028C20_S10_Y(x) (((x) & 0x0F) << 20)
9219 #define G_028C20_S10_Y(x) (((x) >> 20) & 0x0F)
9220 #define C_028C20_S10_Y 0xFF0FFFFF
9221 #define S_028C20_S11_X(x) (((x) & 0x0F) << 24)
9222 #define G_028C20_S11_X(x) (((x) >> 24) & 0x0F)
9223 #define C_028C20_S11_X 0xF0FFFFFF
9224 #define S_028C20_S11_Y(x) (((x) & 0x0F) << 28)
9225 #define G_028C20_S11_Y(x) (((x) >> 28) & 0x0F)
9226 #define C_028C20_S11_Y 0x0FFFFFFF
9227 #define R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x028C24
9228 #define S_028C24_S12_X(x) (((x) & 0x0F) << 0)
9229 #define G_028C24_S12_X(x) (((x) >> 0) & 0x0F)
9230 #define C_028C24_S12_X 0xFFFFFFF0
9231 #define S_028C24_S12_Y(x) (((x) & 0x0F) << 4)
9232 #define G_028C24_S12_Y(x) (((x) >> 4) & 0x0F)
9233 #define C_028C24_S12_Y 0xFFFFFF0F
9234 #define S_028C24_S13_X(x) (((x) & 0x0F) << 8)
9235 #define G_028C24_S13_X(x) (((x) >> 8) & 0x0F)
9236 #define C_028C24_S13_X 0xFFFFF0FF
9237 #define S_028C24_S13_Y(x) (((x) & 0x0F) << 12)
9238 #define G_028C24_S13_Y(x) (((x) >> 12) & 0x0F)
9239 #define C_028C24_S13_Y 0xFFFF0FFF
9240 #define S_028C24_S14_X(x) (((x) & 0x0F) << 16)
9241 #define G_028C24_S14_X(x) (((x) >> 16) & 0x0F)
9242 #define C_028C24_S14_X 0xFFF0FFFF
9243 #define S_028C24_S14_Y(x) (((x) & 0x0F) << 20)
9244 #define G_028C24_S14_Y(x) (((x) >> 20) & 0x0F)
9245 #define C_028C24_S14_Y 0xFF0FFFFF
9246 #define S_028C24_S15_X(x) (((x) & 0x0F) << 24)
9247 #define G_028C24_S15_X(x) (((x) >> 24) & 0x0F)
9248 #define C_028C24_S15_X 0xF0FFFFFF
9249 #define S_028C24_S15_Y(x) (((x) & 0x0F) << 28)
9250 #define G_028C24_S15_Y(x) (((x) >> 28) & 0x0F)
9251 #define C_028C24_S15_Y 0x0FFFFFFF
9252 #define R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x028C28
9253 #define S_028C28_S0_X(x) (((x) & 0x0F) << 0)
9254 #define G_028C28_S0_X(x) (((x) >> 0) & 0x0F)
9255 #define C_028C28_S0_X 0xFFFFFFF0
9256 #define S_028C28_S0_Y(x) (((x) & 0x0F) << 4)
9257 #define G_028C28_S0_Y(x) (((x) >> 4) & 0x0F)
9258 #define C_028C28_S0_Y 0xFFFFFF0F
9259 #define S_028C28_S1_X(x) (((x) & 0x0F) << 8)
9260 #define G_028C28_S1_X(x) (((x) >> 8) & 0x0F)
9261 #define C_028C28_S1_X 0xFFFFF0FF
9262 #define S_028C28_S1_Y(x) (((x) & 0x0F) << 12)
9263 #define G_028C28_S1_Y(x) (((x) >> 12) & 0x0F)
9264 #define C_028C28_S1_Y 0xFFFF0FFF
9265 #define S_028C28_S2_X(x) (((x) & 0x0F) << 16)
9266 #define G_028C28_S2_X(x) (((x) >> 16) & 0x0F)
9267 #define C_028C28_S2_X 0xFFF0FFFF
9268 #define S_028C28_S2_Y(x) (((x) & 0x0F) << 20)
9269 #define G_028C28_S2_Y(x) (((x) >> 20) & 0x0F)
9270 #define C_028C28_S2_Y 0xFF0FFFFF
9271 #define S_028C28_S3_X(x) (((x) & 0x0F) << 24)
9272 #define G_028C28_S3_X(x) (((x) >> 24) & 0x0F)
9273 #define C_028C28_S3_X 0xF0FFFFFF
9274 #define S_028C28_S3_Y(x) (((x) & 0x0F) << 28)
9275 #define G_028C28_S3_Y(x) (((x) >> 28) & 0x0F)
9276 #define C_028C28_S3_Y 0x0FFFFFFF
9277 #define R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x028C2C
9278 #define S_028C2C_S4_X(x) (((x) & 0x0F) << 0)
9279 #define G_028C2C_S4_X(x) (((x) >> 0) & 0x0F)
9280 #define C_028C2C_S4_X 0xFFFFFFF0
9281 #define S_028C2C_S4_Y(x) (((x) & 0x0F) << 4)
9282 #define G_028C2C_S4_Y(x) (((x) >> 4) & 0x0F)
9283 #define C_028C2C_S4_Y 0xFFFFFF0F
9284 #define S_028C2C_S5_X(x) (((x) & 0x0F) << 8)
9285 #define G_028C2C_S5_X(x) (((x) >> 8) & 0x0F)
9286 #define C_028C2C_S5_X 0xFFFFF0FF
9287 #define S_028C2C_S5_Y(x) (((x) & 0x0F) << 12)
9288 #define G_028C2C_S5_Y(x) (((x) >> 12) & 0x0F)
9289 #define C_028C2C_S5_Y 0xFFFF0FFF
9290 #define S_028C2C_S6_X(x) (((x) & 0x0F) << 16)
9291 #define G_028C2C_S6_X(x) (((x) >> 16) & 0x0F)
9292 #define C_028C2C_S6_X 0xFFF0FFFF
9293 #define S_028C2C_S6_Y(x) (((x) & 0x0F) << 20)
9294 #define G_028C2C_S6_Y(x) (((x) >> 20) & 0x0F)
9295 #define C_028C2C_S6_Y 0xFF0FFFFF
9296 #define S_028C2C_S7_X(x) (((x) & 0x0F) << 24)
9297 #define G_028C2C_S7_X(x) (((x) >> 24) & 0x0F)
9298 #define C_028C2C_S7_X 0xF0FFFFFF
9299 #define S_028C2C_S7_Y(x) (((x) & 0x0F) << 28)
9300 #define G_028C2C_S7_Y(x) (((x) >> 28) & 0x0F)
9301 #define C_028C2C_S7_Y 0x0FFFFFFF
9302 #define R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x028C30
9303 #define S_028C30_S8_X(x) (((x) & 0x0F) << 0)
9304 #define G_028C30_S8_X(x) (((x) >> 0) & 0x0F)
9305 #define C_028C30_S8_X 0xFFFFFFF0
9306 #define S_028C30_S8_Y(x) (((x) & 0x0F) << 4)
9307 #define G_028C30_S8_Y(x) (((x) >> 4) & 0x0F)
9308 #define C_028C30_S8_Y 0xFFFFFF0F
9309 #define S_028C30_S9_X(x) (((x) & 0x0F) << 8)
9310 #define G_028C30_S9_X(x) (((x) >> 8) & 0x0F)
9311 #define C_028C30_S9_X 0xFFFFF0FF
9312 #define S_028C30_S9_Y(x) (((x) & 0x0F) << 12)
9313 #define G_028C30_S9_Y(x) (((x) >> 12) & 0x0F)
9314 #define C_028C30_S9_Y 0xFFFF0FFF
9315 #define S_028C30_S10_X(x) (((x) & 0x0F) << 16)
9316 #define G_028C30_S10_X(x) (((x) >> 16) & 0x0F)
9317 #define C_028C30_S10_X 0xFFF0FFFF
9318 #define S_028C30_S10_Y(x) (((x) & 0x0F) << 20)
9319 #define G_028C30_S10_Y(x) (((x) >> 20) & 0x0F)
9320 #define C_028C30_S10_Y 0xFF0FFFFF
9321 #define S_028C30_S11_X(x) (((x) & 0x0F) << 24)
9322 #define G_028C30_S11_X(x) (((x) >> 24) & 0x0F)
9323 #define C_028C30_S11_X 0xF0FFFFFF
9324 #define S_028C30_S11_Y(x) (((x) & 0x0F) << 28)
9325 #define G_028C30_S11_Y(x) (((x) >> 28) & 0x0F)
9326 #define C_028C30_S11_Y 0x0FFFFFFF
9327 #define R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x028C34
9328 #define S_028C34_S12_X(x) (((x) & 0x0F) << 0)
9329 #define G_028C34_S12_X(x) (((x) >> 0) & 0x0F)
9330 #define C_028C34_S12_X 0xFFFFFFF0
9331 #define S_028C34_S12_Y(x) (((x) & 0x0F) << 4)
9332 #define G_028C34_S12_Y(x) (((x) >> 4) & 0x0F)
9333 #define C_028C34_S12_Y 0xFFFFFF0F
9334 #define S_028C34_S13_X(x) (((x) & 0x0F) << 8)
9335 #define G_028C34_S13_X(x) (((x) >> 8) & 0x0F)
9336 #define C_028C34_S13_X 0xFFFFF0FF
9337 #define S_028C34_S13_Y(x) (((x) & 0x0F) << 12)
9338 #define G_028C34_S13_Y(x) (((x) >> 12) & 0x0F)
9339 #define C_028C34_S13_Y 0xFFFF0FFF
9340 #define S_028C34_S14_X(x) (((x) & 0x0F) << 16)
9341 #define G_028C34_S14_X(x) (((x) >> 16) & 0x0F)
9342 #define C_028C34_S14_X 0xFFF0FFFF
9343 #define S_028C34_S14_Y(x) (((x) & 0x0F) << 20)
9344 #define G_028C34_S14_Y(x) (((x) >> 20) & 0x0F)
9345 #define C_028C34_S14_Y 0xFF0FFFFF
9346 #define S_028C34_S15_X(x) (((x) & 0x0F) << 24)
9347 #define G_028C34_S15_X(x) (((x) >> 24) & 0x0F)
9348 #define C_028C34_S15_X 0xF0FFFFFF
9349 #define S_028C34_S15_Y(x) (((x) & 0x0F) << 28)
9350 #define G_028C34_S15_Y(x) (((x) >> 28) & 0x0F)
9351 #define C_028C34_S15_Y 0x0FFFFFFF
9352 #define R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 0x028C38
9353 #define S_028C38_AA_MASK_X0Y0(x) (((x) & 0xFFFF) << 0)
9354 #define G_028C38_AA_MASK_X0Y0(x) (((x) >> 0) & 0xFFFF)
9355 #define C_028C38_AA_MASK_X0Y0 0xFFFF0000
9356 #define S_028C38_AA_MASK_X1Y0(x) (((x) & 0xFFFF) << 16)
9357 #define G_028C38_AA_MASK_X1Y0(x) (((x) >> 16) & 0xFFFF)
9358 #define C_028C38_AA_MASK_X1Y0 0x0000FFFF
9359 #define R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 0x028C3C
9360 #define S_028C3C_AA_MASK_X0Y1(x) (((x) & 0xFFFF) << 0)
9361 #define G_028C3C_AA_MASK_X0Y1(x) (((x) >> 0) & 0xFFFF)
9362 #define C_028C3C_AA_MASK_X0Y1 0xFFFF0000
9363 #define S_028C3C_AA_MASK_X1Y1(x) (((x) & 0xFFFF) << 16)
9364 #define G_028C3C_AA_MASK_X1Y1(x) (((x) >> 16) & 0xFFFF)
9365 #define C_028C3C_AA_MASK_X1Y1 0x0000FFFF
9366 #define R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL 0x028C58
9367 #define S_028C58_VTX_REUSE_DEPTH(x) (((x) & 0xFF) << 0)
9368 #define G_028C58_VTX_REUSE_DEPTH(x) (((x) >> 0) & 0xFF)
9369 #define C_028C58_VTX_REUSE_DEPTH 0xFFFFFF00
9370 #define R_028C5C_VGT_OUT_DEALLOC_CNTL 0x028C5C
9371 #define S_028C5C_DEALLOC_DIST(x) (((x) & 0x7F) << 0)
9372 #define G_028C5C_DEALLOC_DIST(x) (((x) >> 0) & 0x7F)
9373 #define C_028C5C_DEALLOC_DIST 0xFFFFFF80
9374 #define R_028C60_CB_COLOR0_BASE 0x028C60
9375 #define R_028C64_CB_COLOR0_PITCH 0x028C64
9376 #define S_028C64_TILE_MAX(x) (((x) & 0x7FF) << 0)
9377 #define G_028C64_TILE_MAX(x) (((x) >> 0) & 0x7FF)
9378 #define C_028C64_TILE_MAX 0xFFFFF800
9379 /* CIK */
9380 #define S_028C64_FMASK_TILE_MAX(x) (((x) & 0x7FF) << 20)
9381 #define G_028C64_FMASK_TILE_MAX(x) (((x) >> 20) & 0x7FF)
9382 #define C_028C64_FMASK_TILE_MAX 0x800FFFFF
9383 /* */
9384 #define R_028C68_CB_COLOR0_SLICE 0x028C68
9385 #define S_028C68_TILE_MAX(x) (((x) & 0x3FFFFF) << 0)
9386 #define G_028C68_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF)
9387 #define C_028C68_TILE_MAX 0xFFC00000
9388 #define R_028C6C_CB_COLOR0_VIEW 0x028C6C
9389 #define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0)
9390 #define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF)
9391 #define C_028C6C_SLICE_START 0xFFFFF800
9392 #define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13)
9393 #define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
9394 #define C_028C6C_SLICE_MAX 0xFF001FFF
9395 #define R_028C70_CB_COLOR0_INFO 0x028C70
9396 #define S_028C70_ENDIAN(x) (((x) & 0x03) << 0)
9397 #define G_028C70_ENDIAN(x) (((x) >> 0) & 0x03)
9398 #define C_028C70_ENDIAN 0xFFFFFFFC
9399 #define V_028C70_ENDIAN_NONE 0x00
9400 #define V_028C70_ENDIAN_8IN16 0x01
9401 #define V_028C70_ENDIAN_8IN32 0x02
9402 #define V_028C70_ENDIAN_8IN64 0x03
9403 #define S_028C70_FORMAT(x) (((x) & 0x1F) << 2)
9404 #define G_028C70_FORMAT(x) (((x) >> 2) & 0x1F)
9405 #define C_028C70_FORMAT 0xFFFFFF83
9406 #define V_028C70_COLOR_INVALID 0x00
9407 #define V_028C70_COLOR_8 0x01
9408 #define V_028C70_COLOR_16 0x02
9409 #define V_028C70_COLOR_8_8 0x03
9410 #define V_028C70_COLOR_32 0x04
9411 #define V_028C70_COLOR_16_16 0x05
9412 #define V_028C70_COLOR_10_11_11 0x06
9413 #define V_028C70_COLOR_11_11_10 0x07
9414 #define V_028C70_COLOR_10_10_10_2 0x08
9415 #define V_028C70_COLOR_2_10_10_10 0x09
9416 #define V_028C70_COLOR_8_8_8_8 0x0A
9417 #define V_028C70_COLOR_32_32 0x0B
9418 #define V_028C70_COLOR_16_16_16_16 0x0C
9419 #define V_028C70_COLOR_32_32_32_32 0x0E
9420 #define V_028C70_COLOR_5_6_5 0x10
9421 #define V_028C70_COLOR_1_5_5_5 0x11
9422 #define V_028C70_COLOR_5_5_5_1 0x12
9423 #define V_028C70_COLOR_4_4_4_4 0x13
9424 #define V_028C70_COLOR_8_24 0x14
9425 #define V_028C70_COLOR_24_8 0x15
9426 #define V_028C70_COLOR_X24_8_32_FLOAT 0x16
9427 #define S_028C70_LINEAR_GENERAL(x) (((x) & 0x1) << 7)
9428 #define G_028C70_LINEAR_GENERAL(x) (((x) >> 7) & 0x1)
9429 #define C_028C70_LINEAR_GENERAL 0xFFFFFF7F
9430 #define S_028C70_NUMBER_TYPE(x) (((x) & 0x07) << 8)
9431 #define G_028C70_NUMBER_TYPE(x) (((x) >> 8) & 0x07)
9432 #define C_028C70_NUMBER_TYPE 0xFFFFF8FF
9433 #define V_028C70_NUMBER_UNORM 0x00
9434 #define V_028C70_NUMBER_SNORM 0x01
9435 #define V_028C70_NUMBER_UINT 0x04
9436 #define V_028C70_NUMBER_SINT 0x05
9437 #define V_028C70_NUMBER_SRGB 0x06
9438 #define V_028C70_NUMBER_FLOAT 0x07
9439 #define S_028C70_COMP_SWAP(x) (((x) & 0x03) << 11)
9440 #define G_028C70_COMP_SWAP(x) (((x) >> 11) & 0x03)
9441 #define C_028C70_COMP_SWAP 0xFFFFE7FF
9442 #define V_028C70_SWAP_STD 0x00
9443 #define V_028C70_SWAP_ALT 0x01
9444 #define V_028C70_SWAP_STD_REV 0x02
9445 #define V_028C70_SWAP_ALT_REV 0x03
9446 #define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 13)
9447 #define G_028C70_FAST_CLEAR(x) (((x) >> 13) & 0x1)
9448 #define C_028C70_FAST_CLEAR 0xFFFFDFFF
9449 #define S_028C70_COMPRESSION(x) (((x) & 0x1) << 14)
9450 #define G_028C70_COMPRESSION(x) (((x) >> 14) & 0x1)
9451 #define C_028C70_COMPRESSION 0xFFFFBFFF
9452 #define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 15)
9453 #define G_028C70_BLEND_CLAMP(x) (((x) >> 15) & 0x1)
9454 #define C_028C70_BLEND_CLAMP 0xFFFF7FFF
9455 #define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 16)
9456 #define G_028C70_BLEND_BYPASS(x) (((x) >> 16) & 0x1)
9457 #define C_028C70_BLEND_BYPASS 0xFFFEFFFF
9458 #define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 17)
9459 #define G_028C70_SIMPLE_FLOAT(x) (((x) >> 17) & 0x1)
9460 #define C_028C70_SIMPLE_FLOAT 0xFFFDFFFF
9461 #define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 18)
9462 #define G_028C70_ROUND_MODE(x) (((x) >> 18) & 0x1)
9463 #define C_028C70_ROUND_MODE 0xFFFBFFFF
9464 #define S_028C70_CMASK_IS_LINEAR(x) (((x) & 0x1) << 19)
9465 #define G_028C70_CMASK_IS_LINEAR(x) (((x) >> 19) & 0x1)
9466 #define C_028C70_CMASK_IS_LINEAR 0xFFF7FFFF
9467 #define S_028C70_BLEND_OPT_DONT_RD_DST(x) (((x) & 0x07) << 20)
9468 #define G_028C70_BLEND_OPT_DONT_RD_DST(x) (((x) >> 20) & 0x07)
9469 #define C_028C70_BLEND_OPT_DONT_RD_DST 0xFF8FFFFF
9470 #define V_028C70_FORCE_OPT_AUTO 0x00
9471 #define V_028C70_FORCE_OPT_DISABLE 0x01
9472 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_0 0x02
9473 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_0 0x03
9474 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_0 0x04
9475 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_1 0x05
9476 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_1 0x06
9477 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_1 0x07
9478 #define S_028C70_BLEND_OPT_DISCARD_PIXEL(x) (((x) & 0x07) << 23)
9479 #define G_028C70_BLEND_OPT_DISCARD_PIXEL(x) (((x) >> 23) & 0x07)
9480 #define C_028C70_BLEND_OPT_DISCARD_PIXEL 0xFC7FFFFF
9481 #define V_028C70_FORCE_OPT_AUTO 0x00
9482 #define V_028C70_FORCE_OPT_DISABLE 0x01
9483 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_0 0x02
9484 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_0 0x03
9485 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_0 0x04
9486 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_1 0x05
9487 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_1 0x06
9488 #define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_1 0x07
9489 /* CIK */
9490 #define S_028C70_FMASK_COMPRESSION_DISABLE(x) (((x) & 0x1) << 26)
9491 #define G_028C70_FMASK_COMPRESSION_DISABLE(x) (((x) >> 26) & 0x1)
9492 #define C_028C70_FMASK_COMPRESSION_DISABLE 0xFBFFFFFF
9493 /* */
9494 /* VI */
9495 #define S_028C70_FMASK_COMPRESS_1FRAG_ONLY(x) (((x) & 0x1) << 27)
9496 #define G_028C70_FMASK_COMPRESS_1FRAG_ONLY(x) (((x) >> 27) & 0x1)
9497 #define C_028C70_FMASK_COMPRESS_1FRAG_ONLY 0xF7FFFFFF
9498 #define S_028C70_DCC_ENABLE(x) (((x) & 0x1) << 28)
9499 #define G_028C70_DCC_ENABLE(x) (((x) >> 28) & 0x1)
9500 #define C_028C70_DCC_ENABLE 0xEFFFFFFF
9501 #define S_028C70_CMASK_ADDR_TYPE(x) (((x) & 0x03) << 29)
9502 #define G_028C70_CMASK_ADDR_TYPE(x) (((x) >> 29) & 0x03)
9503 #define C_028C70_CMASK_ADDR_TYPE 0x9FFFFFFF
9504 /* */
9505 #define R_028C74_CB_COLOR0_ATTRIB 0x028C74
9506 #define S_028C74_TILE_MODE_INDEX(x) (((x) & 0x1F) << 0)
9507 #define G_028C74_TILE_MODE_INDEX(x) (((x) >> 0) & 0x1F)
9508 #define C_028C74_TILE_MODE_INDEX 0xFFFFFFE0
9509 #define S_028C74_FMASK_TILE_MODE_INDEX(x) (((x) & 0x1F) << 5)
9510 #define G_028C74_FMASK_TILE_MODE_INDEX(x) (((x) >> 5) & 0x1F)
9511 #define C_028C74_FMASK_TILE_MODE_INDEX 0xFFFFFC1F
9512 #define S_028C74_FMASK_BANK_HEIGHT(x) (((x) & 0x03) << 10)
9513 #define G_028C74_FMASK_BANK_HEIGHT(x) (((x) >> 10) & 0x03)
9514 #define C_028C74_FMASK_BANK_HEIGHT 0xFFFFF3FF
9515 #define S_028C74_NUM_SAMPLES(x) (((x) & 0x07) << 12)
9516 #define G_028C74_NUM_SAMPLES(x) (((x) >> 12) & 0x07)
9517 #define C_028C74_NUM_SAMPLES 0xFFFF8FFF
9518 #define S_028C74_NUM_FRAGMENTS(x) (((x) & 0x03) << 15)
9519 #define G_028C74_NUM_FRAGMENTS(x) (((x) >> 15) & 0x03)
9520 #define C_028C74_NUM_FRAGMENTS 0xFFFE7FFF
9521 #define S_028C74_FORCE_DST_ALPHA_1(x) (((x) & 0x1) << 17)
9522 #define G_028C74_FORCE_DST_ALPHA_1(x) (((x) >> 17) & 0x1)
9523 #define C_028C74_FORCE_DST_ALPHA_1 0xFFFDFFFF
9524 /* VI */
9525 #define R_028C78_CB_COLOR0_DCC_CONTROL 0x028C78
9526 #define S_028C78_OVERWRITE_COMBINER_DISABLE(x) (((x) & 0x1) << 0)
9527 #define G_028C78_OVERWRITE_COMBINER_DISABLE(x) (((x) >> 0) & 0x1)
9528 #define C_028C78_OVERWRITE_COMBINER_DISABLE 0xFFFFFFFE
9529 #define S_028C78_KEY_CLEAR_ENABLE(x) (((x) & 0x1) << 1)
9530 #define G_028C78_KEY_CLEAR_ENABLE(x) (((x) >> 1) & 0x1)
9531 #define C_028C78_KEY_CLEAR_ENABLE 0xFFFFFFFD
9532 #define S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(x) (((x) & 0x03) << 2)
9533 #define G_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(x) (((x) >> 2) & 0x03)
9534 #define C_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE 0xFFFFFFF3
9535 #define S_028C78_MIN_COMPRESSED_BLOCK_SIZE(x) (((x) & 0x1) << 4)
9536 #define G_028C78_MIN_COMPRESSED_BLOCK_SIZE(x) (((x) >> 4) & 0x1)
9537 #define C_028C78_MIN_COMPRESSED_BLOCK_SIZE 0xFFFFFFEF
9538 #define S_028C78_MAX_COMPRESSED_BLOCK_SIZE(x) (((x) & 0x03) << 5)
9539 #define G_028C78_MAX_COMPRESSED_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
9540 #define C_028C78_MAX_COMPRESSED_BLOCK_SIZE 0xFFFFFF9F
9541 #define S_028C78_COLOR_TRANSFORM(x) (((x) & 0x03) << 7)
9542 #define G_028C78_COLOR_TRANSFORM(x) (((x) >> 7) & 0x03)
9543 #define C_028C78_COLOR_TRANSFORM 0xFFFFFE7F
9544 #define S_028C78_INDEPENDENT_64B_BLOCKS(x) (((x) & 0x1) << 9)
9545 #define G_028C78_INDEPENDENT_64B_BLOCKS(x) (((x) >> 9) & 0x1)
9546 #define C_028C78_INDEPENDENT_64B_BLOCKS 0xFFFFFDFF
9547 #define S_028C78_LOSSY_RGB_PRECISION(x) (((x) & 0x0F) << 10)
9548 #define G_028C78_LOSSY_RGB_PRECISION(x) (((x) >> 10) & 0x0F)
9549 #define C_028C78_LOSSY_RGB_PRECISION 0xFFFFC3FF
9550 #define S_028C78_LOSSY_ALPHA_PRECISION(x) (((x) & 0x0F) << 14)
9551 #define G_028C78_LOSSY_ALPHA_PRECISION(x) (((x) >> 14) & 0x0F)
9552 #define C_028C78_LOSSY_ALPHA_PRECISION 0xFFFC3FFF
9553 /* */
9554 #define R_028C7C_CB_COLOR0_CMASK 0x028C7C
9555 #define R_028C80_CB_COLOR0_CMASK_SLICE 0x028C80
9556 #define S_028C80_TILE_MAX(x) (((x) & 0x3FFF) << 0)
9557 #define G_028C80_TILE_MAX(x) (((x) >> 0) & 0x3FFF)
9558 #define C_028C80_TILE_MAX 0xFFFFC000
9559 #define R_028C84_CB_COLOR0_FMASK 0x028C84
9560 #define R_028C88_CB_COLOR0_FMASK_SLICE 0x028C88
9561 #define S_028C88_TILE_MAX(x) (((x) & 0x3FFFFF) << 0)
9562 #define G_028C88_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF)
9563 #define C_028C88_TILE_MAX 0xFFC00000
9564 #define R_028C8C_CB_COLOR0_CLEAR_WORD0 0x028C8C
9565 #define R_028C90_CB_COLOR0_CLEAR_WORD1 0x028C90
9566 #define R_028C94_CB_COLOR0_DCC_BASE 0x028C94 /* VI */
9567 #define R_028C9C_CB_COLOR1_BASE 0x028C9C
9568 #define R_028CA0_CB_COLOR1_PITCH 0x028CA0
9569 #define R_028CA4_CB_COLOR1_SLICE 0x028CA4
9570 #define R_028CA8_CB_COLOR1_VIEW 0x028CA8
9571 #define R_028CAC_CB_COLOR1_INFO 0x028CAC
9572 #define R_028CB0_CB_COLOR1_ATTRIB 0x028CB0
9573 #define R_028CB4_CB_COLOR1_DCC_CONTROL 0x028CB4 /* VI */
9574 #define R_028CB8_CB_COLOR1_CMASK 0x028CB8
9575 #define R_028CBC_CB_COLOR1_CMASK_SLICE 0x028CBC
9576 #define R_028CC0_CB_COLOR1_FMASK 0x028CC0
9577 #define R_028CC4_CB_COLOR1_FMASK_SLICE 0x028CC4
9578 #define R_028CC8_CB_COLOR1_CLEAR_WORD0 0x028CC8
9579 #define R_028CCC_CB_COLOR1_CLEAR_WORD1 0x028CCC
9580 #define R_028CD0_CB_COLOR1_DCC_BASE 0x028CD0 /* VI */
9581 #define R_028CD8_CB_COLOR2_BASE 0x028CD8
9582 #define R_028CDC_CB_COLOR2_PITCH 0x028CDC
9583 #define R_028CE0_CB_COLOR2_SLICE 0x028CE0
9584 #define R_028CE4_CB_COLOR2_VIEW 0x028CE4
9585 #define R_028CE8_CB_COLOR2_INFO 0x028CE8
9586 #define R_028CEC_CB_COLOR2_ATTRIB 0x028CEC
9587 #define R_028CF0_CB_COLOR2_DCC_CONTROL 0x028CF0 /* VI */
9588 #define R_028CF4_CB_COLOR2_CMASK 0x028CF4
9589 #define R_028CF8_CB_COLOR2_CMASK_SLICE 0x028CF8
9590 #define R_028CFC_CB_COLOR2_FMASK 0x028CFC
9591 #define R_028D00_CB_COLOR2_FMASK_SLICE 0x028D00
9592 #define R_028D04_CB_COLOR2_CLEAR_WORD0 0x028D04
9593 #define R_028D08_CB_COLOR2_CLEAR_WORD1 0x028D08
9594 #define R_028D0C_CB_COLOR2_DCC_BASE 0x028D0C /* VI */
9595 #define R_028D14_CB_COLOR3_BASE 0x028D14
9596 #define R_028D18_CB_COLOR3_PITCH 0x028D18
9597 #define R_028D1C_CB_COLOR3_SLICE 0x028D1C
9598 #define R_028D20_CB_COLOR3_VIEW 0x028D20
9599 #define R_028D24_CB_COLOR3_INFO 0x028D24
9600 #define R_028D28_CB_COLOR3_ATTRIB 0x028D28
9601 #define R_028D2C_CB_COLOR3_DCC_CONTROL 0x028D2C /* VI */
9602 #define R_028D30_CB_COLOR3_CMASK 0x028D30
9603 #define R_028D34_CB_COLOR3_CMASK_SLICE 0x028D34
9604 #define R_028D38_CB_COLOR3_FMASK 0x028D38
9605 #define R_028D3C_CB_COLOR3_FMASK_SLICE 0x028D3C
9606 #define R_028D40_CB_COLOR3_CLEAR_WORD0 0x028D40
9607 #define R_028D44_CB_COLOR3_CLEAR_WORD1 0x028D44
9608 #define R_028D48_CB_COLOR3_DCC_BASE 0x028D48 /* VI */
9609 #define R_028D50_CB_COLOR4_BASE 0x028D50
9610 #define R_028D54_CB_COLOR4_PITCH 0x028D54
9611 #define R_028D58_CB_COLOR4_SLICE 0x028D58
9612 #define R_028D5C_CB_COLOR4_VIEW 0x028D5C
9613 #define R_028D60_CB_COLOR4_INFO 0x028D60
9614 #define R_028D64_CB_COLOR4_ATTRIB 0x028D64
9615 #define R_028D68_CB_COLOR4_DCC_CONTROL 0x028D68 /* VI */
9616 #define R_028D6C_CB_COLOR4_CMASK 0x028D6C
9617 #define R_028D70_CB_COLOR4_CMASK_SLICE 0x028D70
9618 #define R_028D74_CB_COLOR4_FMASK 0x028D74
9619 #define R_028D78_CB_COLOR4_FMASK_SLICE 0x028D78
9620 #define R_028D7C_CB_COLOR4_CLEAR_WORD0 0x028D7C
9621 #define R_028D80_CB_COLOR4_CLEAR_WORD1 0x028D80
9622 #define R_028D84_CB_COLOR4_DCC_BASE 0x028D84 /* VI */
9623 #define R_028D8C_CB_COLOR5_BASE 0x028D8C
9624 #define R_028D90_CB_COLOR5_PITCH 0x028D90
9625 #define R_028D94_CB_COLOR5_SLICE 0x028D94
9626 #define R_028D98_CB_COLOR5_VIEW 0x028D98
9627 #define R_028D9C_CB_COLOR5_INFO 0x028D9C
9628 #define R_028DA0_CB_COLOR5_ATTRIB 0x028DA0
9629 #define R_028DA4_CB_COLOR5_DCC_CONTROL 0x028DA4 /* VI */
9630 #define R_028DA8_CB_COLOR5_CMASK 0x028DA8
9631 #define R_028DAC_CB_COLOR5_CMASK_SLICE 0x028DAC
9632 #define R_028DB0_CB_COLOR5_FMASK 0x028DB0
9633 #define R_028DB4_CB_COLOR5_FMASK_SLICE 0x028DB4
9634 #define R_028DB8_CB_COLOR5_CLEAR_WORD0 0x028DB8
9635 #define R_028DBC_CB_COLOR5_CLEAR_WORD1 0x028DBC
9636 #define R_028DC0_CB_COLOR5_DCC_BASE 0x028DC0 /* VI */
9637 #define R_028DC8_CB_COLOR6_BASE 0x028DC8
9638 #define R_028DCC_CB_COLOR6_PITCH 0x028DCC
9639 #define R_028DD0_CB_COLOR6_SLICE 0x028DD0
9640 #define R_028DD4_CB_COLOR6_VIEW 0x028DD4
9641 #define R_028DD8_CB_COLOR6_INFO 0x028DD8
9642 #define R_028DDC_CB_COLOR6_ATTRIB 0x028DDC
9643 #define R_028DE0_CB_COLOR6_DCC_CONTROL 0x028DE0 /* VI */
9644 #define R_028DE4_CB_COLOR6_CMASK 0x028DE4
9645 #define R_028DE8_CB_COLOR6_CMASK_SLICE 0x028DE8
9646 #define R_028DEC_CB_COLOR6_FMASK 0x028DEC
9647 #define R_028DF0_CB_COLOR6_FMASK_SLICE 0x028DF0
9648 #define R_028DF4_CB_COLOR6_CLEAR_WORD0 0x028DF4
9649 #define R_028DF8_CB_COLOR6_CLEAR_WORD1 0x028DF8
9650 #define R_028DFC_CB_COLOR6_DCC_BASE 0x028DFC /* VI */
9651 #define R_028E04_CB_COLOR7_BASE 0x028E04
9652 #define R_028E08_CB_COLOR7_PITCH 0x028E08
9653 #define R_028E0C_CB_COLOR7_SLICE 0x028E0C
9654 #define R_028E10_CB_COLOR7_VIEW 0x028E10
9655 #define R_028E14_CB_COLOR7_INFO 0x028E14
9656 #define R_028E18_CB_COLOR7_ATTRIB 0x028E18
9657 #define R_028E1C_CB_COLOR7_DCC_CONTROL 0x028E1C /* VI */
9658 #define R_028E20_CB_COLOR7_CMASK 0x028E20
9659 #define R_028E24_CB_COLOR7_CMASK_SLICE 0x028E24
9660 #define R_028E28_CB_COLOR7_FMASK 0x028E28
9661 #define R_028E2C_CB_COLOR7_FMASK_SLICE 0x028E2C
9662 #define R_028E30_CB_COLOR7_CLEAR_WORD0 0x028E30
9663 #define R_028E34_CB_COLOR7_CLEAR_WORD1 0x028E34
9664 #define R_028E38_CB_COLOR7_DCC_BASE 0x028E38 /* VI */
9665
9666 /* SI async DMA packets */
9667 #define SI_DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) | \
9668 (((sub_cmd) & 0xFF) << 20) |\
9669 (((n) & 0xFFFFF) << 0))
9670 /* SI async DMA Packet types */
9671 #define SI_DMA_PACKET_WRITE 0x2
9672 #define SI_DMA_PACKET_COPY 0x3
9673 #define SI_DMA_COPY_MAX_SIZE 0xfffe0
9674 #define SI_DMA_COPY_MAX_SIZE_DW 0xffff8
9675 #define SI_DMA_COPY_DWORD_ALIGNED 0x00
9676 #define SI_DMA_COPY_BYTE_ALIGNED 0x40
9677 #define SI_DMA_COPY_TILED 0x8
9678 #define SI_DMA_PACKET_INDIRECT_BUFFER 0x4
9679 #define SI_DMA_PACKET_SEMAPHORE 0x5
9680 #define SI_DMA_PACKET_FENCE 0x6
9681 #define SI_DMA_PACKET_TRAP 0x7
9682 #define SI_DMA_PACKET_SRBM_WRITE 0x9
9683 #define SI_DMA_PACKET_CONSTANT_FILL 0xd
9684 #define SI_DMA_PACKET_NOP 0xf
9685
9686 /* CIK async DMA packets */
9687 #define CIK_SDMA_PACKET(op, sub_op, n) ((((n) & 0xFFFF) << 16) | \
9688 (((sub_op) & 0xFF) << 8) | \
9689 (((op) & 0xFF) << 0))
9690 /* CIK async DMA packet types */
9691 #define CIK_SDMA_OPCODE_NOP 0x0
9692 #define CIK_SDMA_OPCODE_COPY 0x1
9693 #define CIK_SDMA_COPY_SUB_OPCODE_LINEAR 0x0
9694 #define CIK_SDMA_COPY_SUB_OPCODE_TILED 0x1
9695 #define CIK_SDMA_COPY_SUB_OPCODE_SOA 0x3
9696 #define CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 0x4
9697 #define CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 0x5
9698 #define CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 0x6
9699 #define CIK_SDMA_OPCODE_WRITE 0x2
9700 #define SDMA_WRITE_SUB_OPCODE_LINEAR 0x0
9701 #define SDMA_WRTIE_SUB_OPCODE_TILED 0x1
9702 #define CIK_SDMA_OPCODE_INDIRECT_BUFFER 0x4
9703 #define CIK_SDMA_PACKET_FENCE 0x5
9704 #define CIK_SDMA_PACKET_TRAP 0x6
9705 #define CIK_SDMA_PACKET_SEMAPHORE 0x7
9706 #define CIK_SDMA_PACKET_CONSTANT_FILL 0xb
9707 #define CIK_SDMA_PACKET_SRBM_WRITE 0xe
9708 #define CIK_SDMA_COPY_MAX_SIZE 0x1fffff
9709
9710 #endif /* _SID_H */
9711