radeonsi: move MRT color exporting into a separate function
[mesa.git] / src / gallium / drivers / radeonsi / sid_tables.py
1 #!/usr/bin/env python
2
3 CopyRight = '''
4 /*
5 * Copyright 2015 Advanced Micro Devices, Inc.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * on the rights to use, copy, modify, merge, publish, distribute, sub
11 * license, and/or sell copies of the Software, and to permit persons to whom
12 * the Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27 '''
28
29 import sys
30 import re
31
32
33 class Field:
34 def __init__(self, reg, s_name):
35 self.s_name = s_name
36 self.name = strip_prefix(s_name)
37 self.values = []
38 self.varname_values = '%s__%s__values' % (reg.r_name.lower(), self.name.lower())
39
40 class Reg:
41 def __init__(self, r_name):
42 self.r_name = r_name
43 self.name = strip_prefix(r_name)
44 self.fields = []
45 self.varname_fields = '%s__fields' % self.r_name.lower()
46 self.own_fields = True
47
48
49 def strip_prefix(s):
50 '''Strip prefix in the form ._.*_, e.g. R_001234_'''
51 return s[s[2:].find('_')+3:]
52
53
54 def parse(filename):
55 stream = open(filename)
56 regs = []
57 packets = []
58
59 for line in stream:
60 if not line.startswith('#define '):
61 continue
62
63 line = line[8:].strip()
64
65 if line.startswith('R_'):
66 reg = Reg(line.split()[0])
67 regs.append(reg)
68
69 elif line.startswith('S_'):
70 field = Field(reg, line[:line.find('(')])
71 reg.fields.append(field)
72
73 elif line.startswith('V_'):
74 field.values.append(line.split()[0])
75
76 elif line.startswith('PKT3_') and line.find('0x') != -1 and line.find('(') == -1:
77 packets.append(line.split()[0])
78
79 # Copy fields to indexed registers which have their fields only defined
80 # at register index 0.
81 # For example, copy fields from CB_COLOR0_INFO to CB_COLORn_INFO, n > 0.
82 match_number = re.compile('[0-9]+')
83 reg_dict = dict()
84
85 # Create a dict of registers with fields and '0' in their name
86 for reg in regs:
87 if len(reg.fields) and reg.name.find('0') != -1:
88 reg_dict[reg.name] = reg
89
90 # Assign fields
91 for reg in regs:
92 if not len(reg.fields):
93 reg0 = reg_dict.get(match_number.sub('0', reg.name))
94 if reg0 != None:
95 reg.fields = reg0.fields
96 reg.varname_fields = reg0.varname_fields
97 reg.own_fields = False
98
99 return (regs, packets)
100
101
102 def write_tables(tables):
103 regs = tables[0]
104 packets = tables[1]
105
106 print '/* This file is autogenerated by sid_tables.py from sid.h. Do not edit directly. */'
107 print
108 print CopyRight.strip()
109 print '''
110 #ifndef SID_TABLES_H
111 #define SID_TABLES_H
112
113 struct si_field {
114 const char *name;
115 unsigned mask;
116 unsigned num_values;
117 const char **values;
118 };
119
120 struct si_reg {
121 const char *name;
122 unsigned offset;
123 unsigned num_fields;
124 const struct si_field *fields;
125 };
126
127 struct si_packet3 {
128 const char *name;
129 unsigned op;
130 };
131 '''
132
133 print 'static const struct si_packet3 packet3_table[] = {'
134 for pkt in packets:
135 print '\t{"%s", %s},' % (pkt[5:], pkt)
136 print '};'
137 print
138
139 for reg in regs:
140 if len(reg.fields) and reg.own_fields:
141 for field in reg.fields:
142 if len(field.values):
143 print 'static const char *%s[] = {' % (field.varname_values)
144 for value in field.values:
145 print '\t[%s] = "%s",' % (value, strip_prefix(value))
146 print '};'
147 print
148
149 print 'static const struct si_field %s[] = {' % (reg.varname_fields)
150 for field in reg.fields:
151 if len(field.values):
152 print '\t{"%s", %s(~0u), ARRAY_SIZE(%s), %s},' % (field.name,
153 field.s_name, field.varname_values, field.varname_values)
154 else:
155 print '\t{"%s", %s(~0u)},' % (field.name, field.s_name)
156 print '};'
157 print
158
159 print 'static const struct si_reg reg_table[] = {'
160 for reg in regs:
161 if len(reg.fields):
162 print '\t{"%s", %s, ARRAY_SIZE(%s), %s},' % (reg.name, reg.r_name,
163 reg.varname_fields, reg.varname_fields)
164 else:
165 print '\t{"%s", %s},' % (reg.name, reg.r_name)
166 print '};'
167 print
168 print '#endif'
169
170
171 def main():
172 tables = []
173 for arg in sys.argv[1:]:
174 tables.extend(parse(arg))
175 write_tables(tables)
176
177
178 if __name__ == '__main__':
179 main()