b9635bee78bb7e6e238c7afb88b376472f045f79
[mesa.git] / src / gallium / drivers / softpipe / sp_tex_tile_cache.c
1 /**************************************************************************
2 *
3 * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /**
29 * Texture tile caching.
30 *
31 * Author:
32 * Brian Paul
33 */
34
35 #include "util/u_inlines.h"
36 #include "util/u_memory.h"
37 #include "util/u_tile.h"
38 #include "util/u_math.h"
39 #include "sp_context.h"
40 #include "sp_texture.h"
41 #include "sp_tex_tile_cache.h"
42
43
44
45 struct softpipe_tex_tile_cache *
46 sp_create_tex_tile_cache( struct pipe_screen *screen )
47 {
48 struct softpipe_tex_tile_cache *tc;
49 uint pos;
50
51 tc = CALLOC_STRUCT( softpipe_tex_tile_cache );
52 if (tc) {
53 tc->screen = screen;
54 for (pos = 0; pos < NUM_ENTRIES; pos++) {
55 tc->entries[pos].addr.bits.invalid = 1;
56 }
57 tc->last_tile = &tc->entries[0]; /* any tile */
58 }
59 return tc;
60 }
61
62
63 void
64 sp_destroy_tex_tile_cache(struct softpipe_tex_tile_cache *tc)
65 {
66 struct pipe_screen *screen;
67 uint pos;
68
69 for (pos = 0; pos < NUM_ENTRIES; pos++) {
70 /*assert(tc->entries[pos].x < 0);*/
71 }
72 if (tc->transfer) {
73 screen = tc->transfer->texture->screen;
74 screen->tex_transfer_destroy(tc->transfer);
75 }
76 if (tc->tex_trans) {
77 screen = tc->tex_trans->texture->screen;
78 screen->tex_transfer_destroy(tc->tex_trans);
79 }
80
81 FREE( tc );
82 }
83
84
85
86
87 void
88 sp_tex_tile_cache_map_transfers(struct softpipe_tex_tile_cache *tc)
89 {
90 if (tc->tex_trans && !tc->tex_trans_map)
91 tc->tex_trans_map = tc->screen->transfer_map(tc->screen, tc->tex_trans);
92 }
93
94
95 void
96 sp_tex_tile_cache_unmap_transfers(struct softpipe_tex_tile_cache *tc)
97 {
98 if (tc->tex_trans_map) {
99 tc->screen->transfer_unmap(tc->screen, tc->tex_trans);
100 tc->tex_trans_map = NULL;
101 }
102 }
103
104 /**
105 * Invalidate all cached tiles for the cached texture.
106 * Should be called when the texture is modified.
107 */
108 void
109 sp_tex_tile_cache_validate_texture(struct softpipe_tex_tile_cache *tc)
110 {
111 unsigned i;
112
113 assert(tc);
114 assert(tc->texture);
115
116 for (i = 0; i < NUM_ENTRIES; i++) {
117 tc->entries[i].addr.bits.invalid = 1;
118 }
119 }
120
121 /**
122 * Specify the sampler view to cache.
123 */
124 void
125 sp_tex_tile_cache_set_sampler_view(struct softpipe_tex_tile_cache *tc,
126 struct pipe_sampler_view *view)
127 {
128 struct pipe_texture *texture = view ? view->texture : NULL;
129 uint i;
130
131 assert(!tc->transfer);
132
133 if (tc->texture != texture) {
134 pipe_texture_reference(&tc->texture, texture);
135
136 if (tc->tex_trans) {
137 struct pipe_screen *screen = tc->tex_trans->texture->screen;
138
139 if (tc->tex_trans_map) {
140 screen->transfer_unmap(screen, tc->tex_trans);
141 tc->tex_trans_map = NULL;
142 }
143
144 screen->tex_transfer_destroy(tc->tex_trans);
145 tc->tex_trans = NULL;
146 }
147
148 if (view) {
149 tc->swizzle_r = view->swizzle_r;
150 tc->swizzle_g = view->swizzle_g;
151 tc->swizzle_b = view->swizzle_b;
152 tc->swizzle_a = view->swizzle_a;
153 }
154
155 /* mark as entries as invalid/empty */
156 /* XXX we should try to avoid this when the teximage hasn't changed */
157 for (i = 0; i < NUM_ENTRIES; i++) {
158 tc->entries[i].addr.bits.invalid = 1;
159 }
160
161 tc->tex_face = -1; /* any invalid value here */
162 }
163 }
164
165
166
167
168 /**
169 * Flush the tile cache: write all dirty tiles back to the transfer.
170 * any tiles "flagged" as cleared will be "really" cleared.
171 */
172 void
173 sp_flush_tex_tile_cache(struct softpipe_tex_tile_cache *tc)
174 {
175 int pos;
176
177 if (tc->texture) {
178 /* caching a texture, mark all entries as empty */
179 for (pos = 0; pos < NUM_ENTRIES; pos++) {
180 tc->entries[pos].addr.bits.invalid = 1;
181 }
182 tc->tex_face = -1;
183 }
184
185 }
186
187
188 /**
189 * Given the texture face, level, zslice, x and y values, compute
190 * the cache entry position/index where we'd hope to find the
191 * cached texture tile.
192 * This is basically a direct-map cache.
193 * XXX There's probably lots of ways in which we can improve this.
194 */
195 static INLINE uint
196 tex_cache_pos( union tex_tile_address addr )
197 {
198 uint entry = (addr.bits.x +
199 addr.bits.y * 9 +
200 addr.bits.z * 3 +
201 addr.bits.face +
202 addr.bits.level * 7);
203
204 return entry % NUM_ENTRIES;
205 }
206
207 /**
208 * Similar to sp_get_cached_tile() but for textures.
209 * Tiles are read-only and indexed with more params.
210 */
211 const struct softpipe_tex_cached_tile *
212 sp_find_cached_tile_tex(struct softpipe_tex_tile_cache *tc,
213 union tex_tile_address addr )
214 {
215 struct pipe_screen *screen = tc->screen;
216 struct softpipe_tex_cached_tile *tile;
217
218 tile = tc->entries + tex_cache_pos( addr );
219
220 if (addr.value != tile->addr.value) {
221
222 /* cache miss. Most misses are because we've invaldiated the
223 * texture cache previously -- most commonly on binding a new
224 * texture. Currently we effectively flush the cache on texture
225 * bind.
226 */
227 #if 0
228 _debug_printf("miss at %u: x=%d y=%d z=%d face=%d level=%d\n"
229 " tile %u: x=%d y=%d z=%d face=%d level=%d\n",
230 pos, x/TILE_SIZE, y/TILE_SIZE, z, face, level,
231 pos, tile->addr.bits.x, tile->addr.bits.y, tile->z, tile->face, tile->level);
232 #endif
233
234 /* check if we need to get a new transfer */
235 if (!tc->tex_trans ||
236 tc->tex_face != addr.bits.face ||
237 tc->tex_level != addr.bits.level ||
238 tc->tex_z != addr.bits.z) {
239 /* get new transfer (view into texture) */
240
241 if (tc->tex_trans) {
242 if (tc->tex_trans_map) {
243 tc->screen->transfer_unmap(tc->screen, tc->tex_trans);
244 tc->tex_trans_map = NULL;
245 }
246
247 screen->tex_transfer_destroy(tc->tex_trans);
248 tc->tex_trans = NULL;
249 }
250
251 tc->tex_trans =
252 screen->get_tex_transfer(screen, tc->texture,
253 addr.bits.face,
254 addr.bits.level,
255 addr.bits.z,
256 PIPE_TRANSFER_READ, 0, 0,
257 u_minify(tc->texture->width0, addr.bits.level),
258 u_minify(tc->texture->height0, addr.bits.level));
259
260 tc->tex_trans_map = screen->transfer_map(screen, tc->tex_trans);
261
262 tc->tex_face = addr.bits.face;
263 tc->tex_level = addr.bits.level;
264 tc->tex_z = addr.bits.z;
265 }
266
267 /* get tile from the transfer (view into texture) */
268 pipe_get_tile_swizzle(tc->tex_trans,
269 addr.bits.x * TILE_SIZE,
270 addr.bits.y * TILE_SIZE,
271 TILE_SIZE,
272 TILE_SIZE,
273 tc->swizzle_r,
274 tc->swizzle_g,
275 tc->swizzle_b,
276 tc->swizzle_a,
277 (float *) tile->data.color);
278 tile->addr = addr;
279 }
280
281 tc->last_tile = tile;
282 return tile;
283 }
284
285
286