src/gallium/drivers/softpipe/sp_tile_cache.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /**
  29  * Render target tile caching.
  30  *
  31  * Author:
  32  *    Brian Paul
  33  */
  34
  35 #include "pipe/p_inlines.h"
  36 #include "util/u_memory.h"
  37 #include "util/u_tile.h"
  38 #include "sp_context.h"
  39 #include "sp_surface.h"
  40 #include "sp_tile_cache.h"
  41
  42
  43
  44 /**
  45  * Return the position in the cache for the tile that contains win pos (x,y).
  46  * We currently use a direct mapped cache so this is like a hack key.
  47  * At some point we should investige something more sophisticated, like
  48  * a LRU replacement policy.
  49  */
  50 #define CACHE_POS(x, y) \
  51    (((x) + (y) * 5) % NUM_ENTRIES)
  52
  53
  54
  55 /**
  56  * Is the tile at (x,y) in cleared state?
  57  */
  58 static INLINE uint
  59 is_clear_flag_set(const uint *bitvec, union tile_address addr)
  60 {
  61    int pos, bit;
  62    pos = addr.bits.y * (MAX_WIDTH / TILE_SIZE) + addr.bits.x;
  63    assert(pos / 32 < (MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32);
  64    bit = bitvec[pos / 32] & (1 << (pos & 31));
  65    return bit;
  66 }
  67
  68
  69 /**
  70  * Mark the tile at (x,y) as not cleared.
  71  */
  72 static INLINE void
  73 clear_clear_flag(uint *bitvec, union tile_address addr)
  74 {
  75    int pos;
  76    pos = addr.bits.y * (MAX_WIDTH / TILE_SIZE) + addr.bits.x;
  77    assert(pos / 32 < (MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32);
  78    bitvec[pos / 32] &= ~(1 << (pos & 31));
  79 }
  80
  81
  82 struct softpipe_tile_cache *
  83 sp_create_tile_cache( struct pipe_screen *screen )
  84 {
  85    struct softpipe_tile_cache *tc;
  86    uint pos;
  87
  88    tc = CALLOC_STRUCT( softpipe_tile_cache );
  89    if (tc) {
  90       tc->screen = screen;
  91       for (pos = 0; pos < NUM_ENTRIES; pos++) {
  92          tc->entries[pos].addr.bits.invalid = 1;
  93       }
  94       tc->last_tile = &tc->entries[0]; /* any tile */
  95    }
  96    return tc;
  97 }
  98
  99
 100 void
 101 sp_destroy_tile_cache(struct softpipe_tile_cache *tc)
 102 {
 103    struct pipe_screen *screen;
 104    uint pos;
 105
 106    for (pos = 0; pos < NUM_ENTRIES; pos++) {
 107       /*assert(tc->entries[pos].x < 0);*/
 108    }
 109    if (tc->transfer) {
 110       screen = tc->transfer->texture->screen;
 111       screen->tex_transfer_destroy(tc->transfer);
 112    }
 113
 114    FREE( tc );
 115 }
 116
 117
 118 /**
 119  * Specify the surface to cache.
 120  */
 121 void
 122 sp_tile_cache_set_surface(struct softpipe_tile_cache *tc,
 123                           struct pipe_surface *ps)
 124 {
 125    if (tc->transfer) {
 126       struct pipe_screen *screen = tc->transfer->texture->screen;
 127
 128       if (ps == tc->surface)
 129          return;
 130
 131       if (tc->transfer_map) {
 132          screen->transfer_unmap(screen, tc->transfer);
 133          tc->transfer_map = NULL;
 134       }
 135
 136       screen->tex_transfer_destroy(tc->transfer);
 137       tc->transfer = NULL;
 138    }
 139
 140    tc->surface = ps;
 141
 142    if (ps) {
 143       struct pipe_screen *screen = ps->texture->screen;
 144
 145       tc->transfer = screen->get_tex_transfer(screen, ps->texture, ps->face,
 146                                               ps->level, ps->zslice,
 147                                               PIPE_TRANSFER_READ_WRITE,
 148                                               0, 0, ps->width, ps->height);
 149
 150       tc->depth_stencil = (ps->format == PIPE_FORMAT_S8Z24_UNORM ||
 151                            ps->format == PIPE_FORMAT_X8Z24_UNORM ||
 152                            ps->format == PIPE_FORMAT_Z24S8_UNORM ||
 153                            ps->format == PIPE_FORMAT_Z24X8_UNORM ||
 154                            ps->format == PIPE_FORMAT_Z16_UNORM ||
 155                            ps->format == PIPE_FORMAT_Z32_UNORM ||
 156                            ps->format == PIPE_FORMAT_S8_UNORM);
 157    }
 158 }
 159
 160
 161 /**
 162  * Return the transfer being cached.
 163  */
 164 struct pipe_surface *
 165 sp_tile_cache_get_surface(struct softpipe_tile_cache *tc)
 166 {
 167    return tc->surface;
 168 }
 169
 170
 171 void
 172 sp_tile_cache_map_transfers(struct softpipe_tile_cache *tc)
 173 {
 174    if (tc->transfer && !tc->transfer_map)
 175       tc->transfer_map = tc->screen->transfer_map(tc->screen, tc->transfer);
 176 }
 177
 178
 179 void
 180 sp_tile_cache_unmap_transfers(struct softpipe_tile_cache *tc)
 181 {
 182    if (tc->transfer_map) {
 183       tc->screen->transfer_unmap(tc->screen, tc->transfer);
 184       tc->transfer_map = NULL;
 185    }
 186 }
 187
 188 /**
 189  * Set pixels in a tile to the given clear color/value, float.
 190  */
 191 static void
 192 clear_tile_rgba(struct softpipe_cached_tile *tile,
 193                 enum pipe_format format,
 194                 const float clear_value[4])
 195 {
 196    if (clear_value[0] == 0.0 &&
 197        clear_value[1] == 0.0 &&
 198        clear_value[2] == 0.0 &&
 199        clear_value[3] == 0.0) {
 200       memset(tile->data.color, 0, sizeof(tile->data.color));
 201    }
 202    else {
 203       uint i, j;
 204       for (i = 0; i < TILE_SIZE; i++) {
 205          for (j = 0; j < TILE_SIZE; j++) {
 206             tile->data.color[i][j][0] = clear_value[0];
 207             tile->data.color[i][j][1] = clear_value[1];
 208             tile->data.color[i][j][2] = clear_value[2];
 209             tile->data.color[i][j][3] = clear_value[3];
 210          }
 211       }
 212    }
 213 }
 214
 215
 216 /**
 217  * Set a tile to a solid value/color.
 218  */
 219 static void
 220 clear_tile(struct softpipe_cached_tile *tile,
 221            enum pipe_format format,
 222            uint clear_value)
 223 {
 224    uint i, j;
 225
 226    switch (pf_get_size(format)) {
 227    case 1:
 228       memset(tile->data.any, 0, TILE_SIZE * TILE_SIZE);
 229       break;
 230    case 2:
 231       if (clear_value == 0) {
 232          memset(tile->data.any, 0, 2 * TILE_SIZE * TILE_SIZE);
 233       }
 234       else {
 235          for (i = 0; i < TILE_SIZE; i++) {
 236             for (j = 0; j < TILE_SIZE; j++) {
 237                tile->data.depth16[i][j] = (ushort) clear_value;
 238             }
 239          }
 240       }
 241       break;
 242    case 4:
 243       if (clear_value == 0) {
 244          memset(tile->data.any, 0, 4 * TILE_SIZE * TILE_SIZE);
 245       }
 246       else {
 247          for (i = 0; i < TILE_SIZE; i++) {
 248             for (j = 0; j < TILE_SIZE; j++) {
 249                tile->data.color32[i][j] = clear_value;
 250             }
 251          }
 252       }
 253       break;
 254    default:
 255       assert(0);
 256    }
 257 }
 258
 259
 260 /**
 261  * Actually clear the tiles which were flagged as being in a clear state.
 262  */
 263 static void
 264 sp_tile_cache_flush_clear(struct softpipe_tile_cache *tc)
 265 {
 266    struct pipe_transfer *pt = tc->transfer;
 267    const uint w = tc->transfer->width;
 268    const uint h = tc->transfer->height;
 269    uint x, y;
 270    uint numCleared = 0;
 271
 272    /* clear the scratch tile to the clear value */
 273    clear_tile(&tc->tile, pt->format, tc->clear_val);
 274
 275    /* push the tile to all positions marked as clear */
 276    for (y = 0; y < h; y += TILE_SIZE) {
 277       for (x = 0; x < w; x += TILE_SIZE) {
 278          union tile_address addr = tile_address(x, y);
 279
 280          if (is_clear_flag_set(tc->clear_flags, addr)) {
 281             pipe_put_tile_raw(pt,
 282                               x, y, TILE_SIZE, TILE_SIZE,
 283                               tc->tile.data.color32, 0/*STRIDE*/);
 284
 285             /* do this? */
 286             clear_clear_flag(tc->clear_flags, addr);
 287
 288             numCleared++;
 289          }
 290       }
 291    }
 292 #if 0
 293    debug_printf("num cleared: %u\n", numCleared);
 294 #endif
 295 }
 296
 297
 298 /**
 299  * Flush the tile cache: write all dirty tiles back to the transfer.
 300  * any tiles "flagged" as cleared will be "really" cleared.
 301  */
 302 void
 303 sp_flush_tile_cache(struct softpipe_tile_cache *tc)
 304 {
 305    struct pipe_transfer *pt = tc->transfer;
 306    int inuse = 0, pos;
 307
 308    if (pt) {
 309       /* caching a drawing transfer */
 310       for (pos = 0; pos < NUM_ENTRIES; pos++) {
 311          struct softpipe_cached_tile *tile = tc->entries + pos;
 312          if (!tile->addr.bits.invalid) {
 313             if (tc->depth_stencil) {
 314                pipe_put_tile_raw(pt,
 315                                  tile->addr.bits.x * TILE_SIZE,
 316                                  tile->addr.bits.y * TILE_SIZE,
 317                                  TILE_SIZE, TILE_SIZE,
 318                                  tile->data.depth32, 0/*STRIDE*/);
 319             }
 320             else {
 321                pipe_put_tile_rgba(pt,
 322                                   tile->addr.bits.x * TILE_SIZE,
 323                                   tile->addr.bits.y * TILE_SIZE,
 324                                   TILE_SIZE, TILE_SIZE,
 325                                   (float *) tile->data.color);
 326             }
 327             tile->addr.bits.invalid = 1;  /* mark as empty */
 328             inuse++;
 329          }
 330       }
 331
 332 #if TILE_CLEAR_OPTIMIZATION
 333       sp_tile_cache_flush_clear(tc);
 334 #endif
 335    }
 336
 337 #if 0
 338    debug_printf("flushed tiles in use: %d\n", inuse);
 339 #endif
 340 }
 341
 342
 343 /**
 344  * Get a tile from the cache.
 345  * \param x, y  position of tile, in pixels
 346  */
 347 struct softpipe_cached_tile *
 348 sp_find_cached_tile(struct softpipe_tile_cache *tc,
 349                     union tile_address addr )
 350 {
 351    struct pipe_transfer *pt = tc->transfer;
 352
 353    /* cache pos/entry: */
 354    const int pos = CACHE_POS(addr.bits.x,
 355                              addr.bits.y);
 356    struct softpipe_cached_tile *tile = tc->entries + pos;
 357
 358    if (addr.value != tile->addr.value) {
 359
 360       if (tile->addr.bits.invalid == 0) {
 361          /* put dirty tile back in framebuffer */
 362          if (tc->depth_stencil) {
 363             pipe_put_tile_raw(pt,
 364                               tile->addr.bits.x * TILE_SIZE,
 365                               tile->addr.bits.y * TILE_SIZE,
 366                               TILE_SIZE, TILE_SIZE,
 367                               tile->data.depth32, 0/*STRIDE*/);
 368          }
 369          else {
 370             pipe_put_tile_rgba(pt,
 371                                tile->addr.bits.x * TILE_SIZE,
 372                                tile->addr.bits.y * TILE_SIZE,
 373                                TILE_SIZE, TILE_SIZE,
 374                                (float *) tile->data.color);
 375          }
 376       }
 377
 378       tile->addr = addr;
 379
 380       if (is_clear_flag_set(tc->clear_flags, addr)) {
 381          /* don't get tile from framebuffer, just clear it */
 382          if (tc->depth_stencil) {
 383             clear_tile(tile, pt->format, tc->clear_val);
 384          }
 385          else {
 386             clear_tile_rgba(tile, pt->format, tc->clear_color);
 387          }
 388          clear_clear_flag(tc->clear_flags, addr);
 389       }
 390       else {
 391          /* get new tile data from transfer */
 392          if (tc->depth_stencil) {
 393             pipe_get_tile_raw(pt,
 394                               tile->addr.bits.x * TILE_SIZE,
 395                               tile->addr.bits.y * TILE_SIZE,
 396                               TILE_SIZE, TILE_SIZE,
 397                               tile->data.depth32, 0/*STRIDE*/);
 398          }
 399          else {
 400             pipe_get_tile_rgba(pt,
 401                                tile->addr.bits.x * TILE_SIZE,
 402                                tile->addr.bits.y * TILE_SIZE,
 403                                TILE_SIZE, TILE_SIZE,
 404                                (float *) tile->data.color);
 405          }
 406       }
 407    }
 408
 409    tc->last_tile = tile;
 410    return tile;
 411 }
 412
 413
 414
 415
 416
 417 /**
 418  * When a whole surface is being cleared to a value we can avoid
 419  * fetching tiles above.
 420  * Save the color and set a 'clearflag' for each tile of the screen.
 421  */
 422 void
 423 sp_tile_cache_clear(struct softpipe_tile_cache *tc, const float *rgba,
 424                     uint clearValue)
 425 {
 426    uint pos;
 427
 428    tc->clear_color[0] = rgba[0];
 429    tc->clear_color[1] = rgba[1];
 430    tc->clear_color[2] = rgba[2];
 431    tc->clear_color[3] = rgba[3];
 432
 433    tc->clear_val = clearValue;
 434
 435 #if TILE_CLEAR_OPTIMIZATION
 436    /* set flags to indicate all the tiles are cleared */
 437    memset(tc->clear_flags, 255, sizeof(tc->clear_flags));
 438 #else
 439    /* disable the optimization */
 440    memset(tc->clear_flags, 0, sizeof(tc->clear_flags));
 441 #endif
 442
 443    for (pos = 0; pos < NUM_ENTRIES; pos++) {
 444       struct softpipe_cached_tile *tile = tc->entries + pos;
 445       tile->addr.bits.invalid = 1;
 446    }
 447 }