src/gallium/drivers/softpipe/sp_tile_cache.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
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  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /**
  29  * Render target tile caching.
  30  *
  31  * Author:
  32  *    Brian Paul
  33  */
  34
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_memory.h"
  38 #include "util/u_tile.h"
  39 #include "sp_tile_cache.h"
  40
  41 static struct softpipe_cached_tile *
  42 sp_alloc_tile(struct softpipe_tile_cache *tc);
  43
  44
  45 /**
  46  * Return the position in the cache for the tile that contains win pos (x,y).
  47  * We currently use a direct mapped cache so this is like a hack key.
  48  * At some point we should investige something more sophisticated, like
  49  * a LRU replacement policy.
  50  */
  51 #define CACHE_POS(x, y) \
  52    (((x) + (y) * 5) % NUM_ENTRIES)
  53
  54
  55
  56 /**
  57  * Is the tile at (x,y) in cleared state?
  58  */
  59 static INLINE uint
  60 is_clear_flag_set(const uint *bitvec, union tile_address addr)
  61 {
  62    int pos, bit;
  63    pos = addr.bits.y * (MAX_WIDTH / TILE_SIZE) + addr.bits.x;
  64    assert(pos / 32 < (MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32);
  65    bit = bitvec[pos / 32] & (1 << (pos & 31));
  66    return bit;
  67 }
  68
  69
  70 /**
  71  * Mark the tile at (x,y) as not cleared.
  72  */
  73 static INLINE void
  74 clear_clear_flag(uint *bitvec, union tile_address addr)
  75 {
  76    int pos;
  77    pos = addr.bits.y * (MAX_WIDTH / TILE_SIZE) + addr.bits.x;
  78    assert(pos / 32 < (MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32);
  79    bitvec[pos / 32] &= ~(1 << (pos & 31));
  80 }
  81
  82
  83 struct softpipe_tile_cache *
  84 sp_create_tile_cache( struct pipe_context *pipe )
  85 {
  86    struct softpipe_tile_cache *tc;
  87    uint pos;
  88    int maxLevels, maxTexSize;
  89
  90    /* sanity checking: max sure MAX_WIDTH/HEIGHT >= largest texture image */
  91    maxLevels = pipe->screen->get_param(pipe->screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS);
  92    maxTexSize = 1 << (maxLevels - 1);
  93    assert(MAX_WIDTH >= maxTexSize);
  94
  95    assert(sizeof(union tile_address) == 4);
  96
  97    assert((TILE_SIZE << TILE_ADDR_BITS) >= MAX_WIDTH);
  98
  99    tc = CALLOC_STRUCT( softpipe_tile_cache );
 100    if (tc) {
 101       tc->pipe = pipe;
 102       for (pos = 0; pos < NUM_ENTRIES; pos++) {
 103          tc->tile_addrs[pos].bits.invalid = 1;
 104       }
 105       tc->last_tile_addr.bits.invalid = 1;
 106
 107       /* this allocation allows us to guarantee that allocation
 108        * failures are never fatal later
 109        */
 110       tc->tile = MALLOC_STRUCT( softpipe_cached_tile );
 111       if (!tc->tile)
 112       {
 113          FREE(tc);
 114          return NULL;
 115       }
 116
 117       /* XXX this code prevents valgrind warnings about use of uninitialized
 118        * memory in programs that don't clear the surface before rendering.
 119        * However, it breaks clearing in other situations (such as in
 120        * progs/tests/drawbuffers, see bug 24402).
 121        */
 122 #if 0
 123       /* set flags to indicate all the tiles are cleared */
 124       memset(tc->clear_flags, 255, sizeof(tc->clear_flags));
 125 #endif
 126    }
 127    return tc;
 128 }
 129
 130
 131 void
 132 sp_destroy_tile_cache(struct softpipe_tile_cache *tc)
 133 {
 134    if (tc) {
 135       uint pos;
 136
 137       for (pos = 0; pos < NUM_ENTRIES; pos++) {
 138          /*assert(tc->entries[pos].x < 0);*/
 139          FREE( tc->entries[pos] );
 140       }
 141       FREE( tc->tile );
 142
 143       if (tc->transfer) {
 144          tc->pipe->transfer_destroy(tc->pipe, tc->transfer);
 145       }
 146
 147       FREE( tc );
 148    }
 149 }
 150
 151
 152 /**
 153  * Specify the surface to cache.
 154  */
 155 void
 156 sp_tile_cache_set_surface(struct softpipe_tile_cache *tc,
 157                           struct pipe_surface *ps)
 158 {
 159    struct pipe_context *pipe = tc->pipe;
 160
 161    if (tc->transfer) {
 162       if (ps == tc->surface)
 163          return;
 164
 165       if (tc->transfer_map) {
 166          pipe->transfer_unmap(pipe, tc->transfer);
 167          tc->transfer_map = NULL;
 168       }
 169
 170       pipe->transfer_destroy(pipe, tc->transfer);
 171       tc->transfer = NULL;
 172    }
 173
 174    tc->surface = ps;
 175
 176    if (ps) {
 177       tc->transfer = pipe_get_transfer(pipe, ps->texture,
 178                                        ps->u.tex.level, ps->u.tex.first_layer,
 179                                        PIPE_TRANSFER_READ_WRITE |
 180                                        PIPE_TRANSFER_UNSYNCHRONIZED,
 181                                        0, 0, ps->width, ps->height);
 182
 183       tc->depth_stencil = (ps->format == PIPE_FORMAT_Z24_UNORM_S8_USCALED ||
 184                            ps->format == PIPE_FORMAT_Z24X8_UNORM ||
 185                            ps->format == PIPE_FORMAT_S8_USCALED_Z24_UNORM ||
 186                            ps->format == PIPE_FORMAT_X8Z24_UNORM ||
 187                            ps->format == PIPE_FORMAT_Z16_UNORM ||
 188                            ps->format == PIPE_FORMAT_Z32_UNORM ||
 189                            ps->format == PIPE_FORMAT_S8_USCALED);
 190    }
 191 }
 192
 193
 194 /**
 195  * Return the transfer being cached.
 196  */
 197 struct pipe_surface *
 198 sp_tile_cache_get_surface(struct softpipe_tile_cache *tc)
 199 {
 200    return tc->surface;
 201 }
 202
 203
 204 void
 205 sp_tile_cache_map_transfers(struct softpipe_tile_cache *tc)
 206 {
 207    if (tc->transfer && !tc->transfer_map)
 208       tc->transfer_map = tc->pipe->transfer_map(tc->pipe, tc->transfer);
 209 }
 210
 211
 212 void
 213 sp_tile_cache_unmap_transfers(struct softpipe_tile_cache *tc)
 214 {
 215    if (tc->transfer_map) {
 216       tc->pipe->transfer_unmap(tc->pipe, tc->transfer);
 217       tc->transfer_map = NULL;
 218    }
 219 }
 220
 221
 222 /**
 223  * Set pixels in a tile to the given clear color/value, float.
 224  */
 225 static void
 226 clear_tile_rgba(struct softpipe_cached_tile *tile,
 227                 enum pipe_format format,
 228                 const float clear_value[4])
 229 {
 230    if (clear_value[0] == 0.0 &&
 231        clear_value[1] == 0.0 &&
 232        clear_value[2] == 0.0 &&
 233        clear_value[3] == 0.0) {
 234       memset(tile->data.color, 0, sizeof(tile->data.color));
 235    }
 236    else {
 237       uint i, j;
 238       for (i = 0; i < TILE_SIZE; i++) {
 239          for (j = 0; j < TILE_SIZE; j++) {
 240             tile->data.color[i][j][0] = clear_value[0];
 241             tile->data.color[i][j][1] = clear_value[1];
 242             tile->data.color[i][j][2] = clear_value[2];
 243             tile->data.color[i][j][3] = clear_value[3];
 244          }
 245       }
 246    }
 247 }
 248
 249
 250 /**
 251  * Set a tile to a solid value/color.
 252  */
 253 static void
 254 clear_tile(struct softpipe_cached_tile *tile,
 255            enum pipe_format format,
 256            uint clear_value)
 257 {
 258    uint i, j;
 259
 260    switch (util_format_get_blocksize(format)) {
 261    case 1:
 262       memset(tile->data.any, clear_value, TILE_SIZE * TILE_SIZE);
 263       break;
 264    case 2:
 265       if (clear_value == 0) {
 266          memset(tile->data.any, 0, 2 * TILE_SIZE * TILE_SIZE);
 267       }
 268       else {
 269          for (i = 0; i < TILE_SIZE; i++) {
 270             for (j = 0; j < TILE_SIZE; j++) {
 271                tile->data.depth16[i][j] = (ushort) clear_value;
 272             }
 273          }
 274       }
 275       break;
 276    case 4:
 277       if (clear_value == 0) {
 278          memset(tile->data.any, 0, 4 * TILE_SIZE * TILE_SIZE);
 279       }
 280       else {
 281          for (i = 0; i < TILE_SIZE; i++) {
 282             for (j = 0; j < TILE_SIZE; j++) {
 283                tile->data.color32[i][j] = clear_value;
 284             }
 285          }
 286       }
 287       break;
 288    default:
 289       assert(0);
 290    }
 291 }
 292
 293
 294 /**
 295  * Actually clear the tiles which were flagged as being in a clear state.
 296  */
 297 static void
 298 sp_tile_cache_flush_clear(struct softpipe_tile_cache *tc)
 299 {
 300    struct pipe_transfer *pt = tc->transfer;
 301    const uint w = tc->transfer->box.width;
 302    const uint h = tc->transfer->box.height;
 303    uint x, y;
 304    uint numCleared = 0;
 305
 306    assert(pt->resource);
 307    if (!tc->tile)
 308       tc->tile = sp_alloc_tile(tc);
 309
 310    /* clear the scratch tile to the clear value */
 311    if (tc->depth_stencil) {
 312       clear_tile(tc->tile, pt->resource->format, tc->clear_val);
 313    } else {
 314       clear_tile_rgba(tc->tile, pt->resource->format, tc->clear_color);
 315    }
 316
 317    /* push the tile to all positions marked as clear */
 318    for (y = 0; y < h; y += TILE_SIZE) {
 319       for (x = 0; x < w; x += TILE_SIZE) {
 320          union tile_address addr = tile_address(x, y);
 321
 322          if (is_clear_flag_set(tc->clear_flags, addr)) {
 323             /* write the scratch tile to the surface */
 324             if (tc->depth_stencil) {
 325                pipe_put_tile_raw(tc->pipe,
 326                                  pt,
 327                                  x, y, TILE_SIZE, TILE_SIZE,
 328                                  tc->tile->data.any, 0/*STRIDE*/);
 329             }
 330             else {
 331                pipe_put_tile_rgba(tc->pipe, pt,
 332                                   x, y, TILE_SIZE, TILE_SIZE,
 333                                   (float *) tc->tile->data.color);
 334             }
 335             numCleared++;
 336          }
 337       }
 338    }
 339
 340    /* reset all clear flags to zero */
 341    memset(tc->clear_flags, 0, sizeof(tc->clear_flags));
 342
 343 #if 0
 344    debug_printf("num cleared: %u\n", numCleared);
 345 #endif
 346 }
 347
 348 static void
 349 sp_flush_tile(struct softpipe_tile_cache* tc, unsigned pos)
 350 {
 351    if (!tc->tile_addrs[pos].bits.invalid) {
 352       if (tc->depth_stencil) {
 353          pipe_put_tile_raw(tc->pipe, tc->transfer,
 354                            tc->tile_addrs[pos].bits.x * TILE_SIZE,
 355                            tc->tile_addrs[pos].bits.y * TILE_SIZE,
 356                            TILE_SIZE, TILE_SIZE,
 357                            tc->entries[pos]->data.depth32, 0/*STRIDE*/);
 358       }
 359       else {
 360          pipe_put_tile_rgba_format(tc->pipe, tc->transfer,
 361                                    tc->tile_addrs[pos].bits.x * TILE_SIZE,
 362                                    tc->tile_addrs[pos].bits.y * TILE_SIZE,
 363                                    TILE_SIZE, TILE_SIZE,
 364                                    tc->surface->format,
 365                                    (float *) tc->entries[pos]->data.color);
 366       }
 367       tc->tile_addrs[pos].bits.invalid = 1;  /* mark as empty */
 368    }
 369 }
 370
 371 /**
 372  * Flush the tile cache: write all dirty tiles back to the transfer.
 373  * any tiles "flagged" as cleared will be "really" cleared.
 374  */
 375 void
 376 sp_flush_tile_cache(struct softpipe_tile_cache *tc)
 377 {
 378    struct pipe_transfer *pt = tc->transfer;
 379    int inuse = 0, pos;
 380
 381    if (pt) {
 382       /* caching a drawing transfer */
 383       for (pos = 0; pos < NUM_ENTRIES; pos++) {
 384          struct softpipe_cached_tile *tile = tc->entries[pos];
 385          if (!tile)
 386          {
 387             assert(tc->tile_addrs[pos].bits.invalid);
 388             continue;
 389          }
 390
 391          sp_flush_tile(tc, pos);
 392          ++inuse;
 393       }
 394
 395       sp_tile_cache_flush_clear(tc);
 396
 397
 398       tc->last_tile_addr.bits.invalid = 1;
 399    }
 400
 401 #if 0
 402    debug_printf("flushed tiles in use: %d\n", inuse);
 403 #endif
 404 }
 405
 406 static struct softpipe_cached_tile *
 407 sp_alloc_tile(struct softpipe_tile_cache *tc)
 408 {
 409    struct softpipe_cached_tile * tile = MALLOC_STRUCT(softpipe_cached_tile);
 410    if (!tile)
 411    {
 412       /* in this case, steal an existing tile */
 413       if (!tc->tile)
 414       {
 415          unsigned pos;
 416          for (pos = 0; pos < NUM_ENTRIES; ++pos) {
 417             if (!tc->entries[pos])
 418                continue;
 419
 420             sp_flush_tile(tc, pos);
 421             tc->tile = tc->entries[pos];
 422             tc->entries[pos] = NULL;
 423             break;
 424          }
 425
 426          /* this should never happen */
 427          if (!tc->tile)
 428             abort();
 429       }
 430
 431       tile = tc->tile;
 432       tc->tile = NULL;
 433
 434       tc->last_tile_addr.bits.invalid = 1;
 435    }
 436    return tile;
 437 }
 438
 439 /**
 440  * Get a tile from the cache.
 441  * \param x, y  position of tile, in pixels
 442  */
 443 struct softpipe_cached_tile *
 444 sp_find_cached_tile(struct softpipe_tile_cache *tc,
 445                     union tile_address addr )
 446 {
 447    struct pipe_transfer *pt = tc->transfer;
 448
 449    /* cache pos/entry: */
 450    const int pos = CACHE_POS(addr.bits.x,
 451                              addr.bits.y);
 452    struct softpipe_cached_tile *tile = tc->entries[pos];
 453
 454    if (!tile) {
 455       tile = sp_alloc_tile(tc);
 456       tc->entries[pos] = tile;
 457    }
 458
 459    if (addr.value != tc->tile_addrs[pos].value) {
 460
 461       assert(pt->resource);
 462       if (tc->tile_addrs[pos].bits.invalid == 0) {
 463          /* put dirty tile back in framebuffer */
 464          if (tc->depth_stencil) {
 465             pipe_put_tile_raw(tc->pipe, pt,
 466                               tc->tile_addrs[pos].bits.x * TILE_SIZE,
 467                               tc->tile_addrs[pos].bits.y * TILE_SIZE,
 468                               TILE_SIZE, TILE_SIZE,
 469                               tile->data.depth32, 0/*STRIDE*/);
 470          }
 471          else {
 472             pipe_put_tile_rgba_format(tc->pipe, pt,
 473                                       tc->tile_addrs[pos].bits.x * TILE_SIZE,
 474                                       tc->tile_addrs[pos].bits.y * TILE_SIZE,
 475                                       TILE_SIZE, TILE_SIZE,
 476                                       tc->surface->format,
 477                                       (float *) tile->data.color);
 478          }
 479       }
 480
 481       tc->tile_addrs[pos] = addr;
 482
 483       if (is_clear_flag_set(tc->clear_flags, addr)) {
 484          /* don't get tile from framebuffer, just clear it */
 485          if (tc->depth_stencil) {
 486             clear_tile(tile, pt->resource->format, tc->clear_val);
 487          }
 488          else {
 489             clear_tile_rgba(tile, pt->resource->format, tc->clear_color);
 490          }
 491          clear_clear_flag(tc->clear_flags, addr);
 492       }
 493       else {
 494          /* get new tile data from transfer */
 495          if (tc->depth_stencil) {
 496             pipe_get_tile_raw(tc->pipe, pt,
 497                               tc->tile_addrs[pos].bits.x * TILE_SIZE,
 498                               tc->tile_addrs[pos].bits.y * TILE_SIZE,
 499                               TILE_SIZE, TILE_SIZE,
 500                               tile->data.depth32, 0/*STRIDE*/);
 501          }
 502          else {
 503             pipe_get_tile_rgba(tc->pipe, pt,
 504                                tc->tile_addrs[pos].bits.x * TILE_SIZE,
 505                                tc->tile_addrs[pos].bits.y * TILE_SIZE,
 506                                TILE_SIZE, TILE_SIZE,
 507                                (float *) tile->data.color);
 508          }
 509       }
 510    }
 511
 512    tc->last_tile = tile;
 513    tc->last_tile_addr = addr;
 514    return tile;
 515 }
 516
 517
 518
 519
 520
 521 /**
 522  * When a whole surface is being cleared to a value we can avoid
 523  * fetching tiles above.
 524  * Save the color and set a 'clearflag' for each tile of the screen.
 525  */
 526 void
 527 sp_tile_cache_clear(struct softpipe_tile_cache *tc, const float *rgba,
 528                     uint clearValue)
 529 {
 530    uint pos;
 531
 532    tc->clear_color[0] = rgba[0];
 533    tc->clear_color[1] = rgba[1];
 534    tc->clear_color[2] = rgba[2];
 535    tc->clear_color[3] = rgba[3];
 536
 537    tc->clear_val = clearValue;
 538
 539    /* set flags to indicate all the tiles are cleared */
 540    memset(tc->clear_flags, 255, sizeof(tc->clear_flags));
 541
 542    for (pos = 0; pos < NUM_ENTRIES; pos++) {
 543       tc->tile_addrs[pos].bits.invalid = 1;
 544    }
 545    tc->last_tile_addr.bits.invalid = 1;
 546 }