src/gallium/drivers/softpipe/sp_tile_cache.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
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  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /**
  29  * Render target tile caching.
  30  *
  31  * Author:
  32  *    Brian Paul
  33  */
  34
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_memory.h"
  38 #include "util/u_tile.h"
  39 #include "sp_tile_cache.h"
  40
  41 static struct softpipe_cached_tile *
  42 sp_alloc_tile(struct softpipe_tile_cache *tc);
  43
  44
  45 /**
  46  * Return the position in the cache for the tile that contains win pos (x,y).
  47  * We currently use a direct mapped cache so this is like a hack key.
  48  * At some point we should investige something more sophisticated, like
  49  * a LRU replacement policy.
  50  */
  51 #define CACHE_POS(x, y) \
  52    (((x) + (y) * 5) % NUM_ENTRIES)
  53
  54
  55
  56 /**
  57  * Is the tile at (x,y) in cleared state?
  58  */
  59 static INLINE uint
  60 is_clear_flag_set(const uint *bitvec, union tile_address addr)
  61 {
  62    int pos, bit;
  63    pos = addr.bits.y * (MAX_WIDTH / TILE_SIZE) + addr.bits.x;
  64    assert(pos / 32 < (MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32);
  65    bit = bitvec[pos / 32] & (1 << (pos & 31));
  66    return bit;
  67 }
  68
  69
  70 /**
  71  * Mark the tile at (x,y) as not cleared.
  72  */
  73 static INLINE void
  74 clear_clear_flag(uint *bitvec, union tile_address addr)
  75 {
  76    int pos;
  77    pos = addr.bits.y * (MAX_WIDTH / TILE_SIZE) + addr.bits.x;
  78    assert(pos / 32 < (MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32);
  79    bitvec[pos / 32] &= ~(1 << (pos & 31));
  80 }
  81
  82
  83 struct softpipe_tile_cache *
  84 sp_create_tile_cache( struct pipe_context *pipe )
  85 {
  86    struct softpipe_tile_cache *tc;
  87    uint pos;
  88    int maxLevels, maxTexSize;
  89
  90    /* sanity checking: max sure MAX_WIDTH/HEIGHT >= largest texture image */
  91    maxLevels = pipe->screen->get_param(pipe->screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS);
  92    maxTexSize = 1 << (maxLevels - 1);
  93    assert(MAX_WIDTH >= maxTexSize);
  94
  95    tc = CALLOC_STRUCT( softpipe_tile_cache );
  96    if (tc) {
  97       tc->pipe = pipe;
  98       for (pos = 0; pos < NUM_ENTRIES; pos++) {
  99          tc->tile_addrs[pos].bits.invalid = 1;
 100       }
 101       tc->last_tile_addr.bits.invalid = 1;
 102
 103       /* this allocation allows us to guarantee that allocation
 104        * failures are never fatal later
 105        */
 106       tc->tile = MALLOC_STRUCT( softpipe_cached_tile );
 107       if (!tc->tile)
 108       {
 109          FREE(tc);
 110          return NULL;
 111       }
 112
 113       /* XXX this code prevents valgrind warnings about use of uninitialized
 114        * memory in programs that don't clear the surface before rendering.
 115        * However, it breaks clearing in other situations (such as in
 116        * progs/tests/drawbuffers, see bug 24402).
 117        */
 118 #if 0
 119       /* set flags to indicate all the tiles are cleared */
 120       memset(tc->clear_flags, 255, sizeof(tc->clear_flags));
 121 #endif
 122    }
 123    return tc;
 124 }
 125
 126
 127 void
 128 sp_destroy_tile_cache(struct softpipe_tile_cache *tc)
 129 {
 130    if (tc) {
 131       uint pos;
 132
 133       for (pos = 0; pos < NUM_ENTRIES; pos++) {
 134          /*assert(tc->entries[pos].x < 0);*/
 135          FREE( tc->entries[pos] );
 136       }
 137       FREE( tc->tile );
 138
 139       if (tc->transfer) {
 140          tc->pipe->transfer_destroy(tc->pipe, tc->transfer);
 141       }
 142
 143       FREE( tc );
 144    }
 145 }
 146
 147
 148 /**
 149  * Specify the surface to cache.
 150  */
 151 void
 152 sp_tile_cache_set_surface(struct softpipe_tile_cache *tc,
 153                           struct pipe_surface *ps)
 154 {
 155    struct pipe_context *pipe = tc->pipe;
 156
 157    if (tc->transfer) {
 158       if (ps == tc->surface)
 159          return;
 160
 161       if (tc->transfer_map) {
 162          pipe->transfer_unmap(pipe, tc->transfer);
 163          tc->transfer_map = NULL;
 164       }
 165
 166       pipe->transfer_destroy(pipe, tc->transfer);
 167       tc->transfer = NULL;
 168    }
 169
 170    tc->surface = ps;
 171
 172    if (ps) {
 173       tc->transfer = pipe_get_transfer(pipe, ps->texture, ps->face,
 174                                            ps->level, ps->zslice,
 175                                            PIPE_TRANSFER_READ_WRITE |
 176                                            PIPE_TRANSFER_UNSYNCHRONIZED,
 177                                            0, 0, ps->width, ps->height);
 178
 179       tc->depth_stencil = (ps->format == PIPE_FORMAT_Z24_UNORM_S8_USCALED ||
 180                            ps->format == PIPE_FORMAT_Z24X8_UNORM ||
 181                            ps->format == PIPE_FORMAT_S8_USCALED_Z24_UNORM ||
 182                            ps->format == PIPE_FORMAT_X8Z24_UNORM ||
 183                            ps->format == PIPE_FORMAT_Z16_UNORM ||
 184                            ps->format == PIPE_FORMAT_Z32_UNORM ||
 185                            ps->format == PIPE_FORMAT_S8_USCALED);
 186    }
 187 }
 188
 189
 190 /**
 191  * Return the transfer being cached.
 192  */
 193 struct pipe_surface *
 194 sp_tile_cache_get_surface(struct softpipe_tile_cache *tc)
 195 {
 196    return tc->surface;
 197 }
 198
 199
 200 void
 201 sp_tile_cache_map_transfers(struct softpipe_tile_cache *tc)
 202 {
 203    if (tc->transfer && !tc->transfer_map)
 204       tc->transfer_map = tc->pipe->transfer_map(tc->pipe, tc->transfer);
 205 }
 206
 207
 208 void
 209 sp_tile_cache_unmap_transfers(struct softpipe_tile_cache *tc)
 210 {
 211    if (tc->transfer_map) {
 212       tc->pipe->transfer_unmap(tc->pipe, tc->transfer);
 213       tc->transfer_map = NULL;
 214    }
 215 }
 216
 217
 218 /**
 219  * Set pixels in a tile to the given clear color/value, float.
 220  */
 221 static void
 222 clear_tile_rgba(struct softpipe_cached_tile *tile,
 223                 enum pipe_format format,
 224                 const float clear_value[4])
 225 {
 226    if (clear_value[0] == 0.0 &&
 227        clear_value[1] == 0.0 &&
 228        clear_value[2] == 0.0 &&
 229        clear_value[3] == 0.0) {
 230       memset(tile->data.color, 0, sizeof(tile->data.color));
 231    }
 232    else {
 233       uint i, j;
 234       for (i = 0; i < TILE_SIZE; i++) {
 235          for (j = 0; j < TILE_SIZE; j++) {
 236             tile->data.color[i][j][0] = clear_value[0];
 237             tile->data.color[i][j][1] = clear_value[1];
 238             tile->data.color[i][j][2] = clear_value[2];
 239             tile->data.color[i][j][3] = clear_value[3];
 240          }
 241       }
 242    }
 243 }
 244
 245
 246 /**
 247  * Set a tile to a solid value/color.
 248  */
 249 static void
 250 clear_tile(struct softpipe_cached_tile *tile,
 251            enum pipe_format format,
 252            uint clear_value)
 253 {
 254    uint i, j;
 255
 256    switch (util_format_get_blocksize(format)) {
 257    case 1:
 258       memset(tile->data.any, clear_value, TILE_SIZE * TILE_SIZE);
 259       break;
 260    case 2:
 261       if (clear_value == 0) {
 262          memset(tile->data.any, 0, 2 * TILE_SIZE * TILE_SIZE);
 263       }
 264       else {
 265          for (i = 0; i < TILE_SIZE; i++) {
 266             for (j = 0; j < TILE_SIZE; j++) {
 267                tile->data.depth16[i][j] = (ushort) clear_value;
 268             }
 269          }
 270       }
 271       break;
 272    case 4:
 273       if (clear_value == 0) {
 274          memset(tile->data.any, 0, 4 * TILE_SIZE * TILE_SIZE);
 275       }
 276       else {
 277          for (i = 0; i < TILE_SIZE; i++) {
 278             for (j = 0; j < TILE_SIZE; j++) {
 279                tile->data.color32[i][j] = clear_value;
 280             }
 281          }
 282       }
 283       break;
 284    default:
 285       assert(0);
 286    }
 287 }
 288
 289
 290 /**
 291  * Actually clear the tiles which were flagged as being in a clear state.
 292  */
 293 static void
 294 sp_tile_cache_flush_clear(struct softpipe_tile_cache *tc)
 295 {
 296    struct pipe_transfer *pt = tc->transfer;
 297    const uint w = tc->transfer->box.width;
 298    const uint h = tc->transfer->box.height;
 299    uint x, y;
 300    uint numCleared = 0;
 301
 302    assert(pt->resource);
 303    if (!tc->tile)
 304       tc->tile = sp_alloc_tile(tc);
 305
 306    /* clear the scratch tile to the clear value */
 307    if (tc->depth_stencil) {
 308       clear_tile(tc->tile, pt->resource->format, tc->clear_val);
 309    } else {
 310       clear_tile_rgba(tc->tile, pt->resource->format, tc->clear_color);
 311    }
 312
 313    /* push the tile to all positions marked as clear */
 314    for (y = 0; y < h; y += TILE_SIZE) {
 315       for (x = 0; x < w; x += TILE_SIZE) {
 316          union tile_address addr = tile_address(x, y);
 317
 318          if (is_clear_flag_set(tc->clear_flags, addr)) {
 319             /* write the scratch tile to the surface */
 320             if (tc->depth_stencil) {
 321                pipe_put_tile_raw(tc->pipe,
 322                                  pt,
 323                                  x, y, TILE_SIZE, TILE_SIZE,
 324                                  tc->tile->data.any, 0/*STRIDE*/);
 325             }
 326             else {
 327                pipe_put_tile_rgba(tc->pipe, pt,
 328                                   x, y, TILE_SIZE, TILE_SIZE,
 329                                   (float *) tc->tile->data.color);
 330             }
 331             numCleared++;
 332          }
 333       }
 334    }
 335
 336    /* reset all clear flags to zero */
 337    memset(tc->clear_flags, 0, sizeof(tc->clear_flags));
 338
 339 #if 0
 340    debug_printf("num cleared: %u\n", numCleared);
 341 #endif
 342 }
 343
 344 static void
 345 sp_flush_tile(struct softpipe_tile_cache* tc, unsigned pos)
 346 {
 347    if (!tc->tile_addrs[pos].bits.invalid) {
 348       if (tc->depth_stencil) {
 349          pipe_put_tile_raw(tc->pipe, tc->transfer,
 350                            tc->tile_addrs[pos].bits.x * TILE_SIZE,
 351                            tc->tile_addrs[pos].bits.y * TILE_SIZE,
 352                            TILE_SIZE, TILE_SIZE,
 353                            tc->entries[pos]->data.depth32, 0/*STRIDE*/);
 354       }
 355       else {
 356          pipe_put_tile_rgba(tc->pipe, tc->transfer,
 357                             tc->tile_addrs[pos].bits.x * TILE_SIZE,
 358                             tc->tile_addrs[pos].bits.y * TILE_SIZE,
 359                             TILE_SIZE, TILE_SIZE,
 360                             (float *) tc->entries[pos]->data.color);
 361       }
 362       tc->tile_addrs[pos].bits.invalid = 1;  /* mark as empty */
 363    }
 364 }
 365
 366 /**
 367  * Flush the tile cache: write all dirty tiles back to the transfer.
 368  * any tiles "flagged" as cleared will be "really" cleared.
 369  */
 370 void
 371 sp_flush_tile_cache(struct softpipe_tile_cache *tc)
 372 {
 373    struct pipe_transfer *pt = tc->transfer;
 374    int inuse = 0, pos;
 375
 376    if (pt) {
 377       /* caching a drawing transfer */
 378       for (pos = 0; pos < NUM_ENTRIES; pos++) {
 379          struct softpipe_cached_tile *tile = tc->entries[pos];
 380          if (!tile)
 381          {
 382             assert(tc->tile_addrs[pos].bits.invalid);
 383             continue;
 384          }
 385
 386          sp_flush_tile(tc, pos);
 387          ++inuse;
 388       }
 389
 390       sp_tile_cache_flush_clear(tc);
 391
 392
 393       tc->last_tile_addr.bits.invalid = 1;
 394    }
 395
 396 #if 0
 397    debug_printf("flushed tiles in use: %d\n", inuse);
 398 #endif
 399 }
 400
 401 static struct softpipe_cached_tile *
 402 sp_alloc_tile(struct softpipe_tile_cache *tc)
 403 {
 404    struct softpipe_cached_tile * tile = MALLOC_STRUCT(softpipe_cached_tile);
 405    if (!tile)
 406    {
 407       /* in this case, steal an existing tile */
 408       if (!tc->tile)
 409       {
 410          unsigned pos;
 411          for (pos = 0; pos < NUM_ENTRIES; ++pos) {
 412             if (!tc->entries[pos])
 413                continue;
 414
 415             sp_flush_tile(tc, pos);
 416             tc->tile = tc->entries[pos];
 417             tc->entries[pos] = NULL;
 418             break;
 419          }
 420
 421          /* this should never happen */
 422          if (!tc->tile)
 423             abort();
 424       }
 425
 426       tile = tc->tile;
 427       tc->tile = NULL;
 428
 429       tc->last_tile_addr.bits.invalid = 1;
 430    }
 431    return tile;
 432 }
 433
 434 /**
 435  * Get a tile from the cache.
 436  * \param x, y  position of tile, in pixels
 437  */
 438 struct softpipe_cached_tile *
 439 sp_find_cached_tile(struct softpipe_tile_cache *tc,
 440                     union tile_address addr )
 441 {
 442    struct pipe_transfer *pt = tc->transfer;
 443
 444    /* cache pos/entry: */
 445    const int pos = CACHE_POS(addr.bits.x,
 446                              addr.bits.y);
 447    struct softpipe_cached_tile *tile = tc->entries[pos];
 448
 449    if (!tile) {
 450       tile = sp_alloc_tile(tc);
 451       tc->entries[pos] = tile;
 452    }
 453
 454    if (addr.value != tc->tile_addrs[pos].value) {
 455
 456       assert(pt->resource);
 457       if (tc->tile_addrs[pos].bits.invalid == 0) {
 458          /* put dirty tile back in framebuffer */
 459          if (tc->depth_stencil) {
 460             pipe_put_tile_raw(tc->pipe, pt,
 461                               tc->tile_addrs[pos].bits.x * TILE_SIZE,
 462                               tc->tile_addrs[pos].bits.y * TILE_SIZE,
 463                               TILE_SIZE, TILE_SIZE,
 464                               tile->data.depth32, 0/*STRIDE*/);
 465          }
 466          else {
 467             pipe_put_tile_rgba(tc->pipe, pt,
 468                                tc->tile_addrs[pos].bits.x * TILE_SIZE,
 469                                tc->tile_addrs[pos].bits.y * TILE_SIZE,
 470                                TILE_SIZE, TILE_SIZE,
 471                                (float *) tile->data.color);
 472          }
 473       }
 474
 475       tc->tile_addrs[pos] = addr;
 476
 477       if (is_clear_flag_set(tc->clear_flags, addr)) {
 478          /* don't get tile from framebuffer, just clear it */
 479          if (tc->depth_stencil) {
 480             clear_tile(tile, pt->resource->format, tc->clear_val);
 481          }
 482          else {
 483             clear_tile_rgba(tile, pt->resource->format, tc->clear_color);
 484          }
 485          clear_clear_flag(tc->clear_flags, addr);
 486       }
 487       else {
 488          /* get new tile data from transfer */
 489          if (tc->depth_stencil) {
 490             pipe_get_tile_raw(tc->pipe, pt,
 491                               tc->tile_addrs[pos].bits.x * TILE_SIZE,
 492                               tc->tile_addrs[pos].bits.y * TILE_SIZE,
 493                               TILE_SIZE, TILE_SIZE,
 494                               tile->data.depth32, 0/*STRIDE*/);
 495          }
 496          else {
 497             pipe_get_tile_rgba(tc->pipe, pt,
 498                                tc->tile_addrs[pos].bits.x * TILE_SIZE,
 499                                tc->tile_addrs[pos].bits.y * TILE_SIZE,
 500                                TILE_SIZE, TILE_SIZE,
 501                                (float *) tile->data.color);
 502          }
 503       }
 504    }
 505
 506    tc->last_tile = tile;
 507    tc->last_tile_addr = addr;
 508    return tile;
 509 }
 510
 511
 512
 513
 514
 515 /**
 516  * When a whole surface is being cleared to a value we can avoid
 517  * fetching tiles above.
 518  * Save the color and set a 'clearflag' for each tile of the screen.
 519  */
 520 void
 521 sp_tile_cache_clear(struct softpipe_tile_cache *tc, const float *rgba,
 522                     uint clearValue)
 523 {
 524    uint pos;
 525
 526    tc->clear_color[0] = rgba[0];
 527    tc->clear_color[1] = rgba[1];
 528    tc->clear_color[2] = rgba[2];
 529    tc->clear_color[3] = rgba[3];
 530
 531    tc->clear_val = clearValue;
 532
 533    /* set flags to indicate all the tiles are cleared */
 534    memset(tc->clear_flags, 255, sizeof(tc->clear_flags));
 535
 536    for (pos = 0; pos < NUM_ENTRIES; pos++) {
 537       tc->tile_addrs[pos].bits.invalid = 1;
 538    }
 539    tc->last_tile_addr.bits.invalid = 1;
 540 }