src/gallium/drivers/softpipe/sp_tile_cache.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /**
  29  * Render target tile caching.
  30  *
  31  * Author:
  32  *    Brian Paul
  33  */
  34
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_memory.h"
  38 #include "util/u_tile.h"
  39 #include "sp_tile_cache.h"
  40
  41
  42
  43 /**
  44  * Return the position in the cache for the tile that contains win pos (x,y).
  45  * We currently use a direct mapped cache so this is like a hack key.
  46  * At some point we should investige something more sophisticated, like
  47  * a LRU replacement policy.
  48  */
  49 #define CACHE_POS(x, y) \
  50    (((x) + (y) * 5) % NUM_ENTRIES)
  51
  52
  53
  54 /**
  55  * Is the tile at (x,y) in cleared state?
  56  */
  57 static INLINE uint
  58 is_clear_flag_set(const uint *bitvec, union tile_address addr)
  59 {
  60    int pos, bit;
  61    pos = addr.bits.y * (MAX_WIDTH / TILE_SIZE) + addr.bits.x;
  62    assert(pos / 32 < (MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32);
  63    bit = bitvec[pos / 32] & (1 << (pos & 31));
  64    return bit;
  65 }
  66
  67
  68 /**
  69  * Mark the tile at (x,y) as not cleared.
  70  */
  71 static INLINE void
  72 clear_clear_flag(uint *bitvec, union tile_address addr)
  73 {
  74    int pos;
  75    pos = addr.bits.y * (MAX_WIDTH / TILE_SIZE) + addr.bits.x;
  76    assert(pos / 32 < (MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32);
  77    bitvec[pos / 32] &= ~(1 << (pos & 31));
  78 }
  79
  80
  81 struct softpipe_tile_cache *
  82 sp_create_tile_cache( struct pipe_context *pipe )
  83 {
  84    struct softpipe_tile_cache *tc;
  85    uint pos;
  86    int maxLevels, maxTexSize;
  87
  88    /* sanity checking: max sure MAX_WIDTH/HEIGHT >= largest texture image */
  89    maxLevels = pipe->screen->get_param(pipe->screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS);
  90    maxTexSize = 1 << (maxLevels - 1);
  91    assert(MAX_WIDTH >= maxTexSize);
  92
  93    tc = CALLOC_STRUCT( softpipe_tile_cache );
  94    if (tc) {
  95       tc->pipe = pipe;
  96       for (pos = 0; pos < NUM_ENTRIES; pos++) {
  97          tc->entries[pos].addr.bits.invalid = 1;
  98       }
  99       tc->last_tile = &tc->entries[0]; /* any tile */
 100
 101       /* XXX this code prevents valgrind warnings about use of uninitialized
 102        * memory in programs that don't clear the surface before rendering.
 103        * However, it breaks clearing in other situations (such as in
 104        * progs/tests/drawbuffers, see bug 24402).
 105        */
 106 #if 0
 107       /* set flags to indicate all the tiles are cleared */
 108       memset(tc->clear_flags, 255, sizeof(tc->clear_flags));
 109 #endif
 110    }
 111    return tc;
 112 }
 113
 114
 115 void
 116 sp_destroy_tile_cache(struct softpipe_tile_cache *tc)
 117 {
 118    uint pos;
 119
 120    for (pos = 0; pos < NUM_ENTRIES; pos++) {
 121       /*assert(tc->entries[pos].x < 0);*/
 122    }
 123    if (tc->transfer) {
 124       tc->pipe->transfer_destroy(tc->pipe, tc->transfer);
 125    }
 126
 127    FREE( tc );
 128 }
 129
 130
 131 /**
 132  * Specify the surface to cache.
 133  */
 134 void
 135 sp_tile_cache_set_surface(struct softpipe_tile_cache *tc,
 136                           struct pipe_surface *ps)
 137 {
 138    struct pipe_context *pipe = tc->pipe;
 139
 140    if (tc->transfer) {
 141       if (ps == tc->surface)
 142          return;
 143
 144       if (tc->transfer_map) {
 145          pipe->transfer_unmap(pipe, tc->transfer);
 146          tc->transfer_map = NULL;
 147       }
 148
 149       pipe->transfer_destroy(pipe, tc->transfer);
 150       tc->transfer = NULL;
 151    }
 152
 153    tc->surface = ps;
 154
 155    if (ps) {
 156       tc->transfer = pipe_get_transfer(pipe, ps->texture, ps->face,
 157                                            ps->level, ps->zslice,
 158                                            PIPE_TRANSFER_READ_WRITE |
 159                                            PIPE_TRANSFER_UNSYNCHRONIZED,
 160                                            0, 0, ps->width, ps->height);
 161
 162       tc->depth_stencil = (ps->format == PIPE_FORMAT_Z24_UNORM_S8_USCALED ||
 163                            ps->format == PIPE_FORMAT_Z24X8_UNORM ||
 164                            ps->format == PIPE_FORMAT_S8_USCALED_Z24_UNORM ||
 165                            ps->format == PIPE_FORMAT_X8Z24_UNORM ||
 166                            ps->format == PIPE_FORMAT_Z16_UNORM ||
 167                            ps->format == PIPE_FORMAT_Z32_UNORM ||
 168                            ps->format == PIPE_FORMAT_S8_USCALED);
 169    }
 170 }
 171
 172
 173 /**
 174  * Return the transfer being cached.
 175  */
 176 struct pipe_surface *
 177 sp_tile_cache_get_surface(struct softpipe_tile_cache *tc)
 178 {
 179    return tc->surface;
 180 }
 181
 182
 183 void
 184 sp_tile_cache_map_transfers(struct softpipe_tile_cache *tc)
 185 {
 186    if (tc->transfer && !tc->transfer_map)
 187       tc->transfer_map = tc->pipe->transfer_map(tc->pipe, tc->transfer);
 188 }
 189
 190
 191 void
 192 sp_tile_cache_unmap_transfers(struct softpipe_tile_cache *tc)
 193 {
 194    if (tc->transfer_map) {
 195       tc->pipe->transfer_unmap(tc->pipe, tc->transfer);
 196       tc->transfer_map = NULL;
 197    }
 198 }
 199
 200
 201 /**
 202  * Set pixels in a tile to the given clear color/value, float.
 203  */
 204 static void
 205 clear_tile_rgba(struct softpipe_cached_tile *tile,
 206                 enum pipe_format format,
 207                 const float clear_value[4])
 208 {
 209    if (clear_value[0] == 0.0 &&
 210        clear_value[1] == 0.0 &&
 211        clear_value[2] == 0.0 &&
 212        clear_value[3] == 0.0) {
 213       memset(tile->data.color, 0, sizeof(tile->data.color));
 214    }
 215    else {
 216       uint i, j;
 217       for (i = 0; i < TILE_SIZE; i++) {
 218          for (j = 0; j < TILE_SIZE; j++) {
 219             tile->data.color[i][j][0] = clear_value[0];
 220             tile->data.color[i][j][1] = clear_value[1];
 221             tile->data.color[i][j][2] = clear_value[2];
 222             tile->data.color[i][j][3] = clear_value[3];
 223          }
 224       }
 225    }
 226 }
 227
 228
 229 /**
 230  * Set a tile to a solid value/color.
 231  */
 232 static void
 233 clear_tile(struct softpipe_cached_tile *tile,
 234            enum pipe_format format,
 235            uint clear_value)
 236 {
 237    uint i, j;
 238
 239    switch (util_format_get_blocksize(format)) {
 240    case 1:
 241       memset(tile->data.any, clear_value, TILE_SIZE * TILE_SIZE);
 242       break;
 243    case 2:
 244       if (clear_value == 0) {
 245          memset(tile->data.any, 0, 2 * TILE_SIZE * TILE_SIZE);
 246       }
 247       else {
 248          for (i = 0; i < TILE_SIZE; i++) {
 249             for (j = 0; j < TILE_SIZE; j++) {
 250                tile->data.depth16[i][j] = (ushort) clear_value;
 251             }
 252          }
 253       }
 254       break;
 255    case 4:
 256       if (clear_value == 0) {
 257          memset(tile->data.any, 0, 4 * TILE_SIZE * TILE_SIZE);
 258       }
 259       else {
 260          for (i = 0; i < TILE_SIZE; i++) {
 261             for (j = 0; j < TILE_SIZE; j++) {
 262                tile->data.color32[i][j] = clear_value;
 263             }
 264          }
 265       }
 266       break;
 267    default:
 268       assert(0);
 269    }
 270 }
 271
 272
 273 /**
 274  * Actually clear the tiles which were flagged as being in a clear state.
 275  */
 276 static void
 277 sp_tile_cache_flush_clear(struct softpipe_tile_cache *tc)
 278 {
 279    struct pipe_transfer *pt = tc->transfer;
 280    const uint w = tc->transfer->box.width;
 281    const uint h = tc->transfer->box.height;
 282    uint x, y;
 283    uint numCleared = 0;
 284
 285    assert(pt->resource);
 286    /* clear the scratch tile to the clear value */
 287    clear_tile(&tc->tile, pt->resource->format, tc->clear_val);
 288
 289    /* push the tile to all positions marked as clear */
 290    for (y = 0; y < h; y += TILE_SIZE) {
 291       for (x = 0; x < w; x += TILE_SIZE) {
 292          union tile_address addr = tile_address(x, y);
 293
 294          if (is_clear_flag_set(tc->clear_flags, addr)) {
 295             pipe_put_tile_raw(tc->pipe,
 296                               pt,
 297                               x, y, TILE_SIZE, TILE_SIZE,
 298                               tc->tile.data.color32, 0/*STRIDE*/);
 299
 300             numCleared++;
 301          }
 302       }
 303    }
 304
 305    /* reset all clear flags to zero */
 306    memset(tc->clear_flags, 0, sizeof(tc->clear_flags));
 307
 308 #if 0
 309    debug_printf("num cleared: %u\n", numCleared);
 310 #endif
 311 }
 312
 313
 314 /**
 315  * Flush the tile cache: write all dirty tiles back to the transfer.
 316  * any tiles "flagged" as cleared will be "really" cleared.
 317  */
 318 void
 319 sp_flush_tile_cache(struct softpipe_tile_cache *tc)
 320 {
 321    struct pipe_transfer *pt = tc->transfer;
 322    int inuse = 0, pos;
 323
 324    if (pt) {
 325       /* caching a drawing transfer */
 326       for (pos = 0; pos < NUM_ENTRIES; pos++) {
 327          struct softpipe_cached_tile *tile = tc->entries + pos;
 328          if (!tile->addr.bits.invalid) {
 329             if (tc->depth_stencil) {
 330                pipe_put_tile_raw(tc->pipe, pt,
 331                                  tile->addr.bits.x * TILE_SIZE,
 332                                  tile->addr.bits.y * TILE_SIZE,
 333                                  TILE_SIZE, TILE_SIZE,
 334                                  tile->data.depth32, 0/*STRIDE*/);
 335             }
 336             else {
 337                pipe_put_tile_rgba(tc->pipe, pt,
 338                                   tile->addr.bits.x * TILE_SIZE,
 339                                   tile->addr.bits.y * TILE_SIZE,
 340                                   TILE_SIZE, TILE_SIZE,
 341                                   (float *) tile->data.color);
 342             }
 343             tile->addr.bits.invalid = 1;  /* mark as empty */
 344             inuse++;
 345          }
 346       }
 347
 348       sp_tile_cache_flush_clear(tc);
 349    }
 350
 351 #if 0
 352    debug_printf("flushed tiles in use: %d\n", inuse);
 353 #endif
 354 }
 355
 356
 357 /**
 358  * Get a tile from the cache.
 359  * \param x, y  position of tile, in pixels
 360  */
 361 struct softpipe_cached_tile *
 362 sp_find_cached_tile(struct softpipe_tile_cache *tc,
 363                     union tile_address addr )
 364 {
 365    struct pipe_transfer *pt = tc->transfer;
 366
 367    /* cache pos/entry: */
 368    const int pos = CACHE_POS(addr.bits.x,
 369                              addr.bits.y);
 370    struct softpipe_cached_tile *tile = tc->entries + pos;
 371
 372    if (addr.value != tile->addr.value) {
 373
 374       assert(pt->resource);
 375       if (tile->addr.bits.invalid == 0) {
 376          /* put dirty tile back in framebuffer */
 377          if (tc->depth_stencil) {
 378             pipe_put_tile_raw(tc->pipe, pt,
 379                               tile->addr.bits.x * TILE_SIZE,
 380                               tile->addr.bits.y * TILE_SIZE,
 381                               TILE_SIZE, TILE_SIZE,
 382                               tile->data.depth32, 0/*STRIDE*/);
 383          }
 384          else {
 385             pipe_put_tile_rgba(tc->pipe, pt,
 386                                tile->addr.bits.x * TILE_SIZE,
 387                                tile->addr.bits.y * TILE_SIZE,
 388                                TILE_SIZE, TILE_SIZE,
 389                                (float *) tile->data.color);
 390          }
 391       }
 392
 393       tile->addr = addr;
 394
 395       if (is_clear_flag_set(tc->clear_flags, addr)) {
 396          /* don't get tile from framebuffer, just clear it */
 397          if (tc->depth_stencil) {
 398             clear_tile(tile, pt->resource->format, tc->clear_val);
 399          }
 400          else {
 401             clear_tile_rgba(tile, pt->resource->format, tc->clear_color);
 402          }
 403          clear_clear_flag(tc->clear_flags, addr);
 404       }
 405       else {
 406          /* get new tile data from transfer */
 407          if (tc->depth_stencil) {
 408             pipe_get_tile_raw(tc->pipe, pt,
 409                               tile->addr.bits.x * TILE_SIZE,
 410                               tile->addr.bits.y * TILE_SIZE,
 411                               TILE_SIZE, TILE_SIZE,
 412                               tile->data.depth32, 0/*STRIDE*/);
 413          }
 414          else {
 415             pipe_get_tile_rgba(tc->pipe, pt,
 416                                tile->addr.bits.x * TILE_SIZE,
 417                                tile->addr.bits.y * TILE_SIZE,
 418                                TILE_SIZE, TILE_SIZE,
 419                                (float *) tile->data.color);
 420          }
 421       }
 422    }
 423
 424    tc->last_tile = tile;
 425    return tile;
 426 }
 427
 428
 429
 430
 431
 432 /**
 433  * When a whole surface is being cleared to a value we can avoid
 434  * fetching tiles above.
 435  * Save the color and set a 'clearflag' for each tile of the screen.
 436  */
 437 void
 438 sp_tile_cache_clear(struct softpipe_tile_cache *tc, const float *rgba,
 439                     uint clearValue)
 440 {
 441    uint pos;
 442
 443    tc->clear_color[0] = rgba[0];
 444    tc->clear_color[1] = rgba[1];
 445    tc->clear_color[2] = rgba[2];
 446    tc->clear_color[3] = rgba[3];
 447
 448    tc->clear_val = clearValue;
 449
 450    /* set flags to indicate all the tiles are cleared */
 451    memset(tc->clear_flags, 255, sizeof(tc->clear_flags));
 452
 453    for (pos = 0; pos < NUM_ENTRIES; pos++) {
 454       struct softpipe_cached_tile *tile = tc->entries + pos;
 455       tile->addr.bits.invalid = 1;
 456    }
 457 }