src/gallium/drivers/softpipe/sp_tile_cache.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
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   7  * copy of this software and associated documentation files (the
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  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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  26  **************************************************************************/
  27
  28 /**
  29  * Render target tile caching.
  30  *
  31  * Author:
  32  *    Brian Paul
  33  */
  34
  35 #include "pipe/p_inlines.h"
  36 #include "util/u_memory.h"
  37 #include "util/u_tile.h"
  38 #include "sp_tile_cache.h"
  39
  40
  41
  42 /**
  43  * Return the position in the cache for the tile that contains win pos (x,y).
  44  * We currently use a direct mapped cache so this is like a hack key.
  45  * At some point we should investige something more sophisticated, like
  46  * a LRU replacement policy.
  47  */
  48 #define CACHE_POS(x, y) \
  49    (((x) + (y) * 5) % NUM_ENTRIES)
  50
  51
  52
  53 /**
  54  * Is the tile at (x,y) in cleared state?
  55  */
  56 static INLINE uint
  57 is_clear_flag_set(const uint *bitvec, union tile_address addr)
  58 {
  59    int pos, bit;
  60    pos = addr.bits.y * (MAX_WIDTH / TILE_SIZE) + addr.bits.x;
  61    assert(pos / 32 < (MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32);
  62    bit = bitvec[pos / 32] & (1 << (pos & 31));
  63    return bit;
  64 }
  65
  66
  67 /**
  68  * Mark the tile at (x,y) as not cleared.
  69  */
  70 static INLINE void
  71 clear_clear_flag(uint *bitvec, union tile_address addr)
  72 {
  73    int pos;
  74    pos = addr.bits.y * (MAX_WIDTH / TILE_SIZE) + addr.bits.x;
  75    assert(pos / 32 < (MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32);
  76    bitvec[pos / 32] &= ~(1 << (pos & 31));
  77 }
  78
  79
  80 struct softpipe_tile_cache *
  81 sp_create_tile_cache( struct pipe_screen *screen )
  82 {
  83    struct softpipe_tile_cache *tc;
  84    uint pos;
  85    int maxLevels, maxTexSize;
  86
  87    /* sanity checking: max sure MAX_WIDTH/HEIGHT >= largest texture image */
  88    maxLevels = screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS);
  89    maxTexSize = 1 << (maxLevels - 1);
  90    assert(MAX_WIDTH >= maxTexSize);
  91
  92    tc = CALLOC_STRUCT( softpipe_tile_cache );
  93    if (tc) {
  94       tc->screen = screen;
  95       for (pos = 0; pos < NUM_ENTRIES; pos++) {
  96          tc->entries[pos].addr.bits.invalid = 1;
  97       }
  98       tc->last_tile = &tc->entries[0]; /* any tile */
  99
 100       /* XXX this code prevents valgrind warnings about use of uninitialized
 101        * memory in programs that don't clear the surface before rendering.
 102        * However, it breaks clearing in other situations (such as in
 103        * progs/tests/drawbuffers, see bug 24402).
 104        */
 105 #if 0 && TILE_CLEAR_OPTIMIZATION
 106       /* set flags to indicate all the tiles are cleared */
 107       memset(tc->clear_flags, 255, sizeof(tc->clear_flags));
 108 #endif
 109    }
 110    return tc;
 111 }
 112
 113
 114 void
 115 sp_destroy_tile_cache(struct softpipe_tile_cache *tc)
 116 {
 117    struct pipe_screen *screen;
 118    uint pos;
 119
 120    for (pos = 0; pos < NUM_ENTRIES; pos++) {
 121       /*assert(tc->entries[pos].x < 0);*/
 122    }
 123    if (tc->transfer) {
 124       screen = tc->transfer->texture->screen;
 125       screen->tex_transfer_destroy(tc->transfer);
 126    }
 127
 128    FREE( tc );
 129 }
 130
 131
 132 /**
 133  * Specify the surface to cache.
 134  */
 135 void
 136 sp_tile_cache_set_surface(struct softpipe_tile_cache *tc,
 137                           struct pipe_surface *ps)
 138 {
 139    if (tc->transfer) {
 140       struct pipe_screen *screen = tc->transfer->texture->screen;
 141
 142       if (ps == tc->surface)
 143          return;
 144
 145       if (tc->transfer_map) {
 146          screen->transfer_unmap(screen, tc->transfer);
 147          tc->transfer_map = NULL;
 148       }
 149
 150       screen->tex_transfer_destroy(tc->transfer);
 151       tc->transfer = NULL;
 152    }
 153
 154    tc->surface = ps;
 155
 156    if (ps) {
 157       struct pipe_screen *screen = ps->texture->screen;
 158
 159       tc->transfer = screen->get_tex_transfer(screen, ps->texture, ps->face,
 160                                               ps->level, ps->zslice,
 161                                               PIPE_TRANSFER_READ_WRITE,
 162                                               0, 0, ps->width, ps->height);
 163
 164       tc->depth_stencil = (ps->format == PIPE_FORMAT_S8Z24_UNORM ||
 165                            ps->format == PIPE_FORMAT_X8Z24_UNORM ||
 166                            ps->format == PIPE_FORMAT_Z24S8_UNORM ||
 167                            ps->format == PIPE_FORMAT_Z24X8_UNORM ||
 168                            ps->format == PIPE_FORMAT_Z16_UNORM ||
 169                            ps->format == PIPE_FORMAT_Z32_UNORM ||
 170                            ps->format == PIPE_FORMAT_S8_UNORM);
 171    }
 172 }
 173
 174
 175 /**
 176  * Return the transfer being cached.
 177  */
 178 struct pipe_surface *
 179 sp_tile_cache_get_surface(struct softpipe_tile_cache *tc)
 180 {
 181    return tc->surface;
 182 }
 183
 184
 185 void
 186 sp_tile_cache_map_transfers(struct softpipe_tile_cache *tc)
 187 {
 188    if (tc->transfer && !tc->transfer_map)
 189       tc->transfer_map = tc->screen->transfer_map(tc->screen, tc->transfer);
 190 }
 191
 192
 193 void
 194 sp_tile_cache_unmap_transfers(struct softpipe_tile_cache *tc)
 195 {
 196    if (tc->transfer_map) {
 197       tc->screen->transfer_unmap(tc->screen, tc->transfer);
 198       tc->transfer_map = NULL;
 199    }
 200 }
 201
 202
 203 /**
 204  * Set pixels in a tile to the given clear color/value, float.
 205  */
 206 static void
 207 clear_tile_rgba(struct softpipe_cached_tile *tile,
 208                 enum pipe_format format,
 209                 const float clear_value[4])
 210 {
 211    if (clear_value[0] == 0.0 &&
 212        clear_value[1] == 0.0 &&
 213        clear_value[2] == 0.0 &&
 214        clear_value[3] == 0.0) {
 215       memset(tile->data.color, 0, sizeof(tile->data.color));
 216    }
 217    else {
 218       uint i, j;
 219       for (i = 0; i < TILE_SIZE; i++) {
 220          for (j = 0; j < TILE_SIZE; j++) {
 221             tile->data.color[i][j][0] = clear_value[0];
 222             tile->data.color[i][j][1] = clear_value[1];
 223             tile->data.color[i][j][2] = clear_value[2];
 224             tile->data.color[i][j][3] = clear_value[3];
 225          }
 226       }
 227    }
 228 }
 229
 230
 231 /**
 232  * Set a tile to a solid value/color.
 233  */
 234 static void
 235 clear_tile(struct softpipe_cached_tile *tile,
 236            enum pipe_format format,
 237            uint clear_value)
 238 {
 239    uint i, j;
 240
 241    switch (pf_get_size(format)) {
 242    case 1:
 243       memset(tile->data.any, clear_value, TILE_SIZE * TILE_SIZE);
 244       break;
 245    case 2:
 246       if (clear_value == 0) {
 247          memset(tile->data.any, 0, 2 * TILE_SIZE * TILE_SIZE);
 248       }
 249       else {
 250          for (i = 0; i < TILE_SIZE; i++) {
 251             for (j = 0; j < TILE_SIZE; j++) {
 252                tile->data.depth16[i][j] = (ushort) clear_value;
 253             }
 254          }
 255       }
 256       break;
 257    case 4:
 258       if (clear_value == 0) {
 259          memset(tile->data.any, 0, 4 * TILE_SIZE * TILE_SIZE);
 260       }
 261       else {
 262          for (i = 0; i < TILE_SIZE; i++) {
 263             for (j = 0; j < TILE_SIZE; j++) {
 264                tile->data.color32[i][j] = clear_value;
 265             }
 266          }
 267       }
 268       break;
 269    default:
 270       assert(0);
 271    }
 272 }
 273
 274
 275 /**
 276  * Actually clear the tiles which were flagged as being in a clear state.
 277  */
 278 static void
 279 sp_tile_cache_flush_clear(struct softpipe_tile_cache *tc)
 280 {
 281    struct pipe_transfer *pt = tc->transfer;
 282    const uint w = tc->transfer->width;
 283    const uint h = tc->transfer->height;
 284    uint x, y;
 285    uint numCleared = 0;
 286
 287    /* clear the scratch tile to the clear value */
 288    clear_tile(&tc->tile, pt->format, tc->clear_val);
 289
 290    /* push the tile to all positions marked as clear */
 291    for (y = 0; y < h; y += TILE_SIZE) {
 292       for (x = 0; x < w; x += TILE_SIZE) {
 293          union tile_address addr = tile_address(x, y);
 294
 295          if (is_clear_flag_set(tc->clear_flags, addr)) {
 296             pipe_put_tile_raw(pt,
 297                               x, y, TILE_SIZE, TILE_SIZE,
 298                               tc->tile.data.color32, 0/*STRIDE*/);
 299
 300             /* do this? */
 301             clear_clear_flag(tc->clear_flags, addr);
 302
 303             numCleared++;
 304          }
 305       }
 306    }
 307 #if 0
 308    debug_printf("num cleared: %u\n", numCleared);
 309 #endif
 310 }
 311
 312
 313 /**
 314  * Flush the tile cache: write all dirty tiles back to the transfer.
 315  * any tiles "flagged" as cleared will be "really" cleared.
 316  */
 317 void
 318 sp_flush_tile_cache(struct softpipe_tile_cache *tc)
 319 {
 320    struct pipe_transfer *pt = tc->transfer;
 321    int inuse = 0, pos;
 322
 323    if (pt) {
 324       /* caching a drawing transfer */
 325       for (pos = 0; pos < NUM_ENTRIES; pos++) {
 326          struct softpipe_cached_tile *tile = tc->entries + pos;
 327          if (!tile->addr.bits.invalid) {
 328             if (tc->depth_stencil) {
 329                pipe_put_tile_raw(pt,
 330                                  tile->addr.bits.x * TILE_SIZE,
 331                                  tile->addr.bits.y * TILE_SIZE,
 332                                  TILE_SIZE, TILE_SIZE,
 333                                  tile->data.depth32, 0/*STRIDE*/);
 334             }
 335             else {
 336                pipe_put_tile_rgba(pt,
 337                                   tile->addr.bits.x * TILE_SIZE,
 338                                   tile->addr.bits.y * TILE_SIZE,
 339                                   TILE_SIZE, TILE_SIZE,
 340                                   (float *) tile->data.color);
 341             }
 342             tile->addr.bits.invalid = 1;  /* mark as empty */
 343             inuse++;
 344          }
 345       }
 346
 347 #if TILE_CLEAR_OPTIMIZATION
 348       sp_tile_cache_flush_clear(tc);
 349 #endif
 350    }
 351
 352 #if 0
 353    debug_printf("flushed tiles in use: %d\n", inuse);
 354 #endif
 355 }
 356
 357
 358 /**
 359  * Get a tile from the cache.
 360  * \param x, y  position of tile, in pixels
 361  */
 362 struct softpipe_cached_tile *
 363 sp_find_cached_tile(struct softpipe_tile_cache *tc,
 364                     union tile_address addr )
 365 {
 366    struct pipe_transfer *pt = tc->transfer;
 367
 368    /* cache pos/entry: */
 369    const int pos = CACHE_POS(addr.bits.x,
 370                              addr.bits.y);
 371    struct softpipe_cached_tile *tile = tc->entries + pos;
 372
 373    if (addr.value != tile->addr.value) {
 374
 375       if (tile->addr.bits.invalid == 0) {
 376          /* put dirty tile back in framebuffer */
 377          if (tc->depth_stencil) {
 378             pipe_put_tile_raw(pt,
 379                               tile->addr.bits.x * TILE_SIZE,
 380                               tile->addr.bits.y * TILE_SIZE,
 381                               TILE_SIZE, TILE_SIZE,
 382                               tile->data.depth32, 0/*STRIDE*/);
 383          }
 384          else {
 385             pipe_put_tile_rgba(pt,
 386                                tile->addr.bits.x * TILE_SIZE,
 387                                tile->addr.bits.y * TILE_SIZE,
 388                                TILE_SIZE, TILE_SIZE,
 389                                (float *) tile->data.color);
 390          }
 391       }
 392
 393       tile->addr = addr;
 394
 395       if (is_clear_flag_set(tc->clear_flags, addr)) {
 396          /* don't get tile from framebuffer, just clear it */
 397          if (tc->depth_stencil) {
 398             clear_tile(tile, pt->format, tc->clear_val);
 399          }
 400          else {
 401             clear_tile_rgba(tile, pt->format, tc->clear_color);
 402          }
 403          clear_clear_flag(tc->clear_flags, addr);
 404       }
 405       else {
 406          /* get new tile data from transfer */
 407          if (tc->depth_stencil) {
 408             pipe_get_tile_raw(pt,
 409                               tile->addr.bits.x * TILE_SIZE,
 410                               tile->addr.bits.y * TILE_SIZE,
 411                               TILE_SIZE, TILE_SIZE,
 412                               tile->data.depth32, 0/*STRIDE*/);
 413          }
 414          else {
 415             pipe_get_tile_rgba(pt,
 416                                tile->addr.bits.x * TILE_SIZE,
 417                                tile->addr.bits.y * TILE_SIZE,
 418                                TILE_SIZE, TILE_SIZE,
 419                                (float *) tile->data.color);
 420          }
 421       }
 422    }
 423
 424    tc->last_tile = tile;
 425    return tile;
 426 }
 427
 428
 429
 430
 431
 432 /**
 433  * When a whole surface is being cleared to a value we can avoid
 434  * fetching tiles above.
 435  * Save the color and set a 'clearflag' for each tile of the screen.
 436  */
 437 void
 438 sp_tile_cache_clear(struct softpipe_tile_cache *tc, const float *rgba,
 439                     uint clearValue)
 440 {
 441    uint pos;
 442
 443    tc->clear_color[0] = rgba[0];
 444    tc->clear_color[1] = rgba[1];
 445    tc->clear_color[2] = rgba[2];
 446    tc->clear_color[3] = rgba[3];
 447
 448    tc->clear_val = clearValue;
 449
 450 #if TILE_CLEAR_OPTIMIZATION
 451    /* set flags to indicate all the tiles are cleared */
 452    memset(tc->clear_flags, 255, sizeof(tc->clear_flags));
 453 #else
 454    /* disable the optimization */
 455    memset(tc->clear_flags, 0, sizeof(tc->clear_flags));
 456 #endif
 457
 458    for (pos = 0; pos < NUM_ENTRIES; pos++) {
 459       struct softpipe_cached_tile *tile = tc->entries + pos;
 460       tile->addr.bits.invalid = 1;
 461    }
 462 }