softpipe: add integer support
[mesa.git] / src / gallium / drivers / softpipe / sp_tile_cache.c
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2 *
3 * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
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27
28 /**
29 * Render target tile caching.
30 *
31 * Author:
32 * Brian Paul
33 */
34
35 #include "util/u_inlines.h"
36 #include "util/u_format.h"
37 #include "util/u_memory.h"
38 #include "util/u_tile.h"
39 #include "sp_tile_cache.h"
40
41 static struct softpipe_cached_tile *
42 sp_alloc_tile(struct softpipe_tile_cache *tc);
43
44
45 /**
46 * Return the position in the cache for the tile that contains win pos (x,y).
47 * We currently use a direct mapped cache so this is like a hack key.
48 * At some point we should investige something more sophisticated, like
49 * a LRU replacement policy.
50 */
51 #define CACHE_POS(x, y) \
52 (((x) + (y) * 5) % NUM_ENTRIES)
53
54
55
56 /**
57 * Is the tile at (x,y) in cleared state?
58 */
59 static INLINE uint
60 is_clear_flag_set(const uint *bitvec, union tile_address addr)
61 {
62 int pos, bit;
63 pos = addr.bits.y * (MAX_WIDTH / TILE_SIZE) + addr.bits.x;
64 assert(pos / 32 < (MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32);
65 bit = bitvec[pos / 32] & (1 << (pos & 31));
66 return bit;
67 }
68
69
70 /**
71 * Mark the tile at (x,y) as not cleared.
72 */
73 static INLINE void
74 clear_clear_flag(uint *bitvec, union tile_address addr)
75 {
76 int pos;
77 pos = addr.bits.y * (MAX_WIDTH / TILE_SIZE) + addr.bits.x;
78 assert(pos / 32 < (MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32);
79 bitvec[pos / 32] &= ~(1 << (pos & 31));
80 }
81
82
83 struct softpipe_tile_cache *
84 sp_create_tile_cache( struct pipe_context *pipe )
85 {
86 struct softpipe_tile_cache *tc;
87 uint pos;
88 int maxLevels, maxTexSize;
89
90 /* sanity checking: max sure MAX_WIDTH/HEIGHT >= largest texture image */
91 maxLevels = pipe->screen->get_param(pipe->screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS);
92 maxTexSize = 1 << (maxLevels - 1);
93 assert(MAX_WIDTH >= maxTexSize);
94
95 assert(sizeof(union tile_address) == 4);
96
97 assert((TILE_SIZE << TILE_ADDR_BITS) >= MAX_WIDTH);
98
99 tc = CALLOC_STRUCT( softpipe_tile_cache );
100 if (tc) {
101 tc->pipe = pipe;
102 for (pos = 0; pos < NUM_ENTRIES; pos++) {
103 tc->tile_addrs[pos].bits.invalid = 1;
104 }
105 tc->last_tile_addr.bits.invalid = 1;
106
107 /* this allocation allows us to guarantee that allocation
108 * failures are never fatal later
109 */
110 tc->tile = MALLOC_STRUCT( softpipe_cached_tile );
111 if (!tc->tile)
112 {
113 FREE(tc);
114 return NULL;
115 }
116
117 /* XXX this code prevents valgrind warnings about use of uninitialized
118 * memory in programs that don't clear the surface before rendering.
119 * However, it breaks clearing in other situations (such as in
120 * progs/tests/drawbuffers, see bug 24402).
121 */
122 #if 0
123 /* set flags to indicate all the tiles are cleared */
124 memset(tc->clear_flags, 255, sizeof(tc->clear_flags));
125 #endif
126 }
127 return tc;
128 }
129
130
131 void
132 sp_destroy_tile_cache(struct softpipe_tile_cache *tc)
133 {
134 if (tc) {
135 uint pos;
136
137 for (pos = 0; pos < NUM_ENTRIES; pos++) {
138 /*assert(tc->entries[pos].x < 0);*/
139 FREE( tc->entries[pos] );
140 }
141 FREE( tc->tile );
142
143 if (tc->transfer) {
144 tc->pipe->transfer_destroy(tc->pipe, tc->transfer);
145 }
146
147 FREE( tc );
148 }
149 }
150
151
152 /**
153 * Specify the surface to cache.
154 */
155 void
156 sp_tile_cache_set_surface(struct softpipe_tile_cache *tc,
157 struct pipe_surface *ps)
158 {
159 struct pipe_context *pipe = tc->pipe;
160
161 if (tc->transfer) {
162 if (ps == tc->surface)
163 return;
164
165 if (tc->transfer_map) {
166 pipe->transfer_unmap(pipe, tc->transfer);
167 tc->transfer_map = NULL;
168 }
169
170 pipe->transfer_destroy(pipe, tc->transfer);
171 tc->transfer = NULL;
172 }
173
174 tc->surface = ps;
175
176 if (ps) {
177 tc->transfer = pipe_get_transfer(pipe, ps->texture,
178 ps->u.tex.level, ps->u.tex.first_layer,
179 PIPE_TRANSFER_READ_WRITE |
180 PIPE_TRANSFER_UNSYNCHRONIZED,
181 0, 0, ps->width, ps->height);
182
183 tc->depth_stencil = util_format_is_depth_or_stencil(ps->format);
184 }
185 }
186
187
188 /**
189 * Return the transfer being cached.
190 */
191 struct pipe_surface *
192 sp_tile_cache_get_surface(struct softpipe_tile_cache *tc)
193 {
194 return tc->surface;
195 }
196
197
198 void
199 sp_tile_cache_map_transfers(struct softpipe_tile_cache *tc)
200 {
201 if (tc->transfer && !tc->transfer_map)
202 tc->transfer_map = tc->pipe->transfer_map(tc->pipe, tc->transfer);
203 }
204
205
206 void
207 sp_tile_cache_unmap_transfers(struct softpipe_tile_cache *tc)
208 {
209 if (tc->transfer_map) {
210 tc->pipe->transfer_unmap(tc->pipe, tc->transfer);
211 tc->transfer_map = NULL;
212 }
213 }
214
215
216 /**
217 * Set pixels in a tile to the given clear color/value, float.
218 */
219 static void
220 clear_tile_rgba(struct softpipe_cached_tile *tile,
221 enum pipe_format format,
222 const union pipe_color_union *clear_value)
223 {
224 if (clear_value->f[0] == 0.0 &&
225 clear_value->f[1] == 0.0 &&
226 clear_value->f[2] == 0.0 &&
227 clear_value->f[3] == 0.0) {
228 memset(tile->data.color, 0, sizeof(tile->data.color));
229 }
230 else {
231 uint i, j;
232
233 if (util_format_is_pure_uint(format)) {
234 for (i = 0; i < TILE_SIZE; i++) {
235 for (j = 0; j < TILE_SIZE; j++) {
236 tile->data.colorui128[i][j][0] = clear_value->ui[0];
237 tile->data.colorui128[i][j][1] = clear_value->ui[1];
238 tile->data.colorui128[i][j][2] = clear_value->ui[2];
239 tile->data.colorui128[i][j][3] = clear_value->ui[3];
240 }
241 }
242 } else if (util_format_is_pure_sint(format)) {
243 for (i = 0; i < TILE_SIZE; i++) {
244 for (j = 0; j < TILE_SIZE; j++) {
245 tile->data.colori128[i][j][0] = clear_value->i[0];
246 tile->data.colori128[i][j][1] = clear_value->i[1];
247 tile->data.colori128[i][j][2] = clear_value->i[2];
248 tile->data.colori128[i][j][3] = clear_value->i[3];
249 }
250 }
251 } else {
252 for (i = 0; i < TILE_SIZE; i++) {
253 for (j = 0; j < TILE_SIZE; j++) {
254 tile->data.color[i][j][0] = clear_value->f[0];
255 tile->data.color[i][j][1] = clear_value->f[1];
256 tile->data.color[i][j][2] = clear_value->f[2];
257 tile->data.color[i][j][3] = clear_value->f[3];
258 }
259 }
260 }
261 }
262 }
263
264
265 /**
266 * Set a tile to a solid value/color.
267 */
268 static void
269 clear_tile(struct softpipe_cached_tile *tile,
270 enum pipe_format format,
271 uint clear_value)
272 {
273 uint i, j;
274
275 switch (util_format_get_blocksize(format)) {
276 case 1:
277 memset(tile->data.any, clear_value, TILE_SIZE * TILE_SIZE);
278 break;
279 case 2:
280 if (clear_value == 0) {
281 memset(tile->data.any, 0, 2 * TILE_SIZE * TILE_SIZE);
282 }
283 else {
284 for (i = 0; i < TILE_SIZE; i++) {
285 for (j = 0; j < TILE_SIZE; j++) {
286 tile->data.depth16[i][j] = (ushort) clear_value;
287 }
288 }
289 }
290 break;
291 case 4:
292 if (clear_value == 0) {
293 memset(tile->data.any, 0, 4 * TILE_SIZE * TILE_SIZE);
294 }
295 else {
296 for (i = 0; i < TILE_SIZE; i++) {
297 for (j = 0; j < TILE_SIZE; j++) {
298 tile->data.color32[i][j] = clear_value;
299 }
300 }
301 }
302 break;
303 default:
304 assert(0);
305 }
306 }
307
308
309 /**
310 * Actually clear the tiles which were flagged as being in a clear state.
311 */
312 static void
313 sp_tile_cache_flush_clear(struct softpipe_tile_cache *tc)
314 {
315 struct pipe_transfer *pt = tc->transfer;
316 const uint w = tc->transfer->box.width;
317 const uint h = tc->transfer->box.height;
318 uint x, y;
319 uint numCleared = 0;
320
321 assert(pt->resource);
322 if (!tc->tile)
323 tc->tile = sp_alloc_tile(tc);
324
325 /* clear the scratch tile to the clear value */
326 if (tc->depth_stencil) {
327 clear_tile(tc->tile, pt->resource->format, tc->clear_val);
328 } else {
329 clear_tile_rgba(tc->tile, pt->resource->format, &tc->clear_color);
330 }
331
332 /* push the tile to all positions marked as clear */
333 for (y = 0; y < h; y += TILE_SIZE) {
334 for (x = 0; x < w; x += TILE_SIZE) {
335 union tile_address addr = tile_address(x, y);
336
337 if (is_clear_flag_set(tc->clear_flags, addr)) {
338 /* write the scratch tile to the surface */
339 if (tc->depth_stencil) {
340 pipe_put_tile_raw(tc->pipe,
341 pt,
342 x, y, TILE_SIZE, TILE_SIZE,
343 tc->tile->data.any, 0/*STRIDE*/);
344 }
345 else {
346 if (util_format_is_pure_uint(tc->surface->format)) {
347 pipe_put_tile_ui_format(tc->pipe, pt,
348 x, y, TILE_SIZE, TILE_SIZE,
349 pt->resource->format,
350 (unsigned *) tc->tile->data.colorui128);
351 } else if (util_format_is_pure_sint(tc->surface->format)) {
352 pipe_put_tile_i_format(tc->pipe, pt,
353 x, y, TILE_SIZE, TILE_SIZE,
354 pt->resource->format,
355 (int *) tc->tile->data.colori128);
356 } else {
357 pipe_put_tile_rgba(tc->pipe, pt,
358 x, y, TILE_SIZE, TILE_SIZE,
359 (float *) tc->tile->data.color);
360 }
361 }
362 numCleared++;
363 }
364 }
365 }
366
367 /* reset all clear flags to zero */
368 memset(tc->clear_flags, 0, sizeof(tc->clear_flags));
369
370 #if 0
371 debug_printf("num cleared: %u\n", numCleared);
372 #endif
373 }
374
375 static void
376 sp_flush_tile(struct softpipe_tile_cache* tc, unsigned pos)
377 {
378 if (!tc->tile_addrs[pos].bits.invalid) {
379 if (tc->depth_stencil) {
380 pipe_put_tile_raw(tc->pipe, tc->transfer,
381 tc->tile_addrs[pos].bits.x * TILE_SIZE,
382 tc->tile_addrs[pos].bits.y * TILE_SIZE,
383 TILE_SIZE, TILE_SIZE,
384 tc->entries[pos]->data.depth32, 0/*STRIDE*/);
385 }
386 else {
387 if (util_format_is_pure_uint(tc->surface->format)) {
388 pipe_put_tile_ui_format(tc->pipe, tc->transfer,
389 tc->tile_addrs[pos].bits.x * TILE_SIZE,
390 tc->tile_addrs[pos].bits.y * TILE_SIZE,
391 TILE_SIZE, TILE_SIZE,
392 tc->surface->format,
393 (unsigned *) tc->entries[pos]->data.colorui128);
394 } else if (util_format_is_pure_sint(tc->surface->format)) {
395 pipe_put_tile_i_format(tc->pipe, tc->transfer,
396 tc->tile_addrs[pos].bits.x * TILE_SIZE,
397 tc->tile_addrs[pos].bits.y * TILE_SIZE,
398 TILE_SIZE, TILE_SIZE,
399 tc->surface->format,
400 (int *) tc->entries[pos]->data.colori128);
401 } else {
402 pipe_put_tile_rgba_format(tc->pipe, tc->transfer,
403 tc->tile_addrs[pos].bits.x * TILE_SIZE,
404 tc->tile_addrs[pos].bits.y * TILE_SIZE,
405 TILE_SIZE, TILE_SIZE,
406 tc->surface->format,
407 (float *) tc->entries[pos]->data.color);
408 }
409 }
410 tc->tile_addrs[pos].bits.invalid = 1; /* mark as empty */
411 }
412 }
413
414 /**
415 * Flush the tile cache: write all dirty tiles back to the transfer.
416 * any tiles "flagged" as cleared will be "really" cleared.
417 */
418 void
419 sp_flush_tile_cache(struct softpipe_tile_cache *tc)
420 {
421 struct pipe_transfer *pt = tc->transfer;
422 int inuse = 0, pos;
423
424 if (pt) {
425 /* caching a drawing transfer */
426 for (pos = 0; pos < NUM_ENTRIES; pos++) {
427 struct softpipe_cached_tile *tile = tc->entries[pos];
428 if (!tile)
429 {
430 assert(tc->tile_addrs[pos].bits.invalid);
431 continue;
432 }
433
434 sp_flush_tile(tc, pos);
435 ++inuse;
436 }
437
438 sp_tile_cache_flush_clear(tc);
439
440
441 tc->last_tile_addr.bits.invalid = 1;
442 }
443
444 #if 0
445 debug_printf("flushed tiles in use: %d\n", inuse);
446 #endif
447 }
448
449 static struct softpipe_cached_tile *
450 sp_alloc_tile(struct softpipe_tile_cache *tc)
451 {
452 struct softpipe_cached_tile * tile = MALLOC_STRUCT(softpipe_cached_tile);
453 if (!tile)
454 {
455 /* in this case, steal an existing tile */
456 if (!tc->tile)
457 {
458 unsigned pos;
459 for (pos = 0; pos < NUM_ENTRIES; ++pos) {
460 if (!tc->entries[pos])
461 continue;
462
463 sp_flush_tile(tc, pos);
464 tc->tile = tc->entries[pos];
465 tc->entries[pos] = NULL;
466 break;
467 }
468
469 /* this should never happen */
470 if (!tc->tile)
471 abort();
472 }
473
474 tile = tc->tile;
475 tc->tile = NULL;
476
477 tc->last_tile_addr.bits.invalid = 1;
478 }
479 return tile;
480 }
481
482 /**
483 * Get a tile from the cache.
484 * \param x, y position of tile, in pixels
485 */
486 struct softpipe_cached_tile *
487 sp_find_cached_tile(struct softpipe_tile_cache *tc,
488 union tile_address addr )
489 {
490 struct pipe_transfer *pt = tc->transfer;
491 /* cache pos/entry: */
492 const int pos = CACHE_POS(addr.bits.x,
493 addr.bits.y);
494 struct softpipe_cached_tile *tile = tc->entries[pos];
495
496 if (!tile) {
497 tile = sp_alloc_tile(tc);
498 tc->entries[pos] = tile;
499 }
500
501 if (addr.value != tc->tile_addrs[pos].value) {
502
503 assert(pt->resource);
504 if (tc->tile_addrs[pos].bits.invalid == 0) {
505 /* put dirty tile back in framebuffer */
506 if (tc->depth_stencil) {
507 pipe_put_tile_raw(tc->pipe, pt,
508 tc->tile_addrs[pos].bits.x * TILE_SIZE,
509 tc->tile_addrs[pos].bits.y * TILE_SIZE,
510 TILE_SIZE, TILE_SIZE,
511 tile->data.depth32, 0/*STRIDE*/);
512 }
513 else {
514 if (util_format_is_pure_uint(tc->surface->format)) {
515 pipe_put_tile_ui_format(tc->pipe, pt,
516 tc->tile_addrs[pos].bits.x * TILE_SIZE,
517 tc->tile_addrs[pos].bits.y * TILE_SIZE,
518 TILE_SIZE, TILE_SIZE,
519 tc->surface->format,
520 (unsigned *) tile->data.colorui128);
521 } else if (util_format_is_pure_sint(tc->surface->format)) {
522 pipe_put_tile_i_format(tc->pipe, pt,
523 tc->tile_addrs[pos].bits.x * TILE_SIZE,
524 tc->tile_addrs[pos].bits.y * TILE_SIZE,
525 TILE_SIZE, TILE_SIZE,
526 tc->surface->format,
527 (int *) tile->data.colori128);
528 } else {
529 pipe_put_tile_rgba_format(tc->pipe, pt,
530 tc->tile_addrs[pos].bits.x * TILE_SIZE,
531 tc->tile_addrs[pos].bits.y * TILE_SIZE,
532 TILE_SIZE, TILE_SIZE,
533 tc->surface->format,
534 (float *) tile->data.color);
535 }
536 }
537 }
538
539 tc->tile_addrs[pos] = addr;
540
541 if (is_clear_flag_set(tc->clear_flags, addr)) {
542 /* don't get tile from framebuffer, just clear it */
543 if (tc->depth_stencil) {
544 clear_tile(tile, pt->resource->format, tc->clear_val);
545 }
546 else {
547 clear_tile_rgba(tile, pt->resource->format, &tc->clear_color);
548 }
549 clear_clear_flag(tc->clear_flags, addr);
550 }
551 else {
552 /* get new tile data from transfer */
553 if (tc->depth_stencil) {
554 pipe_get_tile_raw(tc->pipe, pt,
555 tc->tile_addrs[pos].bits.x * TILE_SIZE,
556 tc->tile_addrs[pos].bits.y * TILE_SIZE,
557 TILE_SIZE, TILE_SIZE,
558 tile->data.depth32, 0/*STRIDE*/);
559 }
560 else {
561 if (util_format_is_pure_uint(tc->surface->format)) {
562 pipe_get_tile_ui_format(tc->pipe, pt,
563 tc->tile_addrs[pos].bits.x * TILE_SIZE,
564 tc->tile_addrs[pos].bits.y * TILE_SIZE,
565 TILE_SIZE, TILE_SIZE,
566 tc->surface->format,
567 (unsigned *) tile->data.colorui128);
568 } else if (util_format_is_pure_sint(tc->surface->format)) {
569 pipe_get_tile_i_format(tc->pipe, pt,
570 tc->tile_addrs[pos].bits.x * TILE_SIZE,
571 tc->tile_addrs[pos].bits.y * TILE_SIZE,
572 TILE_SIZE, TILE_SIZE,
573 tc->surface->format,
574 (int *) tile->data.colori128);
575 } else {
576 pipe_get_tile_rgba_format(tc->pipe, pt,
577 tc->tile_addrs[pos].bits.x * TILE_SIZE,
578 tc->tile_addrs[pos].bits.y * TILE_SIZE,
579 TILE_SIZE, TILE_SIZE,
580 tc->surface->format,
581 (float *) tile->data.color);
582 }
583 }
584 }
585 }
586
587 tc->last_tile = tile;
588 tc->last_tile_addr = addr;
589 return tile;
590 }
591
592
593
594
595
596 /**
597 * When a whole surface is being cleared to a value we can avoid
598 * fetching tiles above.
599 * Save the color and set a 'clearflag' for each tile of the screen.
600 */
601 void
602 sp_tile_cache_clear(struct softpipe_tile_cache *tc,
603 const union pipe_color_union *color,
604 uint clearValue)
605 {
606 uint pos;
607
608 tc->clear_color = *color;
609
610 tc->clear_val = clearValue;
611
612 /* set flags to indicate all the tiles are cleared */
613 memset(tc->clear_flags, 255, sizeof(tc->clear_flags));
614
615 for (pos = 0; pos < NUM_ENTRIES; pos++) {
616 tc->tile_addrs[pos].bits.invalid = 1;
617 }
618 tc->last_tile_addr.bits.invalid = 1;
619 }