src/gallium/drivers/softpipe/sp_tile_cache.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /**
  29  * Render target tile caching.
  30  *
  31  * Author:
  32  *    Brian Paul
  33  */
  34
  35 #include "pipe/p_inlines.h"
  36 #include "util/u_memory.h"
  37 #include "util/u_tile.h"
  38 #include "sp_tile_cache.h"
  39
  40
  41
  42 /**
  43  * Return the position in the cache for the tile that contains win pos (x,y).
  44  * We currently use a direct mapped cache so this is like a hack key.
  45  * At some point we should investige something more sophisticated, like
  46  * a LRU replacement policy.
  47  */
  48 #define CACHE_POS(x, y) \
  49    (((x) + (y) * 5) % NUM_ENTRIES)
  50
  51
  52
  53 /**
  54  * Is the tile at (x,y) in cleared state?
  55  */
  56 static INLINE uint
  57 is_clear_flag_set(const uint *bitvec, union tile_address addr)
  58 {
  59    int pos, bit;
  60    pos = addr.bits.y * (MAX_WIDTH / TILE_SIZE) + addr.bits.x;
  61    assert(pos / 32 < (MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32);
  62    bit = bitvec[pos / 32] & (1 << (pos & 31));
  63    return bit;
  64 }
  65
  66
  67 /**
  68  * Mark the tile at (x,y) as not cleared.
  69  */
  70 static INLINE void
  71 clear_clear_flag(uint *bitvec, union tile_address addr)
  72 {
  73    int pos;
  74    pos = addr.bits.y * (MAX_WIDTH / TILE_SIZE) + addr.bits.x;
  75    assert(pos / 32 < (MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32);
  76    bitvec[pos / 32] &= ~(1 << (pos & 31));
  77 }
  78
  79
  80 struct softpipe_tile_cache *
  81 sp_create_tile_cache( struct pipe_screen *screen )
  82 {
  83    struct softpipe_tile_cache *tc;
  84    uint pos;
  85    int maxLevels, maxTexSize;
  86
  87    /* sanity checking: max sure MAX_WIDTH/HEIGHT >= largest texture image */
  88    maxLevels = screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS);
  89    maxTexSize = 1 << (maxLevels - 1);
  90    assert(MAX_WIDTH >= maxTexSize);
  91
  92    tc = CALLOC_STRUCT( softpipe_tile_cache );
  93    if (tc) {
  94       tc->screen = screen;
  95       for (pos = 0; pos < NUM_ENTRIES; pos++) {
  96          tc->entries[pos].addr.bits.invalid = 1;
  97       }
  98       tc->last_tile = &tc->entries[0]; /* any tile */
  99
 100 #if TILE_CLEAR_OPTIMIZATION
 101       /* set flags to indicate all the tiles are cleared */
 102       memset(tc->clear_flags, 255, sizeof(tc->clear_flags));
 103 #endif
 104    }
 105    return tc;
 106 }
 107
 108
 109 void
 110 sp_destroy_tile_cache(struct softpipe_tile_cache *tc)
 111 {
 112    struct pipe_screen *screen;
 113    uint pos;
 114
 115    for (pos = 0; pos < NUM_ENTRIES; pos++) {
 116       /*assert(tc->entries[pos].x < 0);*/
 117    }
 118    if (tc->transfer) {
 119       screen = tc->transfer->texture->screen;
 120       screen->tex_transfer_destroy(tc->transfer);
 121    }
 122
 123    FREE( tc );
 124 }
 125
 126
 127 /**
 128  * Specify the surface to cache.
 129  */
 130 void
 131 sp_tile_cache_set_surface(struct softpipe_tile_cache *tc,
 132                           struct pipe_surface *ps)
 133 {
 134    if (tc->transfer) {
 135       struct pipe_screen *screen = tc->transfer->texture->screen;
 136
 137       if (ps == tc->surface)
 138          return;
 139
 140       if (tc->transfer_map) {
 141          screen->transfer_unmap(screen, tc->transfer);
 142          tc->transfer_map = NULL;
 143       }
 144
 145       screen->tex_transfer_destroy(tc->transfer);
 146       tc->transfer = NULL;
 147    }
 148
 149    tc->surface = ps;
 150
 151    if (ps) {
 152       struct pipe_screen *screen = ps->texture->screen;
 153
 154       tc->transfer = screen->get_tex_transfer(screen, ps->texture, ps->face,
 155                                               ps->level, ps->zslice,
 156                                               PIPE_TRANSFER_READ_WRITE,
 157                                               0, 0, ps->width, ps->height);
 158
 159       tc->depth_stencil = (ps->format == PIPE_FORMAT_S8Z24_UNORM ||
 160                            ps->format == PIPE_FORMAT_X8Z24_UNORM ||
 161                            ps->format == PIPE_FORMAT_Z24S8_UNORM ||
 162                            ps->format == PIPE_FORMAT_Z24X8_UNORM ||
 163                            ps->format == PIPE_FORMAT_Z16_UNORM ||
 164                            ps->format == PIPE_FORMAT_Z32_UNORM ||
 165                            ps->format == PIPE_FORMAT_S8_UNORM);
 166    }
 167 }
 168
 169
 170 /**
 171  * Return the transfer being cached.
 172  */
 173 struct pipe_surface *
 174 sp_tile_cache_get_surface(struct softpipe_tile_cache *tc)
 175 {
 176    return tc->surface;
 177 }
 178
 179
 180 void
 181 sp_tile_cache_map_transfers(struct softpipe_tile_cache *tc)
 182 {
 183    if (tc->transfer && !tc->transfer_map)
 184       tc->transfer_map = tc->screen->transfer_map(tc->screen, tc->transfer);
 185 }
 186
 187
 188 void
 189 sp_tile_cache_unmap_transfers(struct softpipe_tile_cache *tc)
 190 {
 191    if (tc->transfer_map) {
 192       tc->screen->transfer_unmap(tc->screen, tc->transfer);
 193       tc->transfer_map = NULL;
 194    }
 195 }
 196
 197
 198 /**
 199  * Set pixels in a tile to the given clear color/value, float.
 200  */
 201 static void
 202 clear_tile_rgba(struct softpipe_cached_tile *tile,
 203                 enum pipe_format format,
 204                 const float clear_value[4])
 205 {
 206    if (clear_value[0] == 0.0 &&
 207        clear_value[1] == 0.0 &&
 208        clear_value[2] == 0.0 &&
 209        clear_value[3] == 0.0) {
 210       memset(tile->data.color, 0, sizeof(tile->data.color));
 211    }
 212    else {
 213       uint i, j;
 214       for (i = 0; i < TILE_SIZE; i++) {
 215          for (j = 0; j < TILE_SIZE; j++) {
 216             tile->data.color[i][j][0] = clear_value[0];
 217             tile->data.color[i][j][1] = clear_value[1];
 218             tile->data.color[i][j][2] = clear_value[2];
 219             tile->data.color[i][j][3] = clear_value[3];
 220          }
 221       }
 222    }
 223 }
 224
 225
 226 /**
 227  * Set a tile to a solid value/color.
 228  */
 229 static void
 230 clear_tile(struct softpipe_cached_tile *tile,
 231            enum pipe_format format,
 232            uint clear_value)
 233 {
 234    uint i, j;
 235
 236    switch (pf_get_size(format)) {
 237    case 1:
 238       memset(tile->data.any, clear_value, TILE_SIZE * TILE_SIZE);
 239       break;
 240    case 2:
 241       if (clear_value == 0) {
 242          memset(tile->data.any, 0, 2 * TILE_SIZE * TILE_SIZE);
 243       }
 244       else {
 245          for (i = 0; i < TILE_SIZE; i++) {
 246             for (j = 0; j < TILE_SIZE; j++) {
 247                tile->data.depth16[i][j] = (ushort) clear_value;
 248             }
 249          }
 250       }
 251       break;
 252    case 4:
 253       if (clear_value == 0) {
 254          memset(tile->data.any, 0, 4 * TILE_SIZE * TILE_SIZE);
 255       }
 256       else {
 257          for (i = 0; i < TILE_SIZE; i++) {
 258             for (j = 0; j < TILE_SIZE; j++) {
 259                tile->data.color32[i][j] = clear_value;
 260             }
 261          }
 262       }
 263       break;
 264    default:
 265       assert(0);
 266    }
 267 }
 268
 269
 270 /**
 271  * Actually clear the tiles which were flagged as being in a clear state.
 272  */
 273 static void
 274 sp_tile_cache_flush_clear(struct softpipe_tile_cache *tc)
 275 {
 276    struct pipe_transfer *pt = tc->transfer;
 277    const uint w = tc->transfer->width;
 278    const uint h = tc->transfer->height;
 279    uint x, y;
 280    uint numCleared = 0;
 281
 282    /* clear the scratch tile to the clear value */
 283    clear_tile(&tc->tile, pt->format, tc->clear_val);
 284
 285    /* push the tile to all positions marked as clear */
 286    for (y = 0; y < h; y += TILE_SIZE) {
 287       for (x = 0; x < w; x += TILE_SIZE) {
 288          union tile_address addr = tile_address(x, y);
 289
 290          if (is_clear_flag_set(tc->clear_flags, addr)) {
 291             pipe_put_tile_raw(pt,
 292                               x, y, TILE_SIZE, TILE_SIZE,
 293                               tc->tile.data.color32, 0/*STRIDE*/);
 294
 295             /* do this? */
 296             clear_clear_flag(tc->clear_flags, addr);
 297
 298             numCleared++;
 299          }
 300       }
 301    }
 302 #if 0
 303    debug_printf("num cleared: %u\n", numCleared);
 304 #endif
 305 }
 306
 307
 308 /**
 309  * Flush the tile cache: write all dirty tiles back to the transfer.
 310  * any tiles "flagged" as cleared will be "really" cleared.
 311  */
 312 void
 313 sp_flush_tile_cache(struct softpipe_tile_cache *tc)
 314 {
 315    struct pipe_transfer *pt = tc->transfer;
 316    int inuse = 0, pos;
 317
 318    if (pt) {
 319       /* caching a drawing transfer */
 320       for (pos = 0; pos < NUM_ENTRIES; pos++) {
 321          struct softpipe_cached_tile *tile = tc->entries + pos;
 322          if (!tile->addr.bits.invalid) {
 323             if (tc->depth_stencil) {
 324                pipe_put_tile_raw(pt,
 325                                  tile->addr.bits.x * TILE_SIZE,
 326                                  tile->addr.bits.y * TILE_SIZE,
 327                                  TILE_SIZE, TILE_SIZE,
 328                                  tile->data.depth32, 0/*STRIDE*/);
 329             }
 330             else {
 331                pipe_put_tile_rgba(pt,
 332                                   tile->addr.bits.x * TILE_SIZE,
 333                                   tile->addr.bits.y * TILE_SIZE,
 334                                   TILE_SIZE, TILE_SIZE,
 335                                   (float *) tile->data.color);
 336             }
 337             tile->addr.bits.invalid = 1;  /* mark as empty */
 338             inuse++;
 339          }
 340       }
 341
 342 #if TILE_CLEAR_OPTIMIZATION
 343       sp_tile_cache_flush_clear(tc);
 344 #endif
 345    }
 346
 347 #if 0
 348    debug_printf("flushed tiles in use: %d\n", inuse);
 349 #endif
 350 }
 351
 352
 353 /**
 354  * Get a tile from the cache.
 355  * \param x, y  position of tile, in pixels
 356  */
 357 struct softpipe_cached_tile *
 358 sp_find_cached_tile(struct softpipe_tile_cache *tc,
 359                     union tile_address addr )
 360 {
 361    struct pipe_transfer *pt = tc->transfer;
 362
 363    /* cache pos/entry: */
 364    const int pos = CACHE_POS(addr.bits.x,
 365                              addr.bits.y);
 366    struct softpipe_cached_tile *tile = tc->entries + pos;
 367
 368    if (addr.value != tile->addr.value) {
 369
 370       if (tile->addr.bits.invalid == 0) {
 371          /* put dirty tile back in framebuffer */
 372          if (tc->depth_stencil) {
 373             pipe_put_tile_raw(pt,
 374                               tile->addr.bits.x * TILE_SIZE,
 375                               tile->addr.bits.y * TILE_SIZE,
 376                               TILE_SIZE, TILE_SIZE,
 377                               tile->data.depth32, 0/*STRIDE*/);
 378          }
 379          else {
 380             pipe_put_tile_rgba(pt,
 381                                tile->addr.bits.x * TILE_SIZE,
 382                                tile->addr.bits.y * TILE_SIZE,
 383                                TILE_SIZE, TILE_SIZE,
 384                                (float *) tile->data.color);
 385          }
 386       }
 387
 388       tile->addr = addr;
 389
 390       if (is_clear_flag_set(tc->clear_flags, addr)) {
 391          /* don't get tile from framebuffer, just clear it */
 392          if (tc->depth_stencil) {
 393             clear_tile(tile, pt->format, tc->clear_val);
 394          }
 395          else {
 396             clear_tile_rgba(tile, pt->format, tc->clear_color);
 397          }
 398          clear_clear_flag(tc->clear_flags, addr);
 399       }
 400       else {
 401          /* get new tile data from transfer */
 402          if (tc->depth_stencil) {
 403             pipe_get_tile_raw(pt,
 404                               tile->addr.bits.x * TILE_SIZE,
 405                               tile->addr.bits.y * TILE_SIZE,
 406                               TILE_SIZE, TILE_SIZE,
 407                               tile->data.depth32, 0/*STRIDE*/);
 408          }
 409          else {
 410             pipe_get_tile_rgba(pt,
 411                                tile->addr.bits.x * TILE_SIZE,
 412                                tile->addr.bits.y * TILE_SIZE,
 413                                TILE_SIZE, TILE_SIZE,
 414                                (float *) tile->data.color);
 415          }
 416       }
 417    }
 418
 419    tc->last_tile = tile;
 420    return tile;
 421 }
 422
 423
 424
 425
 426
 427 /**
 428  * When a whole surface is being cleared to a value we can avoid
 429  * fetching tiles above.
 430  * Save the color and set a 'clearflag' for each tile of the screen.
 431  */
 432 void
 433 sp_tile_cache_clear(struct softpipe_tile_cache *tc, const float *rgba,
 434                     uint clearValue)
 435 {
 436    uint pos;
 437
 438    tc->clear_color[0] = rgba[0];
 439    tc->clear_color[1] = rgba[1];
 440    tc->clear_color[2] = rgba[2];
 441    tc->clear_color[3] = rgba[3];
 442
 443    tc->clear_val = clearValue;
 444
 445 #if TILE_CLEAR_OPTIMIZATION
 446    /* set flags to indicate all the tiles are cleared */
 447    memset(tc->clear_flags, 255, sizeof(tc->clear_flags));
 448 #else
 449    /* disable the optimization */
 450    memset(tc->clear_flags, 0, sizeof(tc->clear_flags));
 451 #endif
 452
 453    for (pos = 0; pos < NUM_ENTRIES; pos++) {
 454       struct softpipe_cached_tile *tile = tc->entries + pos;
 455       tile->addr.bits.invalid = 1;
 456    }
 457 }