src/gallium/drivers/softpipe/sp_tile_cache.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /**
  29  * Render target tile caching.
  30  *
  31  * Author:
  32  *    Brian Paul
  33  */
  34
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_memory.h"
  38 #include "util/u_tile.h"
  39 #include "sp_tile_cache.h"
  40
  41 static struct softpipe_cached_tile *
  42 sp_alloc_tile(struct softpipe_tile_cache *tc);
  43
  44
  45 /**
  46  * Return the position in the cache for the tile that contains win pos (x,y).
  47  * We currently use a direct mapped cache so this is like a hack key.
  48  * At some point we should investige something more sophisticated, like
  49  * a LRU replacement policy.
  50  */
  51 #define CACHE_POS(x, y) \
  52    (((x) + (y) * 5) % NUM_ENTRIES)
  53
  54
  55
  56 /**
  57  * Is the tile at (x,y) in cleared state?
  58  */
  59 static INLINE uint
  60 is_clear_flag_set(const uint *bitvec, union tile_address addr)
  61 {
  62    int pos, bit;
  63    pos = addr.bits.y * (MAX_WIDTH / TILE_SIZE) + addr.bits.x;
  64    assert(pos / 32 < (MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32);
  65    bit = bitvec[pos / 32] & (1 << (pos & 31));
  66    return bit;
  67 }
  68
  69
  70 /**
  71  * Mark the tile at (x,y) as not cleared.
  72  */
  73 static INLINE void
  74 clear_clear_flag(uint *bitvec, union tile_address addr)
  75 {
  76    int pos;
  77    pos = addr.bits.y * (MAX_WIDTH / TILE_SIZE) + addr.bits.x;
  78    assert(pos / 32 < (MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32);
  79    bitvec[pos / 32] &= ~(1 << (pos & 31));
  80 }
  81
  82
  83 struct softpipe_tile_cache *
  84 sp_create_tile_cache( struct pipe_context *pipe )
  85 {
  86    struct softpipe_tile_cache *tc;
  87    uint pos;
  88    int maxLevels, maxTexSize;
  89
  90    /* sanity checking: max sure MAX_WIDTH/HEIGHT >= largest texture image */
  91    maxLevels = pipe->screen->get_param(pipe->screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS);
  92    maxTexSize = 1 << (maxLevels - 1);
  93    assert(MAX_WIDTH >= maxTexSize);
  94
  95    assert(sizeof(union tile_address) == 4);
  96
  97    assert((TILE_SIZE << TILE_ADDR_BITS) >= MAX_WIDTH);
  98
  99    tc = CALLOC_STRUCT( softpipe_tile_cache );
 100    if (tc) {
 101       tc->pipe = pipe;
 102       for (pos = 0; pos < NUM_ENTRIES; pos++) {
 103          tc->tile_addrs[pos].bits.invalid = 1;
 104       }
 105       tc->last_tile_addr.bits.invalid = 1;
 106
 107       /* this allocation allows us to guarantee that allocation
 108        * failures are never fatal later
 109        */
 110       tc->tile = MALLOC_STRUCT( softpipe_cached_tile );
 111       if (!tc->tile)
 112       {
 113          FREE(tc);
 114          return NULL;
 115       }
 116
 117       /* XXX this code prevents valgrind warnings about use of uninitialized
 118        * memory in programs that don't clear the surface before rendering.
 119        * However, it breaks clearing in other situations (such as in
 120        * progs/tests/drawbuffers, see bug 24402).
 121        */
 122 #if 0
 123       /* set flags to indicate all the tiles are cleared */
 124       memset(tc->clear_flags, 255, sizeof(tc->clear_flags));
 125 #endif
 126    }
 127    return tc;
 128 }
 129
 130
 131 void
 132 sp_destroy_tile_cache(struct softpipe_tile_cache *tc)
 133 {
 134    if (tc) {
 135       uint pos;
 136
 137       for (pos = 0; pos < NUM_ENTRIES; pos++) {
 138          /*assert(tc->entries[pos].x < 0);*/
 139          FREE( tc->entries[pos] );
 140       }
 141       FREE( tc->tile );
 142
 143       if (tc->transfer) {
 144          tc->pipe->transfer_destroy(tc->pipe, tc->transfer);
 145       }
 146
 147       FREE( tc );
 148    }
 149 }
 150
 151
 152 /**
 153  * Specify the surface to cache.
 154  */
 155 void
 156 sp_tile_cache_set_surface(struct softpipe_tile_cache *tc,
 157                           struct pipe_surface *ps)
 158 {
 159    struct pipe_context *pipe = tc->pipe;
 160
 161    if (tc->transfer) {
 162       if (ps == tc->surface)
 163          return;
 164
 165       if (tc->transfer_map) {
 166          pipe->transfer_unmap(pipe, tc->transfer);
 167          tc->transfer_map = NULL;
 168       }
 169
 170       pipe->transfer_destroy(pipe, tc->transfer);
 171       tc->transfer = NULL;
 172    }
 173
 174    tc->surface = ps;
 175
 176    if (ps) {
 177       tc->transfer = pipe_get_transfer(pipe, ps->texture,
 178                                        ps->u.tex.level, ps->u.tex.first_layer,
 179                                        PIPE_TRANSFER_READ_WRITE |
 180                                        PIPE_TRANSFER_UNSYNCHRONIZED,
 181                                        0, 0, ps->width, ps->height);
 182
 183       tc->depth_stencil = util_format_is_depth_or_stencil(ps->format);
 184    }
 185 }
 186
 187
 188 /**
 189  * Return the transfer being cached.
 190  */
 191 struct pipe_surface *
 192 sp_tile_cache_get_surface(struct softpipe_tile_cache *tc)
 193 {
 194    return tc->surface;
 195 }
 196
 197
 198 void
 199 sp_tile_cache_map_transfers(struct softpipe_tile_cache *tc)
 200 {
 201    if (tc->transfer && !tc->transfer_map)
 202       tc->transfer_map = tc->pipe->transfer_map(tc->pipe, tc->transfer);
 203 }
 204
 205
 206 void
 207 sp_tile_cache_unmap_transfers(struct softpipe_tile_cache *tc)
 208 {
 209    if (tc->transfer_map) {
 210       tc->pipe->transfer_unmap(tc->pipe, tc->transfer);
 211       tc->transfer_map = NULL;
 212    }
 213 }
 214
 215
 216 /**
 217  * Set pixels in a tile to the given clear color/value, float.
 218  */
 219 static void
 220 clear_tile_rgba(struct softpipe_cached_tile *tile,
 221                 enum pipe_format format,
 222                 const float clear_value[4])
 223 {
 224    if (clear_value[0] == 0.0 &&
 225        clear_value[1] == 0.0 &&
 226        clear_value[2] == 0.0 &&
 227        clear_value[3] == 0.0) {
 228       memset(tile->data.color, 0, sizeof(tile->data.color));
 229    }
 230    else {
 231       uint i, j;
 232       for (i = 0; i < TILE_SIZE; i++) {
 233          for (j = 0; j < TILE_SIZE; j++) {
 234             tile->data.color[i][j][0] = clear_value[0];
 235             tile->data.color[i][j][1] = clear_value[1];
 236             tile->data.color[i][j][2] = clear_value[2];
 237             tile->data.color[i][j][3] = clear_value[3];
 238          }
 239       }
 240    }
 241 }
 242
 243
 244 /**
 245  * Set a tile to a solid value/color.
 246  */
 247 static void
 248 clear_tile(struct softpipe_cached_tile *tile,
 249            enum pipe_format format,
 250            uint clear_value)
 251 {
 252    uint i, j;
 253
 254    switch (util_format_get_blocksize(format)) {
 255    case 1:
 256       memset(tile->data.any, clear_value, TILE_SIZE * TILE_SIZE);
 257       break;
 258    case 2:
 259       if (clear_value == 0) {
 260          memset(tile->data.any, 0, 2 * TILE_SIZE * TILE_SIZE);
 261       }
 262       else {
 263          for (i = 0; i < TILE_SIZE; i++) {
 264             for (j = 0; j < TILE_SIZE; j++) {
 265                tile->data.depth16[i][j] = (ushort) clear_value;
 266             }
 267          }
 268       }
 269       break;
 270    case 4:
 271       if (clear_value == 0) {
 272          memset(tile->data.any, 0, 4 * TILE_SIZE * TILE_SIZE);
 273       }
 274       else {
 275          for (i = 0; i < TILE_SIZE; i++) {
 276             for (j = 0; j < TILE_SIZE; j++) {
 277                tile->data.color32[i][j] = clear_value;
 278             }
 279          }
 280       }
 281       break;
 282    default:
 283       assert(0);
 284    }
 285 }
 286
 287
 288 /**
 289  * Actually clear the tiles which were flagged as being in a clear state.
 290  */
 291 static void
 292 sp_tile_cache_flush_clear(struct softpipe_tile_cache *tc)
 293 {
 294    struct pipe_transfer *pt = tc->transfer;
 295    const uint w = tc->transfer->box.width;
 296    const uint h = tc->transfer->box.height;
 297    uint x, y;
 298    uint numCleared = 0;
 299
 300    assert(pt->resource);
 301    if (!tc->tile)
 302       tc->tile = sp_alloc_tile(tc);
 303
 304    /* clear the scratch tile to the clear value */
 305    if (tc->depth_stencil) {
 306       clear_tile(tc->tile, pt->resource->format, tc->clear_val);
 307    } else {
 308       clear_tile_rgba(tc->tile, pt->resource->format, tc->clear_color);
 309    }
 310
 311    /* push the tile to all positions marked as clear */
 312    for (y = 0; y < h; y += TILE_SIZE) {
 313       for (x = 0; x < w; x += TILE_SIZE) {
 314          union tile_address addr = tile_address(x, y);
 315
 316          if (is_clear_flag_set(tc->clear_flags, addr)) {
 317             /* write the scratch tile to the surface */
 318             if (tc->depth_stencil) {
 319                pipe_put_tile_raw(tc->pipe,
 320                                  pt,
 321                                  x, y, TILE_SIZE, TILE_SIZE,
 322                                  tc->tile->data.any, 0/*STRIDE*/);
 323             }
 324             else {
 325                pipe_put_tile_rgba(tc->pipe, pt,
 326                                   x, y, TILE_SIZE, TILE_SIZE,
 327                                   (float *) tc->tile->data.color);
 328             }
 329             numCleared++;
 330          }
 331       }
 332    }
 333
 334    /* reset all clear flags to zero */
 335    memset(tc->clear_flags, 0, sizeof(tc->clear_flags));
 336
 337 #if 0
 338    debug_printf("num cleared: %u\n", numCleared);
 339 #endif
 340 }
 341
 342 static void
 343 sp_flush_tile(struct softpipe_tile_cache* tc, unsigned pos)
 344 {
 345    if (!tc->tile_addrs[pos].bits.invalid) {
 346       if (tc->depth_stencil) {
 347          pipe_put_tile_raw(tc->pipe, tc->transfer,
 348                            tc->tile_addrs[pos].bits.x * TILE_SIZE,
 349                            tc->tile_addrs[pos].bits.y * TILE_SIZE,
 350                            TILE_SIZE, TILE_SIZE,
 351                            tc->entries[pos]->data.depth32, 0/*STRIDE*/);
 352       }
 353       else {
 354          pipe_put_tile_rgba_format(tc->pipe, tc->transfer,
 355                                    tc->tile_addrs[pos].bits.x * TILE_SIZE,
 356                                    tc->tile_addrs[pos].bits.y * TILE_SIZE,
 357                                    TILE_SIZE, TILE_SIZE,
 358                                    tc->surface->format,
 359                                    (float *) tc->entries[pos]->data.color);
 360       }
 361       tc->tile_addrs[pos].bits.invalid = 1;  /* mark as empty */
 362    }
 363 }
 364
 365 /**
 366  * Flush the tile cache: write all dirty tiles back to the transfer.
 367  * any tiles "flagged" as cleared will be "really" cleared.
 368  */
 369 void
 370 sp_flush_tile_cache(struct softpipe_tile_cache *tc)
 371 {
 372    struct pipe_transfer *pt = tc->transfer;
 373    int inuse = 0, pos;
 374
 375    if (pt) {
 376       /* caching a drawing transfer */
 377       for (pos = 0; pos < NUM_ENTRIES; pos++) {
 378          struct softpipe_cached_tile *tile = tc->entries[pos];
 379          if (!tile)
 380          {
 381             assert(tc->tile_addrs[pos].bits.invalid);
 382             continue;
 383          }
 384
 385          sp_flush_tile(tc, pos);
 386          ++inuse;
 387       }
 388
 389       sp_tile_cache_flush_clear(tc);
 390
 391
 392       tc->last_tile_addr.bits.invalid = 1;
 393    }
 394
 395 #if 0
 396    debug_printf("flushed tiles in use: %d\n", inuse);
 397 #endif
 398 }
 399
 400 static struct softpipe_cached_tile *
 401 sp_alloc_tile(struct softpipe_tile_cache *tc)
 402 {
 403    struct softpipe_cached_tile * tile = MALLOC_STRUCT(softpipe_cached_tile);
 404    if (!tile)
 405    {
 406       /* in this case, steal an existing tile */
 407       if (!tc->tile)
 408       {
 409          unsigned pos;
 410          for (pos = 0; pos < NUM_ENTRIES; ++pos) {
 411             if (!tc->entries[pos])
 412                continue;
 413
 414             sp_flush_tile(tc, pos);
 415             tc->tile = tc->entries[pos];
 416             tc->entries[pos] = NULL;
 417             break;
 418          }
 419
 420          /* this should never happen */
 421          if (!tc->tile)
 422             abort();
 423       }
 424
 425       tile = tc->tile;
 426       tc->tile = NULL;
 427
 428       tc->last_tile_addr.bits.invalid = 1;
 429    }
 430    return tile;
 431 }
 432
 433 /**
 434  * Get a tile from the cache.
 435  * \param x, y  position of tile, in pixels
 436  */
 437 struct softpipe_cached_tile *
 438 sp_find_cached_tile(struct softpipe_tile_cache *tc,
 439                     union tile_address addr )
 440 {
 441    struct pipe_transfer *pt = tc->transfer;
 442
 443    /* cache pos/entry: */
 444    const int pos = CACHE_POS(addr.bits.x,
 445                              addr.bits.y);
 446    struct softpipe_cached_tile *tile = tc->entries[pos];
 447
 448    if (!tile) {
 449       tile = sp_alloc_tile(tc);
 450       tc->entries[pos] = tile;
 451    }
 452
 453    if (addr.value != tc->tile_addrs[pos].value) {
 454
 455       assert(pt->resource);
 456       if (tc->tile_addrs[pos].bits.invalid == 0) {
 457          /* put dirty tile back in framebuffer */
 458          if (tc->depth_stencil) {
 459             pipe_put_tile_raw(tc->pipe, pt,
 460                               tc->tile_addrs[pos].bits.x * TILE_SIZE,
 461                               tc->tile_addrs[pos].bits.y * TILE_SIZE,
 462                               TILE_SIZE, TILE_SIZE,
 463                               tile->data.depth32, 0/*STRIDE*/);
 464          }
 465          else {
 466             pipe_put_tile_rgba_format(tc->pipe, pt,
 467                                       tc->tile_addrs[pos].bits.x * TILE_SIZE,
 468                                       tc->tile_addrs[pos].bits.y * TILE_SIZE,
 469                                       TILE_SIZE, TILE_SIZE,
 470                                       tc->surface->format,
 471                                       (float *) tile->data.color);
 472          }
 473       }
 474
 475       tc->tile_addrs[pos] = addr;
 476
 477       if (is_clear_flag_set(tc->clear_flags, addr)) {
 478          /* don't get tile from framebuffer, just clear it */
 479          if (tc->depth_stencil) {
 480             clear_tile(tile, pt->resource->format, tc->clear_val);
 481          }
 482          else {
 483             clear_tile_rgba(tile, pt->resource->format, tc->clear_color);
 484          }
 485          clear_clear_flag(tc->clear_flags, addr);
 486       }
 487       else {
 488          /* get new tile data from transfer */
 489          if (tc->depth_stencil) {
 490             pipe_get_tile_raw(tc->pipe, pt,
 491                               tc->tile_addrs[pos].bits.x * TILE_SIZE,
 492                               tc->tile_addrs[pos].bits.y * TILE_SIZE,
 493                               TILE_SIZE, TILE_SIZE,
 494                               tile->data.depth32, 0/*STRIDE*/);
 495          }
 496          else {
 497             pipe_get_tile_rgba_format(tc->pipe, pt,
 498                                       tc->tile_addrs[pos].bits.x * TILE_SIZE,
 499                                       tc->tile_addrs[pos].bits.y * TILE_SIZE,
 500                                       TILE_SIZE, TILE_SIZE,
 501                                       tc->surface->format,
 502                                       (float *) tile->data.color);
 503          }
 504       }
 505    }
 506
 507    tc->last_tile = tile;
 508    tc->last_tile_addr = addr;
 509    return tile;
 510 }
 511
 512
 513
 514
 515
 516 /**
 517  * When a whole surface is being cleared to a value we can avoid
 518  * fetching tiles above.
 519  * Save the color and set a 'clearflag' for each tile of the screen.
 520  */
 521 void
 522 sp_tile_cache_clear(struct softpipe_tile_cache *tc, const float *rgba,
 523                     uint clearValue)
 524 {
 525    uint pos;
 526
 527    tc->clear_color[0] = rgba[0];
 528    tc->clear_color[1] = rgba[1];
 529    tc->clear_color[2] = rgba[2];
 530    tc->clear_color[3] = rgba[3];
 531
 532    tc->clear_val = clearValue;
 533
 534    /* set flags to indicate all the tiles are cleared */
 535    memset(tc->clear_flags, 255, sizeof(tc->clear_flags));
 536
 537    for (pos = 0; pos < NUM_ENTRIES; pos++) {
 538       tc->tile_addrs[pos].bits.invalid = 1;
 539    }
 540    tc->last_tile_addr.bits.invalid = 1;
 541 }