1 /**********************************************************
2 * Copyright 2007-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
27 * svga3d_shaderdefs.h --
29 * SVGA3D byte code format and limit definitions.
31 * The format of the byte code directly corresponds to that defined
32 * by Microsoft DirectX SDK 9.0c (file d3d9types.h). The format can
33 * also be extended so that different shader formats can be supported
34 * for example GLSL, ARB vp/fp, NV/ATI shader formats, etc.
38 #ifndef __SVGA3D_SHADER_DEFS__
39 #define __SVGA3D_SHADER_DEFS__
41 /* SVGA3D shader hardware limits. */
43 #define SVGA3D_INPUTREG_MAX 16
44 #define SVGA3D_OUTPUTREG_MAX 12
45 #define SVGA3D_VERTEX_SAMPLERREG_MAX 4
46 #define SVGA3D_PIXEL_SAMPLERREG_MAX 16
47 #define SVGA3D_SAMPLERREG_MAX (SVGA3D_PIXEL_SAMPLERREG_MAX+\
48 SVGA3D_VERTEX_SAMPLERREG_MAX)
49 #define SVGA3D_TEMPREG_MAX 32
50 #define SVGA3D_CONSTREG_MAX 256
51 #define SVGA3D_CONSTINTREG_MAX 16
52 #define SVGA3D_CONSTBOOLREG_MAX 16
53 #define SVGA3D_ADDRREG_MAX 1
54 #define SVGA3D_PREDREG_MAX 1
56 /* SVGA3D byte code specific limits */
58 #define SVGA3D_MAX_SRC_REGS 4
59 #define SVGA3D_MAX_NESTING_LEVEL 32
61 /* SVGA3D version information. */
63 #define SVGA3D_VS_TYPE 0xFFFE
64 #define SVGA3D_PS_TYPE 0xFFFF
76 } SVGA3dShaderVersion
;
78 #define SVGA3D_VS_10 ((SVGA3D_VS_TYPE << 16) | 1 << 8)
79 #define SVGA3D_VS_11 (SVGA3D_VS_10 | 1)
80 #define SVGA3D_VS_20 ((SVGA3D_VS_TYPE << 16) | 2 << 8)
81 #define SVGA3D_VS_30 ((SVGA3D_VS_TYPE << 16) | 3 << 8)
83 #define SVGA3D_PS_10 ((SVGA3D_PS_TYPE << 16) | 1 << 8)
84 #define SVGA3D_PS_11 (SVGA3D_PS_10 | 1)
85 #define SVGA3D_PS_12 (SVGA3D_PS_10 | 2)
86 #define SVGA3D_PS_13 (SVGA3D_PS_10 | 3)
87 #define SVGA3D_PS_14 (SVGA3D_PS_10 | 4)
88 #define SVGA3D_PS_20 ((SVGA3D_PS_TYPE << 16) | 2 << 8)
89 #define SVGA3D_PS_30 ((SVGA3D_PS_TYPE << 16) | 3 << 8)
91 /* The *_ENABLED are for backwards compatibility with old drivers */
93 SVGA3DPSVERSION_NONE
= 0,
94 SVGA3DPSVERSION_ENABLED
= 1,
95 SVGA3DPSVERSION_11
= 3,
96 SVGA3DPSVERSION_12
= 5,
97 SVGA3DPSVERSION_13
= 7,
98 SVGA3DPSVERSION_14
= 9,
99 SVGA3DPSVERSION_20
= 11,
100 SVGA3DPSVERSION_30
= 13,
101 SVGA3DPSVERSION_40
= 15,
103 } SVGA3dPixelShaderVersion
;
106 SVGA3DVSVERSION_NONE
= 0,
107 SVGA3DVSVERSION_ENABLED
= 1,
108 SVGA3DVSVERSION_11
= 3,
109 SVGA3DVSVERSION_20
= 5,
110 SVGA3DVSVERSION_30
= 7,
111 SVGA3DVSVERSION_40
= 9,
113 } SVGA3dVertexShaderVersion
;
115 /* SVGA3D instruction op codes. */
167 SVGA3DOP_TEXCOORD
= 64,
173 SVGA3DOP_TEXREG2GB
= 70,
179 SVGA3DOP_TEXM3x3SPEC
,
180 SVGA3DOP_TEXM3x3VSPEC
,
187 SVGA3DOP_TEXM3x2DEPTH
,
193 SVGA3DOP_DP2ADD
= 90,
199 SVGA3DOP_BREAKP
= 96,
201 SVGA3DOP_PHASE
= 0xFFFD,
202 SVGA3DOP_COMMENT
= 0xFFFE,
203 SVGA3DOP_END
= 0xFFFF,
204 } SVGA3dShaderOpCodeType
;
206 /* SVGA3D operation control/comparison function types */
210 SVGA3DOPCONT_PROJECT
, /* Projective texturing */
211 SVGA3DOPCONT_BIAS
, /* Texturing with a LOD bias */
212 } SVGA3dShaderOpCodeControlFnType
;
215 SVGA3DOPCOMP_RESERVED0
= 0,
222 SVGA3DOPCOMP_RESERVED1
223 } SVGA3dShaderOpCodeCompFnType
;
225 /* SVGA3D register types */
228 SVGA3DREG_TEMP
= 0, /* Temporary register file */
229 SVGA3DREG_INPUT
, /* Input register file */
230 SVGA3DREG_CONST
, /* Constant register file */
231 SVGA3DREG_ADDR
, /* Address register for VS */
232 SVGA3DREG_TEXTURE
= 3, /* Texture register file for PS */
233 SVGA3DREG_RASTOUT
, /* Rasterizer register file */
234 SVGA3DREG_ATTROUT
, /* Attribute output register file */
235 SVGA3DREG_TEXCRDOUT
, /* Texture coordinate output register file */
236 SVGA3DREG_OUTPUT
= 6, /* Output register file for VS 3.0+ */
237 SVGA3DREG_CONSTINT
, /* Constant integer vector register file */
238 SVGA3DREG_COLOROUT
, /* Color output register file */
239 SVGA3DREG_DEPTHOUT
, /* Depth output register file */
240 SVGA3DREG_SAMPLER
, /* Sampler state register file */
241 SVGA3DREG_CONST2
, /* Constant register file 2048 - 4095 */
242 SVGA3DREG_CONST3
, /* Constant register file 4096 - 6143 */
243 SVGA3DREG_CONST4
, /* Constant register file 6144 - 8191 */
244 SVGA3DREG_CONSTBOOL
, /* Constant boolean register file */
245 SVGA3DREG_LOOP
, /* Loop counter register file */
246 SVGA3DREG_TEMPFLOAT16
, /* 16-bit float temp register file */
247 SVGA3DREG_MISCTYPE
, /* Miscellaneous (single) registers */
248 SVGA3DREG_LABEL
, /* Label */
249 SVGA3DREG_PREDICATE
, /* Predicate register */
250 } SVGA3dShaderRegType
;
252 /* SVGA3D rasterizer output register types */
255 SVGA3DRASTOUT_POSITION
= 0,
258 } SVGA3dShaderRastOutRegType
;
260 /* SVGA3D miscellaneous register types */
263 SVGA3DMISCREG_POSITION
= 0, /* Input position x,y,z,rhw (PS) */
264 SVGA3DMISCREG_FACE
/* Floating point primitive area (PS) */
265 } SVGA3DShaderMiscRegType
;
267 /* SVGA3D sampler types */
270 SVGA3DSAMP_UNKNOWN
= 0, /* Uninitialized value */
271 SVGA3DSAMP_2D
= 2, /* dcl_2d s# (for declaring a 2-D texture) */
272 SVGA3DSAMP_CUBE
, /* dcl_cube s# (for declaring a cube texture) */
273 SVGA3DSAMP_VOLUME
, /* dcl_volume s# (for declaring a volume texture) */
274 } SVGA3dShaderSamplerType
;
276 /* SVGA3D sampler format classes */
279 SVGA3DSAMPFORMAT_ARGB
, /* ARGB formats */
280 SVGA3DSAMPFORMAT_V8U8
, /* Sign and normalize (SNORM) V & U */
281 SVGA3DSAMPFORMAT_Q8W8V8U8
, /* SNORM all */
282 SVGA3DSAMPFORMAT_CxV8U8
, /* SNORM V & U, C=SQRT(1-U^2-V^2) */
283 SVGA3DSAMPFORMAT_X8L8V8U8
, /* SNORM V & U */
284 SVGA3DSAMPFORMAT_A2W10V10U10
, /* SNORM W, V & U */
285 SVGA3DSAMPFORMAT_DXT_PMA
, /* DXT pre-multiplied alpha */
286 SVGA3DSAMPFORMAT_YUV
, /* YUV video format */
287 SVGA3DSAMPFORMAT_UYVY
, /* UYVY video format */
288 SVGA3DSAMPFORMAT_Rx
, /* R16F/32F */
289 SVGA3DSAMPFORMAT_RxGx
, /* R16FG16F, R32FG32F */
290 SVGA3DSAMPFORMAT_V16U16
, /* SNORM all */
291 } SVGA3DShaderSamplerFormatClass
;
293 /* SVGA3D write mask */
295 #define SVGA3DWRITEMASK_0 1 /* Component 0 (X;Red) */
296 #define SVGA3DWRITEMASK_1 2 /* Component 1 (Y;Green) */
297 #define SVGA3DWRITEMASK_2 4 /* Component 2 (Z;Blue) */
298 #define SVGA3DWRITEMASK_3 8 /* Component 3 (W;Alpha) */
299 #define SVGA3DWRITEMASK_ALL 15 /* All components */
301 /* SVGA3D destination modifiers */
303 #define SVGA3DDSTMOD_NONE 0 /* nop */
304 #define SVGA3DDSTMOD_SATURATE 1 /* clamp to [0, 1] */
305 #define SVGA3DDSTMOD_PARTIALPRECISION 2 /* Partial precision hint */
308 * Relevant to multisampling only:
309 * When the pixel center is not covered, sample
310 * attribute or compute gradients/LOD
311 * using multisample "centroid" location.
312 * "Centroid" is some location within the covered
313 * region of the pixel.
316 #define SVGA3DDSTMOD_MSAMPCENTROID 4
318 /* SVGA3D source swizzle */
320 #define SVGA3DSWIZZLE_REPLICATEX 0x00
321 #define SVGA3DSWIZZLE_REPLICATEY 0x55
322 #define SVGA3DSWIZZLE_REPLICATEZ 0xAA
323 #define SVGA3DSWIZZLE_REPLICATEW 0xFF
324 #define SVGA3DSWIZZLE_NONE 0xE4
325 #define SVGA3DSWIZZLE_YZXW 0xC9
326 #define SVGA3DSWIZZLE_ZXYW 0xD2
327 #define SVGA3DSWIZZLE_WXYZ 0x1B
329 /* SVGA3D source modifiers */
332 SVGA3DSRCMOD_NONE
= 0, /* nop */
333 SVGA3DSRCMOD_NEG
, /* negate */
334 SVGA3DSRCMOD_BIAS
, /* bias */
335 SVGA3DSRCMOD_BIASNEG
, /* bias and negate */
336 SVGA3DSRCMOD_SIGN
, /* sign */
337 SVGA3DSRCMOD_SIGNNEG
, /* sign and negate */
338 SVGA3DSRCMOD_COMP
, /* complement */
339 SVGA3DSRCMOD_X2
, /* x2 */
340 SVGA3DSRCMOD_X2NEG
, /* x2 and negate */
341 SVGA3DSRCMOD_DZ
, /* divide through by z component */
342 SVGA3DSRCMOD_DW
, /* divide through by w component */
343 SVGA3DSRCMOD_ABS
, /* abs() */
344 SVGA3DSRCMOD_ABSNEG
, /* -abs() */
345 SVGA3DSRCMOD_NOT
, /* ! (for predicate register) */
346 } SVGA3dShaderSrcModType
;
348 /* SVGA3D instruction token */
353 uint32 comment_op
: 16;
354 uint32 comment_size
: 16;
360 uint32 reserved2
: 5;
362 uint32 predicated
: 1;
363 uint32 reserved1
: 1;
365 uint32 reserved0
: 1;
370 } SVGA3dShaderInstToken
;
372 /* SVGA3D destination parameter token */
378 uint32 type_upper
: 2;
380 uint32 reserved1
: 2;
384 uint32 type_lower
: 3;
385 uint32 reserved0
: 1;
390 } SVGA3dShaderDestToken
;
392 /* SVGA3D source parameter token */
398 uint32 type_upper
: 2;
400 uint32 reserved1
: 2;
403 uint32 type_lower
: 3;
404 uint32 reserved0
: 1;
409 } SVGA3dShaderSrcToken
;
411 /* SVGA3DOP_DCL parameter tokens */
419 uint32 reserved1
: 11;
421 uint32 reserved0
: 12;
422 }; /* input / output declaration */
425 uint32 reserved3
: 27;
427 uint32 reserved2
: 1;
428 }; /* sampler declaration */
431 SVGA3dShaderDestToken dst
;
438 /* SVGA3DOP_DEF parameter tokens */
443 SVGA3dShaderDestToken dst
;
446 float constValues
[4];
456 /* SVGA3D shader token */
460 SVGA3dShaderInstToken inst
;
461 SVGA3dShaderDestToken dest
;
462 SVGA3dShaderSrcToken src
;
465 /* SVGA3D shader program */
468 SVGA3dShaderVersion version
;
469 /* SVGA3dShaderToken stream */
470 } SVGA3dShaderProgram
;
472 /* SVGA3D version specific register assignments */
474 static const uint32 SVGA3D_INPUT_REG_POSITION_VS11
= 0;
475 static const uint32 SVGA3D_INPUT_REG_PSIZE_VS11
= 1;
476 static const uint32 SVGA3D_INPUT_REG_FOG_VS11
= 3;
477 static const uint32 SVGA3D_INPUT_REG_FOG_MASK_VS11
= SVGA3DWRITEMASK_3
;
478 static const uint32 SVGA3D_INPUT_REG_COLOR_BASE_VS11
= 2;
479 static const uint32 SVGA3D_INPUT_REG_TEXCOORD_BASE_VS11
= 4;
481 static const uint32 SVGA3D_INPUT_REG_COLOR_BASE_PS11
= 0;
482 static const uint32 SVGA3D_INPUT_REG_TEXCOORD_BASE_PS11
= 2;
483 static const uint32 SVGA3D_OUTPUT_REG_DEPTH_PS11
= 0;
484 static const uint32 SVGA3D_OUTPUT_REG_COLOR_PS11
= 1;
486 static const uint32 SVGA3D_INPUT_REG_COLOR_BASE_PS20
= 0;
487 static const uint32 SVGA3D_INPUT_REG_COLOR_NUM_PS20
= 2;
488 static const uint32 SVGA3D_INPUT_REG_TEXCOORD_BASE_PS20
= 2;
489 static const uint32 SVGA3D_INPUT_REG_TEXCOORD_NUM_PS20
= 8;
490 static const uint32 SVGA3D_OUTPUT_REG_COLOR_BASE_PS20
= 1;
491 static const uint32 SVGA3D_OUTPUT_REG_COLOR_NUM_PS20
= 4;
492 static const uint32 SVGA3D_OUTPUT_REG_DEPTH_BASE_PS20
= 0;
493 static const uint32 SVGA3D_OUTPUT_REG_DEPTH_NUM_PS20
= 1;
496 *----------------------------------------------------------------------
498 * SVGA3dShaderGetRegType --
500 * As the register type is split into two non sequential fields,
501 * this function provides an useful way of accessing the actual
502 * register type without having to manually concatenate the
503 * type_upper and type_lower fields.
506 * Returns the register type.
508 *----------------------------------------------------------------------
511 static INLINE SVGA3dShaderRegType
512 SVGA3dShaderGetRegType(uint32 token
)
514 SVGA3dShaderSrcToken src
;
516 return (SVGA3dShaderRegType
)(src
.type_upper
<< 3 | src
.type_lower
);
519 #endif /* __SVGA3D_SHADER_DEFS__ */