1 /**************************************************************************
3 * Copyright © 1998-2015 VMware, Inc., Palo Alto, CA., USA
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 * svga3d_surfacedefs.h --
31 * Surface/format/image helper code.
34 #include "svga3d_reg.h"
36 #define max_t(type, x, y) ((x) > (y) ? (x) : (y))
39 * enum svga3d_block_desc describes the active data channels in a block.
41 * There can be at-most four active channels in a block:
42 * 1. Red, bump W, luminance and depth are stored in the first channel.
43 * 2. Green, bump V and stencil are stored in the second channel.
44 * 3. Blue and bump U are stored in the third channel.
45 * 4. Alpha and bump Q are stored in the fourth channel.
47 * Block channels can be used to store compressed and buffer data:
48 * 1. For compressed formats, only the data channel is used and its size
49 * is equal to that of a singular block in the compression scheme.
50 * 2. For buffer formats, only the data channel is used and its size is
51 * exactly one byte in length.
52 * 3. In each case the bit depth represent the size of a singular block.
54 * Note: Compressed and IEEE formats do not use the bitMask structure.
57 enum svga3d_block_desc
{
59 SVGA3DBLOCKDESC_NONE
= 0, /* No channels are active */
60 SVGA3DBLOCKDESC_BLUE
= 1 << 0, /* Block with red channel data */
61 SVGA3DBLOCKDESC_U
= 1 << 0, /* Block with bump U channel data */
62 SVGA3DBLOCKDESC_GREEN
= 1 << 1, /* Block with green channel data */
63 SVGA3DBLOCKDESC_V
= 1 << 1, /* Block with bump V channel data */
64 SVGA3DBLOCKDESC_RED
= 1 << 2, /* Block with blue channel data */
65 SVGA3DBLOCKDESC_W
= 1 << 2, /* Block with bump W channel data */
66 SVGA3DBLOCKDESC_LUMINANCE
= 1 << 2, /* Block with luminance channel data */
67 SVGA3DBLOCKDESC_Y
= 1 << 2, /* Block with video luminance data */
68 SVGA3DBLOCKDESC_ALPHA
= 1 << 3, /* Block with an alpha channel */
69 SVGA3DBLOCKDESC_Q
= 1 << 3, /* Block with bump Q channel data */
70 SVGA3DBLOCKDESC_BUFFER
= 1 << 4, /* Block stores 1 byte of data */
71 SVGA3DBLOCKDESC_COMPRESSED
= 1 << 5, /* Block stores n bytes of data depending
72 on the compression method used */
73 SVGA3DBLOCKDESC_IEEE_FP
= 1 << 6, /* Block stores data in an IEEE floating point
74 representation in all channels */
75 SVGA3DBLOCKDESC_UV_VIDEO
= 1 << 7, /* Block with alternating video U and V */
76 SVGA3DBLOCKDESC_PLANAR_YUV
= 1 << 8, /* Three separate blocks store data. */
77 SVGA3DBLOCKDESC_U_VIDEO
= 1 << 9, /* Block with U video data */
78 SVGA3DBLOCKDESC_V_VIDEO
= 1 << 10, /* Block with V video data */
79 SVGA3DBLOCKDESC_EXP
= 1 << 11, /* Shared exponent */
80 SVGA3DBLOCKDESC_SRGB
= 1 << 12, /* Data is in sRGB format */
81 SVGA3DBLOCKDESC_2PLANAR_YUV
= 1 << 13, /* 2 planes of Y, UV, e.g., NV12. */
82 SVGA3DBLOCKDESC_3PLANAR_YUV
= 1 << 14, /* 3 planes of separate Y, U, V, e.g., YV12. */
83 SVGA3DBLOCKDESC_DEPTH
= 1 << 15, /* Block with depth channel */
84 SVGA3DBLOCKDESC_STENCIL
= 1 << 16, /* Block with a stencil channel */
86 SVGA3DBLOCKDESC_RG
= SVGA3DBLOCKDESC_RED
|
87 SVGA3DBLOCKDESC_GREEN
,
88 SVGA3DBLOCKDESC_RGB
= SVGA3DBLOCKDESC_RG
|
90 SVGA3DBLOCKDESC_RGB_SRGB
= SVGA3DBLOCKDESC_RGB
|
92 SVGA3DBLOCKDESC_RGBA
= SVGA3DBLOCKDESC_RGB
|
93 SVGA3DBLOCKDESC_ALPHA
,
94 SVGA3DBLOCKDESC_RGBA_SRGB
= SVGA3DBLOCKDESC_RGBA
|
96 SVGA3DBLOCKDESC_UV
= SVGA3DBLOCKDESC_U
|
98 SVGA3DBLOCKDESC_UVL
= SVGA3DBLOCKDESC_UV
|
99 SVGA3DBLOCKDESC_LUMINANCE
,
100 SVGA3DBLOCKDESC_UVW
= SVGA3DBLOCKDESC_UV
|
102 SVGA3DBLOCKDESC_UVWA
= SVGA3DBLOCKDESC_UVW
|
103 SVGA3DBLOCKDESC_ALPHA
,
104 SVGA3DBLOCKDESC_UVWQ
= SVGA3DBLOCKDESC_U
|
108 SVGA3DBLOCKDESC_LA
= SVGA3DBLOCKDESC_LUMINANCE
|
109 SVGA3DBLOCKDESC_ALPHA
,
110 SVGA3DBLOCKDESC_R_FP
= SVGA3DBLOCKDESC_RED
|
111 SVGA3DBLOCKDESC_IEEE_FP
,
112 SVGA3DBLOCKDESC_RG_FP
= SVGA3DBLOCKDESC_R_FP
|
113 SVGA3DBLOCKDESC_GREEN
,
114 SVGA3DBLOCKDESC_RGB_FP
= SVGA3DBLOCKDESC_RG_FP
|
115 SVGA3DBLOCKDESC_BLUE
,
116 SVGA3DBLOCKDESC_RGBA_FP
= SVGA3DBLOCKDESC_RGB_FP
|
117 SVGA3DBLOCKDESC_ALPHA
,
118 SVGA3DBLOCKDESC_DS
= SVGA3DBLOCKDESC_DEPTH
|
119 SVGA3DBLOCKDESC_STENCIL
,
120 SVGA3DBLOCKDESC_YUV
= SVGA3DBLOCKDESC_UV_VIDEO
|
122 SVGA3DBLOCKDESC_AYUV
= SVGA3DBLOCKDESC_ALPHA
|
124 SVGA3DBLOCKDESC_U_VIDEO
|
125 SVGA3DBLOCKDESC_V_VIDEO
,
126 SVGA3DBLOCKDESC_RGBE
= SVGA3DBLOCKDESC_RGB
|
128 SVGA3DBLOCKDESC_COMPRESSED_SRGB
= SVGA3DBLOCKDESC_COMPRESSED
|
129 SVGA3DBLOCKDESC_SRGB
,
130 SVGA3DBLOCKDESC_NV12
= SVGA3DBLOCKDESC_PLANAR_YUV
|
131 SVGA3DBLOCKDESC_2PLANAR_YUV
,
132 SVGA3DBLOCKDESC_YV12
= SVGA3DBLOCKDESC_PLANAR_YUV
|
133 SVGA3DBLOCKDESC_3PLANAR_YUV
,
137 typedef struct SVGA3dChannelDef
{
165 struct svga3d_surface_desc
{
166 SVGA3dSurfaceFormat format
;
167 enum svga3d_block_desc block_desc
;
169 SVGA3dSize block_size
;
170 uint32 bytes_per_block
;
171 uint32 pitch_bytes_per_block
;
173 uint32 totalBitDepth
;
174 SVGA3dChannelDef bitDepth
;
175 SVGA3dChannelDef bitOffset
;
178 static const struct svga3d_surface_desc svga3d_surface_descs
[] = {
179 {SVGA3D_FORMAT_INVALID
, SVGA3DBLOCKDESC_NONE
,
181 0, {{0}, {0}, {0}, {0}},
182 {{0}, {0}, {0}, {0}}},
184 {SVGA3D_X8R8G8B8
, SVGA3DBLOCKDESC_RGB
,
186 24, {{8}, {8}, {8}, {0}},
187 {{0}, {8}, {16}, {24}}},
189 {SVGA3D_A8R8G8B8
, SVGA3DBLOCKDESC_RGBA
,
191 32, {{8}, {8}, {8}, {8}},
192 {{0}, {8}, {16}, {24}}},
194 {SVGA3D_R5G6B5
, SVGA3DBLOCKDESC_RGB
,
196 16, {{5}, {6}, {5}, {0}},
197 {{0}, {5}, {11}, {0}}},
199 {SVGA3D_X1R5G5B5
, SVGA3DBLOCKDESC_RGB
,
201 15, {{5}, {5}, {5}, {0}},
202 {{0}, {5}, {10}, {0}}},
204 {SVGA3D_A1R5G5B5
, SVGA3DBLOCKDESC_RGBA
,
206 16, {{5}, {5}, {5}, {1}},
207 {{0}, {5}, {10}, {15}}},
209 {SVGA3D_A4R4G4B4
, SVGA3DBLOCKDESC_RGBA
,
211 16, {{4}, {4}, {4}, {4}},
212 {{0}, {4}, {8}, {12}}},
214 {SVGA3D_Z_D32
, SVGA3DBLOCKDESC_DEPTH
,
216 32, {{0}, {0}, {32}, {0}},
217 {{0}, {0}, {0}, {0}}},
219 {SVGA3D_Z_D16
, SVGA3DBLOCKDESC_DEPTH
,
221 16, {{0}, {0}, {16}, {0}},
222 {{0}, {0}, {0}, {0}}},
224 {SVGA3D_Z_D24S8
, SVGA3DBLOCKDESC_DS
,
226 32, {{0}, {8}, {24}, {0}},
227 {{0}, {24}, {0}, {0}}},
229 {SVGA3D_Z_D15S1
, SVGA3DBLOCKDESC_DS
,
231 16, {{0}, {1}, {15}, {0}},
232 {{0}, {15}, {0}, {0}}},
234 {SVGA3D_LUMINANCE8
, SVGA3DBLOCKDESC_LUMINANCE
,
236 8, {{0}, {0}, {8}, {0}},
237 {{0}, {0}, {0}, {0}}},
239 {SVGA3D_LUMINANCE4_ALPHA4
, SVGA3DBLOCKDESC_LA
,
241 8, {{0}, {0}, {4}, {4}},
242 {{0}, {0}, {0}, {4}}},
244 {SVGA3D_LUMINANCE16
, SVGA3DBLOCKDESC_LUMINANCE
,
246 16, {{0}, {0}, {16}, {0}},
247 {{0}, {0}, {0}, {0}}},
249 {SVGA3D_LUMINANCE8_ALPHA8
, SVGA3DBLOCKDESC_LA
,
251 16, {{0}, {0}, {8}, {8}},
252 {{0}, {0}, {0}, {8}}},
254 {SVGA3D_DXT1
, SVGA3DBLOCKDESC_COMPRESSED
,
256 64, {{0}, {0}, {64}, {0}},
257 {{0}, {0}, {0}, {0}}},
259 {SVGA3D_DXT2
, SVGA3DBLOCKDESC_COMPRESSED
,
261 128, {{0}, {0}, {128}, {0}},
262 {{0}, {0}, {0}, {0}}},
264 {SVGA3D_DXT3
, SVGA3DBLOCKDESC_COMPRESSED
,
266 128, {{0}, {0}, {128}, {0}},
267 {{0}, {0}, {0}, {0}}},
269 {SVGA3D_DXT4
, SVGA3DBLOCKDESC_COMPRESSED
,
271 128, {{0}, {0}, {128}, {0}},
272 {{0}, {0}, {0}, {0}}},
274 {SVGA3D_DXT5
, SVGA3DBLOCKDESC_COMPRESSED
,
276 128, {{0}, {0}, {128}, {0}},
277 {{0}, {0}, {0}, {0}}},
279 {SVGA3D_BUMPU8V8
, SVGA3DBLOCKDESC_UV
,
281 16, {{0}, {0}, {8}, {8}},
282 {{0}, {0}, {0}, {8}}},
284 {SVGA3D_BUMPL6V5U5
, SVGA3DBLOCKDESC_UVL
,
286 16, {{5}, {5}, {6}, {0}},
287 {{11}, {6}, {0}, {0}}},
289 {SVGA3D_BUMPX8L8V8U8
, SVGA3DBLOCKDESC_UVL
,
291 32, {{8}, {8}, {8}, {0}},
292 {{16}, {8}, {0}, {0}}},
294 {SVGA3D_FORMAT_DEAD1
, SVGA3DBLOCKDESC_UVL
,
296 0, {{0}, {0}, {0}, {0}},
297 {{0}, {0}, {0}, {0}}},
299 {SVGA3D_ARGB_S10E5
, SVGA3DBLOCKDESC_RGBA_FP
,
301 64, {{16}, {16}, {16}, {16}},
302 {{32}, {16}, {0}, {48}}},
304 {SVGA3D_ARGB_S23E8
, SVGA3DBLOCKDESC_RGBA_FP
,
306 128, {{32}, {32}, {32}, {32}},
307 {{64}, {32}, {0}, {96}}},
309 {SVGA3D_A2R10G10B10
, SVGA3DBLOCKDESC_RGBA
,
311 32, {{10}, {10}, {10}, {2}},
312 {{0}, {10}, {20}, {30}}},
314 {SVGA3D_V8U8
, SVGA3DBLOCKDESC_UV
,
316 16, {{8}, {8}, {0}, {0}},
317 {{8}, {0}, {0}, {0}}},
319 {SVGA3D_Q8W8V8U8
, SVGA3DBLOCKDESC_UVWQ
,
321 32, {{8}, {8}, {8}, {8}},
322 {{24}, {16}, {8}, {0}}},
324 {SVGA3D_CxV8U8
, SVGA3DBLOCKDESC_UV
,
326 16, {{8}, {8}, {0}, {0}},
327 {{8}, {0}, {0}, {0}}},
329 {SVGA3D_X8L8V8U8
, SVGA3DBLOCKDESC_UVL
,
331 24, {{8}, {8}, {8}, {0}},
332 {{16}, {8}, {0}, {0}}},
334 {SVGA3D_A2W10V10U10
, SVGA3DBLOCKDESC_UVWA
,
336 32, {{10}, {10}, {10}, {2}},
337 {{0}, {10}, {20}, {30}}},
339 {SVGA3D_ALPHA8
, SVGA3DBLOCKDESC_ALPHA
,
341 8, {{0}, {0}, {0}, {8}},
342 {{0}, {0}, {0}, {0}}},
344 {SVGA3D_R_S10E5
, SVGA3DBLOCKDESC_R_FP
,
346 16, {{0}, {0}, {16}, {0}},
347 {{0}, {0}, {0}, {0}}},
349 {SVGA3D_R_S23E8
, SVGA3DBLOCKDESC_R_FP
,
351 32, {{0}, {0}, {32}, {0}},
352 {{0}, {0}, {0}, {0}}},
354 {SVGA3D_RG_S10E5
, SVGA3DBLOCKDESC_RG_FP
,
356 32, {{0}, {16}, {16}, {0}},
357 {{0}, {16}, {0}, {0}}},
359 {SVGA3D_RG_S23E8
, SVGA3DBLOCKDESC_RG_FP
,
361 64, {{0}, {32}, {32}, {0}},
362 {{0}, {32}, {0}, {0}}},
364 {SVGA3D_BUFFER
, SVGA3DBLOCKDESC_BUFFER
,
366 8, {{0}, {0}, {8}, {0}},
367 {{0}, {0}, {0}, {0}}},
369 {SVGA3D_Z_D24X8
, SVGA3DBLOCKDESC_DEPTH
,
371 32, {{0}, {0}, {24}, {0}},
372 {{0}, {24}, {0}, {0}}},
374 {SVGA3D_V16U16
, SVGA3DBLOCKDESC_UV
,
376 32, {{16}, {16}, {0}, {0}},
377 {{16}, {0}, {0}, {0}}},
379 {SVGA3D_G16R16
, SVGA3DBLOCKDESC_RG
,
381 32, {{0}, {16}, {16}, {0}},
382 {{0}, {0}, {16}, {0}}},
384 {SVGA3D_A16B16G16R16
, SVGA3DBLOCKDESC_RGBA
,
386 64, {{16}, {16}, {16}, {16}},
387 {{32}, {16}, {0}, {48}}},
389 {SVGA3D_UYVY
, SVGA3DBLOCKDESC_YUV
,
391 16, {{8}, {0}, {8}, {0}},
392 {{0}, {0}, {8}, {0}}},
394 {SVGA3D_YUY2
, SVGA3DBLOCKDESC_YUV
,
396 16, {{8}, {0}, {8}, {0}},
397 {{8}, {0}, {0}, {0}}},
399 {SVGA3D_NV12
, SVGA3DBLOCKDESC_NV12
,
401 48, {{0}, {0}, {48}, {0}},
402 {{0}, {0}, {0}, {0}}},
404 {SVGA3D_AYUV
, SVGA3DBLOCKDESC_AYUV
,
406 32, {{8}, {8}, {8}, {8}},
407 {{0}, {8}, {16}, {24}}},
409 {SVGA3D_R32G32B32A32_TYPELESS
, SVGA3DBLOCKDESC_RGBA
,
411 128, {{32}, {32}, {32}, {32}},
412 {{64}, {32}, {0}, {96}}},
414 {SVGA3D_R32G32B32A32_UINT
, SVGA3DBLOCKDESC_RGBA
,
416 128, {{32}, {32}, {32}, {32}},
417 {{64}, {32}, {0}, {96}}},
419 {SVGA3D_R32G32B32A32_SINT
, SVGA3DBLOCKDESC_UVWQ
,
421 128, {{32}, {32}, {32}, {32}},
422 {{64}, {32}, {0}, {96}}},
424 {SVGA3D_R32G32B32_TYPELESS
, SVGA3DBLOCKDESC_RGB
,
426 96, {{32}, {32}, {32}, {0}},
427 {{64}, {32}, {0}, {0}}},
429 {SVGA3D_R32G32B32_FLOAT
, SVGA3DBLOCKDESC_RGB_FP
,
431 96, {{32}, {32}, {32}, {0}},
432 {{64}, {32}, {0}, {0}}},
434 {SVGA3D_R32G32B32_UINT
, SVGA3DBLOCKDESC_RGB
,
436 96, {{32}, {32}, {32}, {0}},
437 {{64}, {32}, {0}, {0}}},
439 {SVGA3D_R32G32B32_SINT
, SVGA3DBLOCKDESC_UVW
,
441 96, {{32}, {32}, {32}, {0}},
442 {{64}, {32}, {0}, {0}}},
444 {SVGA3D_R16G16B16A16_TYPELESS
, SVGA3DBLOCKDESC_RGBA
,
446 64, {{16}, {16}, {16}, {16}},
447 {{32}, {16}, {0}, {48}}},
449 {SVGA3D_R16G16B16A16_UINT
, SVGA3DBLOCKDESC_RGBA
,
451 64, {{16}, {16}, {16}, {16}},
452 {{32}, {16}, {0}, {48}}},
454 {SVGA3D_R16G16B16A16_SNORM
, SVGA3DBLOCKDESC_UVWQ
,
456 64, {{16}, {16}, {16}, {16}},
457 {{32}, {16}, {0}, {48}}},
459 {SVGA3D_R16G16B16A16_SINT
, SVGA3DBLOCKDESC_UVWQ
,
461 64, {{16}, {16}, {16}, {16}},
462 {{32}, {16}, {0}, {48}}},
464 {SVGA3D_R32G32_TYPELESS
, SVGA3DBLOCKDESC_RG
,
466 64, {{0}, {32}, {32}, {0}},
467 {{0}, {32}, {0}, {0}}},
469 {SVGA3D_R32G32_UINT
, SVGA3DBLOCKDESC_RG
,
471 64, {{0}, {32}, {32}, {0}},
472 {{0}, {32}, {0}, {0}}},
474 {SVGA3D_R32G32_SINT
, SVGA3DBLOCKDESC_UV
,
476 64, {{0}, {32}, {32}, {0}},
477 {{0}, {32}, {0}, {0}}},
479 {SVGA3D_R32G8X24_TYPELESS
, SVGA3DBLOCKDESC_RG
,
481 64, {{0}, {8}, {32}, {0}},
482 {{0}, {32}, {0}, {0}}},
484 {SVGA3D_D32_FLOAT_S8X24_UINT
, SVGA3DBLOCKDESC_DS
,
486 64, {{0}, {8}, {32}, {0}},
487 {{0}, {32}, {0}, {0}}},
489 {SVGA3D_R32_FLOAT_X8X24
, SVGA3DBLOCKDESC_R_FP
,
491 64, {{0}, {0}, {32}, {0}},
492 {{0}, {0}, {0}, {0}}},
494 {SVGA3D_X32_G8X24_UINT
, SVGA3DBLOCKDESC_GREEN
,
496 64, {{0}, {8}, {0}, {0}},
497 {{0}, {32}, {0}, {0}}},
499 {SVGA3D_R10G10B10A2_TYPELESS
, SVGA3DBLOCKDESC_RGBA
,
501 32, {{10}, {10}, {10}, {2}},
502 {{0}, {10}, {20}, {30}}},
504 {SVGA3D_R10G10B10A2_UINT
, SVGA3DBLOCKDESC_RGBA
,
506 32, {{10}, {10}, {10}, {2}},
507 {{0}, {10}, {20}, {30}}},
509 {SVGA3D_R11G11B10_FLOAT
, SVGA3DBLOCKDESC_RGB_FP
,
511 32, {{10}, {11}, {11}, {0}},
512 {{0}, {10}, {21}, {0}}},
514 {SVGA3D_R8G8B8A8_TYPELESS
, SVGA3DBLOCKDESC_RGBA
,
516 32, {{8}, {8}, {8}, {8}},
517 {{16}, {8}, {0}, {24}}},
519 {SVGA3D_R8G8B8A8_UNORM
, SVGA3DBLOCKDESC_RGBA
,
521 32, {{8}, {8}, {8}, {8}},
522 {{16}, {8}, {0}, {24}}},
524 {SVGA3D_R8G8B8A8_UNORM_SRGB
, SVGA3DBLOCKDESC_RGBA_SRGB
,
526 32, {{8}, {8}, {8}, {8}},
527 {{16}, {8}, {0}, {24}}},
529 {SVGA3D_R8G8B8A8_UINT
, SVGA3DBLOCKDESC_RGBA
,
531 32, {{8}, {8}, {8}, {8}},
532 {{16}, {8}, {0}, {24}}},
534 {SVGA3D_R8G8B8A8_SINT
, SVGA3DBLOCKDESC_RGBA
,
536 32, {{8}, {8}, {8}, {8}},
537 {{16}, {8}, {0}, {24}}},
539 {SVGA3D_R16G16_TYPELESS
, SVGA3DBLOCKDESC_RG
,
541 32, {{0}, {16}, {16}, {0}},
542 {{0}, {16}, {0}, {0}}},
544 {SVGA3D_R16G16_UINT
, SVGA3DBLOCKDESC_RG_FP
,
546 32, {{0}, {16}, {16}, {0}},
547 {{0}, {16}, {0}, {0}}},
549 {SVGA3D_R16G16_SINT
, SVGA3DBLOCKDESC_UV
,
551 32, {{0}, {16}, {16}, {0}},
552 {{0}, {16}, {0}, {0}}},
554 {SVGA3D_R32_TYPELESS
, SVGA3DBLOCKDESC_RED
,
556 32, {{0}, {0}, {32}, {0}},
557 {{0}, {0}, {0}, {0}}},
559 {SVGA3D_D32_FLOAT
, SVGA3DBLOCKDESC_DEPTH
,
561 32, {{0}, {0}, {32}, {0}},
562 {{0}, {0}, {0}, {0}}},
564 {SVGA3D_R32_UINT
, SVGA3DBLOCKDESC_RED
,
566 32, {{0}, {0}, {32}, {0}},
567 {{0}, {0}, {0}, {0}}},
569 {SVGA3D_R32_SINT
, SVGA3DBLOCKDESC_RED
,
571 32, {{0}, {0}, {32}, {0}},
572 {{0}, {0}, {0}, {0}}},
574 {SVGA3D_R24G8_TYPELESS
, SVGA3DBLOCKDESC_RG
,
576 32, {{0}, {8}, {24}, {0}},
577 {{0}, {24}, {0}, {0}}},
579 {SVGA3D_D24_UNORM_S8_UINT
, SVGA3DBLOCKDESC_DS
,
581 32, {{0}, {8}, {24}, {0}},
582 {{0}, {24}, {0}, {0}}},
584 {SVGA3D_R24_UNORM_X8
, SVGA3DBLOCKDESC_RED
,
586 32, {{0}, {0}, {24}, {0}},
587 {{0}, {0}, {0}, {0}}},
589 {SVGA3D_X24_G8_UINT
, SVGA3DBLOCKDESC_GREEN
,
591 32, {{0}, {8}, {0}, {0}},
592 {{0}, {24}, {0}, {0}}},
594 {SVGA3D_R8G8_TYPELESS
, SVGA3DBLOCKDESC_RG
,
596 16, {{0}, {8}, {8}, {0}},
597 {{0}, {8}, {0}, {0}}},
599 {SVGA3D_R8G8_UNORM
, SVGA3DBLOCKDESC_RG
,
601 16, {{0}, {8}, {8}, {0}},
602 {{0}, {8}, {0}, {0}}},
604 {SVGA3D_R8G8_UINT
, SVGA3DBLOCKDESC_RG
,
606 16, {{0}, {8}, {8}, {0}},
607 {{0}, {8}, {0}, {0}}},
609 {SVGA3D_R8G8_SINT
, SVGA3DBLOCKDESC_UV
,
611 16, {{0}, {8}, {8}, {0}},
612 {{0}, {8}, {0}, {0}}},
614 {SVGA3D_R16_TYPELESS
, SVGA3DBLOCKDESC_RED
,
616 16, {{0}, {0}, {16}, {0}},
617 {{0}, {0}, {0}, {0}}},
619 {SVGA3D_R16_UNORM
, SVGA3DBLOCKDESC_RED
,
621 16, {{0}, {0}, {16}, {0}},
622 {{0}, {0}, {0}, {0}}},
624 {SVGA3D_R16_UINT
, SVGA3DBLOCKDESC_RED
,
626 16, {{0}, {0}, {16}, {0}},
627 {{0}, {0}, {0}, {0}}},
629 {SVGA3D_R16_SNORM
, SVGA3DBLOCKDESC_U
,
631 16, {{0}, {0}, {16}, {0}},
632 {{0}, {0}, {0}, {0}}},
634 {SVGA3D_R16_SINT
, SVGA3DBLOCKDESC_U
,
636 16, {{0}, {0}, {16}, {0}},
637 {{0}, {0}, {0}, {0}}},
639 {SVGA3D_R8_TYPELESS
, SVGA3DBLOCKDESC_RED
,
641 8, {{0}, {0}, {8}, {0}},
642 {{0}, {0}, {0}, {0}}},
644 {SVGA3D_R8_UNORM
, SVGA3DBLOCKDESC_RED
,
646 8, {{0}, {0}, {8}, {0}},
647 {{0}, {0}, {0}, {0}}},
649 {SVGA3D_R8_UINT
, SVGA3DBLOCKDESC_RED
,
651 8, {{0}, {0}, {8}, {0}},
652 {{0}, {0}, {0}, {0}}},
654 {SVGA3D_R8_SNORM
, SVGA3DBLOCKDESC_U
,
656 8, {{0}, {0}, {8}, {0}},
657 {{0}, {0}, {0}, {0}}},
659 {SVGA3D_R8_SINT
, SVGA3DBLOCKDESC_U
,
661 8, {{0}, {0}, {8}, {0}},
662 {{0}, {0}, {0}, {0}}},
664 {SVGA3D_P8
, SVGA3DBLOCKDESC_RED
,
666 8, {{0}, {0}, {8}, {0}},
667 {{0}, {0}, {0}, {0}}},
669 {SVGA3D_R9G9B9E5_SHAREDEXP
, SVGA3DBLOCKDESC_RGBE
,
671 32, {{9}, {9}, {9}, {5}},
672 {{18}, {9}, {0}, {27}}},
674 {SVGA3D_R8G8_B8G8_UNORM
, SVGA3DBLOCKDESC_RG
,
676 16, {{0}, {8}, {8}, {0}},
677 {{0}, {8}, {0}, {0}}},
679 {SVGA3D_G8R8_G8B8_UNORM
, SVGA3DBLOCKDESC_RG
,
681 16, {{0}, {8}, {8}, {0}},
682 {{0}, {8}, {0}, {0}}},
684 {SVGA3D_BC1_TYPELESS
, SVGA3DBLOCKDESC_COMPRESSED
,
686 64, {{0}, {0}, {64}, {0}},
687 {{0}, {0}, {0}, {0}}},
689 {SVGA3D_BC1_UNORM_SRGB
, SVGA3DBLOCKDESC_COMPRESSED_SRGB
,
691 64, {{0}, {0}, {64}, {0}},
692 {{0}, {0}, {0}, {0}}},
694 {SVGA3D_BC2_TYPELESS
, SVGA3DBLOCKDESC_COMPRESSED
,
696 128, {{0}, {0}, {128}, {0}},
697 {{0}, {0}, {0}, {0}}},
699 {SVGA3D_BC2_UNORM_SRGB
, SVGA3DBLOCKDESC_COMPRESSED_SRGB
,
701 128, {{0}, {0}, {128}, {0}},
702 {{0}, {0}, {0}, {0}}},
704 {SVGA3D_BC3_TYPELESS
, SVGA3DBLOCKDESC_COMPRESSED
,
706 128, {{0}, {0}, {128}, {0}},
707 {{0}, {0}, {0}, {0}}},
709 {SVGA3D_BC3_UNORM_SRGB
, SVGA3DBLOCKDESC_COMPRESSED_SRGB
,
711 128, {{0}, {0}, {128}, {0}},
712 {{0}, {0}, {0}, {0}}},
714 {SVGA3D_BC4_TYPELESS
, SVGA3DBLOCKDESC_COMPRESSED
,
716 64, {{0}, {0}, {64}, {0}},
717 {{0}, {0}, {0}, {0}}},
719 {SVGA3D_ATI1
, SVGA3DBLOCKDESC_COMPRESSED
,
721 64, {{0}, {0}, {64}, {0}},
722 {{0}, {0}, {0}, {0}}},
724 {SVGA3D_BC4_SNORM
, SVGA3DBLOCKDESC_COMPRESSED
,
726 64, {{0}, {0}, {64}, {0}},
727 {{0}, {0}, {0}, {0}}},
729 {SVGA3D_BC5_TYPELESS
, SVGA3DBLOCKDESC_COMPRESSED
,
731 128, {{0}, {0}, {128}, {0}},
732 {{0}, {0}, {0}, {0}}},
734 {SVGA3D_ATI2
, SVGA3DBLOCKDESC_COMPRESSED
,
736 128, {{0}, {0}, {128}, {0}},
737 {{0}, {0}, {0}, {0}}},
739 {SVGA3D_BC5_SNORM
, SVGA3DBLOCKDESC_COMPRESSED
,
741 128, {{0}, {0}, {128}, {0}},
742 {{0}, {0}, {0}, {0}}},
744 {SVGA3D_R10G10B10_XR_BIAS_A2_UNORM
, SVGA3DBLOCKDESC_RGBA
,
746 32, {{10}, {10}, {10}, {2}},
747 {{0}, {10}, {20}, {30}}},
749 {SVGA3D_B8G8R8A8_TYPELESS
, SVGA3DBLOCKDESC_RGBA
,
751 32, {{8}, {8}, {8}, {8}},
752 {{0}, {8}, {16}, {24}}},
754 {SVGA3D_B8G8R8A8_UNORM_SRGB
, SVGA3DBLOCKDESC_RGBA_SRGB
,
756 32, {{8}, {8}, {8}, {8}},
757 {{0}, {8}, {16}, {24}}},
759 {SVGA3D_B8G8R8X8_TYPELESS
, SVGA3DBLOCKDESC_RGB
,
761 24, {{8}, {8}, {8}, {0}},
762 {{0}, {8}, {16}, {24}}},
764 {SVGA3D_B8G8R8X8_UNORM_SRGB
, SVGA3DBLOCKDESC_RGB_SRGB
,
766 24, {{8}, {8}, {8}, {0}},
767 {{0}, {8}, {16}, {24}}},
769 {SVGA3D_Z_DF16
, SVGA3DBLOCKDESC_DEPTH
,
771 16, {{0}, {0}, {16}, {0}},
772 {{0}, {0}, {0}, {0}}},
774 {SVGA3D_Z_DF24
, SVGA3DBLOCKDESC_DEPTH
,
776 32, {{0}, {8}, {24}, {0}},
777 {{0}, {24}, {0}, {0}}},
779 {SVGA3D_Z_D24S8_INT
, SVGA3DBLOCKDESC_DS
,
781 32, {{0}, {8}, {24}, {0}},
782 {{0}, {24}, {0}, {0}}},
784 {SVGA3D_YV12
, SVGA3DBLOCKDESC_YV12
,
786 48, {{0}, {0}, {48}, {0}},
787 {{0}, {0}, {0}, {0}}},
789 {SVGA3D_R32G32B32A32_FLOAT
, SVGA3DBLOCKDESC_RGBA_FP
,
791 128, {{32}, {32}, {32}, {32}},
792 {{64}, {32}, {0}, {96}}},
794 {SVGA3D_R16G16B16A16_FLOAT
, SVGA3DBLOCKDESC_RGBA_FP
,
796 64, {{16}, {16}, {16}, {16}},
797 {{32}, {16}, {0}, {48}}},
799 {SVGA3D_R16G16B16A16_UNORM
, SVGA3DBLOCKDESC_RGBA
,
801 64, {{16}, {16}, {16}, {16}},
802 {{32}, {16}, {0}, {48}}},
804 {SVGA3D_R32G32_FLOAT
, SVGA3DBLOCKDESC_RG_FP
,
806 64, {{0}, {32}, {32}, {0}},
807 {{0}, {32}, {0}, {0}}},
809 {SVGA3D_R10G10B10A2_UNORM
, SVGA3DBLOCKDESC_RGBA
,
811 32, {{10}, {10}, {10}, {2}},
812 {{0}, {10}, {20}, {30}}},
814 {SVGA3D_R8G8B8A8_SNORM
, SVGA3DBLOCKDESC_RGBA
,
816 32, {{8}, {8}, {8}, {8}},
817 {{24}, {16}, {8}, {0}}},
819 {SVGA3D_R16G16_FLOAT
, SVGA3DBLOCKDESC_RG_FP
,
821 32, {{0}, {16}, {16}, {0}},
822 {{0}, {16}, {0}, {0}}},
824 {SVGA3D_R16G16_UNORM
, SVGA3DBLOCKDESC_RG
,
826 32, {{0}, {16}, {16}, {0}},
827 {{0}, {0}, {16}, {0}}},
829 {SVGA3D_R16G16_SNORM
, SVGA3DBLOCKDESC_RG
,
831 32, {{16}, {16}, {0}, {0}},
832 {{16}, {0}, {0}, {0}}},
834 {SVGA3D_R32_FLOAT
, SVGA3DBLOCKDESC_R_FP
,
836 32, {{0}, {0}, {32}, {0}},
837 {{0}, {0}, {0}, {0}}},
839 {SVGA3D_R8G8_SNORM
, SVGA3DBLOCKDESC_RG
,
841 16, {{8}, {8}, {0}, {0}},
842 {{8}, {0}, {0}, {0}}},
844 {SVGA3D_R16_FLOAT
, SVGA3DBLOCKDESC_R_FP
,
846 16, {{0}, {0}, {16}, {0}},
847 {{0}, {0}, {0}, {0}}},
849 {SVGA3D_D16_UNORM
, SVGA3DBLOCKDESC_DEPTH
,
851 16, {{0}, {0}, {16}, {0}},
852 {{0}, {0}, {0}, {0}}},
854 {SVGA3D_A8_UNORM
, SVGA3DBLOCKDESC_ALPHA
,
856 8, {{0}, {0}, {0}, {8}},
857 {{0}, {0}, {0}, {0}}},
859 {SVGA3D_BC1_UNORM
, SVGA3DBLOCKDESC_COMPRESSED
,
861 64, {{0}, {0}, {64}, {0}},
862 {{0}, {0}, {0}, {0}}},
864 {SVGA3D_BC2_UNORM
, SVGA3DBLOCKDESC_COMPRESSED
,
866 128, {{0}, {0}, {128}, {0}},
867 {{0}, {0}, {0}, {0}}},
869 {SVGA3D_BC3_UNORM
, SVGA3DBLOCKDESC_COMPRESSED
,
871 128, {{0}, {0}, {128}, {0}},
872 {{0}, {0}, {0}, {0}}},
874 {SVGA3D_B5G6R5_UNORM
, SVGA3DBLOCKDESC_RGB
,
876 16, {{5}, {6}, {5}, {0}},
877 {{0}, {5}, {11}, {0}}},
879 {SVGA3D_B5G5R5A1_UNORM
, SVGA3DBLOCKDESC_RGBA
,
881 16, {{5}, {5}, {5}, {1}},
882 {{0}, {5}, {10}, {15}}},
884 {SVGA3D_B8G8R8A8_UNORM
, SVGA3DBLOCKDESC_RGBA
,
886 32, {{8}, {8}, {8}, {8}},
887 {{0}, {8}, {16}, {24}}},
889 {SVGA3D_B8G8R8X8_UNORM
, SVGA3DBLOCKDESC_RGB
,
891 24, {{8}, {8}, {8}, {0}},
892 {{0}, {8}, {16}, {24}}},
894 {SVGA3D_BC4_UNORM
, SVGA3DBLOCKDESC_COMPRESSED
,
896 64, {{0}, {0}, {64}, {0}},
897 {{0}, {0}, {0}, {0}}},
899 {SVGA3D_BC5_UNORM
, SVGA3DBLOCKDESC_COMPRESSED
,
901 128, {{0}, {0}, {128}, {0}},
902 {{0}, {0}, {0}, {0}}},
906 extern const struct svga3d_surface_desc g_SVGA3dSurfaceDescs
[];
907 extern int g_SVGA3dSurfaceDescs_size
;
909 static inline uint32
clamped_umul32(uint32 a
, uint32 b
)
911 uint64_t tmp
= (uint64_t) a
*b
;
912 return (tmp
> (uint64_t) ((uint32
) -1)) ? (uint32
) -1 : tmp
;
915 static inline uint32
clamped_uadd32(uint32 a
, uint32 b
)
918 if (c
< a
|| c
< b
) {
925 static inline const struct svga3d_surface_desc
*
926 svga3dsurface_get_desc(SVGA3dSurfaceFormat format
)
928 if (format
< ARRAY_SIZE(svga3d_surface_descs
))
929 return &svga3d_surface_descs
[format
];
931 return &svga3d_surface_descs
[SVGA3D_FORMAT_INVALID
];
935 *----------------------------------------------------------------------
937 * svga3dsurface_get_mip_size --
939 * Given a base level size and the mip level, compute the size of
948 *----------------------------------------------------------------------
951 static inline SVGA3dSize
952 svga3dsurface_get_mip_size(SVGA3dSize base_level
, uint32 mip_level
)
956 size
.width
= max_t(uint32
, base_level
.width
>> mip_level
, 1);
957 size
.height
= max_t(uint32
, base_level
.height
>> mip_level
, 1);
958 size
.depth
= max_t(uint32
, base_level
.depth
>> mip_level
, 1);
963 svga3dsurface_get_size_in_blocks(const struct svga3d_surface_desc
*desc
,
964 const SVGA3dSize
*pixel_size
,
965 SVGA3dSize
*block_size
)
967 block_size
->width
= DIV_ROUND_UP(pixel_size
->width
,
968 desc
->block_size
.width
);
969 block_size
->height
= DIV_ROUND_UP(pixel_size
->height
,
970 desc
->block_size
.height
);
971 block_size
->depth
= DIV_ROUND_UP(pixel_size
->depth
,
972 desc
->block_size
.depth
);
976 svga3dsurface_is_planar_surface(const struct svga3d_surface_desc
*desc
)
978 return (desc
->block_desc
& SVGA3DBLOCKDESC_PLANAR_YUV
) != 0;
982 svga3dsurface_calculate_pitch(const struct svga3d_surface_desc
*desc
,
983 const SVGA3dSize
*size
)
988 svga3dsurface_get_size_in_blocks(desc
, size
, &blocks
);
990 pitch
= blocks
.width
* desc
->pitch_bytes_per_block
;
996 *-----------------------------------------------------------------------------
998 * svga3dsurface_get_image_buffer_size --
1000 * Return the number of bytes of buffer space required to store
1001 * one image of a surface, optionally using the specified pitch.
1003 * If pitch is zero, it is assumed that rows are tightly packed.
1005 * This function is overflow-safe. If the result would have
1006 * overflowed, instead we return MAX_UINT32.
1014 *-----------------------------------------------------------------------------
1017 static inline uint32
1018 svga3dsurface_get_image_buffer_size(const struct svga3d_surface_desc
*desc
,
1019 const SVGA3dSize
*size
,
1022 SVGA3dSize image_blocks
;
1023 uint32 slice_size
, total_size
;
1025 svga3dsurface_get_size_in_blocks(desc
, size
, &image_blocks
);
1027 if (svga3dsurface_is_planar_surface(desc
)) {
1028 total_size
= clamped_umul32(image_blocks
.width
,
1029 image_blocks
.height
);
1030 total_size
= clamped_umul32(total_size
, image_blocks
.depth
);
1031 total_size
= clamped_umul32(total_size
, desc
->bytes_per_block
);
1036 pitch
= svga3dsurface_calculate_pitch(desc
, size
);
1038 slice_size
= clamped_umul32(image_blocks
.height
, pitch
);
1039 total_size
= clamped_umul32(slice_size
, image_blocks
.depth
);
1045 static inline uint32
1046 svga3dsurface_get_image_offset(SVGA3dSurfaceFormat format
,
1047 SVGA3dSize baseLevelSize
,
1048 uint32 numMipLevels
,
1054 uint32 mipChainBytes
;
1055 uint32 mipChainBytesToLevel
;
1057 const struct svga3d_surface_desc
*desc
;
1061 desc
= svga3dsurface_get_desc(format
);
1064 mipChainBytesToLevel
= 0;
1065 for (i
= 0; i
< numMipLevels
; i
++) {
1066 mipSize
= svga3dsurface_get_mip_size(baseLevelSize
, i
);
1067 bytes
= svga3dsurface_get_image_buffer_size(desc
, &mipSize
, 0);
1068 mipChainBytes
+= bytes
;
1070 mipChainBytesToLevel
+= bytes
;
1074 offset
= mipChainBytes
* layer
+ mipChainBytesToLevel
;
1080 static inline uint32
1081 svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format
,
1082 SVGA3dSize base_level_size
,
1083 uint32 num_mip_levels
,
1086 const struct svga3d_surface_desc
*desc
= svga3dsurface_get_desc(format
);
1087 uint64_t total_size
= 0;
1090 for (mip
= 0; mip
< num_mip_levels
; mip
++) {
1092 svga3dsurface_get_mip_size(base_level_size
, mip
);
1093 total_size
+= svga3dsurface_get_image_buffer_size(desc
,
1097 total_size
*= num_layers
;
1099 return (total_size
> (uint64_t) MAX_UINT32
) ? MAX_UINT32
:
1100 (uint32
) total_size
;
1105 * svga3dsurface_get_serialized_size_extended - Returns the number of bytes
1106 * required for a surface with given parameters. Support for sample count.
1109 static inline uint32
1110 svga3dsurface_get_serialized_size_extended(SVGA3dSurfaceFormat format
,
1111 SVGA3dSize base_level_size
,
1112 uint32 num_mip_levels
,
1116 uint64_t total_size
= svga3dsurface_get_serialized_size(format
,
1121 total_size
*= (num_samples
> 1 ? num_samples
: 1);
1123 return (total_size
> (uint64_t) MAX_UINT32
) ? MAX_UINT32
:
1124 (uint32
) total_size
;
1129 * Compute the offset (in bytes) to a pixel in an image (or volume).
1130 * 'width' is the image width in pixels
1131 * 'height' is the image height in pixels
1133 static inline uint32
1134 svga3dsurface_get_pixel_offset(SVGA3dSurfaceFormat format
,
1135 uint32 width
, uint32 height
,
1136 uint32 x
, uint32 y
, uint32 z
)
1138 const struct svga3d_surface_desc
*desc
= svga3dsurface_get_desc(format
);
1139 const uint32 bw
= desc
->block_size
.width
, bh
= desc
->block_size
.height
;
1140 const uint32 bd
= desc
->block_size
.depth
;
1141 const uint32 rowstride
= DIV_ROUND_UP(width
, bw
) * desc
->bytes_per_block
;
1142 const uint32 imgstride
= DIV_ROUND_UP(height
, bh
) * rowstride
;
1143 const uint32 offset
= (z
/ bd
* imgstride
+
1144 y
/ bh
* rowstride
+
1145 x
/ bw
* desc
->bytes_per_block
);