1 /**********************************************************
2 * Copyright 1998-2014 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
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9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
29 * Virtual hardware definitions for the VMware SVGA II device.
35 #include "svga_types.h"
38 * SVGA_REG_ENABLE bit definitions.
41 SVGA_REG_ENABLE_DISABLE
= 0,
42 SVGA_REG_ENABLE_ENABLE
= (1 << 0),
43 SVGA_REG_ENABLE_HIDE
= (1 << 1),
47 * Arbitrary and meaningless limits. Please ignore these when writing
50 #define SVGA_MAX_WIDTH 2560
51 #define SVGA_MAX_HEIGHT 1600
52 #define SVGA_MAX_BITS_PER_PIXEL 32
53 #define SVGA_MAX_DEPTH 24
54 #define SVGA_MAX_DISPLAYS 10
57 * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
58 * cursor bypass mode. This is still supported, but no new guest
59 * drivers should use it.
61 #define SVGA_CURSOR_ON_HIDE 0x0 /* Must be 0 to maintain backward compatibility */
62 #define SVGA_CURSOR_ON_SHOW 0x1 /* Must be 1 to maintain backward compatibility */
63 #define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2 /* Remove the cursor from the framebuffer because we need to see what's under it */
64 #define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 /* Put the cursor back in the framebuffer so the user can see it */
67 * The maximum framebuffer size that can traced for e.g. guests in VESA mode.
68 * The changeMap in the monitor is proportional to this number. Therefore, we'd
69 * like to keep it as small as possible to reduce monitor overhead (using
70 * SVGA_VRAM_MAX_SIZE for this increases the size of the shared area by over
73 * NB: For compatibility reasons, this value must be greater than 0xff0000.
76 #define SVGA_FB_MAX_TRACEABLE_SIZE 0x1000000
78 #define SVGA_MAX_PSEUDOCOLOR_DEPTH 8
79 #define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH)
80 #define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS)
82 #define SVGA_MAGIC 0x900000UL
83 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
85 /* Version 2 let the address of the frame buffer be unsigned on Win32 */
86 #define SVGA_VERSION_2 2
87 #define SVGA_ID_2 SVGA_MAKE_ID(SVGA_VERSION_2)
89 /* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so
90 PALETTE_BASE has moved */
91 #define SVGA_VERSION_1 1
92 #define SVGA_ID_1 SVGA_MAKE_ID(SVGA_VERSION_1)
94 /* Version 0 is the initial version */
95 #define SVGA_VERSION_0 0
96 #define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0)
98 /* "Invalid" value for all SVGA IDs. (Version ID, screen object ID, surface ID...) */
99 #define SVGA_ID_INVALID 0xFFFFFFFF
101 /* Port offsets, relative to BAR0 */
102 #define SVGA_INDEX_PORT 0x0
103 #define SVGA_VALUE_PORT 0x1
104 #define SVGA_BIOS_PORT 0x2
105 #define SVGA_IRQSTATUS_PORT 0x8
108 * Interrupt source flags for IRQSTATUS_PORT and IRQMASK.
110 * Interrupts are only supported when the
111 * SVGA_CAP_IRQMASK capability is present.
113 #define SVGA_IRQFLAG_ANY_FENCE 0x1 /* Any fence was passed */
114 #define SVGA_IRQFLAG_FIFO_PROGRESS 0x2 /* Made forward progress in the FIFO */
115 #define SVGA_IRQFLAG_FENCE_GOAL 0x4 /* SVGA_FIFO_FENCE_GOAL reached */
116 #define SVGA_IRQFLAG_COMMAND_BUFFER 0x8 /* Command buffer completed */
117 #define SVGA_IRQFLAG_ERROR 0x10 /* Error while processing commands */
128 SVGA_REG_MAX_WIDTH
= 4,
129 SVGA_REG_MAX_HEIGHT
= 5,
131 SVGA_REG_BITS_PER_PIXEL
= 7, /* Current bpp in the guest */
132 SVGA_REG_PSEUDOCOLOR
= 8,
133 SVGA_REG_RED_MASK
= 9,
134 SVGA_REG_GREEN_MASK
= 10,
135 SVGA_REG_BLUE_MASK
= 11,
136 SVGA_REG_BYTES_PER_LINE
= 12,
137 SVGA_REG_FB_START
= 13, /* (Deprecated) */
138 SVGA_REG_FB_OFFSET
= 14,
139 SVGA_REG_VRAM_SIZE
= 15,
140 SVGA_REG_FB_SIZE
= 16,
142 /* ID 0 implementation only had the above registers, then the palette */
143 SVGA_REG_ID_0_TOP
= 17,
145 SVGA_REG_CAPABILITIES
= 17,
146 SVGA_REG_MEM_START
= 18, /* (Deprecated) */
147 SVGA_REG_MEM_SIZE
= 19,
148 SVGA_REG_CONFIG_DONE
= 20, /* Set when memory area configured */
149 SVGA_REG_SYNC
= 21, /* See "FIFO Synchronization Registers" */
150 SVGA_REG_BUSY
= 22, /* See "FIFO Synchronization Registers" */
151 SVGA_REG_GUEST_ID
= 23, /* Set guest OS identifier */
152 SVGA_REG_CURSOR_ID
= 24, /* (Deprecated) */
153 SVGA_REG_CURSOR_X
= 25, /* (Deprecated) */
154 SVGA_REG_CURSOR_Y
= 26, /* (Deprecated) */
155 SVGA_REG_CURSOR_ON
= 27, /* (Deprecated) */
156 SVGA_REG_HOST_BITS_PER_PIXEL
= 28, /* (Deprecated) */
157 SVGA_REG_SCRATCH_SIZE
= 29, /* Number of scratch registers */
158 SVGA_REG_MEM_REGS
= 30, /* Number of FIFO registers */
159 SVGA_REG_NUM_DISPLAYS
= 31, /* (Deprecated) */
160 SVGA_REG_PITCHLOCK
= 32, /* Fixed pitch for all modes */
161 SVGA_REG_IRQMASK
= 33, /* Interrupt mask */
163 /* Legacy multi-monitor support */
164 SVGA_REG_NUM_GUEST_DISPLAYS
= 34,/* Number of guest displays in X/Y direction */
165 SVGA_REG_DISPLAY_ID
= 35, /* Display ID for the following display attributes */
166 SVGA_REG_DISPLAY_IS_PRIMARY
= 36,/* Whether this is a primary display */
167 SVGA_REG_DISPLAY_POSITION_X
= 37,/* The display position x */
168 SVGA_REG_DISPLAY_POSITION_Y
= 38,/* The display position y */
169 SVGA_REG_DISPLAY_WIDTH
= 39, /* The display's width */
170 SVGA_REG_DISPLAY_HEIGHT
= 40, /* The display's height */
172 /* See "Guest memory regions" below. */
173 SVGA_REG_GMR_ID
= 41,
174 SVGA_REG_GMR_DESCRIPTOR
= 42,
175 SVGA_REG_GMR_MAX_IDS
= 43,
176 SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH
= 44,
178 SVGA_REG_TRACES
= 45, /* Enable trace-based updates even when FIFO is on */
179 SVGA_REG_GMRS_MAX_PAGES
= 46, /* Maximum number of 4KB pages for all GMRs */
180 SVGA_REG_MEMORY_SIZE
= 47, /* Total dedicated device memory excluding FIFO */
181 SVGA_REG_COMMAND_LOW
= 48, /* Lower 32 bits and submits commands */
182 SVGA_REG_COMMAND_HIGH
= 49, /* Upper 32 bits of command buffer PA */
183 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM
= 50, /* Max primary memory */
184 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB
= 51, /* Suggested limit on mob mem */
185 SVGA_REG_DEV_CAP
= 52, /* Write dev cap index, read value */
186 SVGA_REG_CMD_PREPEND_LOW
= 53,
187 SVGA_REG_iCMD_PREPEND_HIGH
= 54,
188 SVGA_REG_SCREENTARGET_MAX_WIDTH
= 55,
189 SVGA_REG_SCREENTARGET_MAX_HEIGHT
= 56,
190 SVGA_REG_MOB_MAX_SIZE
= 57,
191 SVGA_REG_TOP
= 58, /* Must be 1 more than the last register */
193 SVGA_PALETTE_BASE
= 1024, /* Base of SVGA color map */
194 /* Next 768 (== 256*3) registers exist for colormap */
195 SVGA_SCRATCH_BASE
= SVGA_PALETTE_BASE
+ SVGA_NUM_PALETTE_REGS
196 /* Base of scratch registers */
197 /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage:
198 First 4 are reserved for VESA BIOS Extension; any remaining are for
199 the use of the current SVGA driver. */
203 * Guest memory regions (GMRs):
205 * This is a new memory mapping feature available in SVGA devices
206 * which have the SVGA_CAP_GMR bit set. Previously, there were two
207 * fixed memory regions available with which to share data between the
208 * device and the driver: the FIFO ('MEM') and the framebuffer. GMRs
209 * are our name for an extensible way of providing arbitrary DMA
210 * buffers for use between the driver and the SVGA device. They are a
211 * new alternative to framebuffer memory, usable for both 2D and 3D
212 * graphics operations.
214 * Since GMR mapping must be done synchronously with guest CPU
215 * execution, we use a new pair of SVGA registers:
220 * This register holds the 32-bit ID (a small positive integer)
221 * of a GMR to create, delete, or redefine. Writing this register
222 * has no side-effects.
224 * SVGA_REG_GMR_DESCRIPTOR --
227 * Writing this register will create, delete, or redefine the GMR
228 * specified by the above ID register. If this register is zero,
229 * the GMR is deleted. Any pointers into this GMR (including those
230 * currently being processed by FIFO commands) will be
231 * synchronously invalidated.
233 * If this register is nonzero, it must be the physical page
234 * number (PPN) of a data structure which describes the physical
235 * layout of the memory region this GMR should describe. The
236 * descriptor structure will be read synchronously by the SVGA
237 * device when this register is written. The descriptor need not
238 * remain allocated for the lifetime of the GMR.
240 * The guest driver should write SVGA_REG_GMR_ID first, then
241 * SVGA_REG_GMR_DESCRIPTOR.
243 * SVGA_REG_GMR_MAX_IDS --
246 * The SVGA device may choose to support a maximum number of
247 * user-defined GMR IDs. This register holds the number of supported
248 * IDs. (The maximum supported ID plus 1)
250 * SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH --
253 * The SVGA device may choose to put a limit on the total number
254 * of SVGAGuestMemDescriptor structures it will read when defining
257 * The descriptor structure is an array of SVGAGuestMemDescriptor
258 * structures. Each structure may do one of three things:
260 * - Terminate the GMR descriptor list.
261 * (ppn==0, numPages==0)
263 * - Add a PPN or range of PPNs to the GMR's virtual address space.
264 * (ppn != 0, numPages != 0)
266 * - Provide the PPN of the next SVGAGuestMemDescriptor, in order to
267 * support multi-page GMR descriptor tables without forcing the
268 * driver to allocate physically contiguous memory.
269 * (ppn != 0, numPages == 0)
271 * Note that each physical page of SVGAGuestMemDescriptor structures
272 * can describe at least 2MB of guest memory. If the driver needs to
273 * use more than one page of descriptor structures, it must use one of
274 * its SVGAGuestMemDescriptors to point to an additional page. The
275 * device will never automatically cross a page boundary.
277 * Once the driver has described a GMR, it is immediately available
278 * for use via any FIFO command that uses an SVGAGuestPtr structure.
279 * These pointers include a GMR identifier plus an offset into that
282 * The driver must check the SVGA_CAP_GMR bit before using the GMR
287 * Special GMR IDs, allowing SVGAGuestPtrs to point to framebuffer
288 * memory as well. In the future, these IDs could even be used to
289 * allow legacy memory regions to be redefined by the guest as GMRs.
291 * Using the guest framebuffer (GFB) at BAR1 for general purpose DMA
292 * is being phased out. Please try to use user-defined GMRs whenever
295 #define SVGA_GMR_NULL ((uint32) -1)
296 #define SVGA_GMR_FRAMEBUFFER ((uint32) -2) // Guest Framebuffer (GFB)
299 struct SVGAGuestMemDescriptor
{
302 } SVGAGuestMemDescriptor
;
305 struct SVGAGuestPtr
{
311 * Register based command buffers --
313 * Provide an SVGA device interface that allows the guest to submit
314 * command buffers to the SVGA device through an SVGA device register.
315 * The metadata for each command buffer is contained in the
316 * SVGACBHeader structure along with the return status codes.
318 * The SVGA device supports command buffers if
319 * SVGA_CAP_COMMAND_BUFFERS is set in the device caps register. The
320 * fifo must be enabled for command buffers to be submitted.
322 * Command buffers are submitted when the guest writing the 64 byte
323 * aligned physical address into the SVGA_REG_COMMAND_LOW and
324 * SVGA_REG_COMMAND_HIGH. SVGA_REG_COMMAND_HIGH contains the upper 32
325 * bits of the physical address. SVGA_REG_COMMAND_LOW contains the
326 * lower 32 bits of the physical address, since the command buffer
327 * headers are required to be 64 byte aligned the lower 6 bits are
328 * used for the SVGACBContext value. Writing to SVGA_REG_COMMAND_LOW
329 * submits the command buffer to the device and queues it for
330 * execution. The SVGA device supports at least
331 * SVGA_CB_MAX_QUEUED_PER_CONTEXT command buffers that can be queued
332 * per context and if that limit is reached the device will write the
333 * status SVGA_CB_STATUS_QUEUE_FULL to the status value of the command
334 * buffer header synchronously and not raise any IRQs.
336 * It is invalid to submit a command buffer without a valid physical
337 * address and results are undefined.
339 * The device guarantees that command buffers of size SVGA_CB_MAX_SIZE
340 * will be supported. If a larger command buffer is submitted results
341 * are unspecified and the device will either complete the command
342 * buffer or return an error.
344 * The device guarantees that any individual command in a command
345 * buffer can be up to SVGA_CB_MAX_COMMAND_SIZE in size which is
346 * enough to fit a 64x64 color-cursor definition. If the command is
347 * too large the device is allowed to process the command or return an
350 * The device context is a special SVGACBContext that allows for
351 * synchronous register like accesses with the flexibility of
352 * commands. There is a different command set defined by
353 * SVGADeviceContextCmdId. The commands in each command buffer is not
354 * allowed to straddle physical pages.
357 #define SVGA_CB_MAX_SIZE (512 * 1024) // 512 KB
358 #define SVGA_CB_MAX_QUEUED_PER_CONTEXT 32
359 #define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) // 32 KB
361 #define SVGA_CB_CONTEXT_MASK 0x3f
363 SVGA_CB_CONTEXT_DEVICE
= 0x3f,
364 SVGA_CB_CONTEXT_0
= 0x0,
365 SVGA_CB_CONTEXT_MAX
= 0x1,
371 * The guest is supposed to write SVGA_CB_STATUS_NONE to the status
372 * field before submitting the command buffer header, the host will
373 * change the value when it is done with the command buffer.
375 SVGA_CB_STATUS_NONE
= 0,
378 * Written by the host when a command buffer completes successfully.
379 * The device raises an IRQ with SVGA_IRQFLAG_COMMAND_BUFFER unless
380 * the SVGA_CB_FLAG_NO_IRQ flag is set.
382 SVGA_CB_STATUS_COMPLETED
= 1,
385 * Written by the host synchronously with the command buffer
386 * submission to indicate the command buffer was not submitted. No
389 SVGA_CB_STATUS_QUEUE_FULL
= 2,
392 * Written by the host when an error was detected parsing a command
393 * in the command buffer, errorOffset is written to contain the
394 * offset to the first byte of the failing command. The device
395 * raises the IRQ with both SVGA_IRQFLAG_ERROR and
396 * SVGA_IRQFLAG_COMMAND_BUFFER. Some of the commands may have been
399 SVGA_CB_STATUS_COMMAND_ERROR
= 3,
402 * Written by the host if there is an error parsing the command
403 * buffer header. The device raises the IRQ with both
404 * SVGA_IRQFLAG_ERROR and SVGA_IRQFLAG_COMMAND_BUFFER. The device
405 * did not processes any of the command buffer.
407 SVGA_CB_STATUS_CB_HEADER_ERROR
= 4,
410 * Written by the host if the guest requested the host to preempt
411 * the command buffer. The device will not raise any IRQs and the
412 * command buffer was not processed.
414 SVGA_CB_STATUS_PREEMPTED
= 5,
418 SVGA_CB_FLAG_NONE
= 0,
419 SVGA_CB_FLAG_NO_IRQ
= 1 << 0,
424 volatile SVGACBStatus status
;
425 volatile uint32 errorOffset
;
432 uint32 mustBeZero
[8];
437 SVGA_DC_CMD_START_STOP_CONTEXT
= 1,
438 SVGA_DC_CMD_PREEMPT
= 2,
440 SVGA_DC_CMD_FORCE_UINT
= MAX_UINT32
,
441 } SVGADeviceContextCmdId
;
445 SVGACBContext context
;
446 } SVGADCCmdStartStop
;
449 * SVGADCCmdPreempt --
451 * This command allows the guest to request that all command buffers
452 * on the specified context be preempted that can be. After execution
453 * of this command all command buffers that were preempted will
454 * already have SVGA_CB_STATUS_PREEMPTED written into the status
455 * field. The device might still be processing a command buffer,
456 * assuming execution of it started before the preemption request was
457 * received. Specifying the ignoreIDZero flag to TRUE will cause the
458 * device to not preempt command buffers with the id field in the
459 * command buffer header set to zero.
463 SVGACBContext context
;
469 * SVGAGMRImageFormat --
471 * This is a packed representation of the source 2D image format
472 * for a GMR-to-screen blit. Currently it is defined as an encoding
473 * of the screen's color depth and bits-per-pixel, however, 16 bits
474 * are reserved for future use to identify other encodings (such as
475 * RGBA or higher-precision images).
477 * Currently supported formats:
479 * bpp depth Format Name
480 * --- ----- -----------
488 typedef struct SVGAGMRImageFormat
{
491 uint32 bitsPerPixel
: 8;
492 uint32 colorDepth
: 8;
493 uint32 reserved
: 16; // Must be zero
498 } SVGAGMRImageFormat
;
501 struct SVGAGuestImage
{
505 * A note on interpretation of pitch: This value of pitch is the
506 * number of bytes between vertically adjacent image
507 * blocks. Normally this is the number of bytes between the first
508 * pixel of two adjacent scanlines. With compressed textures,
509 * however, this may represent the number of bytes between
510 * compression blocks rather than between rows of pixels.
512 * XXX: Compressed textures currently must be tightly packed in guest memory.
514 * If the image is 1-dimensional, pitch is ignored.
516 * If 'pitch' is zero, the SVGA3D device calculates a pitch value
517 * assuming each row of blocks is tightly packed.
525 * A 24-bit color format (BGRX), which does not depend on the
526 * format of the legacy guest framebuffer (GFB) or the current
530 typedef struct SVGAColorBGRX
{
536 uint32 x
: 8; // Unused
548 * Signed rectangle and point primitives. These are used by the new
549 * 2D primitives for drawing to Screen Objects, which can occupy a
550 * signed virtual coordinate space.
552 * SVGASignedRect specifies a half-open interval: the (left, top)
553 * pixel is part of the rectangle, but the (right, bottom) pixel is
573 * SVGA Device Capabilities
575 * Note the holes in the bitfield. Missing bits have been deprecated,
576 * and must not be reused. Those capabilities will never be reported
577 * by new versions of the SVGA device.
579 * XXX: Add longer descriptions for each capability, including a list
580 * of the new features that each capability provides.
582 * SVGA_CAP_IRQMASK --
583 * Provides device interrupts. Adds device register SVGA_REG_IRQMASK
584 * to set interrupt mask and direct I/O port SVGA_IRQSTATUS_PORT to
585 * set/clear pending interrupts.
588 * Provides synchronous mapping of guest memory regions (GMR).
589 * Adds device registers SVGA_REG_GMR_ID, SVGA_REG_GMR_DESCRIPTOR,
590 * SVGA_REG_GMR_MAX_IDS, and SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH.
593 * Allows framebuffer trace-based updates even when FIFO is enabled.
594 * Adds device register SVGA_REG_TRACES.
597 * Provides asynchronous commands to define and remap guest memory
598 * regions. Adds device registers SVGA_REG_GMRS_MAX_PAGES and
599 * SVGA_REG_MEMORY_SIZE.
601 * SVGA_CAP_SCREEN_OBJECT_2 --
602 * Allow screen object support, and require backing stores from the
603 * guest for each screen object.
605 * SVGA_CAP_COMMAND_BUFFERS --
606 * Enable register based command buffer submission.
608 * SVGA_CAP_GBOBJECTS --
609 * Enable guest-backed objects and surfaces.
613 #define SVGA_CAP_NONE 0x00000000
614 #define SVGA_CAP_RECT_COPY 0x00000002
615 #define SVGA_CAP_CURSOR 0x00000020
616 #define SVGA_CAP_CURSOR_BYPASS 0x00000040 // Legacy (Use Cursor Bypass 3 instead)
617 #define SVGA_CAP_CURSOR_BYPASS_2 0x00000080 // Legacy (Use Cursor Bypass 3 instead)
618 #define SVGA_CAP_8BIT_EMULATION 0x00000100
619 #define SVGA_CAP_ALPHA_CURSOR 0x00000200
620 #define SVGA_CAP_3D 0x00004000
621 #define SVGA_CAP_EXTENDED_FIFO 0x00008000
622 #define SVGA_CAP_MULTIMON 0x00010000 // Legacy multi-monitor support
623 #define SVGA_CAP_PITCHLOCK 0x00020000
624 #define SVGA_CAP_IRQMASK 0x00040000
625 #define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000 // Legacy multi-monitor support
626 #define SVGA_CAP_GMR 0x00100000
627 #define SVGA_CAP_TRACES 0x00200000
628 #define SVGA_CAP_GMR2 0x00400000
629 #define SVGA_CAP_SCREEN_OBJECT_2 0x00800000
630 #define SVGA_CAP_COMMAND_BUFFERS 0x01000000
631 #define SVGA_CAP_DEAD1 0x02000000
632 #define SVGA_CAP_CMD_BUFFERS_2 0x04000000
633 #define SVGA_CAP_GBOBJECTS 0x08000000
637 * The Guest can optionally read some SVGA device capabilities through
638 * the backdoor with command BDOOR_CMD_GET_SVGA_CAPABILITIES before
639 * the SVGA device is initialized. The type of capability the guest
640 * is requesting from the SVGABackdoorCapType enum should be placed in
641 * the upper 16 bits of the backdoor command id (ECX). On success the
642 * the value of EBX will be set to BDOOR_MAGIC and EAX will be set to
643 * the requested capability. If the command is not supported then EBX
644 * will be left unchanged and EAX will be set to -1. Because it is
645 * possible that -1 is the value of the requested cap the correct way
646 * to check if the command was successful is to check if EBX was changed
647 * to BDOOR_MAGIC making sure to initialize the register to something
652 SVGABackdoorCapDeviceCaps
= 0,
653 SVGABackdoorCapFifoCaps
= 1,
654 SVGABackdoorCap3dHWVersion
= 2,
655 SVGABackdoorCapMax
= 3,
656 } SVGABackdoorCapType
;
660 * FIFO register indices.
662 * The FIFO is a chunk of device memory mapped into guest physmem. It
663 * is always treated as 32-bit words.
665 * The guest driver gets to decide how to partition it between
666 * - FIFO registers (there are always at least 4, specifying where the
667 * following data area is and how much data it contains; there may be
668 * more registers following these, depending on the FIFO protocol
670 * - FIFO data, written by the guest and slurped out by the VMX.
671 * These indices are 32-bit word offsets into the FIFO.
676 * Block 1 (basic registers): The originally defined FIFO registers.
677 * These exist and are valid for all versions of the FIFO protocol.
681 SVGA_FIFO_MAX
, /* The distance from MIN to MAX must be at least 10K */
686 * Block 2 (extended registers): Mandatory registers for the extended
687 * FIFO. These exist if the SVGA caps register includes
688 * SVGA_CAP_EXTENDED_FIFO; some of them are valid only if their
689 * associated capability bit is enabled.
691 * Note that when originally defined, SVGA_CAP_EXTENDED_FIFO implied
692 * support only for (FIFO registers) CAPABILITIES, FLAGS, and FENCE.
693 * This means that the guest has to test individually (in most cases
694 * using FIFO caps) for the presence of registers after this; the VMX
695 * can define "extended FIFO" to mean whatever it wants, and currently
696 * won't enable it unless there's room for that set and much more.
699 SVGA_FIFO_CAPABILITIES
= 4,
701 // Valid with SVGA_FIFO_CAP_FENCE:
705 * Block 3a (optional extended registers): Additional registers for the
706 * extended FIFO, whose presence isn't actually implied by
707 * SVGA_CAP_EXTENDED_FIFO; these exist if SVGA_FIFO_MIN is high enough to
708 * leave room for them.
710 * These in block 3a, the VMX currently considers mandatory for the
714 // Valid if exists (i.e. if extended FIFO enabled):
715 SVGA_FIFO_3D_HWVERSION
, /* See SVGA3dHardwareVersion in svga3d_reg.h */
716 // Valid with SVGA_FIFO_CAP_PITCHLOCK:
719 // Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3:
720 SVGA_FIFO_CURSOR_ON
, /* Cursor bypass 3 show/hide register */
721 SVGA_FIFO_CURSOR_X
, /* Cursor bypass 3 x register */
722 SVGA_FIFO_CURSOR_Y
, /* Cursor bypass 3 y register */
723 SVGA_FIFO_CURSOR_COUNT
, /* Incremented when any of the other 3 change */
724 SVGA_FIFO_CURSOR_LAST_UPDATED
,/* Last time the host updated the cursor */
726 // Valid with SVGA_FIFO_CAP_RESERVE:
727 SVGA_FIFO_RESERVED
, /* Bytes past NEXT_CMD with real contents */
730 * Valid with SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2:
732 * By default this is SVGA_ID_INVALID, to indicate that the cursor
733 * coordinates are specified relative to the virtual root. If this
734 * is set to a specific screen ID, cursor position is reinterpreted
735 * as a signed offset relative to that screen's origin.
737 SVGA_FIFO_CURSOR_SCREEN_ID
,
740 * Valid with SVGA_FIFO_CAP_DEAD
742 * An arbitrary value written by the host, drivers should not use it.
747 * Valid with SVGA_FIFO_CAP_3D_HWVERSION_REVISED:
749 * Contains 3D HWVERSION (see SVGA3dHardwareVersion in svga3d_reg.h)
750 * on platforms that can enforce graphics resource limits.
752 SVGA_FIFO_3D_HWVERSION_REVISED
,
755 * XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new
756 * registers, but this must be done carefully and with judicious use of
757 * capability bits, since comparisons based on SVGA_FIFO_MIN aren't
758 * enough to tell you whether the register exists: we've shipped drivers
759 * and products that used SVGA_FIFO_3D_CAPS but didn't know about some of
760 * the earlier ones. The actual order of introduction was:
763 * - CURSOR_* (cursor bypass 3)
765 * So, code that wants to know whether it can use any of the
766 * aforementioned registers, or anything else added after PITCHLOCK and
767 * before 3D_CAPS, needs to reason about something other than
772 * 3D caps block space; valid with 3D hardware version >=
773 * SVGA3D_HWVERSION_WS6_B1.
775 SVGA_FIFO_3D_CAPS
= 32,
776 SVGA_FIFO_3D_CAPS_LAST
= 32 + 255,
779 * End of VMX's current definition of "extended-FIFO registers".
780 * Registers before here are always enabled/disabled as a block; either
781 * the extended FIFO is enabled and includes all preceding registers, or
782 * it's disabled entirely.
784 * Block 3b (truly optional extended registers): Additional registers for
785 * the extended FIFO, which the VMX already knows how to enable and
786 * disable with correct granularity.
788 * Registers after here exist if and only if the guest SVGA driver
789 * sets SVGA_FIFO_MIN high enough to leave room for them.
792 // Valid if register exists:
793 SVGA_FIFO_GUEST_3D_HWVERSION
, /* Guest driver's 3D version */
794 SVGA_FIFO_FENCE_GOAL
, /* Matching target for SVGA_IRQFLAG_FENCE_GOAL */
795 SVGA_FIFO_BUSY
, /* See "FIFO Synchronization Registers" */
798 * Always keep this last. This defines the maximum number of
799 * registers we know about. At power-on, this value is placed in
800 * the SVGA_REG_MEM_REGS register, and we expect the guest driver
801 * to allocate this much space in FIFO memory for registers.
808 * Definition of registers included in extended FIFO support.
810 * The guest SVGA driver gets to allocate the FIFO between registers
811 * and data. It must always allocate at least 4 registers, but old
812 * drivers stopped there.
814 * The VMX will enable extended FIFO support if and only if the guest
815 * left enough room for all registers defined as part of the mandatory
816 * set for the extended FIFO.
818 * Note that the guest drivers typically allocate the FIFO only at
819 * initialization time, not at mode switches, so it's likely that the
820 * number of FIFO registers won't change without a reboot.
822 * All registers less than this value are guaranteed to be present if
823 * svgaUser->fifo.extended is set. Any later registers must be tested
824 * individually for compatibility at each use (in the VMX).
826 * This value is used only by the VMX, so it can change without
827 * affecting driver compatibility; keep it that way?
829 #define SVGA_FIFO_EXTENDED_MANDATORY_REGS (SVGA_FIFO_3D_CAPS_LAST + 1)
833 * FIFO Synchronization Registers
835 * This explains the relationship between the various FIFO
836 * sync-related registers in IOSpace and in FIFO space.
840 * The SYNC register can be used in two different ways by the guest:
842 * 1. If the guest wishes to fully sync (drain) the FIFO,
843 * it will write once to SYNC then poll on the BUSY
844 * register. The FIFO is sync'ed once BUSY is zero.
846 * 2. If the guest wants to asynchronously wake up the host,
847 * it will write once to SYNC without polling on BUSY.
848 * Ideally it will do this after some new commands have
849 * been placed in the FIFO, and after reading a zero
850 * from SVGA_FIFO_BUSY.
852 * (1) is the original behaviour that SYNC was designed to
853 * support. Originally, a write to SYNC would implicitly
854 * trigger a read from BUSY. This causes us to synchronously
857 * This behaviour has since been changed so that writing SYNC
858 * will *not* implicitly cause a read from BUSY. Instead, it
859 * makes a channel call which asynchronously wakes up the MKS
862 * New guests can use this new behaviour to implement (2)
863 * efficiently. This lets guests get the host's attention
864 * without waiting for the MKS to poll, which gives us much
865 * better CPU utilization on SMP hosts and on UP hosts while
866 * we're blocked on the host GPU.
868 * Old guests shouldn't notice the behaviour change. SYNC was
869 * never guaranteed to process the entire FIFO, since it was
870 * bounded to a particular number of CPU cycles. Old guests will
871 * still loop on the BUSY register until the FIFO is empty.
873 * Writing to SYNC currently has the following side-effects:
875 * - Sets SVGA_REG_BUSY to TRUE (in the monitor)
876 * - Asynchronously wakes up the MKS thread for FIFO processing
877 * - The value written to SYNC is recorded as a "reason", for
880 * If SVGA_FIFO_BUSY is available, drivers are advised to only
881 * write to SYNC if SVGA_FIFO_BUSY is FALSE. Drivers should set
882 * SVGA_FIFO_BUSY to TRUE after writing to SYNC. The MKS will
883 * eventually set SVGA_FIFO_BUSY on its own, but this approach
884 * lets the driver avoid sending multiple asynchronous wakeup
885 * messages to the MKS thread.
889 * This register is set to TRUE when SVGA_REG_SYNC is written,
890 * and it reads as FALSE when the FIFO has been completely
893 * Every read from this register causes us to synchronously
894 * process FIFO commands. There is no guarantee as to how many
895 * commands each read will process.
897 * CPU time spent processing FIFO commands will be billed to
900 * New drivers should avoid using this register unless they
901 * need to guarantee that the FIFO is completely drained. It
902 * is overkill for performing a sync-to-fence. Older drivers
903 * will use this register for any type of synchronization.
907 * This register is a fast way for the guest driver to check
908 * whether the FIFO is already being processed. It reads and
909 * writes at normal RAM speeds, with no monitor intervention.
911 * If this register reads as TRUE, the host is guaranteeing that
912 * any new commands written into the FIFO will be noticed before
913 * the MKS goes back to sleep.
915 * If this register reads as FALSE, no such guarantee can be
918 * The guest should use this register to quickly determine
919 * whether or not it needs to wake up the host. If the guest
920 * just wrote a command or group of commands that it would like
921 * the host to begin processing, it should:
923 * 1. Read SVGA_FIFO_BUSY. If it reads as TRUE, no further
924 * action is necessary.
926 * 2. Write TRUE to SVGA_FIFO_BUSY. This informs future guest
927 * code that we've already sent a SYNC to the host and we
928 * don't need to send a duplicate.
930 * 3. Write a reason to SVGA_REG_SYNC. This will send an
931 * asynchronous wakeup to the MKS thread.
938 * Fence -- Fence register and command are supported
939 * Accel Front -- Front buffer only commands are supported
940 * Pitch Lock -- Pitch lock register is supported
941 * Video -- SVGA Video overlay units are supported
942 * Escape -- Escape command is supported
944 * XXX: Add longer descriptions for each capability, including a list
945 * of the new features that each capability provides.
947 * SVGA_FIFO_CAP_SCREEN_OBJECT --
949 * Provides dynamic multi-screen rendering, for improved Unity and
950 * multi-monitor modes. With Screen Object, the guest can
951 * dynamically create and destroy 'screens', which can represent
952 * Unity windows or virtual monitors. Screen Object also provides
953 * strong guarantees that DMA operations happen only when
954 * guest-initiated. Screen Object deprecates the BAR1 guest
955 * framebuffer (GFB) and all commands that work only with the GFB.
958 * FIFO_CURSOR_SCREEN_ID, VIDEO_DATA_GMRID, VIDEO_DST_SCREEN_ID
961 * DEFINE_SCREEN, DESTROY_SCREEN, DEFINE_GMRFB, BLIT_GMRFB_TO_SCREEN,
962 * BLIT_SCREEN_TO_GMRFB, ANNOTATION_FILL, ANNOTATION_COPY
965 * BLIT_SURFACE_TO_SCREEN
969 * - The host will not read or write guest memory, including the GFB,
970 * except when explicitly initiated by a DMA command.
972 * - All DMA, including legacy DMA like UPDATE and PRESENT_READBACK,
973 * is guaranteed to complete before any subsequent FENCEs.
975 * - All legacy commands which affect a Screen (UPDATE, PRESENT,
976 * PRESENT_READBACK) as well as new Screen blit commands will
977 * all behave consistently as blits, and memory will be read
978 * or written in FIFO order.
980 * For example, if you PRESENT from one SVGA3D surface to multiple
981 * places on the screen, the data copied will always be from the
982 * SVGA3D surface at the time the PRESENT was issued in the FIFO.
983 * This was not necessarily true on devices without Screen Object.
985 * This means that on devices that support Screen Object, the
986 * PRESENT_READBACK command should not be necessary unless you
987 * actually want to read back the results of 3D rendering into
988 * system memory. (And for that, the BLIT_SCREEN_TO_GMRFB
989 * command provides a strict superset of functionality.)
991 * - When a screen is resized, either using Screen Object commands or
992 * legacy multimon registers, its contents are preserved.
994 * SVGA_FIFO_CAP_GMR2 --
996 * Provides new commands to define and remap guest memory regions (GMR).
999 * DEFINE_GMR2, REMAP_GMR2.
1001 * SVGA_FIFO_CAP_3D_HWVERSION_REVISED --
1003 * Indicates new register SVGA_FIFO_3D_HWVERSION_REVISED exists.
1004 * This register may replace SVGA_FIFO_3D_HWVERSION on platforms
1005 * that enforce graphics resource limits. This allows the platform
1006 * to clear SVGA_FIFO_3D_HWVERSION and disable 3D in legacy guest
1007 * drivers that do not limit their resources.
1009 * Note this is an alias to SVGA_FIFO_CAP_GMR2 because these indicators
1010 * are codependent (and thus we use a single capability bit).
1012 * SVGA_FIFO_CAP_SCREEN_OBJECT_2 --
1014 * Modifies the DEFINE_SCREEN command to include a guest provided
1015 * backing store in GMR memory and the bytesPerLine for the backing
1016 * store. This capability requires the use of a backing store when
1017 * creating screen objects. However if SVGA_FIFO_CAP_SCREEN_OBJECT
1018 * is present then backing stores are optional.
1020 * SVGA_FIFO_CAP_DEAD --
1022 * Drivers should not use this cap bit. This cap bit can not be
1023 * reused since some hosts already expose it.
1026 #define SVGA_FIFO_CAP_NONE 0
1027 #define SVGA_FIFO_CAP_FENCE (1<<0)
1028 #define SVGA_FIFO_CAP_ACCELFRONT (1<<1)
1029 #define SVGA_FIFO_CAP_PITCHLOCK (1<<2)
1030 #define SVGA_FIFO_CAP_VIDEO (1<<3)
1031 #define SVGA_FIFO_CAP_CURSOR_BYPASS_3 (1<<4)
1032 #define SVGA_FIFO_CAP_ESCAPE (1<<5)
1033 #define SVGA_FIFO_CAP_RESERVE (1<<6)
1034 #define SVGA_FIFO_CAP_SCREEN_OBJECT (1<<7)
1035 #define SVGA_FIFO_CAP_GMR2 (1<<8)
1036 #define SVGA_FIFO_CAP_3D_HWVERSION_REVISED SVGA_FIFO_CAP_GMR2
1037 #define SVGA_FIFO_CAP_SCREEN_OBJECT_2 (1<<9)
1038 #define SVGA_FIFO_CAP_DEAD (1<<10)
1044 * Accel Front -- Driver should use front buffer only commands
1047 #define SVGA_FIFO_FLAG_NONE 0
1048 #define SVGA_FIFO_FLAG_ACCELFRONT (1<<0)
1049 #define SVGA_FIFO_FLAG_RESERVED (1<<31) // Internal use only
1052 * FIFO reservation sentinel value
1055 #define SVGA_FIFO_RESERVED_UNKNOWN 0xffffffff
1059 * Video overlay support
1062 #define SVGA_NUM_OVERLAY_UNITS 32
1066 * Video capabilities that the guest is currently using
1069 #define SVGA_VIDEO_FLAG_COLORKEY 0x0001
1073 * Offsets for the video overlay registers
1077 SVGA_VIDEO_ENABLED
= 0,
1079 SVGA_VIDEO_DATA_OFFSET
,
1081 SVGA_VIDEO_COLORKEY
,
1082 SVGA_VIDEO_SIZE
, // Deprecated
1087 SVGA_VIDEO_SRC_WIDTH
,
1088 SVGA_VIDEO_SRC_HEIGHT
,
1089 SVGA_VIDEO_DST_X
, // Signed int32
1090 SVGA_VIDEO_DST_Y
, // Signed int32
1091 SVGA_VIDEO_DST_WIDTH
,
1092 SVGA_VIDEO_DST_HEIGHT
,
1096 SVGA_VIDEO_DATA_GMRID
, // Optional, defaults to SVGA_GMR_FRAMEBUFFER
1097 SVGA_VIDEO_DST_SCREEN_ID
, // Optional, defaults to virtual coords (SVGA_ID_INVALID)
1103 * SVGA Overlay Units
1105 * width and height relate to the entire source video frame.
1106 * srcX, srcY, srcWidth and srcHeight represent subset of the source
1107 * video frame to be displayed.
1110 typedef struct SVGAOverlayUnit
{
1134 * Guest display topology
1136 * XXX: This structure is not part of the SVGA device's interface, and
1137 * doesn't really belong here.
1139 #define SVGA_INVALID_DISPLAY_ID ((uint32)-1)
1141 typedef struct SVGADisplayTopology
{
1148 } SVGADisplayTopology
;
1152 * SVGAScreenObject --
1154 * This is a new way to represent a guest's multi-monitor screen or
1155 * Unity window. Screen objects are only supported if the
1156 * SVGA_FIFO_CAP_SCREEN_OBJECT capability bit is set.
1158 * If Screen Objects are supported, they can be used to fully
1159 * replace the functionality provided by the framebuffer registers
1160 * (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY.
1162 * The screen object is a struct with guaranteed binary
1163 * compatibility. New flags can be added, and the struct may grow,
1164 * but existing fields must retain their meaning.
1166 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2 are required fields of
1167 * a SVGAGuestPtr that is used to back the screen contents. This
1168 * memory must come from the GFB. The guest is not allowed to
1169 * access the memory and doing so will have undefined results. The
1170 * backing store is required to be page aligned and the size is
1171 * padded to the next page boundry. The number of pages is:
1172 * (bytesPerLine * size.width * 4 + PAGE_SIZE - 1) / PAGE_SIZE
1174 * The pitch in the backingStore is required to be at least large
1175 * enough to hold a 32bbp scanline. It is recommended that the
1176 * driver pad bytesPerLine for a potential performance win.
1178 * The cloneCount field is treated as a hint from the guest that
1179 * the user wants this display to be cloned, countCount times. A
1180 * value of zero means no cloning should happen.
1183 #define SVGA_SCREEN_MUST_BE_SET (1 << 0) // Must be set or results undefined
1184 #define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET // Deprecated
1185 #define SVGA_SCREEN_IS_PRIMARY (1 << 1) // Guest considers this screen to be 'primary'
1186 #define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2) // Guest is running a fullscreen app here
1189 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When the screen is
1190 * deactivated the base layer is defined to lose all contents and
1191 * become black. When a screen is deactivated the backing store is
1192 * optional. When set backingPtr and bytesPerLine will be ignored.
1194 #define SVGA_SCREEN_DEACTIVATE (1 << 3)
1197 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When this flag is set
1198 * the screen contents will be outputted as all black to the user
1199 * though the base layer contents is preserved. The screen base layer
1200 * can still be read and written to like normal though the no visible
1201 * effect will be seen by the user. When the flag is changed the
1202 * screen will be blanked or redrawn to the current contents as needed
1203 * without any extra commands from the driver. This flag only has an
1204 * effect when the screen is not deactivated.
1206 #define SVGA_SCREEN_BLANKING (1 << 4)
1210 uint32 structSize
; // sizeof(SVGAScreenObject)
1223 * Added and required by SVGA_FIFO_CAP_SCREEN_OBJECT_2, optional
1224 * with SVGA_FIFO_CAP_SCREEN_OBJECT.
1226 SVGAGuestImage backingStore
;
1232 * Commands in the command FIFO:
1234 * Command IDs defined below are used for the traditional 2D FIFO
1235 * communication (not all commands are available for all versions of the
1236 * SVGA FIFO protocol).
1238 * Note the holes in the command ID numbers: These commands have been
1239 * deprecated, and the old IDs must not be reused.
1241 * Command IDs from 1000 to 1999 are reserved for use by the SVGA3D
1244 * Each command's parameters are described by the comments and
1249 SVGA_CMD_INVALID_CMD
= 0,
1250 SVGA_CMD_UPDATE
= 1,
1251 SVGA_CMD_RECT_COPY
= 3,
1252 SVGA_CMD_RECT_ROP_COPY
= 14,
1253 SVGA_CMD_DEFINE_CURSOR
= 19,
1254 SVGA_CMD_DEFINE_ALPHA_CURSOR
= 22,
1255 SVGA_CMD_UPDATE_VERBOSE
= 25,
1256 SVGA_CMD_FRONT_ROP_FILL
= 29,
1257 SVGA_CMD_FENCE
= 30,
1258 SVGA_CMD_ESCAPE
= 33,
1259 SVGA_CMD_DEFINE_SCREEN
= 34,
1260 SVGA_CMD_DESTROY_SCREEN
= 35,
1261 SVGA_CMD_DEFINE_GMRFB
= 36,
1262 SVGA_CMD_BLIT_GMRFB_TO_SCREEN
= 37,
1263 SVGA_CMD_BLIT_SCREEN_TO_GMRFB
= 38,
1264 SVGA_CMD_ANNOTATION_FILL
= 39,
1265 SVGA_CMD_ANNOTATION_COPY
= 40,
1266 SVGA_CMD_DEFINE_GMR2
= 41,
1267 SVGA_CMD_REMAP_GMR2
= 42,
1269 SVGA_CMD_DEAD_2
= 44,
1273 #define SVGA_CMD_MAX_DATASIZE (256 * 1024)
1274 #define SVGA_CMD_MAX_ARGS 64
1275 #define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) // 32 KB
1279 * SVGA_CMD_UPDATE --
1281 * This is a DMA transfer which copies from the Guest Framebuffer
1282 * (GFB) at BAR1 + SVGA_REG_FB_OFFSET to any screens which
1283 * intersect with the provided virtual rectangle.
1285 * This command does not support using arbitrary guest memory as a
1286 * data source- it only works with the pre-defined GFB memory.
1287 * This command also does not support signed virtual coordinates.
1288 * If you have defined screens (using SVGA_CMD_DEFINE_SCREEN) with
1289 * negative root x/y coordinates, the negative portion of those
1290 * screens will not be reachable by this command.
1292 * This command is not necessary when using framebuffer
1293 * traces. Traces are automatically enabled if the SVGA FIFO is
1294 * disabled, and you may explicitly enable/disable traces using
1295 * SVGA_REG_TRACES. With traces enabled, any write to the GFB will
1296 * automatically act as if a subsequent SVGA_CMD_UPDATE was issued.
1298 * Traces and SVGA_CMD_UPDATE are the only supported ways to render
1299 * pseudocolor screen updates. The newer Screen Object commands
1300 * only support true color formats.
1312 } SVGAFifoCmdUpdate
;
1316 * SVGA_CMD_RECT_COPY --
1318 * Perform a rectangular DMA transfer from one area of the GFB to
1319 * another, and copy the result to any screens which intersect it.
1322 * SVGA_CAP_RECT_COPY
1333 } SVGAFifoCmdRectCopy
;
1337 * SVGA_CMD_RECT_ROP_COPY --
1339 * Perform a rectangular DMA transfer from one area of the GFB to
1340 * another, and copy the result to any screens which intersect it.
1341 * The value of ROP may only be SVGA_ROP_COPY, and this command is
1342 * only supported for backwards compatibility reasons.
1345 * SVGA_CAP_RECT_COPY
1357 } SVGAFifoCmdRectRopCopy
;
1361 * SVGA_CMD_DEFINE_CURSOR --
1363 * Provide a new cursor image, as an AND/XOR mask.
1365 * The recommended way to position the cursor overlay is by using
1366 * the SVGA_FIFO_CURSOR_* registers, supported by the
1367 * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
1375 uint32 id
; // Reserved, must be zero.
1380 uint32 andMaskDepth
; // Value must be 1 or equal to BITS_PER_PIXEL
1381 uint32 xorMaskDepth
; // Value must be 1 or equal to BITS_PER_PIXEL
1383 * Followed by scanline data for AND mask, then XOR mask.
1384 * Each scanline is padded to a 32-bit boundary.
1386 } SVGAFifoCmdDefineCursor
;
1390 * SVGA_CMD_DEFINE_ALPHA_CURSOR --
1392 * Provide a new cursor image, in 32-bit BGRA format.
1394 * The recommended way to position the cursor overlay is by using
1395 * the SVGA_FIFO_CURSOR_* registers, supported by the
1396 * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
1399 * SVGA_CAP_ALPHA_CURSOR
1404 uint32 id
; // Reserved, must be zero.
1409 /* Followed by scanline data */
1410 } SVGAFifoCmdDefineAlphaCursor
;
1414 * SVGA_CMD_UPDATE_VERBOSE --
1416 * Just like SVGA_CMD_UPDATE, but also provide a per-rectangle
1417 * 'reason' value, an opaque cookie which is used by internal
1418 * debugging tools. Third party drivers should not use this
1422 * SVGA_CAP_EXTENDED_FIFO
1432 } SVGAFifoCmdUpdateVerbose
;
1436 * SVGA_CMD_FRONT_ROP_FILL --
1438 * This is a hint which tells the SVGA device that the driver has
1439 * just filled a rectangular region of the GFB with a solid
1440 * color. Instead of reading these pixels from the GFB, the device
1441 * can assume that they all equal 'color'. This is primarily used
1442 * for remote desktop protocols.
1445 * SVGA_FIFO_CAP_ACCELFRONT
1448 #define SVGA_ROP_COPY 0x03
1452 uint32 color
; // In the same format as the GFB
1457 uint32 rop
; // Must be SVGA_ROP_COPY
1458 } SVGAFifoCmdFrontRopFill
;
1464 * Insert a synchronization fence. When the SVGA device reaches
1465 * this command, it will copy the 'fence' value into the
1466 * SVGA_FIFO_FENCE register. It will also compare the fence against
1467 * SVGA_FIFO_FENCE_GOAL. If the fence matches the goal and the
1468 * SVGA_IRQFLAG_FENCE_GOAL interrupt is enabled, the device will
1469 * raise this interrupt.
1472 * SVGA_FIFO_FENCE for this command,
1473 * SVGA_CAP_IRQMASK for SVGA_FIFO_FENCE_GOAL.
1483 * SVGA_CMD_ESCAPE --
1485 * Send an extended or vendor-specific variable length command.
1486 * This is used for video overlay, third party plugins, and
1487 * internal debugging tools. See svga_escape.h
1490 * SVGA_FIFO_CAP_ESCAPE
1497 /* followed by 'size' bytes of data */
1498 } SVGAFifoCmdEscape
;
1502 * SVGA_CMD_DEFINE_SCREEN --
1504 * Define or redefine an SVGAScreenObject. See the description of
1505 * SVGAScreenObject above. The video driver is responsible for
1506 * generating new screen IDs. They should be small positive
1507 * integers. The virtual device will have an implementation
1508 * specific upper limit on the number of screen IDs
1509 * supported. Drivers are responsible for recycling IDs. The first
1512 * - Interaction with other registers:
1514 * For backwards compatibility, when the GFB mode registers (WIDTH,
1515 * HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1516 * deletes all screens other than screen #0, and redefines screen
1517 * #0 according to the specified mode. Drivers that use
1518 * SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0.
1520 * If you use screen objects, do not use the legacy multi-mon
1521 * registers (SVGA_REG_NUM_GUEST_DISPLAYS, SVGA_REG_DISPLAY_*).
1524 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1529 SVGAScreenObject screen
; // Variable-length according to version
1530 } SVGAFifoCmdDefineScreen
;
1534 * SVGA_CMD_DESTROY_SCREEN --
1536 * Destroy an SVGAScreenObject. Its ID is immediately available for
1540 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1546 } SVGAFifoCmdDestroyScreen
;
1550 * SVGA_CMD_DEFINE_GMRFB --
1552 * This command sets a piece of SVGA device state called the
1553 * Guest Memory Region Framebuffer, or GMRFB. The GMRFB is a
1554 * piece of light-weight state which identifies the location and
1555 * format of an image in guest memory or in BAR1. The GMRFB has
1556 * an arbitrary size, and it doesn't need to match the geometry
1557 * of the GFB or any screen object.
1559 * The GMRFB can be redefined as often as you like. You could
1560 * always use the same GMRFB, you could redefine it before
1561 * rendering from a different guest screen, or you could even
1562 * redefine it before every blit.
1564 * There are multiple ways to use this command. The simplest way is
1565 * to use it to move the framebuffer either to elsewhere in the GFB
1566 * (BAR1) memory region, or to a user-defined GMR. This lets a
1567 * driver use a framebuffer allocated entirely out of normal system
1568 * memory, which we encourage.
1570 * Another way to use this command is to set up a ring buffer of
1571 * updates in GFB memory. If a driver wants to ensure that no
1572 * frames are skipped by the SVGA device, it is important that the
1573 * driver not modify the source data for a blit until the device is
1574 * done processing the command. One efficient way to accomplish
1575 * this is to use a ring of small DMA buffers. Each buffer is used
1576 * for one blit, then we move on to the next buffer in the
1577 * ring. The FENCE mechanism is used to protect each buffer from
1578 * re-use until the device is finished with that buffer's
1579 * corresponding blit.
1581 * This command does not affect the meaning of SVGA_CMD_UPDATE.
1582 * UPDATEs always occur from the legacy GFB memory area. This
1583 * command has no support for pseudocolor GMRFBs. Currently only
1584 * true-color 15, 16, and 24-bit depths are supported. Future
1585 * devices may expose capabilities for additional framebuffer
1588 * The default GMRFB value is undefined. Drivers must always send
1589 * this command at least once before performing any blit from the
1593 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1599 uint32 bytesPerLine
;
1600 SVGAGMRImageFormat format
;
1601 } SVGAFifoCmdDefineGMRFB
;
1605 * SVGA_CMD_BLIT_GMRFB_TO_SCREEN --
1607 * This is a guest-to-host blit. It performs a DMA operation to
1608 * copy a rectangular region of pixels from the current GMRFB to
1609 * one or more Screen Objects.
1611 * The destination coordinate may be specified relative to a
1612 * screen's origin (if a screen ID is specified) or relative to the
1613 * virtual coordinate system's origin (if the screen ID is
1614 * SVGA_ID_INVALID). The actual destination may span zero or more
1615 * screens, in the case of a virtual destination rect or a rect
1616 * which extends off the edge of the specified screen.
1618 * This command writes to the screen's "base layer": the underlying
1619 * framebuffer which exists below any cursor or video overlays. No
1620 * action is necessary to explicitly hide or update any overlays
1621 * which exist on top of the updated region.
1623 * The SVGA device is guaranteed to finish reading from the GMRFB
1624 * by the time any subsequent FENCE commands are reached.
1626 * This command consumes an annotation. See the
1627 * SVGA_CMD_ANNOTATION_* commands for details.
1630 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1635 SVGASignedPoint srcOrigin
;
1636 SVGASignedRect destRect
;
1637 uint32 destScreenId
;
1638 } SVGAFifoCmdBlitGMRFBToScreen
;
1642 * SVGA_CMD_BLIT_SCREEN_TO_GMRFB --
1644 * This is a host-to-guest blit. It performs a DMA operation to
1645 * copy a rectangular region of pixels from a single Screen Object
1646 * back to the current GMRFB.
1648 * Usage note: This command should be used rarely. It will
1649 * typically be inefficient, but it is necessary for some types of
1650 * synchronization between 3D (GPU) and 2D (CPU) rendering into
1651 * overlapping areas of a screen.
1653 * The source coordinate is specified relative to a screen's
1654 * origin. The provided screen ID must be valid. If any parameters
1655 * are invalid, the resulting pixel values are undefined.
1657 * This command reads the screen's "base layer". Overlays like
1658 * video and cursor are not included, but any data which was sent
1659 * using a blit-to-screen primitive will be available, no matter
1660 * whether the data's original source was the GMRFB or the 3D
1661 * acceleration hardware.
1663 * Note that our guest-to-host blits and host-to-guest blits aren't
1664 * symmetric in their current implementation. While the parameters
1665 * are identical, host-to-guest blits are a lot less featureful.
1666 * They do not support clipping: If the source parameters don't
1667 * fully fit within a screen, the blit fails. They must originate
1668 * from exactly one screen. Virtual coordinates are not directly
1671 * Host-to-guest blits do support the same set of GMRFB formats
1672 * offered by guest-to-host blits.
1674 * The SVGA device is guaranteed to finish writing to the GMRFB by
1675 * the time any subsequent FENCE commands are reached.
1678 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1683 SVGASignedPoint destOrigin
;
1684 SVGASignedRect srcRect
;
1686 } SVGAFifoCmdBlitScreenToGMRFB
;
1690 * SVGA_CMD_ANNOTATION_FILL --
1692 * This is a blit annotation. This command stores a small piece of
1693 * device state which is consumed by the next blit-to-screen
1694 * command. The state is only cleared by commands which are
1695 * specifically documented as consuming an annotation. Other
1696 * commands (such as ESCAPEs for debugging) may intervene between
1697 * the annotation and its associated blit.
1699 * This annotation is a promise about the contents of the next
1700 * blit: The video driver is guaranteeing that all pixels in that
1701 * blit will have the same value, specified here as a color in
1702 * SVGAColorBGRX format.
1704 * The SVGA device can still render the blit correctly even if it
1705 * ignores this annotation, but the annotation may allow it to
1706 * perform the blit more efficiently, for example by ignoring the
1707 * source data and performing a fill in hardware.
1709 * This annotation is most important for performance when the
1710 * user's display is being remoted over a network connection.
1713 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1718 SVGAColorBGRX color
;
1719 } SVGAFifoCmdAnnotationFill
;
1723 * SVGA_CMD_ANNOTATION_COPY --
1725 * This is a blit annotation. See SVGA_CMD_ANNOTATION_FILL for more
1726 * information about annotations.
1728 * This annotation is a promise about the contents of the next
1729 * blit: The video driver is guaranteeing that all pixels in that
1730 * blit will have the same value as those which already exist at an
1731 * identically-sized region on the same or a different screen.
1733 * Note that the source pixels for the COPY in this annotation are
1734 * sampled before applying the anqnotation's associated blit. They
1735 * are allowed to overlap with the blit's destination pixels.
1737 * The copy source rectangle is specified the same way as the blit
1738 * destination: it can be a rectangle which spans zero or more
1739 * screens, specified relative to either a screen or to the virtual
1740 * coordinate system's origin. If the source rectangle includes
1741 * pixels which are not from exactly one screen, the results are
1745 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1750 SVGASignedPoint srcOrigin
;
1752 } SVGAFifoCmdAnnotationCopy
;
1756 * SVGA_CMD_DEFINE_GMR2 --
1758 * Define guest memory region v2. See the description of GMRs above.
1768 } SVGAFifoCmdDefineGMR2
;
1772 * SVGA_CMD_REMAP_GMR2 --
1774 * Remap guest memory region v2. See the description of GMRs above.
1776 * This command allows guest to modify a portion of an existing GMR by
1777 * invalidating it or reassigning it to different guest physical pages.
1778 * The pages are identified by physical page number (PPN). The pages
1779 * are assumed to be pinned and valid for DMA operations.
1781 * Description of command flags:
1783 * SVGA_REMAP_GMR2_VIA_GMR: If enabled, references a PPN list in a GMR.
1784 * The PPN list must not overlap with the remap region (this can be
1785 * handled trivially by referencing a separate GMR). If flag is
1786 * disabled, PPN list is appended to SVGARemapGMR command.
1788 * SVGA_REMAP_GMR2_PPN64: If set, PPN list is in PPN64 format, otherwise
1789 * it is in PPN32 format.
1791 * SVGA_REMAP_GMR2_SINGLE_PPN: If set, PPN list contains a single entry.
1792 * A single PPN can be used to invalidate a portion of a GMR or
1793 * map it to to a single guest scratch page.
1800 SVGA_REMAP_GMR2_PPN32
= 0,
1801 SVGA_REMAP_GMR2_VIA_GMR
= (1 << 0),
1802 SVGA_REMAP_GMR2_PPN64
= (1 << 1),
1803 SVGA_REMAP_GMR2_SINGLE_PPN
= (1 << 2),
1804 } SVGARemapGMR2Flags
;
1809 SVGARemapGMR2Flags flags
;
1810 uint32 offsetPages
; // offset in pages to begin remap
1811 uint32 numPages
; // number of pages to remap
1813 * Followed by additional data depending on SVGARemapGMR2Flags.
1815 * If flag SVGA_REMAP_GMR2_VIA_GMR is set, single SVGAGuestPtr follows.
1816 * Otherwise an array of page descriptors in PPN32 or PPN64 format
1817 * (according to flag SVGA_REMAP_GMR2_PPN64) follows. If flag
1818 * SVGA_REMAP_GMR2_SINGLE_PPN is set, array contains a single entry.
1820 } SVGAFifoCmdRemapGMR2
;
1824 * Size of SVGA device memory such as frame buffer and FIFO.
1826 #define SVGA_VRAM_MIN_SIZE (4 * 640 * 480) // bytes
1827 #define SVGA_VRAM_MIN_SIZE_3D (16 * 1024 * 1024)
1828 #define SVGA_VRAM_MAX_SIZE (128 * 1024 * 1024)
1829 #define SVGA_MEMORY_SIZE_MAX (1024 * 1024 * 1024)
1830 #define SVGA_FIFO_SIZE_MAX (2 * 1024 * 1024)
1831 #define SVGA_GRAPHICS_MEMORY_KB_MIN (32 * 1024)
1832 #define SVGA_GRAPHICS_MEMORY_KB_MAX (2 * 1024 * 1024)
1833 #define SVGA_GRAPHICS_MEMORY_KB_DEFAULT (256 * 1024)
1835 #define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024) // 64 MB
1838 * To simplify autoDetect display configuration, support a minimum of
1839 * two 1920x1200 monitors, 32bpp, side-by-side, optionally rotated:
1841 * maxWidth = numDisplay * 1920 = 3840
1842 * maxHeight = rotated width of single monitor = 1920
1843 * vramSize = maxWidth * maxHeight * 4 = 29491200
1845 #define SVGA_VRAM_SIZE_AUTODETECT (32 * 1024 * 1024)
1847 #if defined(VMX86_SERVER)
1848 #define SVGA_VRAM_SIZE (4 * 1024 * 1024)
1849 #define SVGA_VRAM_SIZE_3D (64 * 1024 * 1024)
1850 #define SVGA_FIFO_SIZE (256 * 1024)
1851 #define SVGA_FIFO_SIZE_3D (516 * 1024) // Bump to 516KB to workaround WDDM driver issue (see bug# 744318)
1852 #define SVGA_MEMORY_SIZE_DEFAULT (160 * 1024 * 1024)
1853 #define SVGA_AUTODETECT_DEFAULT FALSE
1855 #define SVGA_VRAM_SIZE (16 * 1024 * 1024)
1856 #define SVGA_VRAM_SIZE_3D SVGA_VRAM_MAX_SIZE
1857 #define SVGA_FIFO_SIZE (2 * 1024 * 1024)
1858 #define SVGA_FIFO_SIZE_3D SVGA_FIFO_SIZE
1859 #define SVGA_MEMORY_SIZE_DEFAULT (768 * 1024 * 1024)
1860 #define SVGA_AUTODETECT_DEFAULT TRUE