projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
svga: add a separate function to get dx format capabilities from vgpu10 device
[mesa.git] / src / gallium / drivers / svga / svga_format.c
1 /**********************************************************
2 * Copyright 2011 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26
27 #include "pipe/p_format.h"
28 #include "util/u_debug.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31
32 #include "svga_winsys.h"
33 #include "svga_screen.h"
34 #include "svga_format.h"
35
36
37 /** Describes mapping from gallium formats to SVGA vertex/pixel formats */
38 struct vgpu10_format_entry
39 {
40 enum pipe_format pformat;
41 SVGA3dSurfaceFormat vertex_format;
42 SVGA3dSurfaceFormat pixel_format;
43 unsigned flags;
44 };
45
46 struct format_compat_entry
47 {
48 enum pipe_format pformat;
49 const SVGA3dSurfaceFormat *compat_format;
50 };
51
52
53 /**
54 * Table mapping Gallium formats to SVGA3d vertex/pixel formats.
55 * Note: the table is ordered according to PIPE_FORMAT_x order.
56 */
57 static const struct vgpu10_format_entry format_conversion_table[] =
58 {
59 /* Gallium format SVGA3D vertex format SVGA3D pixel format Flags */
60 { PIPE_FORMAT_NONE, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
61 { PIPE_FORMAT_B8G8R8A8_UNORM, SVGA3D_B8G8R8A8_UNORM, SVGA3D_B8G8R8A8_UNORM, TF_GEN_MIPS },
62 { PIPE_FORMAT_B8G8R8X8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8X8_UNORM, TF_GEN_MIPS },
63 { PIPE_FORMAT_A8R8G8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
64 { PIPE_FORMAT_X8R8G8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
65 { PIPE_FORMAT_B5G5R5A1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_B5G5R5A1_UNORM, TF_GEN_MIPS },
66 { PIPE_FORMAT_B4G4R4A4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
67 { PIPE_FORMAT_B5G6R5_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_B5G6R5_UNORM, TF_GEN_MIPS },
68 { PIPE_FORMAT_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, TF_GEN_MIPS },
69 { PIPE_FORMAT_L8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
70 { PIPE_FORMAT_A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_A8_UNORM, TF_GEN_MIPS },
71 { PIPE_FORMAT_I8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
72 { PIPE_FORMAT_L8A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
73 { PIPE_FORMAT_L16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
74 { PIPE_FORMAT_UYVY, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
75 { PIPE_FORMAT_YUYV, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
76 { PIPE_FORMAT_Z16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_D16_UNORM, 0 },
77 { PIPE_FORMAT_Z32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
78 { PIPE_FORMAT_Z32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_D32_FLOAT, 0 },
79 { PIPE_FORMAT_Z24_UNORM_S8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_D24_UNORM_S8_UINT, 0 },
80 { PIPE_FORMAT_S8_UINT_Z24_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
81 { PIPE_FORMAT_Z24X8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_D24_UNORM_S8_UINT, 0 },
82 { PIPE_FORMAT_X8Z24_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
83 { PIPE_FORMAT_S8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
84 { PIPE_FORMAT_R64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
85 { PIPE_FORMAT_R64G64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
86 { PIPE_FORMAT_R64G64B64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
87 { PIPE_FORMAT_R64G64B64A64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
88 { PIPE_FORMAT_R32_FLOAT, SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, TF_GEN_MIPS },
89 { PIPE_FORMAT_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, TF_GEN_MIPS },
90 { PIPE_FORMAT_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, TF_GEN_MIPS },
91 { PIPE_FORMAT_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, TF_GEN_MIPS },
92 { PIPE_FORMAT_R32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
93 { PIPE_FORMAT_R32G32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
94 { PIPE_FORMAT_R32G32B32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
95 { PIPE_FORMAT_R32G32B32A32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
96 { PIPE_FORMAT_R32_USCALED, SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
97 { PIPE_FORMAT_R32G32_USCALED, SVGA3D_R32G32_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
98 { PIPE_FORMAT_R32G32B32_USCALED, SVGA3D_R32G32B32_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
99 { PIPE_FORMAT_R32G32B32A32_USCALED, SVGA3D_R32G32B32A32_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
100 { PIPE_FORMAT_R32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
101 { PIPE_FORMAT_R32G32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
102 { PIPE_FORMAT_R32G32B32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
103 { PIPE_FORMAT_R32G32B32A32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
104 { PIPE_FORMAT_R32_SSCALED, SVGA3D_R32_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
105 { PIPE_FORMAT_R32G32_SSCALED, SVGA3D_R32G32_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
106 { PIPE_FORMAT_R32G32B32_SSCALED, SVGA3D_R32G32B32_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
107 { PIPE_FORMAT_R32G32B32A32_SSCALED, SVGA3D_R32G32B32A32_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
108 { PIPE_FORMAT_R16_UNORM, SVGA3D_R16_UNORM, SVGA3D_R16_UNORM, TF_GEN_MIPS },
109 { PIPE_FORMAT_R16G16_UNORM, SVGA3D_R16G16_UNORM, SVGA3D_R16G16_UNORM, TF_GEN_MIPS },
110 { PIPE_FORMAT_R16G16B16_UNORM, SVGA3D_R16G16B16A16_UNORM, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
111 { PIPE_FORMAT_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, TF_GEN_MIPS },
112 { PIPE_FORMAT_R16_USCALED, SVGA3D_R16_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
113 { PIPE_FORMAT_R16G16_USCALED, SVGA3D_R16G16_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
114 { PIPE_FORMAT_R16G16B16_USCALED, SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_U_TO_F_CAST },
115 { PIPE_FORMAT_R16G16B16A16_USCALED, SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
116 { PIPE_FORMAT_R16_SNORM, SVGA3D_R16_SNORM, SVGA3D_R16_SNORM, 0 },
117 { PIPE_FORMAT_R16G16_SNORM, SVGA3D_R16G16_SNORM, SVGA3D_R16G16_SNORM, 0 },
118 { PIPE_FORMAT_R16G16B16_SNORM, SVGA3D_R16G16B16A16_SNORM, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
119 { PIPE_FORMAT_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, 0 },
120 { PIPE_FORMAT_R16_SSCALED, SVGA3D_R16_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
121 { PIPE_FORMAT_R16G16_SSCALED, SVGA3D_R16G16_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
122 { PIPE_FORMAT_R16G16B16_SSCALED, SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_I_TO_F_CAST },
123 { PIPE_FORMAT_R16G16B16A16_SSCALED, SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
124 { PIPE_FORMAT_R8_UNORM, SVGA3D_R8_UNORM, SVGA3D_R8_UNORM, TF_GEN_MIPS },
125 { PIPE_FORMAT_R8G8_UNORM, SVGA3D_R8G8_UNORM, SVGA3D_R8G8_UNORM, TF_GEN_MIPS },
126 { PIPE_FORMAT_R8G8B8_UNORM, SVGA3D_R8G8B8A8_UNORM, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
127 { PIPE_FORMAT_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, TF_GEN_MIPS },
128 { PIPE_FORMAT_X8B8G8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
129 { PIPE_FORMAT_R8_USCALED, SVGA3D_R8_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
130 { PIPE_FORMAT_R8G8_USCALED, SVGA3D_R8G8_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
131 { PIPE_FORMAT_R8G8B8_USCALED, SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_U_TO_F_CAST },
132 { PIPE_FORMAT_R8G8B8A8_USCALED, SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
133 { 73, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
134 { PIPE_FORMAT_R8_SNORM, SVGA3D_R8_SNORM, SVGA3D_R8_SNORM, 0 },
135 { PIPE_FORMAT_R8G8_SNORM, SVGA3D_R8G8_SNORM, SVGA3D_R8G8_SNORM, 0 },
136 { PIPE_FORMAT_R8G8B8_SNORM, SVGA3D_R8G8B8A8_SNORM, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
137 { PIPE_FORMAT_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, 0 },
138 { 78, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
139 { 79, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
140 { 80, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
141 { 81, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
142 { PIPE_FORMAT_R8_SSCALED, SVGA3D_R8_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
143 { PIPE_FORMAT_R8G8_SSCALED, SVGA3D_R8G8_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
144 { PIPE_FORMAT_R8G8B8_SSCALED, SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_I_TO_F_CAST },
145 { PIPE_FORMAT_R8G8B8A8_SSCALED, SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
146 { 86, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
147 { PIPE_FORMAT_R32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
148 { PIPE_FORMAT_R32G32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
149 { PIPE_FORMAT_R32G32B32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
150 { PIPE_FORMAT_R32G32B32A32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
151 { PIPE_FORMAT_R16_FLOAT, SVGA3D_R16_FLOAT, SVGA3D_R16_FLOAT, TF_GEN_MIPS },
152 { PIPE_FORMAT_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, TF_GEN_MIPS },
153 { PIPE_FORMAT_R16G16B16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
154 { PIPE_FORMAT_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, TF_GEN_MIPS },
155 { PIPE_FORMAT_L8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
156 { PIPE_FORMAT_L8A8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
157 { PIPE_FORMAT_R8G8B8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
158 { PIPE_FORMAT_A8B8G8R8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
159 { PIPE_FORMAT_X8B8G8R8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
160 { PIPE_FORMAT_B8G8R8A8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8A8_UNORM_SRGB, TF_GEN_MIPS },
161 { PIPE_FORMAT_B8G8R8X8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8X8_UNORM_SRGB, TF_GEN_MIPS },
162 { PIPE_FORMAT_A8R8G8B8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
163 { PIPE_FORMAT_X8R8G8B8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
164 { PIPE_FORMAT_R8G8B8A8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_R8G8B8A8_UNORM_SRGB, TF_GEN_MIPS },
165 { PIPE_FORMAT_DXT1_RGB, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM, 0 },
166 { PIPE_FORMAT_DXT1_RGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM, 0 },
167 { PIPE_FORMAT_DXT3_RGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC2_UNORM, 0 },
168 { PIPE_FORMAT_DXT5_RGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC3_UNORM, 0 },
169 { PIPE_FORMAT_DXT1_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM_SRGB, 0 },
170 { PIPE_FORMAT_DXT1_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM_SRGB, 0 },
171 { PIPE_FORMAT_DXT3_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC2_UNORM_SRGB, 0 },
172 { PIPE_FORMAT_DXT5_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC3_UNORM_SRGB, 0 },
173 { PIPE_FORMAT_RGTC1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC4_UNORM, 0 },
174 { PIPE_FORMAT_RGTC1_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC4_SNORM, 0 },
175 { PIPE_FORMAT_RGTC2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC5_UNORM, 0 },
176 { PIPE_FORMAT_RGTC2_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC5_SNORM, 0 },
177 { PIPE_FORMAT_R8G8_B8G8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
178 { PIPE_FORMAT_G8R8_G8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
179 { PIPE_FORMAT_R8SG8SB8UX8U_NORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
180 { PIPE_FORMAT_R5SG5SB6U_NORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
181 { PIPE_FORMAT_A8B8G8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
182 { PIPE_FORMAT_B5G5R5X1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
183 { PIPE_FORMAT_R10G10B10A2_USCALED, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_USCALED },
184 { PIPE_FORMAT_R11G11B10_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_R11G11B10_FLOAT, TF_GEN_MIPS },
185 { PIPE_FORMAT_R9G9B9E5_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_R9G9B9E5_SHAREDEXP, 0 },
186 { PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_D32_FLOAT_S8X24_UINT, 0 },
187 { PIPE_FORMAT_R1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
188 { PIPE_FORMAT_R10G10B10X2_USCALED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
189 { PIPE_FORMAT_R10G10B10X2_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
190 { PIPE_FORMAT_L4A4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
191 { PIPE_FORMAT_B10G10R10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, VF_BGRA },
192 { PIPE_FORMAT_R10SG10SB10SA2U_NORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
193 { PIPE_FORMAT_R8G8Bx_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
194 { PIPE_FORMAT_R8G8B8X8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
195 { PIPE_FORMAT_B4G4R4X4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
196 { PIPE_FORMAT_X24S8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
197 { PIPE_FORMAT_S8X24_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
198 { PIPE_FORMAT_X32_S8X24_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
199 { PIPE_FORMAT_B2G3R3_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
200 { PIPE_FORMAT_L16A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
201 { PIPE_FORMAT_A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
202 { PIPE_FORMAT_I16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
203 { PIPE_FORMAT_LATC1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
204 { PIPE_FORMAT_LATC1_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
205 { PIPE_FORMAT_LATC2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
206 { PIPE_FORMAT_LATC2_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
207 { PIPE_FORMAT_A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
208 { PIPE_FORMAT_L8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
209 { PIPE_FORMAT_L8A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
210 { PIPE_FORMAT_I8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
211 { PIPE_FORMAT_A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
212 { PIPE_FORMAT_L16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
213 { PIPE_FORMAT_L16A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
214 { PIPE_FORMAT_I16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
215 { PIPE_FORMAT_A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
216 { PIPE_FORMAT_L16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
217 { PIPE_FORMAT_L16A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
218 { PIPE_FORMAT_I16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
219 { PIPE_FORMAT_A32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
220 { PIPE_FORMAT_L32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
221 { PIPE_FORMAT_L32A32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
222 { PIPE_FORMAT_I32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
223 { PIPE_FORMAT_YV12, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
224 { PIPE_FORMAT_YV16, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
225 { PIPE_FORMAT_IYUV, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
226 { PIPE_FORMAT_NV12, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
227 { PIPE_FORMAT_NV21, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
228 { PIPE_FORMAT_A4R4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
229 { PIPE_FORMAT_R4A4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
230 { PIPE_FORMAT_R8A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
231 { PIPE_FORMAT_A8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
232 { PIPE_FORMAT_R10G10B10A2_SSCALED, SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_SSCALED },
233 { PIPE_FORMAT_R10G10B10A2_SNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_SNORM },
234 { PIPE_FORMAT_B10G10R10A2_USCALED, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_USCALED },
235 { PIPE_FORMAT_B10G10R10A2_SSCALED, SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_SSCALED },
236 { PIPE_FORMAT_B10G10R10A2_SNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_SNORM },
237 { PIPE_FORMAT_R8_UINT, SVGA3D_R8_UINT, SVGA3D_R8_UINT, 0 },
238 { PIPE_FORMAT_R8G8_UINT, SVGA3D_R8G8_UINT, SVGA3D_R8G8_UINT, 0 },
239 { PIPE_FORMAT_R8G8B8_UINT, SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
240 { PIPE_FORMAT_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, 0 },
241 { PIPE_FORMAT_R8_SINT, SVGA3D_R8_SINT, SVGA3D_R8_SINT, 0 },
242 { PIPE_FORMAT_R8G8_SINT, SVGA3D_R8G8_SINT, SVGA3D_R8G8_SINT, 0 },
243 { PIPE_FORMAT_R8G8B8_SINT, SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
244 { PIPE_FORMAT_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, 0 },
245 { PIPE_FORMAT_R16_UINT, SVGA3D_R16_UINT, SVGA3D_R16_UINT, 0 },
246 { PIPE_FORMAT_R16G16_UINT, SVGA3D_R16G16_UINT, SVGA3D_R16G16_UINT, 0 },
247 { PIPE_FORMAT_R16G16B16_UINT, SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
248 { PIPE_FORMAT_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, 0 },
249 { PIPE_FORMAT_R16_SINT, SVGA3D_R16_SINT, SVGA3D_R16_SINT, 0 },
250 { PIPE_FORMAT_R16G16_SINT, SVGA3D_R16G16_SINT, SVGA3D_R16G16_SINT, 0 },
251 { PIPE_FORMAT_R16G16B16_SINT, SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
252 { PIPE_FORMAT_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, 0 },
253 { PIPE_FORMAT_R32_UINT, SVGA3D_R32_UINT, SVGA3D_R32_UINT, 0 },
254 { PIPE_FORMAT_R32G32_UINT, SVGA3D_R32G32_UINT, SVGA3D_R32G32_UINT, 0 },
255 { PIPE_FORMAT_R32G32B32_UINT, SVGA3D_R32G32B32_UINT, SVGA3D_FORMAT_INVALID, 0 },
256 { PIPE_FORMAT_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, 0 },
257 { PIPE_FORMAT_R32_SINT, SVGA3D_R32_SINT, SVGA3D_R32_SINT, 0 },
258 { PIPE_FORMAT_R32G32_SINT, SVGA3D_R32G32_SINT, SVGA3D_R32G32_SINT, 0 },
259 { PIPE_FORMAT_R32G32B32_SINT, SVGA3D_R32G32B32_SINT, SVGA3D_FORMAT_INVALID, 0 },
260 { PIPE_FORMAT_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, 0 },
261 { PIPE_FORMAT_A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
262 { PIPE_FORMAT_I8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
263 { PIPE_FORMAT_L8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
264 { PIPE_FORMAT_L8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
265 { PIPE_FORMAT_A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
266 { PIPE_FORMAT_I8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
267 { PIPE_FORMAT_L8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
268 { PIPE_FORMAT_L8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
269 { PIPE_FORMAT_A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
270 { PIPE_FORMAT_I16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
271 { PIPE_FORMAT_L16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
272 { PIPE_FORMAT_L16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
273 { PIPE_FORMAT_A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
274 { PIPE_FORMAT_I16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
275 { PIPE_FORMAT_L16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
276 { PIPE_FORMAT_L16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
277 { PIPE_FORMAT_A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
278 { PIPE_FORMAT_I32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
279 { PIPE_FORMAT_L32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
280 { PIPE_FORMAT_L32A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
281 { PIPE_FORMAT_A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
282 { PIPE_FORMAT_I32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
283 { PIPE_FORMAT_L32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
284 { PIPE_FORMAT_L32A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
285 { PIPE_FORMAT_B10G10R10A2_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
286 { PIPE_FORMAT_ETC1_RGB8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
287 { PIPE_FORMAT_R8G8_R8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
288 { PIPE_FORMAT_G8R8_B8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
289 { PIPE_FORMAT_R8G8B8X8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
290 { PIPE_FORMAT_R8G8B8X8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
291 { PIPE_FORMAT_R8G8B8X8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
292 { PIPE_FORMAT_R8G8B8X8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
293 { PIPE_FORMAT_B10G10R10X2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
294 { PIPE_FORMAT_R16G16B16X16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
295 { PIPE_FORMAT_R16G16B16X16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
296 { PIPE_FORMAT_R16G16B16X16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
297 { PIPE_FORMAT_R16G16B16X16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
298 { PIPE_FORMAT_R16G16B16X16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
299 { PIPE_FORMAT_R32G32B32X32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
300 { PIPE_FORMAT_R32G32B32X32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
301 { PIPE_FORMAT_R32G32B32X32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
302 { PIPE_FORMAT_R8A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
303 { PIPE_FORMAT_R16A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
304 { PIPE_FORMAT_R16A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
305 { PIPE_FORMAT_R16A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
306 { PIPE_FORMAT_R32A32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
307 { PIPE_FORMAT_R8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
308 { PIPE_FORMAT_R8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
309 { PIPE_FORMAT_R16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
310 { PIPE_FORMAT_R16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
311 { PIPE_FORMAT_R32A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
312 { PIPE_FORMAT_R32A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
313 { PIPE_FORMAT_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, 0 },
314 { PIPE_FORMAT_B5G6R5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
315 { PIPE_FORMAT_BPTC_RGBA_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
316 { PIPE_FORMAT_BPTC_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
317 { PIPE_FORMAT_BPTC_RGB_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
318 { PIPE_FORMAT_BPTC_RGB_UFLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
319 { PIPE_FORMAT_A8L8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
320 { PIPE_FORMAT_A8L8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
321 { PIPE_FORMAT_A8L8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
322 { PIPE_FORMAT_A16L16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
323 { PIPE_FORMAT_G8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
324 { PIPE_FORMAT_G8R8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
325 { PIPE_FORMAT_G16R16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
326 { PIPE_FORMAT_G16R16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
327 { PIPE_FORMAT_A8B8G8R8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
328 { PIPE_FORMAT_X8B8G8R8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
329 { PIPE_FORMAT_ETC2_RGB8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
330 { PIPE_FORMAT_ETC2_SRGB8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
331 { PIPE_FORMAT_ETC2_RGB8A1, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
332 { PIPE_FORMAT_ETC2_SRGB8A1, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
333 { PIPE_FORMAT_ETC2_RGBA8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
334 { PIPE_FORMAT_ETC2_SRGBA8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
335 { PIPE_FORMAT_ETC2_R11_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
336 { PIPE_FORMAT_ETC2_R11_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
337 { PIPE_FORMAT_ETC2_RG11_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
338 { PIPE_FORMAT_ETC2_RG11_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
339 { PIPE_FORMAT_ASTC_4x4, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
340 { PIPE_FORMAT_ASTC_5x4, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
341 { PIPE_FORMAT_ASTC_5x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
342 { PIPE_FORMAT_ASTC_6x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
343 { PIPE_FORMAT_ASTC_6x6, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
344 { PIPE_FORMAT_ASTC_8x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
345 { PIPE_FORMAT_ASTC_8x6, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
346 { PIPE_FORMAT_ASTC_8x8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
347 { PIPE_FORMAT_ASTC_10x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
348 { PIPE_FORMAT_ASTC_10x6, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
349 { PIPE_FORMAT_ASTC_10x8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
350 { PIPE_FORMAT_ASTC_10x10, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
351 { PIPE_FORMAT_ASTC_12x10, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
352 { PIPE_FORMAT_ASTC_12x12, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
353 { PIPE_FORMAT_ASTC_4x4_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
354 { PIPE_FORMAT_ASTC_5x4_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
355 { PIPE_FORMAT_ASTC_5x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
356 { PIPE_FORMAT_ASTC_6x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
357 { PIPE_FORMAT_ASTC_6x6_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
358 { PIPE_FORMAT_ASTC_8x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
359 { PIPE_FORMAT_ASTC_8x6_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
360 { PIPE_FORMAT_ASTC_8x8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
361 { PIPE_FORMAT_ASTC_10x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
362 { PIPE_FORMAT_ASTC_10x6_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
363 { PIPE_FORMAT_ASTC_10x8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
364 { PIPE_FORMAT_ASTC_10x10_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
365 { PIPE_FORMAT_ASTC_12x10_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
366 { PIPE_FORMAT_ASTC_12x12_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
367 { PIPE_FORMAT_P016, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
368 { PIPE_FORMAT_R10G10B10X2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
369 { PIPE_FORMAT_A1B5G5R5_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
370 { PIPE_FORMAT_X1B5G5R5_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
371 { PIPE_FORMAT_A4B4G4R4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
372 };
373
374
375 /**
376 * Translate a gallium vertex format to a vgpu10 vertex format.
377 * Also, return any special vertex format flags.
378 */
379 void
380 svga_translate_vertex_format_vgpu10(enum pipe_format format,
381 SVGA3dSurfaceFormat *svga_format,
382 unsigned *vf_flags)
383 {
384 assert(format < ARRAY_SIZE(format_conversion_table));
385 if (format >= ARRAY_SIZE(format_conversion_table)) {
386 format = PIPE_FORMAT_NONE;
387 }
388 *svga_format = format_conversion_table[format].vertex_format;
389 *vf_flags = format_conversion_table[format].flags;
390 }
391
392
393 /**
394 * Translate a gallium scanout format to a svga format valid
395 * for screen target surface.
396 */
397 static SVGA3dSurfaceFormat
398 svga_translate_screen_target_format_vgpu10(enum pipe_format format)
399 {
400 switch (format) {
401 case PIPE_FORMAT_B8G8R8A8_UNORM:
402 return SVGA3D_B8G8R8A8_UNORM;
403 case PIPE_FORMAT_B8G8R8X8_UNORM:
404 return SVGA3D_B8G8R8X8_UNORM;
405 case PIPE_FORMAT_B5G6R5_UNORM:
406 return SVGA3D_R5G6B5;
407 case PIPE_FORMAT_B5G5R5A1_UNORM:
408 return SVGA3D_A1R5G5B5;
409 default:
410 debug_printf("Invalid format %s specified for screen target\n",
411 svga_format_name(format));
412 return SVGA3D_FORMAT_INVALID;
413 }
414 }
415
416 /*
417 * Translate from gallium format to SVGA3D format.
418 */
419 SVGA3dSurfaceFormat
420 svga_translate_format(const struct svga_screen *ss,
421 enum pipe_format format,
422 unsigned bind)
423 {
424 if (ss->sws->have_vgpu10) {
425 if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) {
426 return format_conversion_table[format].vertex_format;
427 }
428 else if (bind & PIPE_BIND_SCANOUT) {
429 return svga_translate_screen_target_format_vgpu10(format);
430 }
431 else {
432 return format_conversion_table[format].pixel_format;
433 }
434 }
435
436 switch(format) {
437 case PIPE_FORMAT_B8G8R8A8_UNORM:
438 return SVGA3D_A8R8G8B8;
439 case PIPE_FORMAT_B8G8R8X8_UNORM:
440 return SVGA3D_X8R8G8B8;
441
442 /* sRGB required for GL2.1 */
443 case PIPE_FORMAT_B8G8R8A8_SRGB:
444 return SVGA3D_A8R8G8B8;
445 case PIPE_FORMAT_DXT1_SRGB:
446 case PIPE_FORMAT_DXT1_SRGBA:
447 return SVGA3D_DXT1;
448 case PIPE_FORMAT_DXT3_SRGBA:
449 return SVGA3D_DXT3;
450 case PIPE_FORMAT_DXT5_SRGBA:
451 return SVGA3D_DXT5;
452
453 case PIPE_FORMAT_B5G6R5_UNORM:
454 return SVGA3D_R5G6B5;
455 case PIPE_FORMAT_B5G5R5A1_UNORM:
456 return SVGA3D_A1R5G5B5;
457 case PIPE_FORMAT_B4G4R4A4_UNORM:
458 return SVGA3D_A4R4G4B4;
459
460 case PIPE_FORMAT_R16G16B16A16_UNORM:
461 return SVGA3D_A16B16G16R16;
462
463 case PIPE_FORMAT_Z16_UNORM:
464 assert(!ss->sws->have_vgpu10);
465 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.z16 : SVGA3D_Z_D16;
466 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
467 assert(!ss->sws->have_vgpu10);
468 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.s8z24 : SVGA3D_Z_D24S8;
469 case PIPE_FORMAT_X8Z24_UNORM:
470 assert(!ss->sws->have_vgpu10);
471 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.x8z24 : SVGA3D_Z_D24X8;
472
473 case PIPE_FORMAT_A8_UNORM:
474 return SVGA3D_ALPHA8;
475 case PIPE_FORMAT_L8_UNORM:
476 return SVGA3D_LUMINANCE8;
477
478 case PIPE_FORMAT_DXT1_RGB:
479 case PIPE_FORMAT_DXT1_RGBA:
480 return SVGA3D_DXT1;
481 case PIPE_FORMAT_DXT3_RGBA:
482 return SVGA3D_DXT3;
483 case PIPE_FORMAT_DXT5_RGBA:
484 return SVGA3D_DXT5;
485
486 /* Float formats (only 1, 2 and 4-component formats supported) */
487 case PIPE_FORMAT_R32_FLOAT:
488 return SVGA3D_R_S23E8;
489 case PIPE_FORMAT_R32G32_FLOAT:
490 return SVGA3D_RG_S23E8;
491 case PIPE_FORMAT_R32G32B32A32_FLOAT:
492 return SVGA3D_ARGB_S23E8;
493 case PIPE_FORMAT_R16_FLOAT:
494 return SVGA3D_R_S10E5;
495 case PIPE_FORMAT_R16G16_FLOAT:
496 return SVGA3D_RG_S10E5;
497 case PIPE_FORMAT_R16G16B16A16_FLOAT:
498 return SVGA3D_ARGB_S10E5;
499
500 case PIPE_FORMAT_Z32_UNORM:
501 /* SVGA3D_Z_D32 is not yet unsupported */
502 /* fall-through */
503 default:
504 return SVGA3D_FORMAT_INVALID;
505 }
506 }
507
508
509 /*
510 * Format capability description entry.
511 */
512 struct format_cap {
513 const char *name;
514
515 SVGA3dSurfaceFormat format;
516
517 /*
518 * Capability index corresponding to the format.
519 */
520 SVGA3dDevCapIndex devcap;
521
522 /* size of each pixel/block */
523 unsigned block_width, block_height, block_bytes;
524
525 /*
526 * Mask of supported SVGA3dFormatOp operations, to be inferred when the
527 * capability is not explicitly present.
528 */
529 uint32 defaultOperations;
530 };
531
532
533 /*
534 * Format capability description table.
535 *
536 * Ordered by increasing SVGA3dSurfaceFormat value, but with gaps.
537 *
538 * Note: there are some special cases below where we set devcap=0 and
539 * avoid querying the host. In particular, depth/stencil formats which
540 * can be rendered to and sampled from. For example, the gallium format
541 * PIPE_FORMAT_Z24_UNORM_S8_UINT is converted to SVGA3D_D24_UNORM_S8_UINT
542 * for rendering but converted to SVGA3D_R24_UNORM_X8 for sampling.
543 * If we want to query if a format supports both rendering and sampling the
544 * host will tell us no for SVGA3D_D24_UNORM_S8_UINT, SVGA3D_D16_UNORM and
545 * SVGA3D_R24_UNORM_X8. So we override the host query for those
546 * formats and report that both can do rendering and sampling.
547 */
548 static const struct format_cap format_cap_table[] = {
549 {
550 "SVGA3D_FORMAT_INVALID",
551 SVGA3D_FORMAT_INVALID, 0, 0, 0, 0, 0
552 },
553 {
554 "SVGA3D_X8R8G8B8",
555 SVGA3D_X8R8G8B8,
556 SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8,
557 1, 1, 4,
558 SVGA3DFORMAT_OP_TEXTURE |
559 SVGA3DFORMAT_OP_CUBETEXTURE |
560 SVGA3DFORMAT_OP_VOLUMETEXTURE |
561 SVGA3DFORMAT_OP_DISPLAYMODE |
562 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
563 },
564 {
565 "SVGA3D_A8R8G8B8",
566 SVGA3D_A8R8G8B8,
567 SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8,
568 1, 1, 4,
569 SVGA3DFORMAT_OP_TEXTURE |
570 SVGA3DFORMAT_OP_CUBETEXTURE |
571 SVGA3DFORMAT_OP_VOLUMETEXTURE |
572 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
573 },
574 {
575 "SVGA3D_R5G6B5",
576 SVGA3D_R5G6B5,
577 SVGA3D_DEVCAP_SURFACEFMT_R5G6B5,
578 1, 1, 2,
579 SVGA3DFORMAT_OP_TEXTURE |
580 SVGA3DFORMAT_OP_CUBETEXTURE |
581 SVGA3DFORMAT_OP_VOLUMETEXTURE |
582 SVGA3DFORMAT_OP_DISPLAYMODE |
583 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
584 },
585 {
586 "SVGA3D_X1R5G5B5",
587 SVGA3D_X1R5G5B5,
588 SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5,
589 1, 1, 2,
590 SVGA3DFORMAT_OP_TEXTURE |
591 SVGA3DFORMAT_OP_CUBETEXTURE |
592 SVGA3DFORMAT_OP_VOLUMETEXTURE |
593 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
594 },
595 {
596 "SVGA3D_A1R5G5B5",
597 SVGA3D_A1R5G5B5,
598 SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5,
599 1, 1, 2,
600 SVGA3DFORMAT_OP_TEXTURE |
601 SVGA3DFORMAT_OP_CUBETEXTURE |
602 SVGA3DFORMAT_OP_VOLUMETEXTURE |
603 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
604 },
605 {
606 "SVGA3D_A4R4G4B4",
607 SVGA3D_A4R4G4B4,
608 SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4,
609 1, 1, 2,
610 SVGA3DFORMAT_OP_TEXTURE |
611 SVGA3DFORMAT_OP_CUBETEXTURE |
612 SVGA3DFORMAT_OP_VOLUMETEXTURE |
613 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
614 },
615 {
616 /*
617 * SVGA3D_Z_D32 is not yet supported, and has no corresponding
618 * SVGA3D_DEVCAP_xxx.
619 */
620 "SVGA3D_Z_D32",
621 SVGA3D_Z_D32, 0, 0, 0, 0, 0
622 },
623 {
624 "SVGA3D_Z_D16",
625 SVGA3D_Z_D16,
626 SVGA3D_DEVCAP_SURFACEFMT_Z_D16,
627 1, 1, 2,
628 SVGA3DFORMAT_OP_ZSTENCIL
629 },
630 {
631 "SVGA3D_Z_D24S8",
632 SVGA3D_Z_D24S8,
633 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8,
634 1, 1, 4,
635 SVGA3DFORMAT_OP_ZSTENCIL
636 },
637 {
638 "SVGA3D_Z_D15S1",
639 SVGA3D_Z_D15S1,
640 SVGA3D_DEVCAP_MAX,
641 1, 1, 2,
642 SVGA3DFORMAT_OP_ZSTENCIL
643 },
644 {
645 "SVGA3D_LUMINANCE8",
646 SVGA3D_LUMINANCE8,
647 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8,
648 1, 1, 1,
649 SVGA3DFORMAT_OP_TEXTURE |
650 SVGA3DFORMAT_OP_CUBETEXTURE |
651 SVGA3DFORMAT_OP_VOLUMETEXTURE
652 },
653 {
654 /*
655 * SVGA3D_LUMINANCE4_ALPHA4 is not supported, and has no corresponding
656 * SVGA3D_DEVCAP_xxx.
657 */
658 "SVGA3D_LUMINANCE4_ALPHA4",
659 SVGA3D_LUMINANCE4_ALPHA4, 0, 0, 0, 0, 0
660 },
661 {
662 "SVGA3D_LUMINANCE16",
663 SVGA3D_LUMINANCE16,
664 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16,
665 1, 1, 2,
666 SVGA3DFORMAT_OP_TEXTURE |
667 SVGA3DFORMAT_OP_CUBETEXTURE |
668 SVGA3DFORMAT_OP_VOLUMETEXTURE
669 },
670 {
671 "SVGA3D_LUMINANCE8_ALPHA8",
672 SVGA3D_LUMINANCE8_ALPHA8,
673 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8,
674 1, 1, 2,
675 SVGA3DFORMAT_OP_TEXTURE |
676 SVGA3DFORMAT_OP_CUBETEXTURE |
677 SVGA3DFORMAT_OP_VOLUMETEXTURE
678 },
679 {
680 "SVGA3D_DXT1",
681 SVGA3D_DXT1,
682 SVGA3D_DEVCAP_SURFACEFMT_DXT1,
683 4, 4, 8,
684 SVGA3DFORMAT_OP_TEXTURE |
685 SVGA3DFORMAT_OP_CUBETEXTURE
686 },
687 {
688 "SVGA3D_DXT2",
689 SVGA3D_DXT2,
690 SVGA3D_DEVCAP_SURFACEFMT_DXT2,
691 4, 4, 8,
692 SVGA3DFORMAT_OP_TEXTURE |
693 SVGA3DFORMAT_OP_CUBETEXTURE
694 },
695 {
696 "SVGA3D_DXT3",
697 SVGA3D_DXT3,
698 SVGA3D_DEVCAP_SURFACEFMT_DXT3,
699 4, 4, 16,
700 SVGA3DFORMAT_OP_TEXTURE |
701 SVGA3DFORMAT_OP_CUBETEXTURE
702 },
703 {
704 "SVGA3D_DXT4",
705 SVGA3D_DXT4,
706 SVGA3D_DEVCAP_SURFACEFMT_DXT4,
707 4, 4, 16,
708 SVGA3DFORMAT_OP_TEXTURE |
709 SVGA3DFORMAT_OP_CUBETEXTURE
710 },
711 {
712 "SVGA3D_DXT5",
713 SVGA3D_DXT5,
714 SVGA3D_DEVCAP_SURFACEFMT_DXT5,
715 4, 4, 8,
716 SVGA3DFORMAT_OP_TEXTURE |
717 SVGA3DFORMAT_OP_CUBETEXTURE
718 },
719 {
720 "SVGA3D_BUMPU8V8",
721 SVGA3D_BUMPU8V8,
722 SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8,
723 1, 1, 2,
724 SVGA3DFORMAT_OP_TEXTURE |
725 SVGA3DFORMAT_OP_CUBETEXTURE |
726 SVGA3DFORMAT_OP_VOLUMETEXTURE
727 },
728 {
729 /*
730 * SVGA3D_BUMPL6V5U5 is unsupported; it has no corresponding
731 * SVGA3D_DEVCAP_xxx.
732 */
733 "SVGA3D_BUMPL6V5U5",
734 SVGA3D_BUMPL6V5U5, 0, 0, 0, 0, 0
735 },
736 {
737 "SVGA3D_BUMPX8L8V8U8",
738 SVGA3D_BUMPX8L8V8U8,
739 SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8,
740 1, 1, 4,
741 SVGA3DFORMAT_OP_TEXTURE |
742 SVGA3DFORMAT_OP_CUBETEXTURE
743 },
744 {
745 "SVGA3D_FORMAT_DEAD1",
746 SVGA3D_FORMAT_DEAD1, 0, 0, 0, 0, 0
747 },
748 {
749 "SVGA3D_ARGB_S10E5",
750 SVGA3D_ARGB_S10E5,
751 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5,
752 1, 1, 2,
753 SVGA3DFORMAT_OP_TEXTURE |
754 SVGA3DFORMAT_OP_CUBETEXTURE |
755 SVGA3DFORMAT_OP_VOLUMETEXTURE |
756 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
757 },
758 {
759 "SVGA3D_ARGB_S23E8",
760 SVGA3D_ARGB_S23E8,
761 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8,
762 1, 1, 4,
763 SVGA3DFORMAT_OP_TEXTURE |
764 SVGA3DFORMAT_OP_CUBETEXTURE |
765 SVGA3DFORMAT_OP_VOLUMETEXTURE |
766 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
767 },
768 {
769 "SVGA3D_A2R10G10B10",
770 SVGA3D_A2R10G10B10,
771 SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10,
772 1, 1, 4,
773 SVGA3DFORMAT_OP_TEXTURE |
774 SVGA3DFORMAT_OP_CUBETEXTURE |
775 SVGA3DFORMAT_OP_VOLUMETEXTURE |
776 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
777 },
778 {
779 /*
780 * SVGA3D_V8U8 is unsupported; it has no corresponding
781 * SVGA3D_DEVCAP_xxx. SVGA3D_BUMPU8V8 should be used instead.
782 */
783 "SVGA3D_V8U8",
784 SVGA3D_V8U8, 0, 0, 0, 0, 0
785 },
786 {
787 "SVGA3D_Q8W8V8U8",
788 SVGA3D_Q8W8V8U8,
789 SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8,
790 1, 1, 4,
791 SVGA3DFORMAT_OP_TEXTURE |
792 SVGA3DFORMAT_OP_CUBETEXTURE
793 },
794 {
795 "SVGA3D_CxV8U8",
796 SVGA3D_CxV8U8,
797 SVGA3D_DEVCAP_SURFACEFMT_CxV8U8,
798 1, 1, 2,
799 SVGA3DFORMAT_OP_TEXTURE
800 },
801 {
802 /*
803 * SVGA3D_X8L8V8U8 is unsupported; it has no corresponding
804 * SVGA3D_DEVCAP_xxx. SVGA3D_BUMPX8L8V8U8 should be used instead.
805 */
806 "SVGA3D_X8L8V8U8",
807 SVGA3D_X8L8V8U8, 0, 0, 0, 0, 0
808 },
809 {
810 "SVGA3D_A2W10V10U10",
811 SVGA3D_A2W10V10U10,
812 SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10,
813 1, 1, 4,
814 SVGA3DFORMAT_OP_TEXTURE
815 },
816 {
817 "SVGA3D_ALPHA8",
818 SVGA3D_ALPHA8,
819 SVGA3D_DEVCAP_SURFACEFMT_ALPHA8,
820 1, 1, 1,
821 SVGA3DFORMAT_OP_TEXTURE |
822 SVGA3DFORMAT_OP_CUBETEXTURE |
823 SVGA3DFORMAT_OP_VOLUMETEXTURE
824 },
825 {
826 "SVGA3D_R_S10E5",
827 SVGA3D_R_S10E5,
828 SVGA3D_DEVCAP_SURFACEFMT_R_S10E5,
829 1, 1, 2,
830 SVGA3DFORMAT_OP_TEXTURE |
831 SVGA3DFORMAT_OP_VOLUMETEXTURE |
832 SVGA3DFORMAT_OP_CUBETEXTURE |
833 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
834 },
835 {
836 "SVGA3D_R_S23E8",
837 SVGA3D_R_S23E8,
838 SVGA3D_DEVCAP_SURFACEFMT_R_S23E8,
839 1, 1, 4,
840 SVGA3DFORMAT_OP_TEXTURE |
841 SVGA3DFORMAT_OP_VOLUMETEXTURE |
842 SVGA3DFORMAT_OP_CUBETEXTURE |
843 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
844 },
845 {
846 "SVGA3D_RG_S10E5",
847 SVGA3D_RG_S10E5,
848 SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5,
849 1, 1, 2,
850 SVGA3DFORMAT_OP_TEXTURE |
851 SVGA3DFORMAT_OP_VOLUMETEXTURE |
852 SVGA3DFORMAT_OP_CUBETEXTURE |
853 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
854 },
855 {
856 "SVGA3D_RG_S23E8",
857 SVGA3D_RG_S23E8,
858 SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8,
859 1, 1, 4,
860 SVGA3DFORMAT_OP_TEXTURE |
861 SVGA3DFORMAT_OP_VOLUMETEXTURE |
862 SVGA3DFORMAT_OP_CUBETEXTURE |
863 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
864 },
865 {
866 /*
867 * SVGA3D_BUFFER is a placeholder format for index/vertex buffers.
868 */
869 "SVGA3D_BUFFER",
870 SVGA3D_BUFFER, 0, 1, 1, 1, 0
871 },
872 {
873 "SVGA3D_Z_D24X8",
874 SVGA3D_Z_D24X8,
875 SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8,
876 1, 1, 4,
877 SVGA3DFORMAT_OP_ZSTENCIL
878 },
879 {
880 "SVGA3D_V16U16",
881 SVGA3D_V16U16,
882 SVGA3D_DEVCAP_SURFACEFMT_V16U16,
883 1, 1, 4,
884 SVGA3DFORMAT_OP_TEXTURE |
885 SVGA3DFORMAT_OP_CUBETEXTURE |
886 SVGA3DFORMAT_OP_VOLUMETEXTURE
887 },
888 {
889 "SVGA3D_G16R16",
890 SVGA3D_G16R16,
891 SVGA3D_DEVCAP_SURFACEFMT_G16R16,
892 1, 1, 4,
893 SVGA3DFORMAT_OP_TEXTURE |
894 SVGA3DFORMAT_OP_CUBETEXTURE |
895 SVGA3DFORMAT_OP_VOLUMETEXTURE |
896 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
897 },
898 {
899 "SVGA3D_A16B16G16R16",
900 SVGA3D_A16B16G16R16,
901 SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16,
902 1, 1, 8,
903 SVGA3DFORMAT_OP_TEXTURE |
904 SVGA3DFORMAT_OP_CUBETEXTURE |
905 SVGA3DFORMAT_OP_VOLUMETEXTURE |
906 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
907 },
908 {
909 "SVGA3D_UYVY",
910 SVGA3D_UYVY,
911 SVGA3D_DEVCAP_SURFACEFMT_UYVY,
912 0, 0, 0, 0
913 },
914 {
915 "SVGA3D_YUY2",
916 SVGA3D_YUY2,
917 SVGA3D_DEVCAP_SURFACEFMT_YUY2,
918 0, 0, 0, 0
919 },
920 {
921 "SVGA3D_NV12",
922 SVGA3D_NV12,
923 SVGA3D_DEVCAP_SURFACEFMT_NV12,
924 0, 0, 0, 0
925 },
926 {
927 "SVGA3D_AYUV",
928 SVGA3D_AYUV,
929 SVGA3D_DEVCAP_SURFACEFMT_AYUV,
930 0, 0, 0, 0
931 },
932 {
933 "SVGA3D_R32G32B32A32_TYPELESS",
934 SVGA3D_R32G32B32A32_TYPELESS,
935 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS,
936 1, 1, 16, 0
937 },
938 {
939 "SVGA3D_R32G32B32A32_UINT",
940 SVGA3D_R32G32B32A32_UINT,
941 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT,
942 1, 1, 16, 0
943 },
944 {
945 "SVGA3D_R32G32B32A32_SINT",
946 SVGA3D_R32G32B32A32_SINT,
947 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT,
948 1, 1, 16, 0
949 },
950 {
951 "SVGA3D_R32G32B32_TYPELESS",
952 SVGA3D_R32G32B32_TYPELESS,
953 SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS,
954 1, 1, 12, 0
955 },
956 {
957 "SVGA3D_R32G32B32_FLOAT",
958 SVGA3D_R32G32B32_FLOAT,
959 SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT,
960 1, 1, 12, 0
961 },
962 {
963 "SVGA3D_R32G32B32_UINT",
964 SVGA3D_R32G32B32_UINT,
965 SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT,
966 1, 1, 12, 0
967 },
968 {
969 "SVGA3D_R32G32B32_SINT",
970 SVGA3D_R32G32B32_SINT,
971 SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT,
972 1, 1, 12, 0
973 },
974 {
975 "SVGA3D_R16G16B16A16_TYPELESS",
976 SVGA3D_R16G16B16A16_TYPELESS,
977 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS,
978 1, 1, 8, 0
979 },
980 {
981 "SVGA3D_R16G16B16A16_UINT",
982 SVGA3D_R16G16B16A16_UINT,
983 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT,
984 1, 1, 8, 0
985 },
986 {
987 "SVGA3D_R16G16B16A16_SNORM",
988 SVGA3D_R16G16B16A16_SNORM,
989 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM,
990 1, 1, 8, 0
991 },
992 {
993 "SVGA3D_R16G16B16A16_SINT",
994 SVGA3D_R16G16B16A16_SINT,
995 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT,
996 1, 1, 8, 0
997 },
998 {
999 "SVGA3D_R32G32_TYPELESS",
1000 SVGA3D_R32G32_TYPELESS,
1001 SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS,
1002 1, 1, 8, 0
1003 },
1004 {
1005 "SVGA3D_R32G32_UINT",
1006 SVGA3D_R32G32_UINT,
1007 SVGA3D_DEVCAP_DXFMT_R32G32_UINT,
1008 1, 1, 8, 0
1009 },
1010 {
1011 "SVGA3D_R32G32_SINT",
1012 SVGA3D_R32G32_SINT,
1013 SVGA3D_DEVCAP_DXFMT_R32G32_SINT,
1014 1, 1, 8,
1015 0
1016 },
1017 {
1018 "SVGA3D_R32G8X24_TYPELESS",
1019 SVGA3D_R32G8X24_TYPELESS,
1020 SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS,
1021 1, 1, 8, 0
1022 },
1023 {
1024 "SVGA3D_D32_FLOAT_S8X24_UINT",
1025 SVGA3D_D32_FLOAT_S8X24_UINT,
1026 SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT,
1027 1, 1, 8, 0
1028 },
1029 {
1030 "SVGA3D_R32_FLOAT_X8X24",
1031 SVGA3D_R32_FLOAT_X8X24,
1032 SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24_TYPELESS,
1033 1, 1, 8, 0
1034 },
1035 {
1036 "SVGA3D_X32_G8X24_UINT",
1037 SVGA3D_X32_G8X24_UINT,
1038 SVGA3D_DEVCAP_DXFMT_X32_TYPELESS_G8X24_UINT,
1039 1, 1, 4, 0
1040 },
1041 {
1042 "SVGA3D_R10G10B10A2_TYPELESS",
1043 SVGA3D_R10G10B10A2_TYPELESS,
1044 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS,
1045 1, 1, 4, 0
1046 },
1047 {
1048 "SVGA3D_R10G10B10A2_UINT",
1049 SVGA3D_R10G10B10A2_UINT,
1050 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT,
1051 1, 1, 4, 0
1052 },
1053 {
1054 "SVGA3D_R11G11B10_FLOAT",
1055 SVGA3D_R11G11B10_FLOAT,
1056 SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT,
1057 1, 1, 4, 0
1058 },
1059 {
1060 "SVGA3D_R8G8B8A8_TYPELESS",
1061 SVGA3D_R8G8B8A8_TYPELESS,
1062 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS,
1063 1, 1, 4, 0
1064 },
1065 {
1066 "SVGA3D_R8G8B8A8_UNORM",
1067 SVGA3D_R8G8B8A8_UNORM,
1068 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM,
1069 1, 1, 4, 0
1070 },
1071 {
1072 "SVGA3D_R8G8B8A8_UNORM_SRGB",
1073 SVGA3D_R8G8B8A8_UNORM_SRGB,
1074 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB,
1075 1, 1, 4, 0
1076 },
1077 {
1078 "SVGA3D_R8G8B8A8_UINT",
1079 SVGA3D_R8G8B8A8_UINT,
1080 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT,
1081 1, 1, 4, 0
1082 },
1083 {
1084 "SVGA3D_R8G8B8A8_SINT",
1085 SVGA3D_R8G8B8A8_SINT,
1086 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT,
1087 1, 1, 4, 0
1088 },
1089 {
1090 "SVGA3D_R16G16_TYPELESS",
1091 SVGA3D_R16G16_TYPELESS,
1092 SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS,
1093 1, 1, 4, 0
1094 },
1095 {
1096 "SVGA3D_R16G16_UINT",
1097 SVGA3D_R16G16_UINT,
1098 SVGA3D_DEVCAP_DXFMT_R16G16_UINT,
1099 1, 1, 4, 0
1100 },
1101 {
1102 "SVGA3D_R16G16_SINT",
1103 SVGA3D_R16G16_SINT,
1104 SVGA3D_DEVCAP_DXFMT_R16G16_SINT,
1105 1, 1, 4, 0
1106 },
1107 {
1108 "SVGA3D_R32_TYPELESS",
1109 SVGA3D_R32_TYPELESS,
1110 SVGA3D_DEVCAP_DXFMT_R32_TYPELESS,
1111 1, 1, 4, 0
1112 },
1113 {
1114 "SVGA3D_D32_FLOAT",
1115 SVGA3D_D32_FLOAT,
1116 SVGA3D_DEVCAP_DXFMT_D32_FLOAT,
1117 1, 1, 4, 0
1118 },
1119 {
1120 "SVGA3D_R32_UINT",
1121 SVGA3D_R32_UINT,
1122 SVGA3D_DEVCAP_DXFMT_R32_UINT,
1123 1, 1, 4, 0
1124 },
1125 {
1126 "SVGA3D_R32_SINT",
1127 SVGA3D_R32_SINT,
1128 SVGA3D_DEVCAP_DXFMT_R32_SINT,
1129 1, 1, 4, 0
1130 },
1131 {
1132 "SVGA3D_R24G8_TYPELESS",
1133 SVGA3D_R24G8_TYPELESS,
1134 SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS,
1135 1, 1, 4, 0
1136 },
1137 {
1138 "SVGA3D_D24_UNORM_S8_UINT",
1139 SVGA3D_D24_UNORM_S8_UINT,
1140 SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT,
1141 1, 1, 4, 0
1142 },
1143 {
1144 "SVGA3D_R24_UNORM_X8",
1145 SVGA3D_R24_UNORM_X8,
1146 SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8_TYPELESS,
1147 1, 1, 4, 0
1148 },
1149 {
1150 "SVGA3D_X24_G8_UINT",
1151 SVGA3D_X24_G8_UINT,
1152 SVGA3D_DEVCAP_DXFMT_X24_TYPELESS_G8_UINT,
1153 1, 1, 4, 0
1154 },
1155 {
1156 "SVGA3D_R8G8_TYPELESS",
1157 SVGA3D_R8G8_TYPELESS,
1158 SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS,
1159 1, 1, 2, 0
1160 },
1161 {
1162 "SVGA3D_R8G8_UNORM",
1163 SVGA3D_R8G8_UNORM,
1164 SVGA3D_DEVCAP_DXFMT_R8G8_UNORM,
1165 1, 1, 2, 0
1166 },
1167 {
1168 "SVGA3D_R8G8_UINT",
1169 SVGA3D_R8G8_UINT,
1170 SVGA3D_DEVCAP_DXFMT_R8G8_UINT,
1171 1, 1, 2, 0
1172 },
1173 {
1174 "SVGA3D_R8G8_SINT",
1175 SVGA3D_R8G8_SINT,
1176 SVGA3D_DEVCAP_DXFMT_R8G8_SINT,
1177 1, 1, 2, 0
1178 },
1179 {
1180 "SVGA3D_R16_TYPELESS",
1181 SVGA3D_R16_TYPELESS,
1182 SVGA3D_DEVCAP_DXFMT_R16_TYPELESS,
1183 1, 1, 2, 0
1184 },
1185 {
1186 "SVGA3D_R16_UNORM",
1187 SVGA3D_R16_UNORM,
1188 SVGA3D_DEVCAP_DXFMT_R16_UNORM,
1189 1, 1, 2, 0
1190 },
1191 {
1192 "SVGA3D_R16_UINT",
1193 SVGA3D_R16_UINT,
1194 SVGA3D_DEVCAP_DXFMT_R16_UINT,
1195 1, 1, 2, 0
1196 },
1197 {
1198 "SVGA3D_R16_SNORM",
1199 SVGA3D_R16_SNORM,
1200 SVGA3D_DEVCAP_DXFMT_R16_SNORM,
1201 1, 1, 2, 0
1202 },
1203 {
1204 "SVGA3D_R16_SINT",
1205 SVGA3D_R16_SINT,
1206 SVGA3D_DEVCAP_DXFMT_R16_SINT,
1207 1, 1, 2, 0
1208 },
1209 {
1210 "SVGA3D_R8_TYPELESS",
1211 SVGA3D_R8_TYPELESS,
1212 SVGA3D_DEVCAP_DXFMT_R8_TYPELESS,
1213 1, 1, 1, 0
1214 },
1215 {
1216 "SVGA3D_R8_UNORM",
1217 SVGA3D_R8_UNORM,
1218 SVGA3D_DEVCAP_DXFMT_R8_UNORM,
1219 1, 1, 1, 0
1220 },
1221 {
1222 "SVGA3D_R8_UINT",
1223 SVGA3D_R8_UINT,
1224 SVGA3D_DEVCAP_DXFMT_R8_UINT,
1225 1, 1, 1, 0
1226 },
1227 {
1228 "SVGA3D_R8_SNORM",
1229 SVGA3D_R8_SNORM,
1230 SVGA3D_DEVCAP_DXFMT_R8_SNORM,
1231 1, 1, 1, 0
1232 },
1233 {
1234 "SVGA3D_R8_SINT",
1235 SVGA3D_R8_SINT,
1236 SVGA3D_DEVCAP_DXFMT_R8_SINT,
1237 1, 1, 1, 0
1238 },
1239 {
1240 "SVGA3D_P8",
1241 SVGA3D_P8, 0, 0, 0, 0, 0
1242 },
1243 {
1244 "SVGA3D_R9G9B9E5_SHAREDEXP",
1245 SVGA3D_R9G9B9E5_SHAREDEXP,
1246 SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP,
1247 1, 1, 4, 0
1248 },
1249 {
1250 "SVGA3D_R8G8_B8G8_UNORM",
1251 SVGA3D_R8G8_B8G8_UNORM, 0, 0, 0, 0, 0
1252 },
1253 {
1254 "SVGA3D_G8R8_G8B8_UNORM",
1255 SVGA3D_G8R8_G8B8_UNORM, 0, 0, 0, 0, 0
1256 },
1257 {
1258 "SVGA3D_BC1_TYPELESS",
1259 SVGA3D_BC1_TYPELESS,
1260 SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS,
1261 4, 4, 8, 0
1262 },
1263 {
1264 "SVGA3D_BC1_UNORM_SRGB",
1265 SVGA3D_BC1_UNORM_SRGB,
1266 SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB,
1267 4, 4, 8, 0
1268 },
1269 {
1270 "SVGA3D_BC2_TYPELESS",
1271 SVGA3D_BC2_TYPELESS,
1272 SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS,
1273 4, 4, 16, 0
1274 },
1275 {
1276 "SVGA3D_BC2_UNORM_SRGB",
1277 SVGA3D_BC2_UNORM_SRGB,
1278 SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB,
1279 4, 4, 16, 0
1280 },
1281 {
1282 "SVGA3D_BC3_TYPELESS",
1283 SVGA3D_BC3_TYPELESS,
1284 SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS,
1285 4, 4, 16, 0
1286 },
1287 {
1288 "SVGA3D_BC3_UNORM_SRGB",
1289 SVGA3D_BC3_UNORM_SRGB,
1290 4, 4, 16, 0
1291 },
1292 {
1293 "SVGA3D_BC4_TYPELESS",
1294 SVGA3D_BC4_TYPELESS,
1295 SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS,
1296 4, 4, 8, 0
1297 },
1298 {
1299 "SVGA3D_ATI1",
1300 SVGA3D_ATI1, 0, 0, 0, 0, 0
1301 },
1302 {
1303 "SVGA3D_BC4_SNORM",
1304 SVGA3D_BC4_SNORM,
1305 SVGA3D_DEVCAP_DXFMT_BC4_SNORM,
1306 4, 4, 8, 0
1307 },
1308 {
1309 "SVGA3D_BC5_TYPELESS",
1310 SVGA3D_BC5_TYPELESS,
1311 SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS,
1312 4, 4, 16, 0
1313 },
1314 {
1315 "SVGA3D_ATI2",
1316 SVGA3D_ATI2, 0, 0, 0, 0, 0
1317 },
1318 {
1319 "SVGA3D_BC5_SNORM",
1320 SVGA3D_BC5_SNORM,
1321 SVGA3D_DEVCAP_DXFMT_BC5_SNORM,
1322 4, 4, 16, 0
1323 },
1324 {
1325 "SVGA3D_R10G10B10_XR_BIAS_A2_UNORM",
1326 SVGA3D_R10G10B10_XR_BIAS_A2_UNORM, 0, 0, 0, 0, 0
1327 },
1328 {
1329 "SVGA3D_B8G8R8A8_TYPELESS",
1330 SVGA3D_B8G8R8A8_TYPELESS,
1331 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS,
1332 1, 1, 4, 0
1333 },
1334 {
1335 "SVGA3D_B8G8R8A8_UNORM_SRGB",
1336 SVGA3D_B8G8R8A8_UNORM_SRGB,
1337 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB,
1338 1, 1, 4, 0
1339 },
1340 {
1341 "SVGA3D_B8G8R8X8_TYPELESS",
1342 SVGA3D_B8G8R8X8_TYPELESS,
1343 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS,
1344 1, 1, 4, 0
1345 },
1346 {
1347 "SVGA3D_B8G8R8X8_UNORM_SRGB",
1348 SVGA3D_B8G8R8X8_UNORM_SRGB,
1349 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB,
1350 1, 1, 4, 0
1351 },
1352 {
1353 "SVGA3D_Z_DF16",
1354 SVGA3D_Z_DF16,
1355 SVGA3D_DEVCAP_SURFACEFMT_Z_DF16,
1356 1, 1, 2, 0
1357 },
1358 {
1359 "SVGA3D_Z_DF24",
1360 SVGA3D_Z_DF24,
1361 SVGA3D_DEVCAP_SURFACEFMT_Z_DF24,
1362 1, 1, 4, 0
1363 },
1364 {
1365 "SVGA3D_Z_D24S8_INT",
1366 SVGA3D_Z_D24S8_INT,
1367 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT,
1368 1, 1, 4, 0
1369 },
1370 {
1371 "SVGA3D_YV12",
1372 SVGA3D_YV12, 0, 0, 0, 0, 0
1373 },
1374 {
1375 "SVGA3D_R32G32B32A32_FLOAT",
1376 SVGA3D_R32G32B32A32_FLOAT,
1377 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT,
1378 1, 1, 16, 0
1379 },
1380 {
1381 "SVGA3D_R16G16B16A16_FLOAT",
1382 SVGA3D_R16G16B16A16_FLOAT,
1383 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT,
1384 1, 1, 8, 0
1385 },
1386 {
1387 "SVGA3D_R16G16B16A16_UNORM",
1388 SVGA3D_R16G16B16A16_UNORM,
1389 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM,
1390 1, 1, 8, 0
1391 },
1392 {
1393 "SVGA3D_R32G32_FLOAT",
1394 SVGA3D_R32G32_FLOAT,
1395 SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT,
1396 1, 1, 8, 0
1397 },
1398 {
1399 "SVGA3D_R10G10B10A2_UNORM",
1400 SVGA3D_R10G10B10A2_UNORM,
1401 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM,
1402 1, 1, 4, 0
1403 },
1404 {
1405 "SVGA3D_R8G8B8A8_SNORM",
1406 SVGA3D_R8G8B8A8_SNORM,
1407 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM,
1408 1, 1, 4, 0
1409 },
1410 {
1411 "SVGA3D_R16G16_FLOAT",
1412 SVGA3D_R16G16_FLOAT,
1413 SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT,
1414 1, 1, 4, 0
1415 },
1416 {
1417 "SVGA3D_R16G16_UNORM",
1418 SVGA3D_R16G16_UNORM,
1419 SVGA3D_DEVCAP_DXFMT_R16G16_UNORM,
1420 1, 1, 4, 0
1421 },
1422 {
1423 "SVGA3D_R16G16_SNORM",
1424 SVGA3D_R16G16_SNORM,
1425 SVGA3D_DEVCAP_DXFMT_R16G16_SNORM,
1426 1, 1, 4, 0
1427 },
1428 {
1429 "SVGA3D_R32_FLOAT",
1430 SVGA3D_R32_FLOAT,
1431 SVGA3D_DEVCAP_DXFMT_R32_FLOAT,
1432 1, 1, 4, 0
1433 },
1434 {
1435 "SVGA3D_R8G8_SNORM",
1436 SVGA3D_R8G8_SNORM,
1437 SVGA3D_DEVCAP_DXFMT_R8G8_SNORM,
1438 1, 1, 2, 0
1439 },
1440 {
1441 "SVGA3D_R16_FLOAT",
1442 SVGA3D_R16_FLOAT,
1443 SVGA3D_DEVCAP_DXFMT_R16_FLOAT,
1444 1, 1, 2, 0
1445 },
1446 {
1447 "SVGA3D_D16_UNORM",
1448 SVGA3D_D16_UNORM,
1449 SVGA3D_DEVCAP_DXFMT_D16_UNORM,
1450 1, 1, 2, 0
1451 },
1452 {
1453 "SVGA3D_A8_UNORM",
1454 SVGA3D_A8_UNORM,
1455 SVGA3D_DEVCAP_DXFMT_A8_UNORM,
1456 1, 1, 1, 0
1457 },
1458 {
1459 "SVGA3D_BC1_UNORM",
1460 SVGA3D_BC1_UNORM,
1461 SVGA3D_DEVCAP_DXFMT_BC1_UNORM,
1462 4, 4, 8, 0
1463 },
1464 {
1465 "SVGA3D_BC2_UNORM",
1466 SVGA3D_BC2_UNORM,
1467 SVGA3D_DEVCAP_DXFMT_BC2_UNORM,
1468 4, 4, 16, 0
1469 },
1470 {
1471 "SVGA3D_BC3_UNORM",
1472 SVGA3D_BC3_UNORM,
1473 SVGA3D_DEVCAP_DXFMT_BC3_UNORM,
1474 4, 4, 16, 0
1475 },
1476 {
1477 "SVGA3D_B5G6R5_UNORM",
1478 SVGA3D_B5G6R5_UNORM,
1479 SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM,
1480 1, 1, 2, 0
1481 },
1482 {
1483 "SVGA3D_B5G5R5A1_UNORM",
1484 SVGA3D_B5G5R5A1_UNORM,
1485 SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM,
1486 1, 1, 2, 0
1487 },
1488 {
1489 "SVGA3D_B8G8R8A8_UNORM",
1490 SVGA3D_B8G8R8A8_UNORM,
1491 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM,
1492 1, 1, 4, 0
1493 },
1494 {
1495 "SVGA3D_B8G8R8X8_UNORM",
1496 SVGA3D_B8G8R8X8_UNORM,
1497 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM,
1498 1, 1, 4, 0
1499 },
1500 {
1501 "SVGA3D_BC4_UNORM",
1502 SVGA3D_BC4_UNORM,
1503 SVGA3D_DEVCAP_DXFMT_BC4_UNORM,
1504 4, 4, 8, 0
1505 },
1506 {
1507 "SVGA3D_BC5_UNORM",
1508 SVGA3D_BC5_UNORM,
1509 SVGA3D_DEVCAP_DXFMT_BC5_UNORM,
1510 4, 4, 16, 0
1511 }
1512 };
1513
1514 static const SVGA3dSurfaceFormat compat_x8r8g8b8[] = {
1515 SVGA3D_X8R8G8B8, SVGA3D_A8R8G8B8, SVGA3D_B8G8R8X8_UNORM,
1516 SVGA3D_B8G8R8A8_UNORM, 0
1517 };
1518 static const SVGA3dSurfaceFormat compat_r8[] = {
1519 SVGA3D_R8_UNORM, SVGA3D_NV12, SVGA3D_YV12, 0
1520 };
1521 static const SVGA3dSurfaceFormat compat_g8r8[] = {
1522 SVGA3D_R8G8_UNORM, SVGA3D_NV12, 0
1523 };
1524 static const SVGA3dSurfaceFormat compat_r5g6b5[] = {
1525 SVGA3D_R5G6B5, SVGA3D_B5G6R5_UNORM, 0
1526 };
1527
1528 static const struct format_compat_entry format_compats[] = {
1529 {PIPE_FORMAT_B8G8R8X8_UNORM, compat_x8r8g8b8},
1530 {PIPE_FORMAT_B8G8R8A8_UNORM, compat_x8r8g8b8},
1531 {PIPE_FORMAT_R8_UNORM, compat_r8},
1532 {PIPE_FORMAT_R8G8_UNORM, compat_g8r8},
1533 {PIPE_FORMAT_B5G6R5_UNORM, compat_r5g6b5}
1534 };
1535
1536 /**
1537 * Debug only:
1538 * 1. check that format_cap_table[i] matches the i-th SVGA3D format.
1539 * 2. check that format_conversion_table[i].pformat == i.
1540 */
1541 static void
1542 check_format_tables(void)
1543 {
1544 static boolean first_call = TRUE;
1545
1546 if (first_call) {
1547 unsigned i;
1548
1549 STATIC_ASSERT(ARRAY_SIZE(format_cap_table) == SVGA3D_FORMAT_MAX);
1550 for (i = 0; i < ARRAY_SIZE(format_cap_table); i++) {
1551 assert(format_cap_table[i].format == i);
1552 }
1553
1554 STATIC_ASSERT(ARRAY_SIZE(format_conversion_table) == PIPE_FORMAT_COUNT);
1555 for (i = 0; i < ARRAY_SIZE(format_conversion_table); i++) {
1556 assert(format_conversion_table[i].pformat == i);
1557 }
1558
1559 first_call = FALSE;
1560 }
1561 }
1562
1563
1564 /**
1565 * Return string name of an SVGA3dDevCapIndex value.
1566 * For debugging.
1567 */
1568 static const char *
1569 svga_devcap_name(SVGA3dDevCapIndex cap)
1570 {
1571 static const struct debug_named_value devcap_names[] = {
1572 /* Note, we only list the DXFMT devcaps so far */
1573 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X8R8G8B8),
1574 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A8R8G8B8),
1575 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R5G6B5),
1576 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X1R5G5B5),
1577 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A1R5G5B5),
1578 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A4R4G4B4),
1579 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D32),
1580 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D16),
1581 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D24S8),
1582 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D15S1),
1583 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE8),
1584 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4),
1585 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE16),
1586 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8),
1587 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT1),
1588 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT2),
1589 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT3),
1590 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT4),
1591 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT5),
1592 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUMPU8V8),
1593 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5),
1594 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8),
1595 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1),
1596 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5),
1597 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8),
1598 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A2R10G10B10),
1599 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_V8U8),
1600 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8),
1601 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_CxV8U8),
1602 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X8L8V8U8),
1603 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A2W10V10U10),
1604 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ALPHA8),
1605 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R_S10E5),
1606 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R_S23E8),
1607 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_RG_S10E5),
1608 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_RG_S23E8),
1609 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUFFER),
1610 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D24X8),
1611 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_V16U16),
1612 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_G16R16),
1613 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A16B16G16R16),
1614 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_UYVY),
1615 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_YUY2),
1616 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_NV12),
1617 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_AYUV),
1618 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS),
1619 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT),
1620 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT),
1621 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS),
1622 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT),
1623 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT),
1624 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT),
1625 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS),
1626 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT),
1627 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM),
1628 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT),
1629 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS),
1630 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_UINT),
1631 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_SINT),
1632 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS),
1633 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT),
1634 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24_TYPELESS),
1635 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X32_TYPELESS_G8X24_UINT),
1636 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS),
1637 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT),
1638 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT),
1639 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS),
1640 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM),
1641 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB),
1642 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT),
1643 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT),
1644 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS),
1645 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_UINT),
1646 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_SINT),
1647 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS),
1648 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D32_FLOAT),
1649 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_UINT),
1650 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_SINT),
1651 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS),
1652 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT),
1653 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8_TYPELESS),
1654 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X24_TYPELESS_G8_UINT),
1655 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS),
1656 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM),
1657 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_UINT),
1658 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_SINT),
1659 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS),
1660 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_UNORM),
1661 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_UINT),
1662 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_SNORM),
1663 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_SINT),
1664 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS),
1665 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_UNORM),
1666 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_UINT),
1667 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_SNORM),
1668 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_SINT),
1669 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_P8),
1670 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP),
1671 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM),
1672 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM),
1673 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS),
1674 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB),
1675 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS),
1676 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB),
1677 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS),
1678 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB),
1679 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS),
1680 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ATI1),
1681 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC4_SNORM),
1682 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS),
1683 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ATI2),
1684 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC5_SNORM),
1685 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM),
1686 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS),
1687 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB),
1688 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS),
1689 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB),
1690 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_DF16),
1691 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_DF24),
1692 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT),
1693 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_YV12),
1694 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT),
1695 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT),
1696 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM),
1697 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT),
1698 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM),
1699 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM),
1700 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT),
1701 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM),
1702 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM),
1703 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_FLOAT),
1704 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM),
1705 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_FLOAT),
1706 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D16_UNORM),
1707 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A8_UNORM),
1708 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC1_UNORM),
1709 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC2_UNORM),
1710 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC3_UNORM),
1711 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM),
1712 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM),
1713 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM),
1714 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM),
1715 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC4_UNORM),
1716 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC5_UNORM),
1717 DEBUG_NAMED_VALUE_END,
1718 };
1719 return debug_dump_enum(devcap_names, cap);
1720 }
1721
1722
1723 /**
1724 * Return string for a bitmask of name of SVGA3D_DXFMT_x flags.
1725 * For debugging.
1726 */
1727 static const char *
1728 svga_devcap_format_flags(unsigned flags)
1729 {
1730 static const struct debug_named_value devcap_flags[] = {
1731 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_SUPPORTED),
1732 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_SHADER_SAMPLE),
1733 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_COLOR_RENDERTARGET),
1734 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_DEPTH_RENDERTARGET),
1735 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_BLENDABLE),
1736 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_MIPS),
1737 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_ARRAY),
1738 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_VOLUME),
1739 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_DX_VERTEX_BUFFER),
1740 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_MULTISAMPLE),
1741 DEBUG_NAMED_VALUE_END
1742 };
1743
1744 return debug_dump_flags(devcap_flags, flags);
1745 }
1746
1747
1748 /*
1749 * Get format capabilities from the host. It takes in consideration
1750 * deprecated/unsupported formats, and formats which are implicitely assumed to
1751 * be supported when the host does not provide an explicit capability entry.
1752 */
1753 void
1754 svga_get_format_cap(struct svga_screen *ss,
1755 SVGA3dSurfaceFormat format,
1756 SVGA3dSurfaceFormatCaps *caps)
1757 {
1758 struct svga_winsys_screen *sws = ss->sws;
1759 SVGA3dDevCapResult result;
1760 const struct format_cap *entry;
1761
1762 #ifdef DEBUG
1763 check_format_tables();
1764 #else
1765 (void) check_format_tables;
1766 #endif
1767
1768 assert(format < ARRAY_SIZE(format_cap_table));
1769 entry = &format_cap_table[format];
1770 assert(entry->format == format);
1771
1772 if (entry->devcap && sws->get_cap(sws, entry->devcap, &result)) {
1773 assert(format < SVGA3D_UYVY || entry->defaultOperations == 0);
1774 caps->value = result.u;
1775 } else {
1776 /* Implicitly advertised format -- use default caps */
1777 caps->value = entry->defaultOperations;
1778 }
1779 }
1780
1781
1782 /*
1783 * Get DX format capabilities from VGPU10 device.
1784 */
1785 static void
1786 svga_get_dx_format_cap(struct svga_screen *ss,
1787 SVGA3dSurfaceFormat format,
1788 SVGA3dDevCapResult *caps)
1789 {
1790 struct svga_winsys_screen *sws = ss->sws;
1791 const struct format_cap *entry;
1792
1793 #ifdef DEBUG
1794 check_format_tables();
1795 #else
1796 (void) check_format_tables;
1797 #endif
1798
1799 assert(ss->sws->have_vgpu10);
1800 assert(format < ARRAY_SIZE(format_cap_table));
1801 entry = &format_cap_table[format];
1802 assert(entry->format == format);
1803 assert(entry->devcap > SVGA3D_DEVCAP_DXCONTEXT);
1804
1805 caps->u = 0;
1806 if (entry->devcap) {
1807 sws->get_cap(sws, entry->devcap, caps);
1808
1809 /* svga device supports SHADER_SAMPLE capability for these
1810 * formats but does not advertise the devcap.
1811 * So enable this bit here.
1812 */
1813 if (format == SVGA3D_R32_FLOAT_X8X24 ||
1814 format == SVGA3D_R24_UNORM_X8) {
1815 caps->u |= SVGA3D_DXFMT_SHADER_SAMPLE;
1816 }
1817 }
1818
1819 if (0) {
1820 debug_printf("Format %s, devcap %s = 0x%x (%s)\n",
1821 svga_format_name(format),
1822 svga_devcap_name(entry->devcap),
1823 caps->u,
1824 svga_devcap_format_flags(caps->u));
1825 }
1826 }
1827
1828
1829 void
1830 svga_format_size(SVGA3dSurfaceFormat format,
1831 unsigned *block_width,
1832 unsigned *block_height,
1833 unsigned *bytes_per_block)
1834 {
1835 assert(format < ARRAY_SIZE(format_cap_table));
1836 *block_width = format_cap_table[format].block_width;
1837 *block_height = format_cap_table[format].block_height;
1838 *bytes_per_block = format_cap_table[format].block_bytes;
1839 /* Make sure the table entry was valid */
1840 if (*block_width == 0)
1841 debug_printf("Bad table entry for %s\n", svga_format_name(format));
1842 assert(*block_width);
1843 assert(*block_height);
1844 assert(*bytes_per_block);
1845 }
1846
1847
1848 const char *
1849 svga_format_name(SVGA3dSurfaceFormat format)
1850 {
1851 assert(format < ARRAY_SIZE(format_cap_table));
1852 return format_cap_table[format].name;
1853 }
1854
1855
1856 /**
1857 * Is the given SVGA3dSurfaceFormat a signed or unsigned integer color format?
1858 */
1859 boolean
1860 svga_format_is_integer(SVGA3dSurfaceFormat format)
1861 {
1862 switch (format) {
1863 case SVGA3D_R32G32B32A32_SINT:
1864 case SVGA3D_R32G32B32_SINT:
1865 case SVGA3D_R32G32_SINT:
1866 case SVGA3D_R32_SINT:
1867 case SVGA3D_R16G16B16A16_SINT:
1868 case SVGA3D_R16G16_SINT:
1869 case SVGA3D_R16_SINT:
1870 case SVGA3D_R8G8B8A8_SINT:
1871 case SVGA3D_R8G8_SINT:
1872 case SVGA3D_R8_SINT:
1873 case SVGA3D_R32G32B32A32_UINT:
1874 case SVGA3D_R32G32B32_UINT:
1875 case SVGA3D_R32G32_UINT:
1876 case SVGA3D_R32_UINT:
1877 case SVGA3D_R16G16B16A16_UINT:
1878 case SVGA3D_R16G16_UINT:
1879 case SVGA3D_R16_UINT:
1880 case SVGA3D_R8G8B8A8_UINT:
1881 case SVGA3D_R8G8_UINT:
1882 case SVGA3D_R8_UINT:
1883 case SVGA3D_R10G10B10A2_UINT:
1884 return TRUE;
1885 default:
1886 return FALSE;
1887 }
1888 }
1889
1890 boolean
1891 svga_format_support_gen_mips(enum pipe_format format)
1892 {
1893 assert(format < ARRAY_SIZE(format_conversion_table));
1894 return ((format_conversion_table[format].flags & TF_GEN_MIPS) > 0);
1895 }
1896
1897
1898 /**
1899 * Given a texture format, return the expected data type returned from
1900 * the texture sampler. For example, UNORM8 formats return floating point
1901 * values while SINT formats returned signed integer values.
1902 * Note: this function could be moved into the gallum u_format.[ch] code
1903 * if it's useful to anyone else.
1904 */
1905 enum tgsi_return_type
1906 svga_get_texture_datatype(enum pipe_format format)
1907 {
1908 const struct util_format_description *desc = util_format_description(format);
1909 enum tgsi_return_type t;
1910
1911 if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN ) {
1912 if (util_format_is_depth_or_stencil(format)) {
1913 t = TGSI_RETURN_TYPE_FLOAT; /* XXX revisit this */
1914 }
1915 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_FLOAT) {
1916 t = TGSI_RETURN_TYPE_FLOAT;
1917 }
1918 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1919 t = desc->channel[0].normalized ? TGSI_RETURN_TYPE_UNORM : TGSI_RETURN_TYPE_UINT;
1920 }
1921 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
1922 t = desc->channel[0].normalized ? TGSI_RETURN_TYPE_SNORM : TGSI_RETURN_TYPE_SINT;
1923 }
1924 else {
1925 assert(!"Unexpected channel type in svga_get_texture_datatype()");
1926 t = TGSI_RETURN_TYPE_FLOAT;
1927 }
1928 }
1929 else {
1930 /* compressed format, shared exponent format, etc. */
1931 switch (format) {
1932 case PIPE_FORMAT_DXT1_RGB:
1933 case PIPE_FORMAT_DXT1_RGBA:
1934 case PIPE_FORMAT_DXT3_RGBA:
1935 case PIPE_FORMAT_DXT5_RGBA:
1936 case PIPE_FORMAT_DXT1_SRGB:
1937 case PIPE_FORMAT_DXT1_SRGBA:
1938 case PIPE_FORMAT_DXT3_SRGBA:
1939 case PIPE_FORMAT_DXT5_SRGBA:
1940 case PIPE_FORMAT_RGTC1_UNORM:
1941 case PIPE_FORMAT_RGTC2_UNORM:
1942 case PIPE_FORMAT_LATC1_UNORM:
1943 case PIPE_FORMAT_LATC2_UNORM:
1944 case PIPE_FORMAT_ETC1_RGB8:
1945 t = TGSI_RETURN_TYPE_UNORM;
1946 break;
1947 case PIPE_FORMAT_RGTC1_SNORM:
1948 case PIPE_FORMAT_RGTC2_SNORM:
1949 case PIPE_FORMAT_LATC1_SNORM:
1950 case PIPE_FORMAT_LATC2_SNORM:
1951 case PIPE_FORMAT_R10G10B10X2_SNORM:
1952 t = TGSI_RETURN_TYPE_SNORM;
1953 break;
1954 case PIPE_FORMAT_R11G11B10_FLOAT:
1955 case PIPE_FORMAT_R9G9B9E5_FLOAT:
1956 t = TGSI_RETURN_TYPE_FLOAT;
1957 break;
1958 default:
1959 assert(!"Unexpected channel type in svga_get_texture_datatype()");
1960 t = TGSI_RETURN_TYPE_FLOAT;
1961 }
1962 }
1963
1964 return t;
1965 }
1966
1967
1968 /**
1969 * Given an svga context, return true iff there are currently any integer color
1970 * buffers attached to the framebuffer.
1971 */
1972 boolean
1973 svga_has_any_integer_cbufs(const struct svga_context *svga)
1974 {
1975 unsigned i;
1976 for (i = 0; i < PIPE_MAX_COLOR_BUFS; ++i) {
1977 struct pipe_surface *cbuf = svga->curr.framebuffer.cbufs[i];
1978
1979 if (cbuf && util_format_is_pure_integer(cbuf->format)) {
1980 return TRUE;
1981 }
1982 }
1983 return FALSE;
1984 }
1985
1986
1987 /**
1988 * Given an SVGA format, return the corresponding typeless format.
1989 * If there is no typeless format, return the format unchanged.
1990 */
1991 SVGA3dSurfaceFormat
1992 svga_typeless_format(SVGA3dSurfaceFormat format)
1993 {
1994 switch (format) {
1995 case SVGA3D_R32G32B32A32_UINT:
1996 case SVGA3D_R32G32B32A32_SINT:
1997 case SVGA3D_R32G32B32A32_FLOAT:
1998 return SVGA3D_R32G32B32A32_TYPELESS;
1999 case SVGA3D_R32G32B32_FLOAT:
2000 case SVGA3D_R32G32B32_UINT:
2001 case SVGA3D_R32G32B32_SINT:
2002 return SVGA3D_R32G32B32_TYPELESS;
2003 case SVGA3D_R16G16B16A16_UINT:
2004 case SVGA3D_R16G16B16A16_UNORM:
2005 case SVGA3D_R16G16B16A16_SNORM:
2006 case SVGA3D_R16G16B16A16_SINT:
2007 case SVGA3D_R16G16B16A16_FLOAT:
2008 return SVGA3D_R16G16B16A16_TYPELESS;
2009 case SVGA3D_R32G32_UINT:
2010 case SVGA3D_R32G32_SINT:
2011 case SVGA3D_R32G32_FLOAT:
2012 return SVGA3D_R32G32_TYPELESS;
2013 case SVGA3D_D32_FLOAT_S8X24_UINT:
2014 case SVGA3D_X32_G8X24_UINT:
2015 case SVGA3D_R32G8X24_TYPELESS:
2016 return SVGA3D_R32G8X24_TYPELESS;
2017 case SVGA3D_R10G10B10A2_UINT:
2018 case SVGA3D_R10G10B10A2_UNORM:
2019 return SVGA3D_R10G10B10A2_TYPELESS;
2020 case SVGA3D_R8G8B8A8_UNORM:
2021 case SVGA3D_R8G8B8A8_SNORM:
2022 case SVGA3D_R8G8B8A8_UNORM_SRGB:
2023 case SVGA3D_R8G8B8A8_UINT:
2024 case SVGA3D_R8G8B8A8_SINT:
2025 case SVGA3D_R8G8B8A8_TYPELESS:
2026 return SVGA3D_R8G8B8A8_TYPELESS;
2027 case SVGA3D_R16G16_UINT:
2028 case SVGA3D_R16G16_SINT:
2029 case SVGA3D_R16G16_UNORM:
2030 case SVGA3D_R16G16_SNORM:
2031 case SVGA3D_R16G16_FLOAT:
2032 return SVGA3D_R16G16_TYPELESS;
2033 case SVGA3D_D32_FLOAT:
2034 case SVGA3D_R32_FLOAT:
2035 case SVGA3D_R32_UINT:
2036 case SVGA3D_R32_SINT:
2037 case SVGA3D_R32_TYPELESS:
2038 return SVGA3D_R32_TYPELESS;
2039 case SVGA3D_D24_UNORM_S8_UINT:
2040 case SVGA3D_R24G8_TYPELESS:
2041 return SVGA3D_R24G8_TYPELESS;
2042 case SVGA3D_X24_G8_UINT:
2043 return SVGA3D_R24_UNORM_X8;
2044 case SVGA3D_R8G8_UNORM:
2045 case SVGA3D_R8G8_SNORM:
2046 case SVGA3D_R8G8_UINT:
2047 case SVGA3D_R8G8_SINT:
2048 return SVGA3D_R8G8_TYPELESS;
2049 case SVGA3D_D16_UNORM:
2050 case SVGA3D_R16_UNORM:
2051 case SVGA3D_R16_UINT:
2052 case SVGA3D_R16_SNORM:
2053 case SVGA3D_R16_SINT:
2054 case SVGA3D_R16_FLOAT:
2055 case SVGA3D_R16_TYPELESS:
2056 return SVGA3D_R16_TYPELESS;
2057 case SVGA3D_R8_UNORM:
2058 case SVGA3D_R8_UINT:
2059 case SVGA3D_R8_SNORM:
2060 case SVGA3D_R8_SINT:
2061 return SVGA3D_R8_TYPELESS;
2062 case SVGA3D_B8G8R8A8_UNORM_SRGB:
2063 case SVGA3D_B8G8R8A8_UNORM:
2064 case SVGA3D_B8G8R8A8_TYPELESS:
2065 return SVGA3D_B8G8R8A8_TYPELESS;
2066 case SVGA3D_B8G8R8X8_UNORM_SRGB:
2067 case SVGA3D_B8G8R8X8_UNORM:
2068 case SVGA3D_B8G8R8X8_TYPELESS:
2069 return SVGA3D_B8G8R8X8_TYPELESS;
2070 case SVGA3D_BC1_UNORM:
2071 case SVGA3D_BC1_UNORM_SRGB:
2072 case SVGA3D_BC1_TYPELESS:
2073 return SVGA3D_BC1_TYPELESS;
2074 case SVGA3D_BC2_UNORM:
2075 case SVGA3D_BC2_UNORM_SRGB:
2076 case SVGA3D_BC2_TYPELESS:
2077 return SVGA3D_BC2_TYPELESS;
2078 case SVGA3D_BC3_UNORM:
2079 case SVGA3D_BC3_UNORM_SRGB:
2080 case SVGA3D_BC3_TYPELESS:
2081 return SVGA3D_BC3_TYPELESS;
2082 case SVGA3D_BC4_UNORM:
2083 case SVGA3D_BC4_SNORM:
2084 return SVGA3D_BC4_TYPELESS;
2085 case SVGA3D_BC5_UNORM:
2086 case SVGA3D_BC5_SNORM:
2087 return SVGA3D_BC5_TYPELESS;
2088
2089 /* Special cases (no corresponding _TYPELESS formats) */
2090 case SVGA3D_A8_UNORM:
2091 case SVGA3D_B5G5R5A1_UNORM:
2092 case SVGA3D_B5G6R5_UNORM:
2093 case SVGA3D_R11G11B10_FLOAT:
2094 case SVGA3D_R9G9B9E5_SHAREDEXP:
2095 return format;
2096 default:
2097 debug_printf("Unexpected format %s in %s\n",
2098 svga_format_name(format), __FUNCTION__);
2099 return format;
2100 }
2101 }
2102
2103
2104 /**
2105 * Given a surface format, return the corresponding format to use for
2106 * a texture sampler. In most cases, it's the format unchanged, but there
2107 * are some special cases.
2108 */
2109 SVGA3dSurfaceFormat
2110 svga_sampler_format(SVGA3dSurfaceFormat format)
2111 {
2112 switch (format) {
2113 case SVGA3D_D16_UNORM:
2114 return SVGA3D_R16_UNORM;
2115 case SVGA3D_D24_UNORM_S8_UINT:
2116 return SVGA3D_R24_UNORM_X8;
2117 case SVGA3D_D32_FLOAT:
2118 return SVGA3D_R32_FLOAT;
2119 case SVGA3D_D32_FLOAT_S8X24_UINT:
2120 return SVGA3D_R32_FLOAT_X8X24;
2121 default:
2122 return format;
2123 }
2124 }
2125
2126
2127 /**
2128 * Is the given format an uncompressed snorm format?
2129 */
2130 bool
2131 svga_format_is_uncompressed_snorm(SVGA3dSurfaceFormat format)
2132 {
2133 switch (format) {
2134 case SVGA3D_R8G8B8A8_SNORM:
2135 case SVGA3D_R8G8_SNORM:
2136 case SVGA3D_R8_SNORM:
2137 case SVGA3D_R16G16B16A16_SNORM:
2138 case SVGA3D_R16G16_SNORM:
2139 case SVGA3D_R16_SNORM:
2140 return true;
2141 default:
2142 return false;
2143 }
2144 }
2145
2146
2147 bool
2148 svga_format_is_typeless(SVGA3dSurfaceFormat format)
2149 {
2150 switch (format) {
2151 case SVGA3D_R32G32B32A32_TYPELESS:
2152 case SVGA3D_R32G32B32_TYPELESS:
2153 case SVGA3D_R16G16B16A16_TYPELESS:
2154 case SVGA3D_R32G32_TYPELESS:
2155 case SVGA3D_R32G8X24_TYPELESS:
2156 case SVGA3D_R10G10B10A2_TYPELESS:
2157 case SVGA3D_R8G8B8A8_TYPELESS:
2158 case SVGA3D_R16G16_TYPELESS:
2159 case SVGA3D_R32_TYPELESS:
2160 case SVGA3D_R24G8_TYPELESS:
2161 case SVGA3D_R8G8_TYPELESS:
2162 case SVGA3D_R16_TYPELESS:
2163 case SVGA3D_R8_TYPELESS:
2164 case SVGA3D_BC1_TYPELESS:
2165 case SVGA3D_BC2_TYPELESS:
2166 case SVGA3D_BC3_TYPELESS:
2167 case SVGA3D_BC4_TYPELESS:
2168 case SVGA3D_BC5_TYPELESS:
2169 case SVGA3D_B8G8R8A8_TYPELESS:
2170 case SVGA3D_B8G8R8X8_TYPELESS:
2171 return true;
2172 default:
2173 return false;
2174 }
2175 }
2176
2177
2178 /**
2179 * \brief Can we import a surface with a given SVGA3D format as a texture?
2180 *
2181 * \param ss[in] pointer to the svga screen.
2182 * \param pformat[in] pipe format of the local texture.
2183 * \param sformat[in] svga3d format of the imported surface.
2184 * \param bind[in] bind flags of the imported texture.
2185 * \param verbose[in] Print out incompatibilities in debug mode.
2186 */
2187 bool
2188 svga_format_is_shareable(const struct svga_screen *ss,
2189 enum pipe_format pformat,
2190 SVGA3dSurfaceFormat sformat,
2191 unsigned bind,
2192 bool verbose)
2193 {
2194 SVGA3dSurfaceFormat default_format =
2195 svga_translate_format(ss, pformat, bind);
2196 int i;
2197
2198 if (default_format == SVGA3D_FORMAT_INVALID)
2199 return false;
2200 if (default_format == sformat)
2201 return true;
2202
2203 for (i = 0; i < ARRAY_SIZE(format_compats); ++i) {
2204 if (format_compats[i].pformat == pformat) {
2205 const SVGA3dSurfaceFormat *compat_format =
2206 format_compats[i].compat_format;
2207 while (*compat_format != 0) {
2208 if (*compat_format == sformat)
2209 return true;
2210 compat_format++;
2211 }
2212 }
2213 }
2214
2215 if (verbose) {
2216 debug_printf("Incompatible imported surface format.\n");
2217 debug_printf("Texture format: \"%s\". Imported format: \"%s\".\n",
2218 svga_format_name(default_format),
2219 svga_format_name(sformat));
2220 }
2221
2222 return false;
2223 }
2224
2225
2226 /**
2227 * Return the sRGB format which corresponds to the given (linear) format.
2228 * If there's no such sRGB format, return the format as-is.
2229 */
2230 SVGA3dSurfaceFormat
2231 svga_linear_to_srgb(SVGA3dSurfaceFormat format)
2232 {
2233 switch (format) {
2234 case SVGA3D_R8G8B8A8_UNORM:
2235 return SVGA3D_R8G8B8A8_UNORM_SRGB;
2236 case SVGA3D_BC1_UNORM:
2237 return SVGA3D_BC1_UNORM_SRGB;
2238 case SVGA3D_BC2_UNORM:
2239 return SVGA3D_BC2_UNORM_SRGB;
2240 case SVGA3D_BC3_UNORM:
2241 return SVGA3D_BC3_UNORM_SRGB;
2242 case SVGA3D_B8G8R8A8_UNORM:
2243 return SVGA3D_B8G8R8A8_UNORM_SRGB;
2244 case SVGA3D_B8G8R8X8_UNORM:
2245 return SVGA3D_B8G8R8X8_UNORM_SRGB;
2246 default:
2247 return format;
2248 }
2249 }
2250
2251
2252 /**
2253 * Implement pipe_screen::is_format_supported().
2254 * \param bindings bitmask of PIPE_BIND_x flags
2255 */
2256 boolean
2257 svga_is_format_supported(struct pipe_screen *screen,
2258 enum pipe_format format,
2259 enum pipe_texture_target target,
2260 unsigned sample_count,
2261 unsigned storage_sample_count,
2262 unsigned bindings)
2263 {
2264 struct svga_screen *ss = svga_screen(screen);
2265 SVGA3dSurfaceFormat svga_format;
2266 SVGA3dSurfaceFormatCaps caps;
2267 SVGA3dSurfaceFormatCaps mask;
2268
2269 assert(bindings);
2270 assert(!ss->sws->have_vgpu10);
2271
2272 svga_format = svga_translate_format(ss, format, bindings);
2273 if (svga_format == SVGA3D_FORMAT_INVALID) {
2274 return FALSE;
2275 }
2276
2277 if (util_format_is_srgb(format) &&
2278 (bindings & PIPE_BIND_DISPLAY_TARGET)) {
2279 /* We only support sRGB rendering with vgpu10 */
2280 return FALSE;
2281 }
2282
2283 /*
2284 * Override host capabilities, so that we end up with the same
2285 * visuals for all virtual hardware implementations.
2286 */
2287 if (bindings & PIPE_BIND_DISPLAY_TARGET) {
2288 switch (svga_format) {
2289 case SVGA3D_A8R8G8B8:
2290 case SVGA3D_X8R8G8B8:
2291 case SVGA3D_R5G6B5:
2292 break;
2293
2294 /* VGPU10 formats */
2295 case SVGA3D_B8G8R8A8_UNORM:
2296 case SVGA3D_B8G8R8X8_UNORM:
2297 case SVGA3D_B5G6R5_UNORM:
2298 case SVGA3D_B8G8R8X8_UNORM_SRGB:
2299 case SVGA3D_B8G8R8A8_UNORM_SRGB:
2300 case SVGA3D_R8G8B8A8_UNORM_SRGB:
2301 break;
2302
2303 /* Often unsupported/problematic. This means we end up with the same
2304 * visuals for all virtual hardware implementations.
2305 */
2306 case SVGA3D_A4R4G4B4:
2307 case SVGA3D_A1R5G5B5:
2308 return FALSE;
2309
2310 default:
2311 return FALSE;
2312 }
2313 }
2314
2315 /*
2316 * Query the host capabilities.
2317 */
2318 svga_get_format_cap(ss, svga_format, &caps);
2319
2320 if (bindings & PIPE_BIND_RENDER_TARGET) {
2321 /* Check that the color surface is blendable, unless it's an
2322 * integer format.
2323 */
2324 if (!svga_format_is_integer(svga_format) &&
2325 (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
2326 return FALSE;
2327 }
2328 }
2329
2330 mask.value = 0;
2331 if (bindings & PIPE_BIND_RENDER_TARGET)
2332 mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
2333
2334 if (bindings & PIPE_BIND_DEPTH_STENCIL)
2335 mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
2336
2337 if (bindings & PIPE_BIND_SAMPLER_VIEW)
2338 mask.value |= SVGA3DFORMAT_OP_TEXTURE;
2339
2340 if (target == PIPE_TEXTURE_CUBE)
2341 mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
2342 else if (target == PIPE_TEXTURE_3D)
2343 mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
2344
2345 return (caps.value & mask.value) == mask.value;
2346 }
2347
2348
2349 /**
2350 * Implement pipe_screen::is_format_supported() for VGPU10 device.
2351 * \param bindings bitmask of PIPE_BIND_x flags
2352 */
2353 boolean
2354 svga_is_dx_format_supported(struct pipe_screen *screen,
2355 enum pipe_format format,
2356 enum pipe_texture_target target,
2357 unsigned sample_count,
2358 unsigned storage_sample_count,
2359 unsigned bindings)
2360 {
2361 struct svga_screen *ss = svga_screen(screen);
2362 SVGA3dSurfaceFormat svga_format;
2363 SVGA3dDevCapResult caps;
2364 unsigned int mask = 0;
2365
2366 assert(bindings);
2367 assert(ss->sws->have_vgpu10);
2368
2369 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
2370 return false;
2371
2372 if (sample_count > 1) {
2373 /* In ms_samples, if bit N is set it means that we support
2374 * multisample with N+1 samples per pixel.
2375 */
2376 if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
2377 return FALSE;
2378 }
2379 }
2380
2381 /*
2382 * For VGPU10 vertex formats, skip querying host capabilities
2383 */
2384
2385 if (bindings & PIPE_BIND_VERTEX_BUFFER) {
2386 SVGA3dSurfaceFormat svga_format;
2387 unsigned flags;
2388 svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
2389 return svga_format != SVGA3D_FORMAT_INVALID;
2390 }
2391
2392 svga_format = svga_translate_format(ss, format, bindings);
2393 if (svga_format == SVGA3D_FORMAT_INVALID) {
2394 return FALSE;
2395 }
2396
2397 /*
2398 * Override host capabilities, so that we end up with the same
2399 * visuals for all virtual hardware implementations.
2400 */
2401 if (bindings & PIPE_BIND_DISPLAY_TARGET) {
2402 switch (svga_format) {
2403 case SVGA3D_A8R8G8B8:
2404 case SVGA3D_X8R8G8B8:
2405 case SVGA3D_R5G6B5:
2406 break;
2407
2408 /* VGPU10 formats */
2409 case SVGA3D_B8G8R8A8_UNORM:
2410 case SVGA3D_B8G8R8X8_UNORM:
2411 case SVGA3D_B5G6R5_UNORM:
2412 case SVGA3D_B8G8R8X8_UNORM_SRGB:
2413 case SVGA3D_B8G8R8A8_UNORM_SRGB:
2414 case SVGA3D_R8G8B8A8_UNORM_SRGB:
2415 break;
2416
2417 /* Often unsupported/problematic. This means we end up with the same
2418 * visuals for all virtual hardware implementations.
2419 */
2420 case SVGA3D_A4R4G4B4:
2421 case SVGA3D_A1R5G5B5:
2422 return FALSE;
2423
2424 default:
2425 return FALSE;
2426 }
2427 }
2428
2429 /*
2430 * Query the host capabilities.
2431 */
2432 svga_get_dx_format_cap(ss, svga_format, &caps);
2433
2434 if (bindings & PIPE_BIND_RENDER_TARGET) {
2435 /* Check that the color surface is blendable, unless it's an
2436 * integer format.
2437 */
2438 if (!(svga_format_is_integer(svga_format) ||
2439 (caps.u & SVGA3D_DXFMT_BLENDABLE))) {
2440 return FALSE;
2441 }
2442 mask |= SVGA3D_DXFMT_COLOR_RENDERTARGET;
2443 }
2444
2445 if (bindings & PIPE_BIND_DEPTH_STENCIL)
2446 mask |= SVGA3D_DXFMT_DEPTH_RENDERTARGET;
2447
2448 if (target == PIPE_TEXTURE_3D)
2449 mask |= SVGA3D_DXFMT_VOLUME;
2450
2451 /* Is the format supported for rendering */
2452 if ((caps.u & mask) != mask)
2453 return FALSE;
2454
2455 if (bindings & PIPE_BIND_SAMPLER_VIEW) {
2456 SVGA3dSurfaceFormat sampler_format;
2457
2458 /* Get the sampler view format */
2459 sampler_format = svga_sampler_format(svga_format);
2460 if (sampler_format != svga_format) {
2461 caps.u = 0;
2462 svga_get_dx_format_cap(ss, sampler_format, &caps);
2463 mask &= (SVGA3D_DXFMT_VOLUME | SVGA3D_DXFMT_MULTISAMPLE);
2464 mask |= SVGA3D_DXFMT_SHADER_SAMPLE;
2465 if ((caps.u & mask) != mask)
2466 return FALSE;
2467 }
2468 }
2469
2470 return TRUE;
2471 }