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svga: Factor out the format conversion table entry lookup.
[mesa.git] / src / gallium / drivers / svga / svga_format.c
1 /**********************************************************
2 * Copyright 2011 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26
27 #include "pipe/p_format.h"
28 #include "util/u_debug.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31
32 #include "svga_winsys.h"
33 #include "svga_screen.h"
34 #include "svga_format.h"
35
36
37 /** Describes mapping from gallium formats to SVGA vertex/pixel formats */
38 struct vgpu10_format_entry
39 {
40 enum pipe_format pformat;
41 SVGA3dSurfaceFormat vertex_format;
42 SVGA3dSurfaceFormat pixel_format;
43 SVGA3dSurfaceFormat view_format; /* view format for texture buffer */
44 unsigned flags;
45 };
46
47 struct format_compat_entry
48 {
49 enum pipe_format pformat;
50 const SVGA3dSurfaceFormat *compat_format;
51 };
52
53
54 /**
55 * Table mapping Gallium formats to SVGA3d vertex/pixel formats.
56 * Note: the table is ordered according to PIPE_FORMAT_x order.
57 */
58 static const struct vgpu10_format_entry format_conversion_table[] =
59 {
60 /* Gallium format SVGA3D vertex format SVGA3D pixel format SVGA3D texbuf view format Flags */
61 { PIPE_FORMAT_NONE, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
62 { PIPE_FORMAT_B8G8R8A8_UNORM, SVGA3D_B8G8R8A8_UNORM, SVGA3D_B8G8R8A8_UNORM, SVGA3D_B8G8R8A8_UNORM, TF_GEN_MIPS },
63 { PIPE_FORMAT_B8G8R8X8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8X8_UNORM, SVGA3D_B8G8R8X8_UNORM, TF_GEN_MIPS },
64 { PIPE_FORMAT_A8R8G8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
65 { PIPE_FORMAT_X8R8G8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
66 { PIPE_FORMAT_B5G5R5A1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_B5G5R5A1_UNORM, SVGA3D_B5G5R5A1_UNORM, TF_GEN_MIPS },
67 { PIPE_FORMAT_B4G4R4A4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
68 { PIPE_FORMAT_B5G6R5_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_B5G6R5_UNORM, SVGA3D_B5G6R5_UNORM, TF_GEN_MIPS },
69 { PIPE_FORMAT_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, TF_GEN_MIPS },
70 { PIPE_FORMAT_L8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UNORM, TF_XXX1 },
71 { PIPE_FORMAT_A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_A8_UNORM, SVGA3D_R8_UNORM, TF_GEN_MIPS | TF_000X},
72 { PIPE_FORMAT_I8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UNORM, TF_XXXX },
73 { PIPE_FORMAT_L8A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8G8_UNORM, TF_XXXY },
74 { PIPE_FORMAT_L16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UNORM, TF_XXX1 },
75 { PIPE_FORMAT_UYVY, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
76 { PIPE_FORMAT_YUYV, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
77 { PIPE_FORMAT_Z16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_D16_UNORM, SVGA3D_D16_UNORM, 0 },
78 { PIPE_FORMAT_Z32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
79 { PIPE_FORMAT_Z32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_D32_FLOAT, SVGA3D_D32_FLOAT, 0 },
80 { PIPE_FORMAT_Z24_UNORM_S8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_D24_UNORM_S8_UINT, SVGA3D_D24_UNORM_S8_UINT, 0 },
81 { PIPE_FORMAT_S8_UINT_Z24_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
82 { PIPE_FORMAT_Z24X8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_D24_UNORM_S8_UINT, SVGA3D_D24_UNORM_S8_UINT, 0 },
83 { PIPE_FORMAT_X8Z24_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
84 { PIPE_FORMAT_S8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
85 { PIPE_FORMAT_R64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
86 { PIPE_FORMAT_R64G64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
87 { PIPE_FORMAT_R64G64B64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
88 { PIPE_FORMAT_R64G64B64A64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
89 { PIPE_FORMAT_R32_FLOAT, SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, TF_GEN_MIPS },
90 { PIPE_FORMAT_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, TF_GEN_MIPS },
91 { PIPE_FORMAT_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, TF_GEN_MIPS },
92 { PIPE_FORMAT_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, TF_GEN_MIPS },
93 { PIPE_FORMAT_R32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
94 { PIPE_FORMAT_R32G32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
95 { PIPE_FORMAT_R32G32B32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
96 { PIPE_FORMAT_R32G32B32A32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
97 { PIPE_FORMAT_R32_USCALED, SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
98 { PIPE_FORMAT_R32G32_USCALED, SVGA3D_R32G32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
99 { PIPE_FORMAT_R32G32B32_USCALED, SVGA3D_R32G32B32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
100 { PIPE_FORMAT_R32G32B32A32_USCALED, SVGA3D_R32G32B32A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
101 { PIPE_FORMAT_R32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
102 { PIPE_FORMAT_R32G32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
103 { PIPE_FORMAT_R32G32B32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
104 { PIPE_FORMAT_R32G32B32A32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
105 { PIPE_FORMAT_R32_SSCALED, SVGA3D_R32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
106 { PIPE_FORMAT_R32G32_SSCALED, SVGA3D_R32G32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
107 { PIPE_FORMAT_R32G32B32_SSCALED, SVGA3D_R32G32B32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
108 { PIPE_FORMAT_R32G32B32A32_SSCALED, SVGA3D_R32G32B32A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
109 { PIPE_FORMAT_R16_UNORM, SVGA3D_R16_UNORM, SVGA3D_R16_UNORM, SVGA3D_R16_UNORM, TF_GEN_MIPS },
110 { PIPE_FORMAT_R16G16_UNORM, SVGA3D_R16G16_UNORM, SVGA3D_R16G16_UNORM, SVGA3D_R16G16_UNORM, TF_GEN_MIPS },
111 { PIPE_FORMAT_R16G16B16_UNORM, SVGA3D_R16G16B16A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
112 { PIPE_FORMAT_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, TF_GEN_MIPS },
113 { PIPE_FORMAT_R16_USCALED, SVGA3D_R16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
114 { PIPE_FORMAT_R16G16_USCALED, SVGA3D_R16G16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
115 { PIPE_FORMAT_R16G16B16_USCALED, SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_U_TO_F_CAST },
116 { PIPE_FORMAT_R16G16B16A16_USCALED, SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
117 { PIPE_FORMAT_R16_SNORM, SVGA3D_R16_SNORM, SVGA3D_R16_SNORM, SVGA3D_R16_SNORM, 0 },
118 { PIPE_FORMAT_R16G16_SNORM, SVGA3D_R16G16_SNORM, SVGA3D_R16G16_SNORM, SVGA3D_R16G16_SNORM, 0 },
119 { PIPE_FORMAT_R16G16B16_SNORM, SVGA3D_R16G16B16A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
120 { PIPE_FORMAT_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, 0 },
121 { PIPE_FORMAT_R16_SSCALED, SVGA3D_R16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
122 { PIPE_FORMAT_R16G16_SSCALED, SVGA3D_R16G16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
123 { PIPE_FORMAT_R16G16B16_SSCALED, SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_I_TO_F_CAST },
124 { PIPE_FORMAT_R16G16B16A16_SSCALED, SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
125 { PIPE_FORMAT_R8_UNORM, SVGA3D_R8_UNORM, SVGA3D_R8_UNORM, SVGA3D_R8_UNORM, TF_GEN_MIPS },
126 { PIPE_FORMAT_R8G8_UNORM, SVGA3D_R8G8_UNORM, SVGA3D_R8G8_UNORM, SVGA3D_R8G8_UNORM, TF_GEN_MIPS },
127 { PIPE_FORMAT_R8G8B8_UNORM, SVGA3D_R8G8B8A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
128 { PIPE_FORMAT_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, TF_GEN_MIPS },
129 { PIPE_FORMAT_X8B8G8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
130 { PIPE_FORMAT_R8_USCALED, SVGA3D_R8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
131 { PIPE_FORMAT_R8G8_USCALED, SVGA3D_R8G8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
132 { PIPE_FORMAT_R8G8B8_USCALED, SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_U_TO_F_CAST },
133 { PIPE_FORMAT_R8G8B8A8_USCALED, SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
134 { 73, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
135 { PIPE_FORMAT_R8_SNORM, SVGA3D_R8_SNORM, SVGA3D_R8_SNORM, SVGA3D_R8_SNORM, 0 },
136 { PIPE_FORMAT_R8G8_SNORM, SVGA3D_R8G8_SNORM, SVGA3D_R8G8_SNORM, SVGA3D_R8G8_SNORM, 0 },
137 { PIPE_FORMAT_R8G8B8_SNORM, SVGA3D_R8G8B8A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
138 { PIPE_FORMAT_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, 0 },
139 { 78, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
140 { 79, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
141 { 80, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
142 { 81, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
143 { PIPE_FORMAT_R8_SSCALED, SVGA3D_R8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
144 { PIPE_FORMAT_R8G8_SSCALED, SVGA3D_R8G8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
145 { PIPE_FORMAT_R8G8B8_SSCALED, SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_I_TO_F_CAST },
146 { PIPE_FORMAT_R8G8B8A8_SSCALED, SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
147 { 86, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
148 { PIPE_FORMAT_R32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
149 { PIPE_FORMAT_R32G32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
150 { PIPE_FORMAT_R32G32B32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
151 { PIPE_FORMAT_R32G32B32A32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
152 { PIPE_FORMAT_R16_FLOAT, SVGA3D_R16_FLOAT, SVGA3D_R16_FLOAT, SVGA3D_R16_FLOAT, TF_GEN_MIPS },
153 { PIPE_FORMAT_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, TF_GEN_MIPS },
154 { PIPE_FORMAT_R16G16B16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
155 { PIPE_FORMAT_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, TF_GEN_MIPS },
156 { PIPE_FORMAT_L8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
157 { PIPE_FORMAT_L8A8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
158 { PIPE_FORMAT_R8G8B8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
159 { PIPE_FORMAT_A8B8G8R8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
160 { PIPE_FORMAT_X8B8G8R8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
161 { PIPE_FORMAT_B8G8R8A8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8A8_UNORM_SRGB, SVGA3D_FORMAT_INVALID, TF_GEN_MIPS },
162 { PIPE_FORMAT_B8G8R8X8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8X8_UNORM_SRGB, SVGA3D_FORMAT_INVALID, TF_GEN_MIPS },
163 { PIPE_FORMAT_A8R8G8B8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
164 { PIPE_FORMAT_X8R8G8B8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
165 { PIPE_FORMAT_R8G8B8A8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_R8G8B8A8_UNORM_SRGB, SVGA3D_FORMAT_INVALID, TF_GEN_MIPS },
166 { PIPE_FORMAT_DXT1_RGB, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM, SVGA3D_FORMAT_INVALID, 0 },
167 { PIPE_FORMAT_DXT1_RGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM, SVGA3D_FORMAT_INVALID, 0 },
168 { PIPE_FORMAT_DXT3_RGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC2_UNORM, SVGA3D_FORMAT_INVALID, 0 },
169 { PIPE_FORMAT_DXT5_RGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC3_UNORM, SVGA3D_FORMAT_INVALID, 0 },
170 { PIPE_FORMAT_DXT1_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM_SRGB, SVGA3D_FORMAT_INVALID, 0 },
171 { PIPE_FORMAT_DXT1_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM_SRGB, SVGA3D_FORMAT_INVALID, 0 },
172 { PIPE_FORMAT_DXT3_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC2_UNORM_SRGB, SVGA3D_FORMAT_INVALID, 0 },
173 { PIPE_FORMAT_DXT5_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC3_UNORM_SRGB, SVGA3D_FORMAT_INVALID, 0 },
174 { PIPE_FORMAT_RGTC1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC4_UNORM, SVGA3D_FORMAT_INVALID, 0 },
175 { PIPE_FORMAT_RGTC1_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC4_SNORM, SVGA3D_FORMAT_INVALID, 0 },
176 { PIPE_FORMAT_RGTC2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC5_UNORM, SVGA3D_FORMAT_INVALID, 0 },
177 { PIPE_FORMAT_RGTC2_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC5_SNORM, SVGA3D_FORMAT_INVALID, 0 },
178 { PIPE_FORMAT_R8G8_B8G8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
179 { PIPE_FORMAT_G8R8_G8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
180 { PIPE_FORMAT_R8SG8SB8UX8U_NORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
181 { PIPE_FORMAT_R5SG5SB6U_NORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
182 { PIPE_FORMAT_A8B8G8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
183 { PIPE_FORMAT_B5G5R5X1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
184 { PIPE_FORMAT_R10G10B10A2_USCALED, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_USCALED },
185 { PIPE_FORMAT_R11G11B10_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_R11G11B10_FLOAT, SVGA3D_R11G11B10_FLOAT, TF_GEN_MIPS },
186 { PIPE_FORMAT_R9G9B9E5_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_R9G9B9E5_SHAREDEXP, SVGA3D_FORMAT_INVALID, 0 },
187 { PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_D32_FLOAT_S8X24_UINT, SVGA3D_FORMAT_INVALID, 0 },
188 { PIPE_FORMAT_R1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
189 { PIPE_FORMAT_R10G10B10X2_USCALED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
190 { PIPE_FORMAT_R10G10B10X2_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
191 { PIPE_FORMAT_L4A4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
192 { PIPE_FORMAT_B10G10R10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA },
193 { PIPE_FORMAT_R10SG10SB10SA2U_NORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
194 { PIPE_FORMAT_R8G8Bx_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
195 { PIPE_FORMAT_R8G8B8X8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
196 { PIPE_FORMAT_B4G4R4X4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
197 { PIPE_FORMAT_X24S8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
198 { PIPE_FORMAT_S8X24_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
199 { PIPE_FORMAT_X32_S8X24_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
200 { PIPE_FORMAT_B2G3R3_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
201 { PIPE_FORMAT_L16A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16G16_UNORM, TF_XXXY },
202 { PIPE_FORMAT_A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UNORM, TF_000X },
203 { PIPE_FORMAT_I16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UNORM, TF_XXXX },
204 { PIPE_FORMAT_LATC1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
205 { PIPE_FORMAT_LATC1_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
206 { PIPE_FORMAT_LATC2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
207 { PIPE_FORMAT_LATC2_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
208 { PIPE_FORMAT_A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
209 { PIPE_FORMAT_L8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
210 { PIPE_FORMAT_L8A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
211 { PIPE_FORMAT_I8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
212 { PIPE_FORMAT_A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
213 { PIPE_FORMAT_L16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
214 { PIPE_FORMAT_L16A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
215 { PIPE_FORMAT_I16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
216 { PIPE_FORMAT_A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_FLOAT, TF_000X },
217 { PIPE_FORMAT_L16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_FLOAT, TF_XXX1 },
218 { PIPE_FORMAT_L16A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16G16_FLOAT, TF_XXXY },
219 { PIPE_FORMAT_I16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_FLOAT, TF_XXXX },
220 { PIPE_FORMAT_A32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_FLOAT, TF_000X },
221 { PIPE_FORMAT_L32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_FLOAT, TF_XXX1 },
222 { PIPE_FORMAT_L32A32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32G32_FLOAT, TF_XXXY },
223 { PIPE_FORMAT_I32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_FLOAT, TF_XXXX },
224 { PIPE_FORMAT_YV12, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
225 { PIPE_FORMAT_YV16, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
226 { PIPE_FORMAT_IYUV, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
227 { PIPE_FORMAT_NV12, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
228 { PIPE_FORMAT_NV21, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
229 { PIPE_FORMAT_A4R4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
230 { PIPE_FORMAT_R4A4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
231 { PIPE_FORMAT_R8A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
232 { PIPE_FORMAT_A8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
233 { PIPE_FORMAT_R10G10B10A2_SSCALED, SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_SSCALED },
234 { PIPE_FORMAT_R10G10B10A2_SNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_SNORM },
235 { PIPE_FORMAT_B10G10R10A2_USCALED, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_USCALED },
236 { PIPE_FORMAT_B10G10R10A2_SSCALED, SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_SSCALED },
237 { PIPE_FORMAT_B10G10R10A2_SNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_SNORM },
238 { PIPE_FORMAT_R8_UINT, SVGA3D_R8_UINT, SVGA3D_R8_UINT, SVGA3D_R8_UINT, 0 },
239 { PIPE_FORMAT_R8G8_UINT, SVGA3D_R8G8_UINT, SVGA3D_R8G8_UINT, SVGA3D_R8G8_UINT, 0 },
240 { PIPE_FORMAT_R8G8B8_UINT, SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
241 { PIPE_FORMAT_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, 0 },
242 { PIPE_FORMAT_R8_SINT, SVGA3D_R8_SINT, SVGA3D_R8_SINT, SVGA3D_R8_SINT, 0 },
243 { PIPE_FORMAT_R8G8_SINT, SVGA3D_R8G8_SINT, SVGA3D_R8G8_SINT, SVGA3D_R8G8_SINT, 0 },
244 { PIPE_FORMAT_R8G8B8_SINT, SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
245 { PIPE_FORMAT_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, 0 },
246 { PIPE_FORMAT_R16_UINT, SVGA3D_R16_UINT, SVGA3D_R16_UINT, SVGA3D_R16_UINT, 0 },
247 { PIPE_FORMAT_R16G16_UINT, SVGA3D_R16G16_UINT, SVGA3D_R16G16_UINT, SVGA3D_R16G16_UINT, 0 },
248 { PIPE_FORMAT_R16G16B16_UINT, SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
249 { PIPE_FORMAT_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, 0 },
250 { PIPE_FORMAT_R16_SINT, SVGA3D_R16_SINT, SVGA3D_R16_SINT, SVGA3D_R16_SINT, 0 },
251 { PIPE_FORMAT_R16G16_SINT, SVGA3D_R16G16_SINT, SVGA3D_R16G16_SINT, SVGA3D_R16G16_SINT, 0 },
252 { PIPE_FORMAT_R16G16B16_SINT, SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
253 { PIPE_FORMAT_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, 0 },
254 { PIPE_FORMAT_R32_UINT, SVGA3D_R32_UINT, SVGA3D_R32_UINT, SVGA3D_R32_UINT, 0 },
255 { PIPE_FORMAT_R32G32_UINT, SVGA3D_R32G32_UINT, SVGA3D_R32G32_UINT, SVGA3D_R32G32_UINT, 0 },
256 { PIPE_FORMAT_R32G32B32_UINT, SVGA3D_R32G32B32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
257 { PIPE_FORMAT_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, 0 },
258 { PIPE_FORMAT_R32_SINT, SVGA3D_R32_SINT, SVGA3D_R32_SINT, SVGA3D_R32_SINT, 0 },
259 { PIPE_FORMAT_R32G32_SINT, SVGA3D_R32G32_SINT, SVGA3D_R32G32_SINT, SVGA3D_R32G32_SINT, 0 },
260 { PIPE_FORMAT_R32G32B32_SINT, SVGA3D_R32G32B32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
261 { PIPE_FORMAT_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, 0 },
262 { PIPE_FORMAT_A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UINT, TF_000X },
263 { PIPE_FORMAT_I8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UINT, TF_XXXX },
264 { PIPE_FORMAT_L8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UINT, TF_XXX1 },
265 { PIPE_FORMAT_L8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8G8_UINT, TF_XXXY },
266 { PIPE_FORMAT_A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_SINT, TF_000X },
267 { PIPE_FORMAT_I8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_SINT, TF_XXXX },
268 { PIPE_FORMAT_L8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_SINT, TF_XXX1 },
269 { PIPE_FORMAT_L8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8G8_SINT, TF_XXXY },
270 { PIPE_FORMAT_A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UINT, TF_000X },
271 { PIPE_FORMAT_I16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UINT, TF_XXXX },
272 { PIPE_FORMAT_L16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UINT, TF_XXX1 },
273 { PIPE_FORMAT_L16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16G16_UINT, TF_XXXY },
274 { PIPE_FORMAT_A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_SINT, TF_000X },
275 { PIPE_FORMAT_I16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_SINT, TF_XXXX },
276 { PIPE_FORMAT_L16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_SINT, TF_XXX1 },
277 { PIPE_FORMAT_L16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16G16_SINT, TF_XXXY },
278 { PIPE_FORMAT_A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_UINT, TF_000X },
279 { PIPE_FORMAT_I32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_UINT, TF_XXXX },
280 { PIPE_FORMAT_L32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_UINT, TF_XXX1 },
281 { PIPE_FORMAT_L32A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32G32_UINT, TF_XXXY },
282 { PIPE_FORMAT_A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_SINT, TF_000X },
283 { PIPE_FORMAT_I32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_SINT, TF_XXXX },
284 { PIPE_FORMAT_L32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_SINT, TF_XXX1 },
285 { PIPE_FORMAT_L32A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32G32_SINT, TF_XXXY },
286 { PIPE_FORMAT_B10G10R10A2_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
287 { PIPE_FORMAT_ETC1_RGB8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
288 { PIPE_FORMAT_R8G8_R8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
289 { PIPE_FORMAT_G8R8_B8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
290 { PIPE_FORMAT_R8G8B8X8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
291 { PIPE_FORMAT_R8G8B8X8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
292 { PIPE_FORMAT_R8G8B8X8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
293 { PIPE_FORMAT_R8G8B8X8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
294 { PIPE_FORMAT_B10G10R10X2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
295 { PIPE_FORMAT_R16G16B16X16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
296 { PIPE_FORMAT_R16G16B16X16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
297 { PIPE_FORMAT_R16G16B16X16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
298 { PIPE_FORMAT_R16G16B16X16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
299 { PIPE_FORMAT_R16G16B16X16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
300 { PIPE_FORMAT_R32G32B32X32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
301 { PIPE_FORMAT_R32G32B32X32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
302 { PIPE_FORMAT_R32G32B32X32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
303 { PIPE_FORMAT_R8A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
304 { PIPE_FORMAT_R16A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
305 { PIPE_FORMAT_R16A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
306 { PIPE_FORMAT_R16A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
307 { PIPE_FORMAT_R32A32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
308 { PIPE_FORMAT_R8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
309 { PIPE_FORMAT_R8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
310 { PIPE_FORMAT_R16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
311 { PIPE_FORMAT_R16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
312 { PIPE_FORMAT_R32A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
313 { PIPE_FORMAT_R32A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
314 { PIPE_FORMAT_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, 0 },
315 { PIPE_FORMAT_B5G6R5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
316 { PIPE_FORMAT_BPTC_RGBA_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
317 { PIPE_FORMAT_BPTC_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
318 { PIPE_FORMAT_BPTC_RGB_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
319 { PIPE_FORMAT_BPTC_RGB_UFLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
320 { PIPE_FORMAT_A8L8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
321 { PIPE_FORMAT_A8L8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
322 { PIPE_FORMAT_A8L8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
323 { PIPE_FORMAT_A16L16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
324 { PIPE_FORMAT_G8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
325 { PIPE_FORMAT_G8R8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
326 { PIPE_FORMAT_G16R16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
327 { PIPE_FORMAT_G16R16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
328 { PIPE_FORMAT_A8B8G8R8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
329 { PIPE_FORMAT_X8B8G8R8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
330 { PIPE_FORMAT_ETC2_RGB8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
331 { PIPE_FORMAT_ETC2_SRGB8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
332 { PIPE_FORMAT_ETC2_RGB8A1, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
333 { PIPE_FORMAT_ETC2_SRGB8A1, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
334 { PIPE_FORMAT_ETC2_RGBA8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
335 { PIPE_FORMAT_ETC2_SRGBA8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
336 { PIPE_FORMAT_ETC2_R11_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
337 { PIPE_FORMAT_ETC2_R11_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
338 { PIPE_FORMAT_ETC2_RG11_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
339 { PIPE_FORMAT_ETC2_RG11_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
340 { PIPE_FORMAT_ASTC_4x4, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
341 { PIPE_FORMAT_ASTC_5x4, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
342 { PIPE_FORMAT_ASTC_5x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
343 { PIPE_FORMAT_ASTC_6x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
344 { PIPE_FORMAT_ASTC_6x6, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
345 { PIPE_FORMAT_ASTC_8x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
346 { PIPE_FORMAT_ASTC_8x6, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
347 { PIPE_FORMAT_ASTC_8x8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
348 { PIPE_FORMAT_ASTC_10x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
349 { PIPE_FORMAT_ASTC_10x6, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
350 { PIPE_FORMAT_ASTC_10x8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
351 { PIPE_FORMAT_ASTC_10x10, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
352 { PIPE_FORMAT_ASTC_12x10, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
353 { PIPE_FORMAT_ASTC_12x12, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
354 { PIPE_FORMAT_ASTC_4x4_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
355 { PIPE_FORMAT_ASTC_5x4_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
356 { PIPE_FORMAT_ASTC_5x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
357 { PIPE_FORMAT_ASTC_6x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
358 { PIPE_FORMAT_ASTC_6x6_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
359 { PIPE_FORMAT_ASTC_8x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
360 { PIPE_FORMAT_ASTC_8x6_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
361 { PIPE_FORMAT_ASTC_8x8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
362 { PIPE_FORMAT_ASTC_10x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
363 { PIPE_FORMAT_ASTC_10x6_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
364 { PIPE_FORMAT_ASTC_10x8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
365 { PIPE_FORMAT_ASTC_10x10_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
366 { PIPE_FORMAT_ASTC_12x10_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
367 { PIPE_FORMAT_ASTC_12x12_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
368 { PIPE_FORMAT_P016, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
369 { PIPE_FORMAT_R10G10B10X2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
370 { PIPE_FORMAT_A1B5G5R5_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
371 { PIPE_FORMAT_X1B5G5R5_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
372 { PIPE_FORMAT_A4B4G4R4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
373 { PIPE_FORMAT_R8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
374 { PIPE_FORMAT_A8L8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
375 { PIPE_FORMAT_G8R8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
376 { PIPE_FORMAT_A8B8G8R8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
377 { PIPE_FORMAT_X8B8G8R8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
378 { PIPE_FORMAT_ATC_RGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
379 { PIPE_FORMAT_ATC_RGBA_EXPLICIT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
380 { PIPE_FORMAT_ATC_RGBA_INTERPOLATED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
381 { PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
382 { PIPE_FORMAT_AYUV, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
383 { PIPE_FORMAT_XYUV, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
384 };
385
386
387 static const struct vgpu10_format_entry *
388 svga_format_entry(enum pipe_format format)
389 {
390 assert(format < ARRAY_SIZE(format_conversion_table));
391 if (format >= ARRAY_SIZE(format_conversion_table))
392 return &format_conversion_table[PIPE_FORMAT_NONE];
393 else
394 return &format_conversion_table[format];
395 }
396
397 /**
398 * Translate a gallium vertex format to a vgpu10 vertex format.
399 * Also, return any special vertex format flags.
400 */
401 void
402 svga_translate_vertex_format_vgpu10(enum pipe_format format,
403 SVGA3dSurfaceFormat *svga_format,
404 unsigned *vf_flags)
405 {
406 const struct vgpu10_format_entry *entry = svga_format_entry(format);
407
408 *svga_format = entry->vertex_format;
409 *vf_flags = entry->flags;
410 }
411
412
413 /**
414 * Translate a gallium pixel format to a vgpu10 format
415 * to be used in a shader resource view for a texture buffer.
416 * Also return any special texture format flags such as
417 * any special swizzle mask.
418 */
419 void
420 svga_translate_texture_buffer_view_format(enum pipe_format format,
421 SVGA3dSurfaceFormat *svga_format,
422 unsigned *tf_flags)
423 {
424 const struct vgpu10_format_entry *entry = svga_format_entry(format);
425
426 *svga_format = entry->view_format;
427 *tf_flags = entry->flags;
428 }
429
430
431 /**
432 * Translate a gallium scanout format to a svga format valid
433 * for screen target surface.
434 */
435 static SVGA3dSurfaceFormat
436 svga_translate_screen_target_format_vgpu10(enum pipe_format format)
437 {
438 switch (format) {
439 case PIPE_FORMAT_B8G8R8A8_UNORM:
440 return SVGA3D_B8G8R8A8_UNORM;
441 case PIPE_FORMAT_B8G8R8X8_UNORM:
442 return SVGA3D_B8G8R8X8_UNORM;
443 case PIPE_FORMAT_B5G6R5_UNORM:
444 return SVGA3D_R5G6B5;
445 case PIPE_FORMAT_B5G5R5A1_UNORM:
446 return SVGA3D_A1R5G5B5;
447 default:
448 debug_printf("Invalid format %s specified for screen target\n",
449 svga_format_name(format));
450 return SVGA3D_FORMAT_INVALID;
451 }
452 }
453
454 /*
455 * Translate from gallium format to SVGA3D format.
456 */
457 SVGA3dSurfaceFormat
458 svga_translate_format(const struct svga_screen *ss,
459 enum pipe_format format,
460 unsigned bind)
461 {
462 const struct vgpu10_format_entry *entry = svga_format_entry(format);
463
464 if (ss->sws->have_vgpu10) {
465 if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) {
466 return entry->vertex_format;
467 }
468 else if (bind & PIPE_BIND_SCANOUT) {
469 return svga_translate_screen_target_format_vgpu10(format);
470 }
471 else {
472 return entry->pixel_format;
473 }
474 }
475
476 switch(format) {
477 case PIPE_FORMAT_B8G8R8A8_UNORM:
478 return SVGA3D_A8R8G8B8;
479 case PIPE_FORMAT_B8G8R8X8_UNORM:
480 return SVGA3D_X8R8G8B8;
481
482 /* sRGB required for GL2.1 */
483 case PIPE_FORMAT_B8G8R8A8_SRGB:
484 return SVGA3D_A8R8G8B8;
485 case PIPE_FORMAT_DXT1_SRGB:
486 case PIPE_FORMAT_DXT1_SRGBA:
487 return SVGA3D_DXT1;
488 case PIPE_FORMAT_DXT3_SRGBA:
489 return SVGA3D_DXT3;
490 case PIPE_FORMAT_DXT5_SRGBA:
491 return SVGA3D_DXT5;
492
493 case PIPE_FORMAT_B5G6R5_UNORM:
494 return SVGA3D_R5G6B5;
495 case PIPE_FORMAT_B5G5R5A1_UNORM:
496 return SVGA3D_A1R5G5B5;
497 case PIPE_FORMAT_B4G4R4A4_UNORM:
498 return SVGA3D_A4R4G4B4;
499
500 case PIPE_FORMAT_R16G16B16A16_UNORM:
501 return SVGA3D_A16B16G16R16;
502
503 case PIPE_FORMAT_Z16_UNORM:
504 assert(!ss->sws->have_vgpu10);
505 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.z16 : SVGA3D_Z_D16;
506 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
507 assert(!ss->sws->have_vgpu10);
508 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.s8z24 : SVGA3D_Z_D24S8;
509 case PIPE_FORMAT_X8Z24_UNORM:
510 assert(!ss->sws->have_vgpu10);
511 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.x8z24 : SVGA3D_Z_D24X8;
512
513 case PIPE_FORMAT_A8_UNORM:
514 return SVGA3D_ALPHA8;
515 case PIPE_FORMAT_L8_UNORM:
516 return SVGA3D_LUMINANCE8;
517
518 case PIPE_FORMAT_DXT1_RGB:
519 case PIPE_FORMAT_DXT1_RGBA:
520 return SVGA3D_DXT1;
521 case PIPE_FORMAT_DXT3_RGBA:
522 return SVGA3D_DXT3;
523 case PIPE_FORMAT_DXT5_RGBA:
524 return SVGA3D_DXT5;
525
526 /* Float formats (only 1, 2 and 4-component formats supported) */
527 case PIPE_FORMAT_R32_FLOAT:
528 return SVGA3D_R_S23E8;
529 case PIPE_FORMAT_R32G32_FLOAT:
530 return SVGA3D_RG_S23E8;
531 case PIPE_FORMAT_R32G32B32A32_FLOAT:
532 return SVGA3D_ARGB_S23E8;
533 case PIPE_FORMAT_R16_FLOAT:
534 return SVGA3D_R_S10E5;
535 case PIPE_FORMAT_R16G16_FLOAT:
536 return SVGA3D_RG_S10E5;
537 case PIPE_FORMAT_R16G16B16A16_FLOAT:
538 return SVGA3D_ARGB_S10E5;
539
540 case PIPE_FORMAT_Z32_UNORM:
541 /* SVGA3D_Z_D32 is not yet unsupported */
542 /* fall-through */
543 default:
544 return SVGA3D_FORMAT_INVALID;
545 }
546 }
547
548
549 /*
550 * Format capability description entry.
551 */
552 struct format_cap {
553 const char *name;
554
555 SVGA3dSurfaceFormat format;
556
557 /*
558 * Capability index corresponding to the format.
559 */
560 SVGA3dDevCapIndex devcap;
561
562 /* size of each pixel/block */
563 unsigned block_width, block_height, block_bytes;
564
565 /*
566 * Mask of supported SVGA3dFormatOp operations, to be inferred when the
567 * capability is not explicitly present.
568 */
569 uint32 defaultOperations;
570 };
571
572
573 /*
574 * Format capability description table.
575 *
576 * Ordered by increasing SVGA3dSurfaceFormat value, but with gaps.
577 */
578 static const struct format_cap format_cap_table[] = {
579 {
580 "SVGA3D_FORMAT_INVALID",
581 SVGA3D_FORMAT_INVALID, 0, 0, 0, 0, 0
582 },
583 {
584 "SVGA3D_X8R8G8B8",
585 SVGA3D_X8R8G8B8,
586 SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8,
587 1, 1, 4,
588 SVGA3DFORMAT_OP_TEXTURE |
589 SVGA3DFORMAT_OP_CUBETEXTURE |
590 SVGA3DFORMAT_OP_VOLUMETEXTURE |
591 SVGA3DFORMAT_OP_DISPLAYMODE |
592 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
593 },
594 {
595 "SVGA3D_A8R8G8B8",
596 SVGA3D_A8R8G8B8,
597 SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8,
598 1, 1, 4,
599 SVGA3DFORMAT_OP_TEXTURE |
600 SVGA3DFORMAT_OP_CUBETEXTURE |
601 SVGA3DFORMAT_OP_VOLUMETEXTURE |
602 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
603 },
604 {
605 "SVGA3D_R5G6B5",
606 SVGA3D_R5G6B5,
607 SVGA3D_DEVCAP_SURFACEFMT_R5G6B5,
608 1, 1, 2,
609 SVGA3DFORMAT_OP_TEXTURE |
610 SVGA3DFORMAT_OP_CUBETEXTURE |
611 SVGA3DFORMAT_OP_VOLUMETEXTURE |
612 SVGA3DFORMAT_OP_DISPLAYMODE |
613 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
614 },
615 {
616 "SVGA3D_X1R5G5B5",
617 SVGA3D_X1R5G5B5,
618 SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5,
619 1, 1, 2,
620 SVGA3DFORMAT_OP_TEXTURE |
621 SVGA3DFORMAT_OP_CUBETEXTURE |
622 SVGA3DFORMAT_OP_VOLUMETEXTURE |
623 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
624 },
625 {
626 "SVGA3D_A1R5G5B5",
627 SVGA3D_A1R5G5B5,
628 SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5,
629 1, 1, 2,
630 SVGA3DFORMAT_OP_TEXTURE |
631 SVGA3DFORMAT_OP_CUBETEXTURE |
632 SVGA3DFORMAT_OP_VOLUMETEXTURE |
633 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
634 },
635 {
636 "SVGA3D_A4R4G4B4",
637 SVGA3D_A4R4G4B4,
638 SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4,
639 1, 1, 2,
640 SVGA3DFORMAT_OP_TEXTURE |
641 SVGA3DFORMAT_OP_CUBETEXTURE |
642 SVGA3DFORMAT_OP_VOLUMETEXTURE |
643 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
644 },
645 {
646 /*
647 * SVGA3D_Z_D32 is not yet supported, and has no corresponding
648 * SVGA3D_DEVCAP_xxx.
649 */
650 "SVGA3D_Z_D32",
651 SVGA3D_Z_D32, 0, 0, 0, 0, 0
652 },
653 {
654 "SVGA3D_Z_D16",
655 SVGA3D_Z_D16,
656 SVGA3D_DEVCAP_SURFACEFMT_Z_D16,
657 1, 1, 2,
658 SVGA3DFORMAT_OP_ZSTENCIL
659 },
660 {
661 "SVGA3D_Z_D24S8",
662 SVGA3D_Z_D24S8,
663 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8,
664 1, 1, 4,
665 SVGA3DFORMAT_OP_ZSTENCIL
666 },
667 {
668 "SVGA3D_Z_D15S1",
669 SVGA3D_Z_D15S1,
670 SVGA3D_DEVCAP_MAX,
671 1, 1, 2,
672 SVGA3DFORMAT_OP_ZSTENCIL
673 },
674 {
675 "SVGA3D_LUMINANCE8",
676 SVGA3D_LUMINANCE8,
677 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8,
678 1, 1, 1,
679 SVGA3DFORMAT_OP_TEXTURE |
680 SVGA3DFORMAT_OP_CUBETEXTURE |
681 SVGA3DFORMAT_OP_VOLUMETEXTURE
682 },
683 {
684 /*
685 * SVGA3D_LUMINANCE4_ALPHA4 is not supported, and has no corresponding
686 * SVGA3D_DEVCAP_xxx.
687 */
688 "SVGA3D_LUMINANCE4_ALPHA4",
689 SVGA3D_LUMINANCE4_ALPHA4, 0, 0, 0, 0, 0
690 },
691 {
692 "SVGA3D_LUMINANCE16",
693 SVGA3D_LUMINANCE16,
694 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16,
695 1, 1, 2,
696 SVGA3DFORMAT_OP_TEXTURE |
697 SVGA3DFORMAT_OP_CUBETEXTURE |
698 SVGA3DFORMAT_OP_VOLUMETEXTURE
699 },
700 {
701 "SVGA3D_LUMINANCE8_ALPHA8",
702 SVGA3D_LUMINANCE8_ALPHA8,
703 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8,
704 1, 1, 2,
705 SVGA3DFORMAT_OP_TEXTURE |
706 SVGA3DFORMAT_OP_CUBETEXTURE |
707 SVGA3DFORMAT_OP_VOLUMETEXTURE
708 },
709 {
710 "SVGA3D_DXT1",
711 SVGA3D_DXT1,
712 SVGA3D_DEVCAP_SURFACEFMT_DXT1,
713 4, 4, 8,
714 SVGA3DFORMAT_OP_TEXTURE |
715 SVGA3DFORMAT_OP_CUBETEXTURE
716 },
717 {
718 "SVGA3D_DXT2",
719 SVGA3D_DXT2,
720 SVGA3D_DEVCAP_SURFACEFMT_DXT2,
721 4, 4, 8,
722 SVGA3DFORMAT_OP_TEXTURE |
723 SVGA3DFORMAT_OP_CUBETEXTURE
724 },
725 {
726 "SVGA3D_DXT3",
727 SVGA3D_DXT3,
728 SVGA3D_DEVCAP_SURFACEFMT_DXT3,
729 4, 4, 16,
730 SVGA3DFORMAT_OP_TEXTURE |
731 SVGA3DFORMAT_OP_CUBETEXTURE
732 },
733 {
734 "SVGA3D_DXT4",
735 SVGA3D_DXT4,
736 SVGA3D_DEVCAP_SURFACEFMT_DXT4,
737 4, 4, 16,
738 SVGA3DFORMAT_OP_TEXTURE |
739 SVGA3DFORMAT_OP_CUBETEXTURE
740 },
741 {
742 "SVGA3D_DXT5",
743 SVGA3D_DXT5,
744 SVGA3D_DEVCAP_SURFACEFMT_DXT5,
745 4, 4, 8,
746 SVGA3DFORMAT_OP_TEXTURE |
747 SVGA3DFORMAT_OP_CUBETEXTURE
748 },
749 {
750 "SVGA3D_BUMPU8V8",
751 SVGA3D_BUMPU8V8,
752 SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8,
753 1, 1, 2,
754 SVGA3DFORMAT_OP_TEXTURE |
755 SVGA3DFORMAT_OP_CUBETEXTURE |
756 SVGA3DFORMAT_OP_VOLUMETEXTURE
757 },
758 {
759 /*
760 * SVGA3D_BUMPL6V5U5 is unsupported; it has no corresponding
761 * SVGA3D_DEVCAP_xxx.
762 */
763 "SVGA3D_BUMPL6V5U5",
764 SVGA3D_BUMPL6V5U5, 0, 0, 0, 0, 0
765 },
766 {
767 "SVGA3D_BUMPX8L8V8U8",
768 SVGA3D_BUMPX8L8V8U8,
769 SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8,
770 1, 1, 4,
771 SVGA3DFORMAT_OP_TEXTURE |
772 SVGA3DFORMAT_OP_CUBETEXTURE
773 },
774 {
775 "SVGA3D_FORMAT_DEAD1",
776 SVGA3D_FORMAT_DEAD1, 0, 0, 0, 0, 0
777 },
778 {
779 "SVGA3D_ARGB_S10E5",
780 SVGA3D_ARGB_S10E5,
781 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5,
782 1, 1, 2,
783 SVGA3DFORMAT_OP_TEXTURE |
784 SVGA3DFORMAT_OP_CUBETEXTURE |
785 SVGA3DFORMAT_OP_VOLUMETEXTURE |
786 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
787 },
788 {
789 "SVGA3D_ARGB_S23E8",
790 SVGA3D_ARGB_S23E8,
791 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8,
792 1, 1, 4,
793 SVGA3DFORMAT_OP_TEXTURE |
794 SVGA3DFORMAT_OP_CUBETEXTURE |
795 SVGA3DFORMAT_OP_VOLUMETEXTURE |
796 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
797 },
798 {
799 "SVGA3D_A2R10G10B10",
800 SVGA3D_A2R10G10B10,
801 SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10,
802 1, 1, 4,
803 SVGA3DFORMAT_OP_TEXTURE |
804 SVGA3DFORMAT_OP_CUBETEXTURE |
805 SVGA3DFORMAT_OP_VOLUMETEXTURE |
806 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
807 },
808 {
809 /*
810 * SVGA3D_V8U8 is unsupported; it has no corresponding
811 * SVGA3D_DEVCAP_xxx. SVGA3D_BUMPU8V8 should be used instead.
812 */
813 "SVGA3D_V8U8",
814 SVGA3D_V8U8, 0, 0, 0, 0, 0
815 },
816 {
817 "SVGA3D_Q8W8V8U8",
818 SVGA3D_Q8W8V8U8,
819 SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8,
820 1, 1, 4,
821 SVGA3DFORMAT_OP_TEXTURE |
822 SVGA3DFORMAT_OP_CUBETEXTURE
823 },
824 {
825 "SVGA3D_CxV8U8",
826 SVGA3D_CxV8U8,
827 SVGA3D_DEVCAP_SURFACEFMT_CxV8U8,
828 1, 1, 2,
829 SVGA3DFORMAT_OP_TEXTURE
830 },
831 {
832 /*
833 * SVGA3D_X8L8V8U8 is unsupported; it has no corresponding
834 * SVGA3D_DEVCAP_xxx. SVGA3D_BUMPX8L8V8U8 should be used instead.
835 */
836 "SVGA3D_X8L8V8U8",
837 SVGA3D_X8L8V8U8, 0, 0, 0, 0, 0
838 },
839 {
840 "SVGA3D_A2W10V10U10",
841 SVGA3D_A2W10V10U10,
842 SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10,
843 1, 1, 4,
844 SVGA3DFORMAT_OP_TEXTURE
845 },
846 {
847 "SVGA3D_ALPHA8",
848 SVGA3D_ALPHA8,
849 SVGA3D_DEVCAP_SURFACEFMT_ALPHA8,
850 1, 1, 1,
851 SVGA3DFORMAT_OP_TEXTURE |
852 SVGA3DFORMAT_OP_CUBETEXTURE |
853 SVGA3DFORMAT_OP_VOLUMETEXTURE
854 },
855 {
856 "SVGA3D_R_S10E5",
857 SVGA3D_R_S10E5,
858 SVGA3D_DEVCAP_SURFACEFMT_R_S10E5,
859 1, 1, 2,
860 SVGA3DFORMAT_OP_TEXTURE |
861 SVGA3DFORMAT_OP_VOLUMETEXTURE |
862 SVGA3DFORMAT_OP_CUBETEXTURE |
863 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
864 },
865 {
866 "SVGA3D_R_S23E8",
867 SVGA3D_R_S23E8,
868 SVGA3D_DEVCAP_SURFACEFMT_R_S23E8,
869 1, 1, 4,
870 SVGA3DFORMAT_OP_TEXTURE |
871 SVGA3DFORMAT_OP_VOLUMETEXTURE |
872 SVGA3DFORMAT_OP_CUBETEXTURE |
873 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
874 },
875 {
876 "SVGA3D_RG_S10E5",
877 SVGA3D_RG_S10E5,
878 SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5,
879 1, 1, 2,
880 SVGA3DFORMAT_OP_TEXTURE |
881 SVGA3DFORMAT_OP_VOLUMETEXTURE |
882 SVGA3DFORMAT_OP_CUBETEXTURE |
883 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
884 },
885 {
886 "SVGA3D_RG_S23E8",
887 SVGA3D_RG_S23E8,
888 SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8,
889 1, 1, 4,
890 SVGA3DFORMAT_OP_TEXTURE |
891 SVGA3DFORMAT_OP_VOLUMETEXTURE |
892 SVGA3DFORMAT_OP_CUBETEXTURE |
893 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
894 },
895 {
896 /*
897 * SVGA3D_BUFFER is a placeholder format for index/vertex buffers.
898 */
899 "SVGA3D_BUFFER",
900 SVGA3D_BUFFER, 0, 1, 1, 1, 0
901 },
902 {
903 "SVGA3D_Z_D24X8",
904 SVGA3D_Z_D24X8,
905 SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8,
906 1, 1, 4,
907 SVGA3DFORMAT_OP_ZSTENCIL
908 },
909 {
910 "SVGA3D_V16U16",
911 SVGA3D_V16U16,
912 SVGA3D_DEVCAP_SURFACEFMT_V16U16,
913 1, 1, 4,
914 SVGA3DFORMAT_OP_TEXTURE |
915 SVGA3DFORMAT_OP_CUBETEXTURE |
916 SVGA3DFORMAT_OP_VOLUMETEXTURE
917 },
918 {
919 "SVGA3D_G16R16",
920 SVGA3D_G16R16,
921 SVGA3D_DEVCAP_SURFACEFMT_G16R16,
922 1, 1, 4,
923 SVGA3DFORMAT_OP_TEXTURE |
924 SVGA3DFORMAT_OP_CUBETEXTURE |
925 SVGA3DFORMAT_OP_VOLUMETEXTURE |
926 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
927 },
928 {
929 "SVGA3D_A16B16G16R16",
930 SVGA3D_A16B16G16R16,
931 SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16,
932 1, 1, 8,
933 SVGA3DFORMAT_OP_TEXTURE |
934 SVGA3DFORMAT_OP_CUBETEXTURE |
935 SVGA3DFORMAT_OP_VOLUMETEXTURE |
936 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
937 },
938 {
939 "SVGA3D_UYVY",
940 SVGA3D_UYVY,
941 SVGA3D_DEVCAP_SURFACEFMT_UYVY,
942 0, 0, 0, 0
943 },
944 {
945 "SVGA3D_YUY2",
946 SVGA3D_YUY2,
947 SVGA3D_DEVCAP_SURFACEFMT_YUY2,
948 0, 0, 0, 0
949 },
950 {
951 "SVGA3D_NV12",
952 SVGA3D_NV12,
953 SVGA3D_DEVCAP_SURFACEFMT_NV12,
954 0, 0, 0, 0
955 },
956 {
957 "SVGA3D_AYUV",
958 SVGA3D_AYUV,
959 SVGA3D_DEVCAP_SURFACEFMT_AYUV,
960 0, 0, 0, 0
961 },
962 {
963 "SVGA3D_R32G32B32A32_TYPELESS",
964 SVGA3D_R32G32B32A32_TYPELESS,
965 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS,
966 1, 1, 16, 0
967 },
968 {
969 "SVGA3D_R32G32B32A32_UINT",
970 SVGA3D_R32G32B32A32_UINT,
971 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT,
972 1, 1, 16, 0
973 },
974 {
975 "SVGA3D_R32G32B32A32_SINT",
976 SVGA3D_R32G32B32A32_SINT,
977 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT,
978 1, 1, 16, 0
979 },
980 {
981 "SVGA3D_R32G32B32_TYPELESS",
982 SVGA3D_R32G32B32_TYPELESS,
983 SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS,
984 1, 1, 12, 0
985 },
986 {
987 "SVGA3D_R32G32B32_FLOAT",
988 SVGA3D_R32G32B32_FLOAT,
989 SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT,
990 1, 1, 12, 0
991 },
992 {
993 "SVGA3D_R32G32B32_UINT",
994 SVGA3D_R32G32B32_UINT,
995 SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT,
996 1, 1, 12, 0
997 },
998 {
999 "SVGA3D_R32G32B32_SINT",
1000 SVGA3D_R32G32B32_SINT,
1001 SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT,
1002 1, 1, 12, 0
1003 },
1004 {
1005 "SVGA3D_R16G16B16A16_TYPELESS",
1006 SVGA3D_R16G16B16A16_TYPELESS,
1007 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS,
1008 1, 1, 8, 0
1009 },
1010 {
1011 "SVGA3D_R16G16B16A16_UINT",
1012 SVGA3D_R16G16B16A16_UINT,
1013 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT,
1014 1, 1, 8, 0
1015 },
1016 {
1017 "SVGA3D_R16G16B16A16_SNORM",
1018 SVGA3D_R16G16B16A16_SNORM,
1019 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM,
1020 1, 1, 8, 0
1021 },
1022 {
1023 "SVGA3D_R16G16B16A16_SINT",
1024 SVGA3D_R16G16B16A16_SINT,
1025 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT,
1026 1, 1, 8, 0
1027 },
1028 {
1029 "SVGA3D_R32G32_TYPELESS",
1030 SVGA3D_R32G32_TYPELESS,
1031 SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS,
1032 1, 1, 8, 0
1033 },
1034 {
1035 "SVGA3D_R32G32_UINT",
1036 SVGA3D_R32G32_UINT,
1037 SVGA3D_DEVCAP_DXFMT_R32G32_UINT,
1038 1, 1, 8, 0
1039 },
1040 {
1041 "SVGA3D_R32G32_SINT",
1042 SVGA3D_R32G32_SINT,
1043 SVGA3D_DEVCAP_DXFMT_R32G32_SINT,
1044 1, 1, 8,
1045 0
1046 },
1047 {
1048 "SVGA3D_R32G8X24_TYPELESS",
1049 SVGA3D_R32G8X24_TYPELESS,
1050 SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS,
1051 1, 1, 8, 0
1052 },
1053 {
1054 "SVGA3D_D32_FLOAT_S8X24_UINT",
1055 SVGA3D_D32_FLOAT_S8X24_UINT,
1056 SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT,
1057 1, 1, 8, 0
1058 },
1059 {
1060 "SVGA3D_R32_FLOAT_X8X24",
1061 SVGA3D_R32_FLOAT_X8X24,
1062 SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24,
1063 1, 1, 8, 0
1064 },
1065 {
1066 "SVGA3D_X32_G8X24_UINT",
1067 SVGA3D_X32_G8X24_UINT,
1068 SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT,
1069 1, 1, 4, 0
1070 },
1071 {
1072 "SVGA3D_R10G10B10A2_TYPELESS",
1073 SVGA3D_R10G10B10A2_TYPELESS,
1074 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS,
1075 1, 1, 4, 0
1076 },
1077 {
1078 "SVGA3D_R10G10B10A2_UINT",
1079 SVGA3D_R10G10B10A2_UINT,
1080 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT,
1081 1, 1, 4, 0
1082 },
1083 {
1084 "SVGA3D_R11G11B10_FLOAT",
1085 SVGA3D_R11G11B10_FLOAT,
1086 SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT,
1087 1, 1, 4, 0
1088 },
1089 {
1090 "SVGA3D_R8G8B8A8_TYPELESS",
1091 SVGA3D_R8G8B8A8_TYPELESS,
1092 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS,
1093 1, 1, 4, 0
1094 },
1095 {
1096 "SVGA3D_R8G8B8A8_UNORM",
1097 SVGA3D_R8G8B8A8_UNORM,
1098 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM,
1099 1, 1, 4, 0
1100 },
1101 {
1102 "SVGA3D_R8G8B8A8_UNORM_SRGB",
1103 SVGA3D_R8G8B8A8_UNORM_SRGB,
1104 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB,
1105 1, 1, 4, 0
1106 },
1107 {
1108 "SVGA3D_R8G8B8A8_UINT",
1109 SVGA3D_R8G8B8A8_UINT,
1110 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT,
1111 1, 1, 4, 0
1112 },
1113 {
1114 "SVGA3D_R8G8B8A8_SINT",
1115 SVGA3D_R8G8B8A8_SINT,
1116 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT,
1117 1, 1, 4, 0
1118 },
1119 {
1120 "SVGA3D_R16G16_TYPELESS",
1121 SVGA3D_R16G16_TYPELESS,
1122 SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS,
1123 1, 1, 4, 0
1124 },
1125 {
1126 "SVGA3D_R16G16_UINT",
1127 SVGA3D_R16G16_UINT,
1128 SVGA3D_DEVCAP_DXFMT_R16G16_UINT,
1129 1, 1, 4, 0
1130 },
1131 {
1132 "SVGA3D_R16G16_SINT",
1133 SVGA3D_R16G16_SINT,
1134 SVGA3D_DEVCAP_DXFMT_R16G16_SINT,
1135 1, 1, 4, 0
1136 },
1137 {
1138 "SVGA3D_R32_TYPELESS",
1139 SVGA3D_R32_TYPELESS,
1140 SVGA3D_DEVCAP_DXFMT_R32_TYPELESS,
1141 1, 1, 4, 0
1142 },
1143 {
1144 "SVGA3D_D32_FLOAT",
1145 SVGA3D_D32_FLOAT,
1146 SVGA3D_DEVCAP_DXFMT_D32_FLOAT,
1147 1, 1, 4, 0
1148 },
1149 {
1150 "SVGA3D_R32_UINT",
1151 SVGA3D_R32_UINT,
1152 SVGA3D_DEVCAP_DXFMT_R32_UINT,
1153 1, 1, 4, 0
1154 },
1155 {
1156 "SVGA3D_R32_SINT",
1157 SVGA3D_R32_SINT,
1158 SVGA3D_DEVCAP_DXFMT_R32_SINT,
1159 1, 1, 4, 0
1160 },
1161 {
1162 "SVGA3D_R24G8_TYPELESS",
1163 SVGA3D_R24G8_TYPELESS,
1164 SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS,
1165 1, 1, 4, 0
1166 },
1167 {
1168 "SVGA3D_D24_UNORM_S8_UINT",
1169 SVGA3D_D24_UNORM_S8_UINT,
1170 SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT,
1171 1, 1, 4, 0
1172 },
1173 {
1174 "SVGA3D_R24_UNORM_X8",
1175 SVGA3D_R24_UNORM_X8,
1176 SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8,
1177 1, 1, 4, 0
1178 },
1179 {
1180 "SVGA3D_X24_G8_UINT",
1181 SVGA3D_X24_G8_UINT,
1182 SVGA3D_DEVCAP_DXFMT_X24_G8_UINT,
1183 1, 1, 4, 0
1184 },
1185 {
1186 "SVGA3D_R8G8_TYPELESS",
1187 SVGA3D_R8G8_TYPELESS,
1188 SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS,
1189 1, 1, 2, 0
1190 },
1191 {
1192 "SVGA3D_R8G8_UNORM",
1193 SVGA3D_R8G8_UNORM,
1194 SVGA3D_DEVCAP_DXFMT_R8G8_UNORM,
1195 1, 1, 2, 0
1196 },
1197 {
1198 "SVGA3D_R8G8_UINT",
1199 SVGA3D_R8G8_UINT,
1200 SVGA3D_DEVCAP_DXFMT_R8G8_UINT,
1201 1, 1, 2, 0
1202 },
1203 {
1204 "SVGA3D_R8G8_SINT",
1205 SVGA3D_R8G8_SINT,
1206 SVGA3D_DEVCAP_DXFMT_R8G8_SINT,
1207 1, 1, 2, 0
1208 },
1209 {
1210 "SVGA3D_R16_TYPELESS",
1211 SVGA3D_R16_TYPELESS,
1212 SVGA3D_DEVCAP_DXFMT_R16_TYPELESS,
1213 1, 1, 2, 0
1214 },
1215 {
1216 "SVGA3D_R16_UNORM",
1217 SVGA3D_R16_UNORM,
1218 SVGA3D_DEVCAP_DXFMT_R16_UNORM,
1219 1, 1, 2, 0
1220 },
1221 {
1222 "SVGA3D_R16_UINT",
1223 SVGA3D_R16_UINT,
1224 SVGA3D_DEVCAP_DXFMT_R16_UINT,
1225 1, 1, 2, 0
1226 },
1227 {
1228 "SVGA3D_R16_SNORM",
1229 SVGA3D_R16_SNORM,
1230 SVGA3D_DEVCAP_DXFMT_R16_SNORM,
1231 1, 1, 2, 0
1232 },
1233 {
1234 "SVGA3D_R16_SINT",
1235 SVGA3D_R16_SINT,
1236 SVGA3D_DEVCAP_DXFMT_R16_SINT,
1237 1, 1, 2, 0
1238 },
1239 {
1240 "SVGA3D_R8_TYPELESS",
1241 SVGA3D_R8_TYPELESS,
1242 SVGA3D_DEVCAP_DXFMT_R8_TYPELESS,
1243 1, 1, 1, 0
1244 },
1245 {
1246 "SVGA3D_R8_UNORM",
1247 SVGA3D_R8_UNORM,
1248 SVGA3D_DEVCAP_DXFMT_R8_UNORM,
1249 1, 1, 1, 0
1250 },
1251 {
1252 "SVGA3D_R8_UINT",
1253 SVGA3D_R8_UINT,
1254 SVGA3D_DEVCAP_DXFMT_R8_UINT,
1255 1, 1, 1, 0
1256 },
1257 {
1258 "SVGA3D_R8_SNORM",
1259 SVGA3D_R8_SNORM,
1260 SVGA3D_DEVCAP_DXFMT_R8_SNORM,
1261 1, 1, 1, 0
1262 },
1263 {
1264 "SVGA3D_R8_SINT",
1265 SVGA3D_R8_SINT,
1266 SVGA3D_DEVCAP_DXFMT_R8_SINT,
1267 1, 1, 1, 0
1268 },
1269 {
1270 "SVGA3D_P8",
1271 SVGA3D_P8, 0, 0, 0, 0, 0
1272 },
1273 {
1274 "SVGA3D_R9G9B9E5_SHAREDEXP",
1275 SVGA3D_R9G9B9E5_SHAREDEXP,
1276 SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP,
1277 1, 1, 4, 0
1278 },
1279 {
1280 "SVGA3D_R8G8_B8G8_UNORM",
1281 SVGA3D_R8G8_B8G8_UNORM, 0, 0, 0, 0, 0
1282 },
1283 {
1284 "SVGA3D_G8R8_G8B8_UNORM",
1285 SVGA3D_G8R8_G8B8_UNORM, 0, 0, 0, 0, 0
1286 },
1287 {
1288 "SVGA3D_BC1_TYPELESS",
1289 SVGA3D_BC1_TYPELESS,
1290 SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS,
1291 4, 4, 8, 0
1292 },
1293 {
1294 "SVGA3D_BC1_UNORM_SRGB",
1295 SVGA3D_BC1_UNORM_SRGB,
1296 SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB,
1297 4, 4, 8, 0
1298 },
1299 {
1300 "SVGA3D_BC2_TYPELESS",
1301 SVGA3D_BC2_TYPELESS,
1302 SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS,
1303 4, 4, 16, 0
1304 },
1305 {
1306 "SVGA3D_BC2_UNORM_SRGB",
1307 SVGA3D_BC2_UNORM_SRGB,
1308 SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB,
1309 4, 4, 16, 0
1310 },
1311 {
1312 "SVGA3D_BC3_TYPELESS",
1313 SVGA3D_BC3_TYPELESS,
1314 SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS,
1315 4, 4, 16, 0
1316 },
1317 {
1318 "SVGA3D_BC3_UNORM_SRGB",
1319 SVGA3D_BC3_UNORM_SRGB,
1320 SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB,
1321 4, 4, 16, 0
1322 },
1323 {
1324 "SVGA3D_BC4_TYPELESS",
1325 SVGA3D_BC4_TYPELESS,
1326 SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS,
1327 4, 4, 8, 0
1328 },
1329 {
1330 "SVGA3D_ATI1",
1331 SVGA3D_ATI1, 0, 0, 0, 0, 0
1332 },
1333 {
1334 "SVGA3D_BC4_SNORM",
1335 SVGA3D_BC4_SNORM,
1336 SVGA3D_DEVCAP_DXFMT_BC4_SNORM,
1337 4, 4, 8, 0
1338 },
1339 {
1340 "SVGA3D_BC5_TYPELESS",
1341 SVGA3D_BC5_TYPELESS,
1342 SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS,
1343 4, 4, 16, 0
1344 },
1345 {
1346 "SVGA3D_ATI2",
1347 SVGA3D_ATI2, 0, 0, 0, 0, 0
1348 },
1349 {
1350 "SVGA3D_BC5_SNORM",
1351 SVGA3D_BC5_SNORM,
1352 SVGA3D_DEVCAP_DXFMT_BC5_SNORM,
1353 4, 4, 16, 0
1354 },
1355 {
1356 "SVGA3D_R10G10B10_XR_BIAS_A2_UNORM",
1357 SVGA3D_R10G10B10_XR_BIAS_A2_UNORM, 0, 0, 0, 0, 0
1358 },
1359 {
1360 "SVGA3D_B8G8R8A8_TYPELESS",
1361 SVGA3D_B8G8R8A8_TYPELESS,
1362 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS,
1363 1, 1, 4, 0
1364 },
1365 {
1366 "SVGA3D_B8G8R8A8_UNORM_SRGB",
1367 SVGA3D_B8G8R8A8_UNORM_SRGB,
1368 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB,
1369 1, 1, 4, 0
1370 },
1371 {
1372 "SVGA3D_B8G8R8X8_TYPELESS",
1373 SVGA3D_B8G8R8X8_TYPELESS,
1374 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS,
1375 1, 1, 4, 0
1376 },
1377 {
1378 "SVGA3D_B8G8R8X8_UNORM_SRGB",
1379 SVGA3D_B8G8R8X8_UNORM_SRGB,
1380 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB,
1381 1, 1, 4, 0
1382 },
1383 {
1384 "SVGA3D_Z_DF16",
1385 SVGA3D_Z_DF16,
1386 SVGA3D_DEVCAP_SURFACEFMT_Z_DF16,
1387 1, 1, 2, 0
1388 },
1389 {
1390 "SVGA3D_Z_DF24",
1391 SVGA3D_Z_DF24,
1392 SVGA3D_DEVCAP_SURFACEFMT_Z_DF24,
1393 1, 1, 4, 0
1394 },
1395 {
1396 "SVGA3D_Z_D24S8_INT",
1397 SVGA3D_Z_D24S8_INT,
1398 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT,
1399 1, 1, 4, 0
1400 },
1401 {
1402 "SVGA3D_YV12",
1403 SVGA3D_YV12, 0, 0, 0, 0, 0
1404 },
1405 {
1406 "SVGA3D_R32G32B32A32_FLOAT",
1407 SVGA3D_R32G32B32A32_FLOAT,
1408 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT,
1409 1, 1, 16, 0
1410 },
1411 {
1412 "SVGA3D_R16G16B16A16_FLOAT",
1413 SVGA3D_R16G16B16A16_FLOAT,
1414 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT,
1415 1, 1, 8, 0
1416 },
1417 {
1418 "SVGA3D_R16G16B16A16_UNORM",
1419 SVGA3D_R16G16B16A16_UNORM,
1420 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM,
1421 1, 1, 8, 0
1422 },
1423 {
1424 "SVGA3D_R32G32_FLOAT",
1425 SVGA3D_R32G32_FLOAT,
1426 SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT,
1427 1, 1, 8, 0
1428 },
1429 {
1430 "SVGA3D_R10G10B10A2_UNORM",
1431 SVGA3D_R10G10B10A2_UNORM,
1432 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM,
1433 1, 1, 4, 0
1434 },
1435 {
1436 "SVGA3D_R8G8B8A8_SNORM",
1437 SVGA3D_R8G8B8A8_SNORM,
1438 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM,
1439 1, 1, 4, 0
1440 },
1441 {
1442 "SVGA3D_R16G16_FLOAT",
1443 SVGA3D_R16G16_FLOAT,
1444 SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT,
1445 1, 1, 4, 0
1446 },
1447 {
1448 "SVGA3D_R16G16_UNORM",
1449 SVGA3D_R16G16_UNORM,
1450 SVGA3D_DEVCAP_DXFMT_R16G16_UNORM,
1451 1, 1, 4, 0
1452 },
1453 {
1454 "SVGA3D_R16G16_SNORM",
1455 SVGA3D_R16G16_SNORM,
1456 SVGA3D_DEVCAP_DXFMT_R16G16_SNORM,
1457 1, 1, 4, 0
1458 },
1459 {
1460 "SVGA3D_R32_FLOAT",
1461 SVGA3D_R32_FLOAT,
1462 SVGA3D_DEVCAP_DXFMT_R32_FLOAT,
1463 1, 1, 4, 0
1464 },
1465 {
1466 "SVGA3D_R8G8_SNORM",
1467 SVGA3D_R8G8_SNORM,
1468 SVGA3D_DEVCAP_DXFMT_R8G8_SNORM,
1469 1, 1, 2, 0
1470 },
1471 {
1472 "SVGA3D_R16_FLOAT",
1473 SVGA3D_R16_FLOAT,
1474 SVGA3D_DEVCAP_DXFMT_R16_FLOAT,
1475 1, 1, 2, 0
1476 },
1477 {
1478 "SVGA3D_D16_UNORM",
1479 SVGA3D_D16_UNORM,
1480 SVGA3D_DEVCAP_DXFMT_D16_UNORM,
1481 1, 1, 2, 0
1482 },
1483 {
1484 "SVGA3D_A8_UNORM",
1485 SVGA3D_A8_UNORM,
1486 SVGA3D_DEVCAP_DXFMT_A8_UNORM,
1487 1, 1, 1, 0
1488 },
1489 {
1490 "SVGA3D_BC1_UNORM",
1491 SVGA3D_BC1_UNORM,
1492 SVGA3D_DEVCAP_DXFMT_BC1_UNORM,
1493 4, 4, 8, 0
1494 },
1495 {
1496 "SVGA3D_BC2_UNORM",
1497 SVGA3D_BC2_UNORM,
1498 SVGA3D_DEVCAP_DXFMT_BC2_UNORM,
1499 4, 4, 16, 0
1500 },
1501 {
1502 "SVGA3D_BC3_UNORM",
1503 SVGA3D_BC3_UNORM,
1504 SVGA3D_DEVCAP_DXFMT_BC3_UNORM,
1505 4, 4, 16, 0
1506 },
1507 {
1508 "SVGA3D_B5G6R5_UNORM",
1509 SVGA3D_B5G6R5_UNORM,
1510 SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM,
1511 1, 1, 2, 0
1512 },
1513 {
1514 "SVGA3D_B5G5R5A1_UNORM",
1515 SVGA3D_B5G5R5A1_UNORM,
1516 SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM,
1517 1, 1, 2, 0
1518 },
1519 {
1520 "SVGA3D_B8G8R8A8_UNORM",
1521 SVGA3D_B8G8R8A8_UNORM,
1522 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM,
1523 1, 1, 4, 0
1524 },
1525 {
1526 "SVGA3D_B8G8R8X8_UNORM",
1527 SVGA3D_B8G8R8X8_UNORM,
1528 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM,
1529 1, 1, 4, 0
1530 },
1531 {
1532 "SVGA3D_BC4_UNORM",
1533 SVGA3D_BC4_UNORM,
1534 SVGA3D_DEVCAP_DXFMT_BC4_UNORM,
1535 4, 4, 8, 0
1536 },
1537 {
1538 "SVGA3D_BC5_UNORM",
1539 SVGA3D_BC5_UNORM,
1540 SVGA3D_DEVCAP_DXFMT_BC5_UNORM,
1541 4, 4, 16, 0
1542 }
1543 };
1544
1545 static const SVGA3dSurfaceFormat compat_x8r8g8b8[] = {
1546 SVGA3D_X8R8G8B8, SVGA3D_A8R8G8B8, SVGA3D_B8G8R8X8_UNORM,
1547 SVGA3D_B8G8R8A8_UNORM, 0
1548 };
1549 static const SVGA3dSurfaceFormat compat_r8[] = {
1550 SVGA3D_R8_UNORM, SVGA3D_NV12, SVGA3D_YV12, 0
1551 };
1552 static const SVGA3dSurfaceFormat compat_g8r8[] = {
1553 SVGA3D_R8G8_UNORM, SVGA3D_NV12, 0
1554 };
1555 static const SVGA3dSurfaceFormat compat_r5g6b5[] = {
1556 SVGA3D_R5G6B5, SVGA3D_B5G6R5_UNORM, 0
1557 };
1558
1559 static const struct format_compat_entry format_compats[] = {
1560 {PIPE_FORMAT_B8G8R8X8_UNORM, compat_x8r8g8b8},
1561 {PIPE_FORMAT_B8G8R8A8_UNORM, compat_x8r8g8b8},
1562 {PIPE_FORMAT_R8_UNORM, compat_r8},
1563 {PIPE_FORMAT_R8G8_UNORM, compat_g8r8},
1564 {PIPE_FORMAT_B5G6R5_UNORM, compat_r5g6b5}
1565 };
1566
1567 /**
1568 * Debug only:
1569 * 1. check that format_cap_table[i] matches the i-th SVGA3D format.
1570 * 2. check that format_conversion_table[i].pformat == i.
1571 */
1572 static void
1573 check_format_tables(void)
1574 {
1575 static boolean first_call = TRUE;
1576
1577 if (first_call) {
1578 unsigned i;
1579
1580 STATIC_ASSERT(ARRAY_SIZE(format_cap_table) == SVGA3D_FORMAT_MAX);
1581 for (i = 0; i < ARRAY_SIZE(format_cap_table); i++) {
1582 assert(format_cap_table[i].format == i);
1583 }
1584
1585 STATIC_ASSERT(ARRAY_SIZE(format_conversion_table) == PIPE_FORMAT_COUNT);
1586 for (i = 0; i < ARRAY_SIZE(format_conversion_table); i++) {
1587 assert(format_conversion_table[i].pformat == i);
1588 }
1589
1590 first_call = FALSE;
1591 }
1592 }
1593
1594
1595 /**
1596 * Return string name of an SVGA3dDevCapIndex value.
1597 * For debugging.
1598 */
1599 static const char *
1600 svga_devcap_name(SVGA3dDevCapIndex cap)
1601 {
1602 static const struct debug_named_value devcap_names[] = {
1603 /* Note, we only list the DXFMT devcaps so far */
1604 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X8R8G8B8),
1605 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A8R8G8B8),
1606 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R5G6B5),
1607 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X1R5G5B5),
1608 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A1R5G5B5),
1609 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A4R4G4B4),
1610 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D32),
1611 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D16),
1612 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D24S8),
1613 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D15S1),
1614 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE8),
1615 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4),
1616 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE16),
1617 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8),
1618 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT1),
1619 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT2),
1620 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT3),
1621 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT4),
1622 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT5),
1623 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUMPU8V8),
1624 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5),
1625 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8),
1626 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1),
1627 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5),
1628 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8),
1629 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A2R10G10B10),
1630 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_V8U8),
1631 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8),
1632 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_CxV8U8),
1633 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X8L8V8U8),
1634 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A2W10V10U10),
1635 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ALPHA8),
1636 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R_S10E5),
1637 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R_S23E8),
1638 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_RG_S10E5),
1639 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_RG_S23E8),
1640 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUFFER),
1641 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D24X8),
1642 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_V16U16),
1643 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_G16R16),
1644 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A16B16G16R16),
1645 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_UYVY),
1646 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_YUY2),
1647 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_NV12),
1648 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_AYUV),
1649 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS),
1650 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT),
1651 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT),
1652 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS),
1653 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT),
1654 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT),
1655 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT),
1656 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS),
1657 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT),
1658 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM),
1659 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT),
1660 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS),
1661 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_UINT),
1662 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_SINT),
1663 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS),
1664 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT),
1665 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24),
1666 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT),
1667 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS),
1668 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT),
1669 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT),
1670 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS),
1671 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM),
1672 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB),
1673 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT),
1674 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT),
1675 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS),
1676 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_UINT),
1677 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_SINT),
1678 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS),
1679 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D32_FLOAT),
1680 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_UINT),
1681 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_SINT),
1682 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS),
1683 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT),
1684 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8),
1685 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X24_G8_UINT),
1686 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS),
1687 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM),
1688 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_UINT),
1689 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_SINT),
1690 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS),
1691 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_UNORM),
1692 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_UINT),
1693 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_SNORM),
1694 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_SINT),
1695 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS),
1696 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_UNORM),
1697 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_UINT),
1698 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_SNORM),
1699 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_SINT),
1700 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_P8),
1701 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP),
1702 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM),
1703 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM),
1704 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS),
1705 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB),
1706 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS),
1707 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB),
1708 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS),
1709 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB),
1710 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS),
1711 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ATI1),
1712 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC4_SNORM),
1713 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS),
1714 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ATI2),
1715 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC5_SNORM),
1716 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM),
1717 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS),
1718 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB),
1719 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS),
1720 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB),
1721 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_DF16),
1722 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_DF24),
1723 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT),
1724 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_YV12),
1725 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT),
1726 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT),
1727 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM),
1728 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT),
1729 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM),
1730 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM),
1731 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT),
1732 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM),
1733 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM),
1734 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_FLOAT),
1735 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM),
1736 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_FLOAT),
1737 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D16_UNORM),
1738 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A8_UNORM),
1739 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC1_UNORM),
1740 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC2_UNORM),
1741 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC3_UNORM),
1742 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM),
1743 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM),
1744 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM),
1745 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM),
1746 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC4_UNORM),
1747 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC5_UNORM),
1748 DEBUG_NAMED_VALUE_END,
1749 };
1750 return debug_dump_enum(devcap_names, cap);
1751 }
1752
1753
1754 /**
1755 * Return string for a bitmask of name of SVGA3D_DXFMT_x flags.
1756 * For debugging.
1757 */
1758 static const char *
1759 svga_devcap_format_flags(unsigned flags)
1760 {
1761 static const struct debug_named_value devcap_flags[] = {
1762 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_SUPPORTED),
1763 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_SHADER_SAMPLE),
1764 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_COLOR_RENDERTARGET),
1765 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_DEPTH_RENDERTARGET),
1766 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_BLENDABLE),
1767 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_MIPS),
1768 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_ARRAY),
1769 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_VOLUME),
1770 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_DX_VERTEX_BUFFER),
1771 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_MULTISAMPLE),
1772 DEBUG_NAMED_VALUE_END
1773 };
1774
1775 return debug_dump_flags(devcap_flags, flags);
1776 }
1777
1778
1779 /*
1780 * Get format capabilities from the host. It takes in consideration
1781 * deprecated/unsupported formats, and formats which are implicitely assumed to
1782 * be supported when the host does not provide an explicit capability entry.
1783 */
1784 void
1785 svga_get_format_cap(struct svga_screen *ss,
1786 SVGA3dSurfaceFormat format,
1787 SVGA3dSurfaceFormatCaps *caps)
1788 {
1789 struct svga_winsys_screen *sws = ss->sws;
1790 SVGA3dDevCapResult result;
1791 const struct format_cap *entry;
1792
1793 #ifdef DEBUG
1794 check_format_tables();
1795 #else
1796 (void) check_format_tables;
1797 #endif
1798
1799 assert(format < ARRAY_SIZE(format_cap_table));
1800 entry = &format_cap_table[format];
1801 assert(entry->format == format);
1802
1803 if (entry->devcap && sws->get_cap(sws, entry->devcap, &result)) {
1804 assert(format < SVGA3D_UYVY || entry->defaultOperations == 0);
1805 caps->value = result.u;
1806 } else {
1807 /* Implicitly advertised format -- use default caps */
1808 caps->value = entry->defaultOperations;
1809 }
1810 }
1811
1812
1813 /*
1814 * Get DX format capabilities from VGPU10 device.
1815 */
1816 static void
1817 svga_get_dx_format_cap(struct svga_screen *ss,
1818 SVGA3dSurfaceFormat format,
1819 SVGA3dDevCapResult *caps)
1820 {
1821 struct svga_winsys_screen *sws = ss->sws;
1822 const struct format_cap *entry;
1823
1824 #ifdef DEBUG
1825 check_format_tables();
1826 #else
1827 (void) check_format_tables;
1828 #endif
1829
1830 assert(sws->have_vgpu10);
1831 assert(format < ARRAY_SIZE(format_cap_table));
1832 entry = &format_cap_table[format];
1833 assert(entry->format == format);
1834 assert(entry->devcap > SVGA3D_DEVCAP_DXCONTEXT);
1835
1836 caps->u = 0;
1837 if (entry->devcap) {
1838 sws->get_cap(sws, entry->devcap, caps);
1839
1840 /* pre-SM41 capabable svga device supports SHADER_SAMPLE capability for
1841 * these formats but does not advertise the devcap.
1842 * So enable this bit here.
1843 */
1844 if (!sws->have_sm4_1 &&
1845 (format == SVGA3D_R32_FLOAT_X8X24 ||
1846 format == SVGA3D_R24_UNORM_X8)) {
1847 caps->u |= SVGA3D_DXFMT_SHADER_SAMPLE;
1848 }
1849 }
1850
1851 if (0) {
1852 debug_printf("Format %s, devcap %s = 0x%x (%s)\n",
1853 svga_format_name(format),
1854 svga_devcap_name(entry->devcap),
1855 caps->u,
1856 svga_devcap_format_flags(caps->u));
1857 }
1858 }
1859
1860
1861 void
1862 svga_format_size(SVGA3dSurfaceFormat format,
1863 unsigned *block_width,
1864 unsigned *block_height,
1865 unsigned *bytes_per_block)
1866 {
1867 assert(format < ARRAY_SIZE(format_cap_table));
1868 *block_width = format_cap_table[format].block_width;
1869 *block_height = format_cap_table[format].block_height;
1870 *bytes_per_block = format_cap_table[format].block_bytes;
1871 /* Make sure the table entry was valid */
1872 if (*block_width == 0)
1873 debug_printf("Bad table entry for %s\n", svga_format_name(format));
1874 assert(*block_width);
1875 assert(*block_height);
1876 assert(*bytes_per_block);
1877 }
1878
1879
1880 const char *
1881 svga_format_name(SVGA3dSurfaceFormat format)
1882 {
1883 assert(format < ARRAY_SIZE(format_cap_table));
1884 return format_cap_table[format].name;
1885 }
1886
1887
1888 /**
1889 * Is the given SVGA3dSurfaceFormat a signed or unsigned integer color format?
1890 */
1891 boolean
1892 svga_format_is_integer(SVGA3dSurfaceFormat format)
1893 {
1894 switch (format) {
1895 case SVGA3D_R32G32B32A32_SINT:
1896 case SVGA3D_R32G32B32_SINT:
1897 case SVGA3D_R32G32_SINT:
1898 case SVGA3D_R32_SINT:
1899 case SVGA3D_R16G16B16A16_SINT:
1900 case SVGA3D_R16G16_SINT:
1901 case SVGA3D_R16_SINT:
1902 case SVGA3D_R8G8B8A8_SINT:
1903 case SVGA3D_R8G8_SINT:
1904 case SVGA3D_R8_SINT:
1905 case SVGA3D_R32G32B32A32_UINT:
1906 case SVGA3D_R32G32B32_UINT:
1907 case SVGA3D_R32G32_UINT:
1908 case SVGA3D_R32_UINT:
1909 case SVGA3D_R16G16B16A16_UINT:
1910 case SVGA3D_R16G16_UINT:
1911 case SVGA3D_R16_UINT:
1912 case SVGA3D_R8G8B8A8_UINT:
1913 case SVGA3D_R8G8_UINT:
1914 case SVGA3D_R8_UINT:
1915 case SVGA3D_R10G10B10A2_UINT:
1916 return TRUE;
1917 default:
1918 return FALSE;
1919 }
1920 }
1921
1922 boolean
1923 svga_format_support_gen_mips(enum pipe_format format)
1924 {
1925 const struct vgpu10_format_entry *entry = svga_format_entry(format);
1926
1927 return (entry->flags & TF_GEN_MIPS) > 0;
1928 }
1929
1930
1931 /**
1932 * Given a texture format, return the expected data type returned from
1933 * the texture sampler. For example, UNORM8 formats return floating point
1934 * values while SINT formats returned signed integer values.
1935 * Note: this function could be moved into the gallum u_format.[ch] code
1936 * if it's useful to anyone else.
1937 */
1938 enum tgsi_return_type
1939 svga_get_texture_datatype(enum pipe_format format)
1940 {
1941 const struct util_format_description *desc = util_format_description(format);
1942 enum tgsi_return_type t;
1943
1944 if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN ) {
1945 if (util_format_is_depth_or_stencil(format)) {
1946 t = TGSI_RETURN_TYPE_FLOAT; /* XXX revisit this */
1947 }
1948 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_FLOAT) {
1949 t = TGSI_RETURN_TYPE_FLOAT;
1950 }
1951 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1952 t = desc->channel[0].normalized ? TGSI_RETURN_TYPE_UNORM : TGSI_RETURN_TYPE_UINT;
1953 }
1954 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
1955 t = desc->channel[0].normalized ? TGSI_RETURN_TYPE_SNORM : TGSI_RETURN_TYPE_SINT;
1956 }
1957 else {
1958 assert(!"Unexpected channel type in svga_get_texture_datatype()");
1959 t = TGSI_RETURN_TYPE_FLOAT;
1960 }
1961 }
1962 else {
1963 /* compressed format, shared exponent format, etc. */
1964 switch (format) {
1965 case PIPE_FORMAT_DXT1_RGB:
1966 case PIPE_FORMAT_DXT1_RGBA:
1967 case PIPE_FORMAT_DXT3_RGBA:
1968 case PIPE_FORMAT_DXT5_RGBA:
1969 case PIPE_FORMAT_DXT1_SRGB:
1970 case PIPE_FORMAT_DXT1_SRGBA:
1971 case PIPE_FORMAT_DXT3_SRGBA:
1972 case PIPE_FORMAT_DXT5_SRGBA:
1973 case PIPE_FORMAT_RGTC1_UNORM:
1974 case PIPE_FORMAT_RGTC2_UNORM:
1975 case PIPE_FORMAT_LATC1_UNORM:
1976 case PIPE_FORMAT_LATC2_UNORM:
1977 case PIPE_FORMAT_ETC1_RGB8:
1978 t = TGSI_RETURN_TYPE_UNORM;
1979 break;
1980 case PIPE_FORMAT_RGTC1_SNORM:
1981 case PIPE_FORMAT_RGTC2_SNORM:
1982 case PIPE_FORMAT_LATC1_SNORM:
1983 case PIPE_FORMAT_LATC2_SNORM:
1984 case PIPE_FORMAT_R10G10B10X2_SNORM:
1985 t = TGSI_RETURN_TYPE_SNORM;
1986 break;
1987 case PIPE_FORMAT_R11G11B10_FLOAT:
1988 case PIPE_FORMAT_R9G9B9E5_FLOAT:
1989 t = TGSI_RETURN_TYPE_FLOAT;
1990 break;
1991 default:
1992 assert(!"Unexpected channel type in svga_get_texture_datatype()");
1993 t = TGSI_RETURN_TYPE_FLOAT;
1994 }
1995 }
1996
1997 return t;
1998 }
1999
2000
2001 /**
2002 * Given an svga context, return true iff there are currently any integer color
2003 * buffers attached to the framebuffer.
2004 */
2005 boolean
2006 svga_has_any_integer_cbufs(const struct svga_context *svga)
2007 {
2008 unsigned i;
2009 for (i = 0; i < PIPE_MAX_COLOR_BUFS; ++i) {
2010 struct pipe_surface *cbuf = svga->curr.framebuffer.cbufs[i];
2011
2012 if (cbuf && util_format_is_pure_integer(cbuf->format)) {
2013 return TRUE;
2014 }
2015 }
2016 return FALSE;
2017 }
2018
2019
2020 /**
2021 * Given an SVGA format, return the corresponding typeless format.
2022 * If there is no typeless format, return the format unchanged.
2023 */
2024 SVGA3dSurfaceFormat
2025 svga_typeless_format(SVGA3dSurfaceFormat format)
2026 {
2027 switch (format) {
2028 case SVGA3D_R32G32B32A32_UINT:
2029 case SVGA3D_R32G32B32A32_SINT:
2030 case SVGA3D_R32G32B32A32_FLOAT:
2031 return SVGA3D_R32G32B32A32_TYPELESS;
2032 case SVGA3D_R32G32B32_FLOAT:
2033 case SVGA3D_R32G32B32_UINT:
2034 case SVGA3D_R32G32B32_SINT:
2035 return SVGA3D_R32G32B32_TYPELESS;
2036 case SVGA3D_R16G16B16A16_UINT:
2037 case SVGA3D_R16G16B16A16_UNORM:
2038 case SVGA3D_R16G16B16A16_SNORM:
2039 case SVGA3D_R16G16B16A16_SINT:
2040 case SVGA3D_R16G16B16A16_FLOAT:
2041 return SVGA3D_R16G16B16A16_TYPELESS;
2042 case SVGA3D_R32G32_UINT:
2043 case SVGA3D_R32G32_SINT:
2044 case SVGA3D_R32G32_FLOAT:
2045 return SVGA3D_R32G32_TYPELESS;
2046 case SVGA3D_D32_FLOAT_S8X24_UINT:
2047 case SVGA3D_X32_G8X24_UINT:
2048 case SVGA3D_R32G8X24_TYPELESS:
2049 return SVGA3D_R32G8X24_TYPELESS;
2050 case SVGA3D_R10G10B10A2_UINT:
2051 case SVGA3D_R10G10B10A2_UNORM:
2052 return SVGA3D_R10G10B10A2_TYPELESS;
2053 case SVGA3D_R8G8B8A8_UNORM:
2054 case SVGA3D_R8G8B8A8_SNORM:
2055 case SVGA3D_R8G8B8A8_UNORM_SRGB:
2056 case SVGA3D_R8G8B8A8_UINT:
2057 case SVGA3D_R8G8B8A8_SINT:
2058 case SVGA3D_R8G8B8A8_TYPELESS:
2059 return SVGA3D_R8G8B8A8_TYPELESS;
2060 case SVGA3D_R16G16_UINT:
2061 case SVGA3D_R16G16_SINT:
2062 case SVGA3D_R16G16_UNORM:
2063 case SVGA3D_R16G16_SNORM:
2064 case SVGA3D_R16G16_FLOAT:
2065 return SVGA3D_R16G16_TYPELESS;
2066 case SVGA3D_D32_FLOAT:
2067 case SVGA3D_R32_FLOAT:
2068 case SVGA3D_R32_UINT:
2069 case SVGA3D_R32_SINT:
2070 case SVGA3D_R32_TYPELESS:
2071 return SVGA3D_R32_TYPELESS;
2072 case SVGA3D_D24_UNORM_S8_UINT:
2073 case SVGA3D_R24G8_TYPELESS:
2074 return SVGA3D_R24G8_TYPELESS;
2075 case SVGA3D_X24_G8_UINT:
2076 return SVGA3D_R24_UNORM_X8;
2077 case SVGA3D_R8G8_UNORM:
2078 case SVGA3D_R8G8_SNORM:
2079 case SVGA3D_R8G8_UINT:
2080 case SVGA3D_R8G8_SINT:
2081 return SVGA3D_R8G8_TYPELESS;
2082 case SVGA3D_D16_UNORM:
2083 case SVGA3D_R16_UNORM:
2084 case SVGA3D_R16_UINT:
2085 case SVGA3D_R16_SNORM:
2086 case SVGA3D_R16_SINT:
2087 case SVGA3D_R16_FLOAT:
2088 case SVGA3D_R16_TYPELESS:
2089 return SVGA3D_R16_TYPELESS;
2090 case SVGA3D_R8_UNORM:
2091 case SVGA3D_R8_UINT:
2092 case SVGA3D_R8_SNORM:
2093 case SVGA3D_R8_SINT:
2094 return SVGA3D_R8_TYPELESS;
2095 case SVGA3D_B8G8R8A8_UNORM_SRGB:
2096 case SVGA3D_B8G8R8A8_UNORM:
2097 case SVGA3D_B8G8R8A8_TYPELESS:
2098 return SVGA3D_B8G8R8A8_TYPELESS;
2099 case SVGA3D_B8G8R8X8_UNORM_SRGB:
2100 case SVGA3D_B8G8R8X8_UNORM:
2101 case SVGA3D_B8G8R8X8_TYPELESS:
2102 return SVGA3D_B8G8R8X8_TYPELESS;
2103 case SVGA3D_BC1_UNORM:
2104 case SVGA3D_BC1_UNORM_SRGB:
2105 case SVGA3D_BC1_TYPELESS:
2106 return SVGA3D_BC1_TYPELESS;
2107 case SVGA3D_BC2_UNORM:
2108 case SVGA3D_BC2_UNORM_SRGB:
2109 case SVGA3D_BC2_TYPELESS:
2110 return SVGA3D_BC2_TYPELESS;
2111 case SVGA3D_BC3_UNORM:
2112 case SVGA3D_BC3_UNORM_SRGB:
2113 case SVGA3D_BC3_TYPELESS:
2114 return SVGA3D_BC3_TYPELESS;
2115 case SVGA3D_BC4_UNORM:
2116 case SVGA3D_BC4_SNORM:
2117 return SVGA3D_BC4_TYPELESS;
2118 case SVGA3D_BC5_UNORM:
2119 case SVGA3D_BC5_SNORM:
2120 return SVGA3D_BC5_TYPELESS;
2121
2122 /* Special cases (no corresponding _TYPELESS formats) */
2123 case SVGA3D_A8_UNORM:
2124 case SVGA3D_B5G5R5A1_UNORM:
2125 case SVGA3D_B5G6R5_UNORM:
2126 case SVGA3D_R11G11B10_FLOAT:
2127 case SVGA3D_R9G9B9E5_SHAREDEXP:
2128 return format;
2129 default:
2130 debug_printf("Unexpected format %s in %s\n",
2131 svga_format_name(format), __FUNCTION__);
2132 return format;
2133 }
2134 }
2135
2136
2137 /**
2138 * Given a surface format, return the corresponding format to use for
2139 * a texture sampler. In most cases, it's the format unchanged, but there
2140 * are some special cases.
2141 */
2142 SVGA3dSurfaceFormat
2143 svga_sampler_format(SVGA3dSurfaceFormat format)
2144 {
2145 switch (format) {
2146 case SVGA3D_D16_UNORM:
2147 return SVGA3D_R16_UNORM;
2148 case SVGA3D_D24_UNORM_S8_UINT:
2149 return SVGA3D_R24_UNORM_X8;
2150 case SVGA3D_D32_FLOAT:
2151 return SVGA3D_R32_FLOAT;
2152 case SVGA3D_D32_FLOAT_S8X24_UINT:
2153 return SVGA3D_R32_FLOAT_X8X24;
2154 default:
2155 return format;
2156 }
2157 }
2158
2159
2160 /**
2161 * Is the given format an uncompressed snorm format?
2162 */
2163 bool
2164 svga_format_is_uncompressed_snorm(SVGA3dSurfaceFormat format)
2165 {
2166 switch (format) {
2167 case SVGA3D_R8G8B8A8_SNORM:
2168 case SVGA3D_R8G8_SNORM:
2169 case SVGA3D_R8_SNORM:
2170 case SVGA3D_R16G16B16A16_SNORM:
2171 case SVGA3D_R16G16_SNORM:
2172 case SVGA3D_R16_SNORM:
2173 return true;
2174 default:
2175 return false;
2176 }
2177 }
2178
2179
2180 bool
2181 svga_format_is_typeless(SVGA3dSurfaceFormat format)
2182 {
2183 switch (format) {
2184 case SVGA3D_R32G32B32A32_TYPELESS:
2185 case SVGA3D_R32G32B32_TYPELESS:
2186 case SVGA3D_R16G16B16A16_TYPELESS:
2187 case SVGA3D_R32G32_TYPELESS:
2188 case SVGA3D_R32G8X24_TYPELESS:
2189 case SVGA3D_R10G10B10A2_TYPELESS:
2190 case SVGA3D_R8G8B8A8_TYPELESS:
2191 case SVGA3D_R16G16_TYPELESS:
2192 case SVGA3D_R32_TYPELESS:
2193 case SVGA3D_R24G8_TYPELESS:
2194 case SVGA3D_R8G8_TYPELESS:
2195 case SVGA3D_R16_TYPELESS:
2196 case SVGA3D_R8_TYPELESS:
2197 case SVGA3D_BC1_TYPELESS:
2198 case SVGA3D_BC2_TYPELESS:
2199 case SVGA3D_BC3_TYPELESS:
2200 case SVGA3D_BC4_TYPELESS:
2201 case SVGA3D_BC5_TYPELESS:
2202 case SVGA3D_B8G8R8A8_TYPELESS:
2203 case SVGA3D_B8G8R8X8_TYPELESS:
2204 return true;
2205 default:
2206 return false;
2207 }
2208 }
2209
2210
2211 /**
2212 * \brief Can we import a surface with a given SVGA3D format as a texture?
2213 *
2214 * \param ss[in] pointer to the svga screen.
2215 * \param pformat[in] pipe format of the local texture.
2216 * \param sformat[in] svga3d format of the imported surface.
2217 * \param bind[in] bind flags of the imported texture.
2218 * \param verbose[in] Print out incompatibilities in debug mode.
2219 */
2220 bool
2221 svga_format_is_shareable(const struct svga_screen *ss,
2222 enum pipe_format pformat,
2223 SVGA3dSurfaceFormat sformat,
2224 unsigned bind,
2225 bool verbose)
2226 {
2227 SVGA3dSurfaceFormat default_format =
2228 svga_translate_format(ss, pformat, bind);
2229 int i;
2230
2231 if (default_format == SVGA3D_FORMAT_INVALID)
2232 return false;
2233 if (default_format == sformat)
2234 return true;
2235
2236 for (i = 0; i < ARRAY_SIZE(format_compats); ++i) {
2237 if (format_compats[i].pformat == pformat) {
2238 const SVGA3dSurfaceFormat *compat_format =
2239 format_compats[i].compat_format;
2240 while (*compat_format != 0) {
2241 if (*compat_format == sformat)
2242 return true;
2243 compat_format++;
2244 }
2245 }
2246 }
2247
2248 if (verbose) {
2249 debug_printf("Incompatible imported surface format.\n");
2250 debug_printf("Texture format: \"%s\". Imported format: \"%s\".\n",
2251 svga_format_name(default_format),
2252 svga_format_name(sformat));
2253 }
2254
2255 return false;
2256 }
2257
2258
2259 /**
2260 * Return the sRGB format which corresponds to the given (linear) format.
2261 * If there's no such sRGB format, return the format as-is.
2262 */
2263 SVGA3dSurfaceFormat
2264 svga_linear_to_srgb(SVGA3dSurfaceFormat format)
2265 {
2266 switch (format) {
2267 case SVGA3D_R8G8B8A8_UNORM:
2268 return SVGA3D_R8G8B8A8_UNORM_SRGB;
2269 case SVGA3D_BC1_UNORM:
2270 return SVGA3D_BC1_UNORM_SRGB;
2271 case SVGA3D_BC2_UNORM:
2272 return SVGA3D_BC2_UNORM_SRGB;
2273 case SVGA3D_BC3_UNORM:
2274 return SVGA3D_BC3_UNORM_SRGB;
2275 case SVGA3D_B8G8R8A8_UNORM:
2276 return SVGA3D_B8G8R8A8_UNORM_SRGB;
2277 case SVGA3D_B8G8R8X8_UNORM:
2278 return SVGA3D_B8G8R8X8_UNORM_SRGB;
2279 default:
2280 return format;
2281 }
2282 }
2283
2284
2285 /**
2286 * Implement pipe_screen::is_format_supported().
2287 * \param bindings bitmask of PIPE_BIND_x flags
2288 */
2289 bool
2290 svga_is_format_supported(struct pipe_screen *screen,
2291 enum pipe_format format,
2292 enum pipe_texture_target target,
2293 unsigned sample_count,
2294 unsigned storage_sample_count,
2295 unsigned bindings)
2296 {
2297 struct svga_screen *ss = svga_screen(screen);
2298 SVGA3dSurfaceFormat svga_format;
2299 SVGA3dSurfaceFormatCaps caps;
2300 SVGA3dSurfaceFormatCaps mask;
2301
2302 assert(bindings);
2303 assert(!ss->sws->have_vgpu10);
2304
2305 /* Multisamples is not supported in VGPU9 device */
2306 if (sample_count > 1)
2307 return false;
2308
2309 svga_format = svga_translate_format(ss, format, bindings);
2310 if (svga_format == SVGA3D_FORMAT_INVALID) {
2311 return false;
2312 }
2313
2314 if (util_format_is_srgb(format) &&
2315 (bindings & PIPE_BIND_DISPLAY_TARGET)) {
2316 /* We only support sRGB rendering with vgpu10 */
2317 return false;
2318 }
2319
2320 /*
2321 * Override host capabilities, so that we end up with the same
2322 * visuals for all virtual hardware implementations.
2323 */
2324 if (bindings & PIPE_BIND_DISPLAY_TARGET) {
2325 switch (svga_format) {
2326 case SVGA3D_A8R8G8B8:
2327 case SVGA3D_X8R8G8B8:
2328 case SVGA3D_R5G6B5:
2329 break;
2330
2331 /* VGPU10 formats */
2332 case SVGA3D_B8G8R8A8_UNORM:
2333 case SVGA3D_B8G8R8X8_UNORM:
2334 case SVGA3D_B5G6R5_UNORM:
2335 case SVGA3D_B8G8R8X8_UNORM_SRGB:
2336 case SVGA3D_B8G8R8A8_UNORM_SRGB:
2337 case SVGA3D_R8G8B8A8_UNORM_SRGB:
2338 break;
2339
2340 /* Often unsupported/problematic. This means we end up with the same
2341 * visuals for all virtual hardware implementations.
2342 */
2343 case SVGA3D_A4R4G4B4:
2344 case SVGA3D_A1R5G5B5:
2345 return false;
2346
2347 default:
2348 return false;
2349 }
2350 }
2351
2352 /*
2353 * Query the host capabilities.
2354 */
2355 svga_get_format_cap(ss, svga_format, &caps);
2356
2357 if (bindings & PIPE_BIND_RENDER_TARGET) {
2358 /* Check that the color surface is blendable, unless it's an
2359 * integer format.
2360 */
2361 if (!svga_format_is_integer(svga_format) &&
2362 (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
2363 return false;
2364 }
2365 }
2366
2367 mask.value = 0;
2368 if (bindings & PIPE_BIND_RENDER_TARGET)
2369 mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
2370
2371 if (bindings & PIPE_BIND_DEPTH_STENCIL)
2372 mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
2373
2374 if (bindings & PIPE_BIND_SAMPLER_VIEW)
2375 mask.value |= SVGA3DFORMAT_OP_TEXTURE;
2376
2377 if (target == PIPE_TEXTURE_CUBE)
2378 mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
2379 else if (target == PIPE_TEXTURE_3D)
2380 mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
2381
2382 return (caps.value & mask.value) == mask.value;
2383 }
2384
2385
2386 /**
2387 * Implement pipe_screen::is_format_supported() for VGPU10 device.
2388 * \param bindings bitmask of PIPE_BIND_x flags
2389 */
2390 bool
2391 svga_is_dx_format_supported(struct pipe_screen *screen,
2392 enum pipe_format format,
2393 enum pipe_texture_target target,
2394 unsigned sample_count,
2395 unsigned storage_sample_count,
2396 unsigned bindings)
2397 {
2398 struct svga_screen *ss = svga_screen(screen);
2399 SVGA3dSurfaceFormat svga_format;
2400 SVGA3dDevCapResult caps;
2401 unsigned int mask = 0;
2402
2403 assert(bindings);
2404 assert(ss->sws->have_vgpu10);
2405
2406 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
2407 return false;
2408
2409 if (sample_count > 1) {
2410 /* In ms_samples, if bit N is set it means that we support
2411 * multisample with N+1 samples per pixel.
2412 */
2413 if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
2414 return false;
2415 }
2416 mask |= SVGA3D_DXFMT_MULTISAMPLE;
2417 }
2418
2419 /*
2420 * For VGPU10 vertex formats, skip querying host capabilities
2421 */
2422
2423 if (bindings & PIPE_BIND_VERTEX_BUFFER) {
2424 SVGA3dSurfaceFormat svga_format;
2425 unsigned flags;
2426 svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
2427 return svga_format != SVGA3D_FORMAT_INVALID;
2428 }
2429
2430 svga_format = svga_translate_format(ss, format, bindings);
2431 if (svga_format == SVGA3D_FORMAT_INVALID) {
2432 return false;
2433 }
2434
2435 /*
2436 * Override host capabilities, so that we end up with the same
2437 * visuals for all virtual hardware implementations.
2438 */
2439 if (bindings & PIPE_BIND_DISPLAY_TARGET) {
2440 switch (svga_format) {
2441 case SVGA3D_A8R8G8B8:
2442 case SVGA3D_X8R8G8B8:
2443 case SVGA3D_R5G6B5:
2444 break;
2445
2446 /* VGPU10 formats */
2447 case SVGA3D_B8G8R8A8_UNORM:
2448 case SVGA3D_B8G8R8X8_UNORM:
2449 case SVGA3D_B5G6R5_UNORM:
2450 case SVGA3D_B8G8R8X8_UNORM_SRGB:
2451 case SVGA3D_B8G8R8A8_UNORM_SRGB:
2452 case SVGA3D_R8G8B8A8_UNORM_SRGB:
2453 break;
2454
2455 /* Often unsupported/problematic. This means we end up with the same
2456 * visuals for all virtual hardware implementations.
2457 */
2458 case SVGA3D_A4R4G4B4:
2459 case SVGA3D_A1R5G5B5:
2460 return false;
2461
2462 default:
2463 return false;
2464 }
2465 }
2466
2467 /*
2468 * Query the host capabilities.
2469 */
2470 svga_get_dx_format_cap(ss, svga_format, &caps);
2471
2472 if (bindings & PIPE_BIND_RENDER_TARGET) {
2473 /* Check that the color surface is blendable, unless it's an
2474 * integer format.
2475 */
2476 if (!(svga_format_is_integer(svga_format) ||
2477 (caps.u & SVGA3D_DXFMT_BLENDABLE))) {
2478 return false;
2479 }
2480 mask |= SVGA3D_DXFMT_COLOR_RENDERTARGET;
2481 }
2482
2483 if (bindings & PIPE_BIND_DEPTH_STENCIL)
2484 mask |= SVGA3D_DXFMT_DEPTH_RENDERTARGET;
2485
2486 switch (target) {
2487 case PIPE_TEXTURE_3D:
2488 mask |= SVGA3D_DXFMT_VOLUME;
2489 break;
2490 case PIPE_TEXTURE_1D_ARRAY:
2491 case PIPE_TEXTURE_2D_ARRAY:
2492 case PIPE_TEXTURE_CUBE_ARRAY:
2493 mask |= SVGA3D_DXFMT_ARRAY;
2494 break;
2495 default:
2496 break;
2497 }
2498
2499 /* Is the format supported for rendering */
2500 if ((caps.u & mask) != mask)
2501 return false;
2502
2503 if (bindings & PIPE_BIND_SAMPLER_VIEW) {
2504 SVGA3dSurfaceFormat sampler_format;
2505
2506 /* Get the sampler view format */
2507 sampler_format = svga_sampler_format(svga_format);
2508 if (sampler_format != svga_format) {
2509 caps.u = 0;
2510 svga_get_dx_format_cap(ss, sampler_format, &caps);
2511 mask &= SVGA3D_DXFMT_VOLUME;
2512 mask |= SVGA3D_DXFMT_SHADER_SAMPLE;
2513 if ((caps.u & mask) != mask)
2514 return false;
2515 }
2516 }
2517
2518 return true;
2519 }