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svga: explicit set DXFMT_SHADER_SAMPLE for DS format for pre-SM41 device
[mesa.git] / src / gallium / drivers / svga / svga_format.c
1 /**********************************************************
2 * Copyright 2011 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26
27 #include "pipe/p_format.h"
28 #include "util/u_debug.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31
32 #include "svga_winsys.h"
33 #include "svga_screen.h"
34 #include "svga_format.h"
35
36
37 /** Describes mapping from gallium formats to SVGA vertex/pixel formats */
38 struct vgpu10_format_entry
39 {
40 enum pipe_format pformat;
41 SVGA3dSurfaceFormat vertex_format;
42 SVGA3dSurfaceFormat pixel_format;
43 unsigned flags;
44 };
45
46 struct format_compat_entry
47 {
48 enum pipe_format pformat;
49 const SVGA3dSurfaceFormat *compat_format;
50 };
51
52
53 /**
54 * Table mapping Gallium formats to SVGA3d vertex/pixel formats.
55 * Note: the table is ordered according to PIPE_FORMAT_x order.
56 */
57 static const struct vgpu10_format_entry format_conversion_table[] =
58 {
59 /* Gallium format SVGA3D vertex format SVGA3D pixel format Flags */
60 { PIPE_FORMAT_NONE, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
61 { PIPE_FORMAT_B8G8R8A8_UNORM, SVGA3D_B8G8R8A8_UNORM, SVGA3D_B8G8R8A8_UNORM, TF_GEN_MIPS },
62 { PIPE_FORMAT_B8G8R8X8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8X8_UNORM, TF_GEN_MIPS },
63 { PIPE_FORMAT_A8R8G8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
64 { PIPE_FORMAT_X8R8G8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
65 { PIPE_FORMAT_B5G5R5A1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_B5G5R5A1_UNORM, TF_GEN_MIPS },
66 { PIPE_FORMAT_B4G4R4A4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
67 { PIPE_FORMAT_B5G6R5_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_B5G6R5_UNORM, TF_GEN_MIPS },
68 { PIPE_FORMAT_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, TF_GEN_MIPS },
69 { PIPE_FORMAT_L8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
70 { PIPE_FORMAT_A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_A8_UNORM, TF_GEN_MIPS },
71 { PIPE_FORMAT_I8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
72 { PIPE_FORMAT_L8A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
73 { PIPE_FORMAT_L16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
74 { PIPE_FORMAT_UYVY, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
75 { PIPE_FORMAT_YUYV, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
76 { PIPE_FORMAT_Z16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_D16_UNORM, 0 },
77 { PIPE_FORMAT_Z32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
78 { PIPE_FORMAT_Z32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_D32_FLOAT, 0 },
79 { PIPE_FORMAT_Z24_UNORM_S8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_D24_UNORM_S8_UINT, 0 },
80 { PIPE_FORMAT_S8_UINT_Z24_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
81 { PIPE_FORMAT_Z24X8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_D24_UNORM_S8_UINT, 0 },
82 { PIPE_FORMAT_X8Z24_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
83 { PIPE_FORMAT_S8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
84 { PIPE_FORMAT_R64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
85 { PIPE_FORMAT_R64G64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
86 { PIPE_FORMAT_R64G64B64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
87 { PIPE_FORMAT_R64G64B64A64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
88 { PIPE_FORMAT_R32_FLOAT, SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, TF_GEN_MIPS },
89 { PIPE_FORMAT_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, TF_GEN_MIPS },
90 { PIPE_FORMAT_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, TF_GEN_MIPS },
91 { PIPE_FORMAT_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, TF_GEN_MIPS },
92 { PIPE_FORMAT_R32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
93 { PIPE_FORMAT_R32G32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
94 { PIPE_FORMAT_R32G32B32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
95 { PIPE_FORMAT_R32G32B32A32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
96 { PIPE_FORMAT_R32_USCALED, SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
97 { PIPE_FORMAT_R32G32_USCALED, SVGA3D_R32G32_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
98 { PIPE_FORMAT_R32G32B32_USCALED, SVGA3D_R32G32B32_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
99 { PIPE_FORMAT_R32G32B32A32_USCALED, SVGA3D_R32G32B32A32_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
100 { PIPE_FORMAT_R32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
101 { PIPE_FORMAT_R32G32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
102 { PIPE_FORMAT_R32G32B32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
103 { PIPE_FORMAT_R32G32B32A32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
104 { PIPE_FORMAT_R32_SSCALED, SVGA3D_R32_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
105 { PIPE_FORMAT_R32G32_SSCALED, SVGA3D_R32G32_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
106 { PIPE_FORMAT_R32G32B32_SSCALED, SVGA3D_R32G32B32_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
107 { PIPE_FORMAT_R32G32B32A32_SSCALED, SVGA3D_R32G32B32A32_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
108 { PIPE_FORMAT_R16_UNORM, SVGA3D_R16_UNORM, SVGA3D_R16_UNORM, TF_GEN_MIPS },
109 { PIPE_FORMAT_R16G16_UNORM, SVGA3D_R16G16_UNORM, SVGA3D_R16G16_UNORM, TF_GEN_MIPS },
110 { PIPE_FORMAT_R16G16B16_UNORM, SVGA3D_R16G16B16A16_UNORM, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
111 { PIPE_FORMAT_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, TF_GEN_MIPS },
112 { PIPE_FORMAT_R16_USCALED, SVGA3D_R16_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
113 { PIPE_FORMAT_R16G16_USCALED, SVGA3D_R16G16_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
114 { PIPE_FORMAT_R16G16B16_USCALED, SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_U_TO_F_CAST },
115 { PIPE_FORMAT_R16G16B16A16_USCALED, SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
116 { PIPE_FORMAT_R16_SNORM, SVGA3D_R16_SNORM, SVGA3D_R16_SNORM, 0 },
117 { PIPE_FORMAT_R16G16_SNORM, SVGA3D_R16G16_SNORM, SVGA3D_R16G16_SNORM, 0 },
118 { PIPE_FORMAT_R16G16B16_SNORM, SVGA3D_R16G16B16A16_SNORM, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
119 { PIPE_FORMAT_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, 0 },
120 { PIPE_FORMAT_R16_SSCALED, SVGA3D_R16_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
121 { PIPE_FORMAT_R16G16_SSCALED, SVGA3D_R16G16_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
122 { PIPE_FORMAT_R16G16B16_SSCALED, SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_I_TO_F_CAST },
123 { PIPE_FORMAT_R16G16B16A16_SSCALED, SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
124 { PIPE_FORMAT_R8_UNORM, SVGA3D_R8_UNORM, SVGA3D_R8_UNORM, TF_GEN_MIPS },
125 { PIPE_FORMAT_R8G8_UNORM, SVGA3D_R8G8_UNORM, SVGA3D_R8G8_UNORM, TF_GEN_MIPS },
126 { PIPE_FORMAT_R8G8B8_UNORM, SVGA3D_R8G8B8A8_UNORM, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
127 { PIPE_FORMAT_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, TF_GEN_MIPS },
128 { PIPE_FORMAT_X8B8G8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
129 { PIPE_FORMAT_R8_USCALED, SVGA3D_R8_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
130 { PIPE_FORMAT_R8G8_USCALED, SVGA3D_R8G8_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
131 { PIPE_FORMAT_R8G8B8_USCALED, SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_U_TO_F_CAST },
132 { PIPE_FORMAT_R8G8B8A8_USCALED, SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
133 { 73, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
134 { PIPE_FORMAT_R8_SNORM, SVGA3D_R8_SNORM, SVGA3D_R8_SNORM, 0 },
135 { PIPE_FORMAT_R8G8_SNORM, SVGA3D_R8G8_SNORM, SVGA3D_R8G8_SNORM, 0 },
136 { PIPE_FORMAT_R8G8B8_SNORM, SVGA3D_R8G8B8A8_SNORM, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
137 { PIPE_FORMAT_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, 0 },
138 { 78, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
139 { 79, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
140 { 80, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
141 { 81, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
142 { PIPE_FORMAT_R8_SSCALED, SVGA3D_R8_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
143 { PIPE_FORMAT_R8G8_SSCALED, SVGA3D_R8G8_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
144 { PIPE_FORMAT_R8G8B8_SSCALED, SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_I_TO_F_CAST },
145 { PIPE_FORMAT_R8G8B8A8_SSCALED, SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
146 { 86, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
147 { PIPE_FORMAT_R32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
148 { PIPE_FORMAT_R32G32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
149 { PIPE_FORMAT_R32G32B32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
150 { PIPE_FORMAT_R32G32B32A32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
151 { PIPE_FORMAT_R16_FLOAT, SVGA3D_R16_FLOAT, SVGA3D_R16_FLOAT, TF_GEN_MIPS },
152 { PIPE_FORMAT_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, TF_GEN_MIPS },
153 { PIPE_FORMAT_R16G16B16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
154 { PIPE_FORMAT_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, TF_GEN_MIPS },
155 { PIPE_FORMAT_L8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
156 { PIPE_FORMAT_L8A8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
157 { PIPE_FORMAT_R8G8B8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
158 { PIPE_FORMAT_A8B8G8R8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
159 { PIPE_FORMAT_X8B8G8R8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
160 { PIPE_FORMAT_B8G8R8A8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8A8_UNORM_SRGB, TF_GEN_MIPS },
161 { PIPE_FORMAT_B8G8R8X8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8X8_UNORM_SRGB, TF_GEN_MIPS },
162 { PIPE_FORMAT_A8R8G8B8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
163 { PIPE_FORMAT_X8R8G8B8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
164 { PIPE_FORMAT_R8G8B8A8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_R8G8B8A8_UNORM_SRGB, TF_GEN_MIPS },
165 { PIPE_FORMAT_DXT1_RGB, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM, 0 },
166 { PIPE_FORMAT_DXT1_RGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM, 0 },
167 { PIPE_FORMAT_DXT3_RGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC2_UNORM, 0 },
168 { PIPE_FORMAT_DXT5_RGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC3_UNORM, 0 },
169 { PIPE_FORMAT_DXT1_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM_SRGB, 0 },
170 { PIPE_FORMAT_DXT1_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM_SRGB, 0 },
171 { PIPE_FORMAT_DXT3_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC2_UNORM_SRGB, 0 },
172 { PIPE_FORMAT_DXT5_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC3_UNORM_SRGB, 0 },
173 { PIPE_FORMAT_RGTC1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC4_UNORM, 0 },
174 { PIPE_FORMAT_RGTC1_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC4_SNORM, 0 },
175 { PIPE_FORMAT_RGTC2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC5_UNORM, 0 },
176 { PIPE_FORMAT_RGTC2_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC5_SNORM, 0 },
177 { PIPE_FORMAT_R8G8_B8G8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
178 { PIPE_FORMAT_G8R8_G8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
179 { PIPE_FORMAT_R8SG8SB8UX8U_NORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
180 { PIPE_FORMAT_R5SG5SB6U_NORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
181 { PIPE_FORMAT_A8B8G8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
182 { PIPE_FORMAT_B5G5R5X1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
183 { PIPE_FORMAT_R10G10B10A2_USCALED, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_USCALED },
184 { PIPE_FORMAT_R11G11B10_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_R11G11B10_FLOAT, TF_GEN_MIPS },
185 { PIPE_FORMAT_R9G9B9E5_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_R9G9B9E5_SHAREDEXP, 0 },
186 { PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_D32_FLOAT_S8X24_UINT, 0 },
187 { PIPE_FORMAT_R1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
188 { PIPE_FORMAT_R10G10B10X2_USCALED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
189 { PIPE_FORMAT_R10G10B10X2_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
190 { PIPE_FORMAT_L4A4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
191 { PIPE_FORMAT_B10G10R10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, VF_BGRA },
192 { PIPE_FORMAT_R10SG10SB10SA2U_NORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
193 { PIPE_FORMAT_R8G8Bx_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
194 { PIPE_FORMAT_R8G8B8X8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
195 { PIPE_FORMAT_B4G4R4X4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
196 { PIPE_FORMAT_X24S8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
197 { PIPE_FORMAT_S8X24_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
198 { PIPE_FORMAT_X32_S8X24_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
199 { PIPE_FORMAT_B2G3R3_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
200 { PIPE_FORMAT_L16A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
201 { PIPE_FORMAT_A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
202 { PIPE_FORMAT_I16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
203 { PIPE_FORMAT_LATC1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
204 { PIPE_FORMAT_LATC1_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
205 { PIPE_FORMAT_LATC2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
206 { PIPE_FORMAT_LATC2_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
207 { PIPE_FORMAT_A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
208 { PIPE_FORMAT_L8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
209 { PIPE_FORMAT_L8A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
210 { PIPE_FORMAT_I8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
211 { PIPE_FORMAT_A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
212 { PIPE_FORMAT_L16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
213 { PIPE_FORMAT_L16A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
214 { PIPE_FORMAT_I16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
215 { PIPE_FORMAT_A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
216 { PIPE_FORMAT_L16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
217 { PIPE_FORMAT_L16A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
218 { PIPE_FORMAT_I16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
219 { PIPE_FORMAT_A32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
220 { PIPE_FORMAT_L32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
221 { PIPE_FORMAT_L32A32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
222 { PIPE_FORMAT_I32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
223 { PIPE_FORMAT_YV12, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
224 { PIPE_FORMAT_YV16, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
225 { PIPE_FORMAT_IYUV, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
226 { PIPE_FORMAT_NV12, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
227 { PIPE_FORMAT_NV21, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
228 { PIPE_FORMAT_A4R4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
229 { PIPE_FORMAT_R4A4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
230 { PIPE_FORMAT_R8A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
231 { PIPE_FORMAT_A8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
232 { PIPE_FORMAT_R10G10B10A2_SSCALED, SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_SSCALED },
233 { PIPE_FORMAT_R10G10B10A2_SNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_SNORM },
234 { PIPE_FORMAT_B10G10R10A2_USCALED, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_USCALED },
235 { PIPE_FORMAT_B10G10R10A2_SSCALED, SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_SSCALED },
236 { PIPE_FORMAT_B10G10R10A2_SNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_SNORM },
237 { PIPE_FORMAT_R8_UINT, SVGA3D_R8_UINT, SVGA3D_R8_UINT, 0 },
238 { PIPE_FORMAT_R8G8_UINT, SVGA3D_R8G8_UINT, SVGA3D_R8G8_UINT, 0 },
239 { PIPE_FORMAT_R8G8B8_UINT, SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
240 { PIPE_FORMAT_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, 0 },
241 { PIPE_FORMAT_R8_SINT, SVGA3D_R8_SINT, SVGA3D_R8_SINT, 0 },
242 { PIPE_FORMAT_R8G8_SINT, SVGA3D_R8G8_SINT, SVGA3D_R8G8_SINT, 0 },
243 { PIPE_FORMAT_R8G8B8_SINT, SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
244 { PIPE_FORMAT_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, 0 },
245 { PIPE_FORMAT_R16_UINT, SVGA3D_R16_UINT, SVGA3D_R16_UINT, 0 },
246 { PIPE_FORMAT_R16G16_UINT, SVGA3D_R16G16_UINT, SVGA3D_R16G16_UINT, 0 },
247 { PIPE_FORMAT_R16G16B16_UINT, SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
248 { PIPE_FORMAT_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, 0 },
249 { PIPE_FORMAT_R16_SINT, SVGA3D_R16_SINT, SVGA3D_R16_SINT, 0 },
250 { PIPE_FORMAT_R16G16_SINT, SVGA3D_R16G16_SINT, SVGA3D_R16G16_SINT, 0 },
251 { PIPE_FORMAT_R16G16B16_SINT, SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
252 { PIPE_FORMAT_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, 0 },
253 { PIPE_FORMAT_R32_UINT, SVGA3D_R32_UINT, SVGA3D_R32_UINT, 0 },
254 { PIPE_FORMAT_R32G32_UINT, SVGA3D_R32G32_UINT, SVGA3D_R32G32_UINT, 0 },
255 { PIPE_FORMAT_R32G32B32_UINT, SVGA3D_R32G32B32_UINT, SVGA3D_FORMAT_INVALID, 0 },
256 { PIPE_FORMAT_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, 0 },
257 { PIPE_FORMAT_R32_SINT, SVGA3D_R32_SINT, SVGA3D_R32_SINT, 0 },
258 { PIPE_FORMAT_R32G32_SINT, SVGA3D_R32G32_SINT, SVGA3D_R32G32_SINT, 0 },
259 { PIPE_FORMAT_R32G32B32_SINT, SVGA3D_R32G32B32_SINT, SVGA3D_FORMAT_INVALID, 0 },
260 { PIPE_FORMAT_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, 0 },
261 { PIPE_FORMAT_A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
262 { PIPE_FORMAT_I8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
263 { PIPE_FORMAT_L8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
264 { PIPE_FORMAT_L8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
265 { PIPE_FORMAT_A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
266 { PIPE_FORMAT_I8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
267 { PIPE_FORMAT_L8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
268 { PIPE_FORMAT_L8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
269 { PIPE_FORMAT_A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
270 { PIPE_FORMAT_I16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
271 { PIPE_FORMAT_L16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
272 { PIPE_FORMAT_L16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
273 { PIPE_FORMAT_A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
274 { PIPE_FORMAT_I16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
275 { PIPE_FORMAT_L16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
276 { PIPE_FORMAT_L16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
277 { PIPE_FORMAT_A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
278 { PIPE_FORMAT_I32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
279 { PIPE_FORMAT_L32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
280 { PIPE_FORMAT_L32A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
281 { PIPE_FORMAT_A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
282 { PIPE_FORMAT_I32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
283 { PIPE_FORMAT_L32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
284 { PIPE_FORMAT_L32A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
285 { PIPE_FORMAT_B10G10R10A2_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
286 { PIPE_FORMAT_ETC1_RGB8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
287 { PIPE_FORMAT_R8G8_R8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
288 { PIPE_FORMAT_G8R8_B8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
289 { PIPE_FORMAT_R8G8B8X8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
290 { PIPE_FORMAT_R8G8B8X8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
291 { PIPE_FORMAT_R8G8B8X8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
292 { PIPE_FORMAT_R8G8B8X8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
293 { PIPE_FORMAT_B10G10R10X2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
294 { PIPE_FORMAT_R16G16B16X16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
295 { PIPE_FORMAT_R16G16B16X16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
296 { PIPE_FORMAT_R16G16B16X16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
297 { PIPE_FORMAT_R16G16B16X16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
298 { PIPE_FORMAT_R16G16B16X16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
299 { PIPE_FORMAT_R32G32B32X32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
300 { PIPE_FORMAT_R32G32B32X32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
301 { PIPE_FORMAT_R32G32B32X32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
302 { PIPE_FORMAT_R8A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
303 { PIPE_FORMAT_R16A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
304 { PIPE_FORMAT_R16A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
305 { PIPE_FORMAT_R16A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
306 { PIPE_FORMAT_R32A32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
307 { PIPE_FORMAT_R8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
308 { PIPE_FORMAT_R8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
309 { PIPE_FORMAT_R16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
310 { PIPE_FORMAT_R16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
311 { PIPE_FORMAT_R32A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
312 { PIPE_FORMAT_R32A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
313 { PIPE_FORMAT_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, 0 },
314 { PIPE_FORMAT_B5G6R5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
315 { PIPE_FORMAT_BPTC_RGBA_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
316 { PIPE_FORMAT_BPTC_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
317 { PIPE_FORMAT_BPTC_RGB_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
318 { PIPE_FORMAT_BPTC_RGB_UFLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
319 { PIPE_FORMAT_A8L8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
320 { PIPE_FORMAT_A8L8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
321 { PIPE_FORMAT_A8L8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
322 { PIPE_FORMAT_A16L16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
323 { PIPE_FORMAT_G8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
324 { PIPE_FORMAT_G8R8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
325 { PIPE_FORMAT_G16R16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
326 { PIPE_FORMAT_G16R16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
327 { PIPE_FORMAT_A8B8G8R8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
328 { PIPE_FORMAT_X8B8G8R8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
329 { PIPE_FORMAT_ETC2_RGB8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
330 { PIPE_FORMAT_ETC2_SRGB8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
331 { PIPE_FORMAT_ETC2_RGB8A1, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
332 { PIPE_FORMAT_ETC2_SRGB8A1, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
333 { PIPE_FORMAT_ETC2_RGBA8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
334 { PIPE_FORMAT_ETC2_SRGBA8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
335 { PIPE_FORMAT_ETC2_R11_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
336 { PIPE_FORMAT_ETC2_R11_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
337 { PIPE_FORMAT_ETC2_RG11_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
338 { PIPE_FORMAT_ETC2_RG11_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
339 { PIPE_FORMAT_ASTC_4x4, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
340 { PIPE_FORMAT_ASTC_5x4, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
341 { PIPE_FORMAT_ASTC_5x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
342 { PIPE_FORMAT_ASTC_6x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
343 { PIPE_FORMAT_ASTC_6x6, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
344 { PIPE_FORMAT_ASTC_8x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
345 { PIPE_FORMAT_ASTC_8x6, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
346 { PIPE_FORMAT_ASTC_8x8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
347 { PIPE_FORMAT_ASTC_10x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
348 { PIPE_FORMAT_ASTC_10x6, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
349 { PIPE_FORMAT_ASTC_10x8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
350 { PIPE_FORMAT_ASTC_10x10, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
351 { PIPE_FORMAT_ASTC_12x10, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
352 { PIPE_FORMAT_ASTC_12x12, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
353 { PIPE_FORMAT_ASTC_4x4_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
354 { PIPE_FORMAT_ASTC_5x4_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
355 { PIPE_FORMAT_ASTC_5x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
356 { PIPE_FORMAT_ASTC_6x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
357 { PIPE_FORMAT_ASTC_6x6_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
358 { PIPE_FORMAT_ASTC_8x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
359 { PIPE_FORMAT_ASTC_8x6_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
360 { PIPE_FORMAT_ASTC_8x8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
361 { PIPE_FORMAT_ASTC_10x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
362 { PIPE_FORMAT_ASTC_10x6_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
363 { PIPE_FORMAT_ASTC_10x8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
364 { PIPE_FORMAT_ASTC_10x10_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
365 { PIPE_FORMAT_ASTC_12x10_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
366 { PIPE_FORMAT_ASTC_12x12_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
367 { PIPE_FORMAT_P016, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
368 { PIPE_FORMAT_R10G10B10X2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
369 { PIPE_FORMAT_A1B5G5R5_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
370 { PIPE_FORMAT_X1B5G5R5_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
371 { PIPE_FORMAT_A4B4G4R4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
372 };
373
374
375 /**
376 * Translate a gallium vertex format to a vgpu10 vertex format.
377 * Also, return any special vertex format flags.
378 */
379 void
380 svga_translate_vertex_format_vgpu10(enum pipe_format format,
381 SVGA3dSurfaceFormat *svga_format,
382 unsigned *vf_flags)
383 {
384 assert(format < ARRAY_SIZE(format_conversion_table));
385 if (format >= ARRAY_SIZE(format_conversion_table)) {
386 format = PIPE_FORMAT_NONE;
387 }
388 *svga_format = format_conversion_table[format].vertex_format;
389 *vf_flags = format_conversion_table[format].flags;
390 }
391
392
393 /**
394 * Translate a gallium scanout format to a svga format valid
395 * for screen target surface.
396 */
397 static SVGA3dSurfaceFormat
398 svga_translate_screen_target_format_vgpu10(enum pipe_format format)
399 {
400 switch (format) {
401 case PIPE_FORMAT_B8G8R8A8_UNORM:
402 return SVGA3D_B8G8R8A8_UNORM;
403 case PIPE_FORMAT_B8G8R8X8_UNORM:
404 return SVGA3D_B8G8R8X8_UNORM;
405 case PIPE_FORMAT_B5G6R5_UNORM:
406 return SVGA3D_R5G6B5;
407 case PIPE_FORMAT_B5G5R5A1_UNORM:
408 return SVGA3D_A1R5G5B5;
409 default:
410 debug_printf("Invalid format %s specified for screen target\n",
411 svga_format_name(format));
412 return SVGA3D_FORMAT_INVALID;
413 }
414 }
415
416 /*
417 * Translate from gallium format to SVGA3D format.
418 */
419 SVGA3dSurfaceFormat
420 svga_translate_format(const struct svga_screen *ss,
421 enum pipe_format format,
422 unsigned bind)
423 {
424 if (ss->sws->have_vgpu10) {
425 if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) {
426 return format_conversion_table[format].vertex_format;
427 }
428 else if (bind & PIPE_BIND_SCANOUT) {
429 return svga_translate_screen_target_format_vgpu10(format);
430 }
431 else {
432 return format_conversion_table[format].pixel_format;
433 }
434 }
435
436 switch(format) {
437 case PIPE_FORMAT_B8G8R8A8_UNORM:
438 return SVGA3D_A8R8G8B8;
439 case PIPE_FORMAT_B8G8R8X8_UNORM:
440 return SVGA3D_X8R8G8B8;
441
442 /* sRGB required for GL2.1 */
443 case PIPE_FORMAT_B8G8R8A8_SRGB:
444 return SVGA3D_A8R8G8B8;
445 case PIPE_FORMAT_DXT1_SRGB:
446 case PIPE_FORMAT_DXT1_SRGBA:
447 return SVGA3D_DXT1;
448 case PIPE_FORMAT_DXT3_SRGBA:
449 return SVGA3D_DXT3;
450 case PIPE_FORMAT_DXT5_SRGBA:
451 return SVGA3D_DXT5;
452
453 case PIPE_FORMAT_B5G6R5_UNORM:
454 return SVGA3D_R5G6B5;
455 case PIPE_FORMAT_B5G5R5A1_UNORM:
456 return SVGA3D_A1R5G5B5;
457 case PIPE_FORMAT_B4G4R4A4_UNORM:
458 return SVGA3D_A4R4G4B4;
459
460 case PIPE_FORMAT_R16G16B16A16_UNORM:
461 return SVGA3D_A16B16G16R16;
462
463 case PIPE_FORMAT_Z16_UNORM:
464 assert(!ss->sws->have_vgpu10);
465 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.z16 : SVGA3D_Z_D16;
466 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
467 assert(!ss->sws->have_vgpu10);
468 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.s8z24 : SVGA3D_Z_D24S8;
469 case PIPE_FORMAT_X8Z24_UNORM:
470 assert(!ss->sws->have_vgpu10);
471 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.x8z24 : SVGA3D_Z_D24X8;
472
473 case PIPE_FORMAT_A8_UNORM:
474 return SVGA3D_ALPHA8;
475 case PIPE_FORMAT_L8_UNORM:
476 return SVGA3D_LUMINANCE8;
477
478 case PIPE_FORMAT_DXT1_RGB:
479 case PIPE_FORMAT_DXT1_RGBA:
480 return SVGA3D_DXT1;
481 case PIPE_FORMAT_DXT3_RGBA:
482 return SVGA3D_DXT3;
483 case PIPE_FORMAT_DXT5_RGBA:
484 return SVGA3D_DXT5;
485
486 /* Float formats (only 1, 2 and 4-component formats supported) */
487 case PIPE_FORMAT_R32_FLOAT:
488 return SVGA3D_R_S23E8;
489 case PIPE_FORMAT_R32G32_FLOAT:
490 return SVGA3D_RG_S23E8;
491 case PIPE_FORMAT_R32G32B32A32_FLOAT:
492 return SVGA3D_ARGB_S23E8;
493 case PIPE_FORMAT_R16_FLOAT:
494 return SVGA3D_R_S10E5;
495 case PIPE_FORMAT_R16G16_FLOAT:
496 return SVGA3D_RG_S10E5;
497 case PIPE_FORMAT_R16G16B16A16_FLOAT:
498 return SVGA3D_ARGB_S10E5;
499
500 case PIPE_FORMAT_Z32_UNORM:
501 /* SVGA3D_Z_D32 is not yet unsupported */
502 /* fall-through */
503 default:
504 return SVGA3D_FORMAT_INVALID;
505 }
506 }
507
508
509 /*
510 * Format capability description entry.
511 */
512 struct format_cap {
513 const char *name;
514
515 SVGA3dSurfaceFormat format;
516
517 /*
518 * Capability index corresponding to the format.
519 */
520 SVGA3dDevCapIndex devcap;
521
522 /* size of each pixel/block */
523 unsigned block_width, block_height, block_bytes;
524
525 /*
526 * Mask of supported SVGA3dFormatOp operations, to be inferred when the
527 * capability is not explicitly present.
528 */
529 uint32 defaultOperations;
530 };
531
532
533 /*
534 * Format capability description table.
535 *
536 * Ordered by increasing SVGA3dSurfaceFormat value, but with gaps.
537 */
538 static const struct format_cap format_cap_table[] = {
539 {
540 "SVGA3D_FORMAT_INVALID",
541 SVGA3D_FORMAT_INVALID, 0, 0, 0, 0, 0
542 },
543 {
544 "SVGA3D_X8R8G8B8",
545 SVGA3D_X8R8G8B8,
546 SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8,
547 1, 1, 4,
548 SVGA3DFORMAT_OP_TEXTURE |
549 SVGA3DFORMAT_OP_CUBETEXTURE |
550 SVGA3DFORMAT_OP_VOLUMETEXTURE |
551 SVGA3DFORMAT_OP_DISPLAYMODE |
552 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
553 },
554 {
555 "SVGA3D_A8R8G8B8",
556 SVGA3D_A8R8G8B8,
557 SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8,
558 1, 1, 4,
559 SVGA3DFORMAT_OP_TEXTURE |
560 SVGA3DFORMAT_OP_CUBETEXTURE |
561 SVGA3DFORMAT_OP_VOLUMETEXTURE |
562 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
563 },
564 {
565 "SVGA3D_R5G6B5",
566 SVGA3D_R5G6B5,
567 SVGA3D_DEVCAP_SURFACEFMT_R5G6B5,
568 1, 1, 2,
569 SVGA3DFORMAT_OP_TEXTURE |
570 SVGA3DFORMAT_OP_CUBETEXTURE |
571 SVGA3DFORMAT_OP_VOLUMETEXTURE |
572 SVGA3DFORMAT_OP_DISPLAYMODE |
573 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
574 },
575 {
576 "SVGA3D_X1R5G5B5",
577 SVGA3D_X1R5G5B5,
578 SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5,
579 1, 1, 2,
580 SVGA3DFORMAT_OP_TEXTURE |
581 SVGA3DFORMAT_OP_CUBETEXTURE |
582 SVGA3DFORMAT_OP_VOLUMETEXTURE |
583 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
584 },
585 {
586 "SVGA3D_A1R5G5B5",
587 SVGA3D_A1R5G5B5,
588 SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5,
589 1, 1, 2,
590 SVGA3DFORMAT_OP_TEXTURE |
591 SVGA3DFORMAT_OP_CUBETEXTURE |
592 SVGA3DFORMAT_OP_VOLUMETEXTURE |
593 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
594 },
595 {
596 "SVGA3D_A4R4G4B4",
597 SVGA3D_A4R4G4B4,
598 SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4,
599 1, 1, 2,
600 SVGA3DFORMAT_OP_TEXTURE |
601 SVGA3DFORMAT_OP_CUBETEXTURE |
602 SVGA3DFORMAT_OP_VOLUMETEXTURE |
603 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
604 },
605 {
606 /*
607 * SVGA3D_Z_D32 is not yet supported, and has no corresponding
608 * SVGA3D_DEVCAP_xxx.
609 */
610 "SVGA3D_Z_D32",
611 SVGA3D_Z_D32, 0, 0, 0, 0, 0
612 },
613 {
614 "SVGA3D_Z_D16",
615 SVGA3D_Z_D16,
616 SVGA3D_DEVCAP_SURFACEFMT_Z_D16,
617 1, 1, 2,
618 SVGA3DFORMAT_OP_ZSTENCIL
619 },
620 {
621 "SVGA3D_Z_D24S8",
622 SVGA3D_Z_D24S8,
623 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8,
624 1, 1, 4,
625 SVGA3DFORMAT_OP_ZSTENCIL
626 },
627 {
628 "SVGA3D_Z_D15S1",
629 SVGA3D_Z_D15S1,
630 SVGA3D_DEVCAP_MAX,
631 1, 1, 2,
632 SVGA3DFORMAT_OP_ZSTENCIL
633 },
634 {
635 "SVGA3D_LUMINANCE8",
636 SVGA3D_LUMINANCE8,
637 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8,
638 1, 1, 1,
639 SVGA3DFORMAT_OP_TEXTURE |
640 SVGA3DFORMAT_OP_CUBETEXTURE |
641 SVGA3DFORMAT_OP_VOLUMETEXTURE
642 },
643 {
644 /*
645 * SVGA3D_LUMINANCE4_ALPHA4 is not supported, and has no corresponding
646 * SVGA3D_DEVCAP_xxx.
647 */
648 "SVGA3D_LUMINANCE4_ALPHA4",
649 SVGA3D_LUMINANCE4_ALPHA4, 0, 0, 0, 0, 0
650 },
651 {
652 "SVGA3D_LUMINANCE16",
653 SVGA3D_LUMINANCE16,
654 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16,
655 1, 1, 2,
656 SVGA3DFORMAT_OP_TEXTURE |
657 SVGA3DFORMAT_OP_CUBETEXTURE |
658 SVGA3DFORMAT_OP_VOLUMETEXTURE
659 },
660 {
661 "SVGA3D_LUMINANCE8_ALPHA8",
662 SVGA3D_LUMINANCE8_ALPHA8,
663 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8,
664 1, 1, 2,
665 SVGA3DFORMAT_OP_TEXTURE |
666 SVGA3DFORMAT_OP_CUBETEXTURE |
667 SVGA3DFORMAT_OP_VOLUMETEXTURE
668 },
669 {
670 "SVGA3D_DXT1",
671 SVGA3D_DXT1,
672 SVGA3D_DEVCAP_SURFACEFMT_DXT1,
673 4, 4, 8,
674 SVGA3DFORMAT_OP_TEXTURE |
675 SVGA3DFORMAT_OP_CUBETEXTURE
676 },
677 {
678 "SVGA3D_DXT2",
679 SVGA3D_DXT2,
680 SVGA3D_DEVCAP_SURFACEFMT_DXT2,
681 4, 4, 8,
682 SVGA3DFORMAT_OP_TEXTURE |
683 SVGA3DFORMAT_OP_CUBETEXTURE
684 },
685 {
686 "SVGA3D_DXT3",
687 SVGA3D_DXT3,
688 SVGA3D_DEVCAP_SURFACEFMT_DXT3,
689 4, 4, 16,
690 SVGA3DFORMAT_OP_TEXTURE |
691 SVGA3DFORMAT_OP_CUBETEXTURE
692 },
693 {
694 "SVGA3D_DXT4",
695 SVGA3D_DXT4,
696 SVGA3D_DEVCAP_SURFACEFMT_DXT4,
697 4, 4, 16,
698 SVGA3DFORMAT_OP_TEXTURE |
699 SVGA3DFORMAT_OP_CUBETEXTURE
700 },
701 {
702 "SVGA3D_DXT5",
703 SVGA3D_DXT5,
704 SVGA3D_DEVCAP_SURFACEFMT_DXT5,
705 4, 4, 8,
706 SVGA3DFORMAT_OP_TEXTURE |
707 SVGA3DFORMAT_OP_CUBETEXTURE
708 },
709 {
710 "SVGA3D_BUMPU8V8",
711 SVGA3D_BUMPU8V8,
712 SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8,
713 1, 1, 2,
714 SVGA3DFORMAT_OP_TEXTURE |
715 SVGA3DFORMAT_OP_CUBETEXTURE |
716 SVGA3DFORMAT_OP_VOLUMETEXTURE
717 },
718 {
719 /*
720 * SVGA3D_BUMPL6V5U5 is unsupported; it has no corresponding
721 * SVGA3D_DEVCAP_xxx.
722 */
723 "SVGA3D_BUMPL6V5U5",
724 SVGA3D_BUMPL6V5U5, 0, 0, 0, 0, 0
725 },
726 {
727 "SVGA3D_BUMPX8L8V8U8",
728 SVGA3D_BUMPX8L8V8U8,
729 SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8,
730 1, 1, 4,
731 SVGA3DFORMAT_OP_TEXTURE |
732 SVGA3DFORMAT_OP_CUBETEXTURE
733 },
734 {
735 "SVGA3D_FORMAT_DEAD1",
736 SVGA3D_FORMAT_DEAD1, 0, 0, 0, 0, 0
737 },
738 {
739 "SVGA3D_ARGB_S10E5",
740 SVGA3D_ARGB_S10E5,
741 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5,
742 1, 1, 2,
743 SVGA3DFORMAT_OP_TEXTURE |
744 SVGA3DFORMAT_OP_CUBETEXTURE |
745 SVGA3DFORMAT_OP_VOLUMETEXTURE |
746 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
747 },
748 {
749 "SVGA3D_ARGB_S23E8",
750 SVGA3D_ARGB_S23E8,
751 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8,
752 1, 1, 4,
753 SVGA3DFORMAT_OP_TEXTURE |
754 SVGA3DFORMAT_OP_CUBETEXTURE |
755 SVGA3DFORMAT_OP_VOLUMETEXTURE |
756 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
757 },
758 {
759 "SVGA3D_A2R10G10B10",
760 SVGA3D_A2R10G10B10,
761 SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10,
762 1, 1, 4,
763 SVGA3DFORMAT_OP_TEXTURE |
764 SVGA3DFORMAT_OP_CUBETEXTURE |
765 SVGA3DFORMAT_OP_VOLUMETEXTURE |
766 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
767 },
768 {
769 /*
770 * SVGA3D_V8U8 is unsupported; it has no corresponding
771 * SVGA3D_DEVCAP_xxx. SVGA3D_BUMPU8V8 should be used instead.
772 */
773 "SVGA3D_V8U8",
774 SVGA3D_V8U8, 0, 0, 0, 0, 0
775 },
776 {
777 "SVGA3D_Q8W8V8U8",
778 SVGA3D_Q8W8V8U8,
779 SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8,
780 1, 1, 4,
781 SVGA3DFORMAT_OP_TEXTURE |
782 SVGA3DFORMAT_OP_CUBETEXTURE
783 },
784 {
785 "SVGA3D_CxV8U8",
786 SVGA3D_CxV8U8,
787 SVGA3D_DEVCAP_SURFACEFMT_CxV8U8,
788 1, 1, 2,
789 SVGA3DFORMAT_OP_TEXTURE
790 },
791 {
792 /*
793 * SVGA3D_X8L8V8U8 is unsupported; it has no corresponding
794 * SVGA3D_DEVCAP_xxx. SVGA3D_BUMPX8L8V8U8 should be used instead.
795 */
796 "SVGA3D_X8L8V8U8",
797 SVGA3D_X8L8V8U8, 0, 0, 0, 0, 0
798 },
799 {
800 "SVGA3D_A2W10V10U10",
801 SVGA3D_A2W10V10U10,
802 SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10,
803 1, 1, 4,
804 SVGA3DFORMAT_OP_TEXTURE
805 },
806 {
807 "SVGA3D_ALPHA8",
808 SVGA3D_ALPHA8,
809 SVGA3D_DEVCAP_SURFACEFMT_ALPHA8,
810 1, 1, 1,
811 SVGA3DFORMAT_OP_TEXTURE |
812 SVGA3DFORMAT_OP_CUBETEXTURE |
813 SVGA3DFORMAT_OP_VOLUMETEXTURE
814 },
815 {
816 "SVGA3D_R_S10E5",
817 SVGA3D_R_S10E5,
818 SVGA3D_DEVCAP_SURFACEFMT_R_S10E5,
819 1, 1, 2,
820 SVGA3DFORMAT_OP_TEXTURE |
821 SVGA3DFORMAT_OP_VOLUMETEXTURE |
822 SVGA3DFORMAT_OP_CUBETEXTURE |
823 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
824 },
825 {
826 "SVGA3D_R_S23E8",
827 SVGA3D_R_S23E8,
828 SVGA3D_DEVCAP_SURFACEFMT_R_S23E8,
829 1, 1, 4,
830 SVGA3DFORMAT_OP_TEXTURE |
831 SVGA3DFORMAT_OP_VOLUMETEXTURE |
832 SVGA3DFORMAT_OP_CUBETEXTURE |
833 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
834 },
835 {
836 "SVGA3D_RG_S10E5",
837 SVGA3D_RG_S10E5,
838 SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5,
839 1, 1, 2,
840 SVGA3DFORMAT_OP_TEXTURE |
841 SVGA3DFORMAT_OP_VOLUMETEXTURE |
842 SVGA3DFORMAT_OP_CUBETEXTURE |
843 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
844 },
845 {
846 "SVGA3D_RG_S23E8",
847 SVGA3D_RG_S23E8,
848 SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8,
849 1, 1, 4,
850 SVGA3DFORMAT_OP_TEXTURE |
851 SVGA3DFORMAT_OP_VOLUMETEXTURE |
852 SVGA3DFORMAT_OP_CUBETEXTURE |
853 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
854 },
855 {
856 /*
857 * SVGA3D_BUFFER is a placeholder format for index/vertex buffers.
858 */
859 "SVGA3D_BUFFER",
860 SVGA3D_BUFFER, 0, 1, 1, 1, 0
861 },
862 {
863 "SVGA3D_Z_D24X8",
864 SVGA3D_Z_D24X8,
865 SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8,
866 1, 1, 4,
867 SVGA3DFORMAT_OP_ZSTENCIL
868 },
869 {
870 "SVGA3D_V16U16",
871 SVGA3D_V16U16,
872 SVGA3D_DEVCAP_SURFACEFMT_V16U16,
873 1, 1, 4,
874 SVGA3DFORMAT_OP_TEXTURE |
875 SVGA3DFORMAT_OP_CUBETEXTURE |
876 SVGA3DFORMAT_OP_VOLUMETEXTURE
877 },
878 {
879 "SVGA3D_G16R16",
880 SVGA3D_G16R16,
881 SVGA3D_DEVCAP_SURFACEFMT_G16R16,
882 1, 1, 4,
883 SVGA3DFORMAT_OP_TEXTURE |
884 SVGA3DFORMAT_OP_CUBETEXTURE |
885 SVGA3DFORMAT_OP_VOLUMETEXTURE |
886 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
887 },
888 {
889 "SVGA3D_A16B16G16R16",
890 SVGA3D_A16B16G16R16,
891 SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16,
892 1, 1, 8,
893 SVGA3DFORMAT_OP_TEXTURE |
894 SVGA3DFORMAT_OP_CUBETEXTURE |
895 SVGA3DFORMAT_OP_VOLUMETEXTURE |
896 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
897 },
898 {
899 "SVGA3D_UYVY",
900 SVGA3D_UYVY,
901 SVGA3D_DEVCAP_SURFACEFMT_UYVY,
902 0, 0, 0, 0
903 },
904 {
905 "SVGA3D_YUY2",
906 SVGA3D_YUY2,
907 SVGA3D_DEVCAP_SURFACEFMT_YUY2,
908 0, 0, 0, 0
909 },
910 {
911 "SVGA3D_NV12",
912 SVGA3D_NV12,
913 SVGA3D_DEVCAP_SURFACEFMT_NV12,
914 0, 0, 0, 0
915 },
916 {
917 "SVGA3D_AYUV",
918 SVGA3D_AYUV,
919 SVGA3D_DEVCAP_SURFACEFMT_AYUV,
920 0, 0, 0, 0
921 },
922 {
923 "SVGA3D_R32G32B32A32_TYPELESS",
924 SVGA3D_R32G32B32A32_TYPELESS,
925 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS,
926 1, 1, 16, 0
927 },
928 {
929 "SVGA3D_R32G32B32A32_UINT",
930 SVGA3D_R32G32B32A32_UINT,
931 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT,
932 1, 1, 16, 0
933 },
934 {
935 "SVGA3D_R32G32B32A32_SINT",
936 SVGA3D_R32G32B32A32_SINT,
937 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT,
938 1, 1, 16, 0
939 },
940 {
941 "SVGA3D_R32G32B32_TYPELESS",
942 SVGA3D_R32G32B32_TYPELESS,
943 SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS,
944 1, 1, 12, 0
945 },
946 {
947 "SVGA3D_R32G32B32_FLOAT",
948 SVGA3D_R32G32B32_FLOAT,
949 SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT,
950 1, 1, 12, 0
951 },
952 {
953 "SVGA3D_R32G32B32_UINT",
954 SVGA3D_R32G32B32_UINT,
955 SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT,
956 1, 1, 12, 0
957 },
958 {
959 "SVGA3D_R32G32B32_SINT",
960 SVGA3D_R32G32B32_SINT,
961 SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT,
962 1, 1, 12, 0
963 },
964 {
965 "SVGA3D_R16G16B16A16_TYPELESS",
966 SVGA3D_R16G16B16A16_TYPELESS,
967 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS,
968 1, 1, 8, 0
969 },
970 {
971 "SVGA3D_R16G16B16A16_UINT",
972 SVGA3D_R16G16B16A16_UINT,
973 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT,
974 1, 1, 8, 0
975 },
976 {
977 "SVGA3D_R16G16B16A16_SNORM",
978 SVGA3D_R16G16B16A16_SNORM,
979 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM,
980 1, 1, 8, 0
981 },
982 {
983 "SVGA3D_R16G16B16A16_SINT",
984 SVGA3D_R16G16B16A16_SINT,
985 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT,
986 1, 1, 8, 0
987 },
988 {
989 "SVGA3D_R32G32_TYPELESS",
990 SVGA3D_R32G32_TYPELESS,
991 SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS,
992 1, 1, 8, 0
993 },
994 {
995 "SVGA3D_R32G32_UINT",
996 SVGA3D_R32G32_UINT,
997 SVGA3D_DEVCAP_DXFMT_R32G32_UINT,
998 1, 1, 8, 0
999 },
1000 {
1001 "SVGA3D_R32G32_SINT",
1002 SVGA3D_R32G32_SINT,
1003 SVGA3D_DEVCAP_DXFMT_R32G32_SINT,
1004 1, 1, 8,
1005 0
1006 },
1007 {
1008 "SVGA3D_R32G8X24_TYPELESS",
1009 SVGA3D_R32G8X24_TYPELESS,
1010 SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS,
1011 1, 1, 8, 0
1012 },
1013 {
1014 "SVGA3D_D32_FLOAT_S8X24_UINT",
1015 SVGA3D_D32_FLOAT_S8X24_UINT,
1016 SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT,
1017 1, 1, 8, 0
1018 },
1019 {
1020 "SVGA3D_R32_FLOAT_X8X24",
1021 SVGA3D_R32_FLOAT_X8X24,
1022 SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24_TYPELESS,
1023 1, 1, 8, 0
1024 },
1025 {
1026 "SVGA3D_X32_G8X24_UINT",
1027 SVGA3D_X32_G8X24_UINT,
1028 SVGA3D_DEVCAP_DXFMT_X32_TYPELESS_G8X24_UINT,
1029 1, 1, 4, 0
1030 },
1031 {
1032 "SVGA3D_R10G10B10A2_TYPELESS",
1033 SVGA3D_R10G10B10A2_TYPELESS,
1034 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS,
1035 1, 1, 4, 0
1036 },
1037 {
1038 "SVGA3D_R10G10B10A2_UINT",
1039 SVGA3D_R10G10B10A2_UINT,
1040 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT,
1041 1, 1, 4, 0
1042 },
1043 {
1044 "SVGA3D_R11G11B10_FLOAT",
1045 SVGA3D_R11G11B10_FLOAT,
1046 SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT,
1047 1, 1, 4, 0
1048 },
1049 {
1050 "SVGA3D_R8G8B8A8_TYPELESS",
1051 SVGA3D_R8G8B8A8_TYPELESS,
1052 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS,
1053 1, 1, 4, 0
1054 },
1055 {
1056 "SVGA3D_R8G8B8A8_UNORM",
1057 SVGA3D_R8G8B8A8_UNORM,
1058 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM,
1059 1, 1, 4, 0
1060 },
1061 {
1062 "SVGA3D_R8G8B8A8_UNORM_SRGB",
1063 SVGA3D_R8G8B8A8_UNORM_SRGB,
1064 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB,
1065 1, 1, 4, 0
1066 },
1067 {
1068 "SVGA3D_R8G8B8A8_UINT",
1069 SVGA3D_R8G8B8A8_UINT,
1070 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT,
1071 1, 1, 4, 0
1072 },
1073 {
1074 "SVGA3D_R8G8B8A8_SINT",
1075 SVGA3D_R8G8B8A8_SINT,
1076 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT,
1077 1, 1, 4, 0
1078 },
1079 {
1080 "SVGA3D_R16G16_TYPELESS",
1081 SVGA3D_R16G16_TYPELESS,
1082 SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS,
1083 1, 1, 4, 0
1084 },
1085 {
1086 "SVGA3D_R16G16_UINT",
1087 SVGA3D_R16G16_UINT,
1088 SVGA3D_DEVCAP_DXFMT_R16G16_UINT,
1089 1, 1, 4, 0
1090 },
1091 {
1092 "SVGA3D_R16G16_SINT",
1093 SVGA3D_R16G16_SINT,
1094 SVGA3D_DEVCAP_DXFMT_R16G16_SINT,
1095 1, 1, 4, 0
1096 },
1097 {
1098 "SVGA3D_R32_TYPELESS",
1099 SVGA3D_R32_TYPELESS,
1100 SVGA3D_DEVCAP_DXFMT_R32_TYPELESS,
1101 1, 1, 4, 0
1102 },
1103 {
1104 "SVGA3D_D32_FLOAT",
1105 SVGA3D_D32_FLOAT,
1106 SVGA3D_DEVCAP_DXFMT_D32_FLOAT,
1107 1, 1, 4, 0
1108 },
1109 {
1110 "SVGA3D_R32_UINT",
1111 SVGA3D_R32_UINT,
1112 SVGA3D_DEVCAP_DXFMT_R32_UINT,
1113 1, 1, 4, 0
1114 },
1115 {
1116 "SVGA3D_R32_SINT",
1117 SVGA3D_R32_SINT,
1118 SVGA3D_DEVCAP_DXFMT_R32_SINT,
1119 1, 1, 4, 0
1120 },
1121 {
1122 "SVGA3D_R24G8_TYPELESS",
1123 SVGA3D_R24G8_TYPELESS,
1124 SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS,
1125 1, 1, 4, 0
1126 },
1127 {
1128 "SVGA3D_D24_UNORM_S8_UINT",
1129 SVGA3D_D24_UNORM_S8_UINT,
1130 SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT,
1131 1, 1, 4, 0
1132 },
1133 {
1134 "SVGA3D_R24_UNORM_X8",
1135 SVGA3D_R24_UNORM_X8,
1136 SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8_TYPELESS,
1137 1, 1, 4, 0
1138 },
1139 {
1140 "SVGA3D_X24_G8_UINT",
1141 SVGA3D_X24_G8_UINT,
1142 SVGA3D_DEVCAP_DXFMT_X24_TYPELESS_G8_UINT,
1143 1, 1, 4, 0
1144 },
1145 {
1146 "SVGA3D_R8G8_TYPELESS",
1147 SVGA3D_R8G8_TYPELESS,
1148 SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS,
1149 1, 1, 2, 0
1150 },
1151 {
1152 "SVGA3D_R8G8_UNORM",
1153 SVGA3D_R8G8_UNORM,
1154 SVGA3D_DEVCAP_DXFMT_R8G8_UNORM,
1155 1, 1, 2, 0
1156 },
1157 {
1158 "SVGA3D_R8G8_UINT",
1159 SVGA3D_R8G8_UINT,
1160 SVGA3D_DEVCAP_DXFMT_R8G8_UINT,
1161 1, 1, 2, 0
1162 },
1163 {
1164 "SVGA3D_R8G8_SINT",
1165 SVGA3D_R8G8_SINT,
1166 SVGA3D_DEVCAP_DXFMT_R8G8_SINT,
1167 1, 1, 2, 0
1168 },
1169 {
1170 "SVGA3D_R16_TYPELESS",
1171 SVGA3D_R16_TYPELESS,
1172 SVGA3D_DEVCAP_DXFMT_R16_TYPELESS,
1173 1, 1, 2, 0
1174 },
1175 {
1176 "SVGA3D_R16_UNORM",
1177 SVGA3D_R16_UNORM,
1178 SVGA3D_DEVCAP_DXFMT_R16_UNORM,
1179 1, 1, 2, 0
1180 },
1181 {
1182 "SVGA3D_R16_UINT",
1183 SVGA3D_R16_UINT,
1184 SVGA3D_DEVCAP_DXFMT_R16_UINT,
1185 1, 1, 2, 0
1186 },
1187 {
1188 "SVGA3D_R16_SNORM",
1189 SVGA3D_R16_SNORM,
1190 SVGA3D_DEVCAP_DXFMT_R16_SNORM,
1191 1, 1, 2, 0
1192 },
1193 {
1194 "SVGA3D_R16_SINT",
1195 SVGA3D_R16_SINT,
1196 SVGA3D_DEVCAP_DXFMT_R16_SINT,
1197 1, 1, 2, 0
1198 },
1199 {
1200 "SVGA3D_R8_TYPELESS",
1201 SVGA3D_R8_TYPELESS,
1202 SVGA3D_DEVCAP_DXFMT_R8_TYPELESS,
1203 1, 1, 1, 0
1204 },
1205 {
1206 "SVGA3D_R8_UNORM",
1207 SVGA3D_R8_UNORM,
1208 SVGA3D_DEVCAP_DXFMT_R8_UNORM,
1209 1, 1, 1, 0
1210 },
1211 {
1212 "SVGA3D_R8_UINT",
1213 SVGA3D_R8_UINT,
1214 SVGA3D_DEVCAP_DXFMT_R8_UINT,
1215 1, 1, 1, 0
1216 },
1217 {
1218 "SVGA3D_R8_SNORM",
1219 SVGA3D_R8_SNORM,
1220 SVGA3D_DEVCAP_DXFMT_R8_SNORM,
1221 1, 1, 1, 0
1222 },
1223 {
1224 "SVGA3D_R8_SINT",
1225 SVGA3D_R8_SINT,
1226 SVGA3D_DEVCAP_DXFMT_R8_SINT,
1227 1, 1, 1, 0
1228 },
1229 {
1230 "SVGA3D_P8",
1231 SVGA3D_P8, 0, 0, 0, 0, 0
1232 },
1233 {
1234 "SVGA3D_R9G9B9E5_SHAREDEXP",
1235 SVGA3D_R9G9B9E5_SHAREDEXP,
1236 SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP,
1237 1, 1, 4, 0
1238 },
1239 {
1240 "SVGA3D_R8G8_B8G8_UNORM",
1241 SVGA3D_R8G8_B8G8_UNORM, 0, 0, 0, 0, 0
1242 },
1243 {
1244 "SVGA3D_G8R8_G8B8_UNORM",
1245 SVGA3D_G8R8_G8B8_UNORM, 0, 0, 0, 0, 0
1246 },
1247 {
1248 "SVGA3D_BC1_TYPELESS",
1249 SVGA3D_BC1_TYPELESS,
1250 SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS,
1251 4, 4, 8, 0
1252 },
1253 {
1254 "SVGA3D_BC1_UNORM_SRGB",
1255 SVGA3D_BC1_UNORM_SRGB,
1256 SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB,
1257 4, 4, 8, 0
1258 },
1259 {
1260 "SVGA3D_BC2_TYPELESS",
1261 SVGA3D_BC2_TYPELESS,
1262 SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS,
1263 4, 4, 16, 0
1264 },
1265 {
1266 "SVGA3D_BC2_UNORM_SRGB",
1267 SVGA3D_BC2_UNORM_SRGB,
1268 SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB,
1269 4, 4, 16, 0
1270 },
1271 {
1272 "SVGA3D_BC3_TYPELESS",
1273 SVGA3D_BC3_TYPELESS,
1274 SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS,
1275 4, 4, 16, 0
1276 },
1277 {
1278 "SVGA3D_BC3_UNORM_SRGB",
1279 SVGA3D_BC3_UNORM_SRGB,
1280 SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB,
1281 4, 4, 16, 0
1282 },
1283 {
1284 "SVGA3D_BC4_TYPELESS",
1285 SVGA3D_BC4_TYPELESS,
1286 SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS,
1287 4, 4, 8, 0
1288 },
1289 {
1290 "SVGA3D_ATI1",
1291 SVGA3D_ATI1, 0, 0, 0, 0, 0
1292 },
1293 {
1294 "SVGA3D_BC4_SNORM",
1295 SVGA3D_BC4_SNORM,
1296 SVGA3D_DEVCAP_DXFMT_BC4_SNORM,
1297 4, 4, 8, 0
1298 },
1299 {
1300 "SVGA3D_BC5_TYPELESS",
1301 SVGA3D_BC5_TYPELESS,
1302 SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS,
1303 4, 4, 16, 0
1304 },
1305 {
1306 "SVGA3D_ATI2",
1307 SVGA3D_ATI2, 0, 0, 0, 0, 0
1308 },
1309 {
1310 "SVGA3D_BC5_SNORM",
1311 SVGA3D_BC5_SNORM,
1312 SVGA3D_DEVCAP_DXFMT_BC5_SNORM,
1313 4, 4, 16, 0
1314 },
1315 {
1316 "SVGA3D_R10G10B10_XR_BIAS_A2_UNORM",
1317 SVGA3D_R10G10B10_XR_BIAS_A2_UNORM, 0, 0, 0, 0, 0
1318 },
1319 {
1320 "SVGA3D_B8G8R8A8_TYPELESS",
1321 SVGA3D_B8G8R8A8_TYPELESS,
1322 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS,
1323 1, 1, 4, 0
1324 },
1325 {
1326 "SVGA3D_B8G8R8A8_UNORM_SRGB",
1327 SVGA3D_B8G8R8A8_UNORM_SRGB,
1328 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB,
1329 1, 1, 4, 0
1330 },
1331 {
1332 "SVGA3D_B8G8R8X8_TYPELESS",
1333 SVGA3D_B8G8R8X8_TYPELESS,
1334 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS,
1335 1, 1, 4, 0
1336 },
1337 {
1338 "SVGA3D_B8G8R8X8_UNORM_SRGB",
1339 SVGA3D_B8G8R8X8_UNORM_SRGB,
1340 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB,
1341 1, 1, 4, 0
1342 },
1343 {
1344 "SVGA3D_Z_DF16",
1345 SVGA3D_Z_DF16,
1346 SVGA3D_DEVCAP_SURFACEFMT_Z_DF16,
1347 1, 1, 2, 0
1348 },
1349 {
1350 "SVGA3D_Z_DF24",
1351 SVGA3D_Z_DF24,
1352 SVGA3D_DEVCAP_SURFACEFMT_Z_DF24,
1353 1, 1, 4, 0
1354 },
1355 {
1356 "SVGA3D_Z_D24S8_INT",
1357 SVGA3D_Z_D24S8_INT,
1358 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT,
1359 1, 1, 4, 0
1360 },
1361 {
1362 "SVGA3D_YV12",
1363 SVGA3D_YV12, 0, 0, 0, 0, 0
1364 },
1365 {
1366 "SVGA3D_R32G32B32A32_FLOAT",
1367 SVGA3D_R32G32B32A32_FLOAT,
1368 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT,
1369 1, 1, 16, 0
1370 },
1371 {
1372 "SVGA3D_R16G16B16A16_FLOAT",
1373 SVGA3D_R16G16B16A16_FLOAT,
1374 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT,
1375 1, 1, 8, 0
1376 },
1377 {
1378 "SVGA3D_R16G16B16A16_UNORM",
1379 SVGA3D_R16G16B16A16_UNORM,
1380 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM,
1381 1, 1, 8, 0
1382 },
1383 {
1384 "SVGA3D_R32G32_FLOAT",
1385 SVGA3D_R32G32_FLOAT,
1386 SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT,
1387 1, 1, 8, 0
1388 },
1389 {
1390 "SVGA3D_R10G10B10A2_UNORM",
1391 SVGA3D_R10G10B10A2_UNORM,
1392 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM,
1393 1, 1, 4, 0
1394 },
1395 {
1396 "SVGA3D_R8G8B8A8_SNORM",
1397 SVGA3D_R8G8B8A8_SNORM,
1398 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM,
1399 1, 1, 4, 0
1400 },
1401 {
1402 "SVGA3D_R16G16_FLOAT",
1403 SVGA3D_R16G16_FLOAT,
1404 SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT,
1405 1, 1, 4, 0
1406 },
1407 {
1408 "SVGA3D_R16G16_UNORM",
1409 SVGA3D_R16G16_UNORM,
1410 SVGA3D_DEVCAP_DXFMT_R16G16_UNORM,
1411 1, 1, 4, 0
1412 },
1413 {
1414 "SVGA3D_R16G16_SNORM",
1415 SVGA3D_R16G16_SNORM,
1416 SVGA3D_DEVCAP_DXFMT_R16G16_SNORM,
1417 1, 1, 4, 0
1418 },
1419 {
1420 "SVGA3D_R32_FLOAT",
1421 SVGA3D_R32_FLOAT,
1422 SVGA3D_DEVCAP_DXFMT_R32_FLOAT,
1423 1, 1, 4, 0
1424 },
1425 {
1426 "SVGA3D_R8G8_SNORM",
1427 SVGA3D_R8G8_SNORM,
1428 SVGA3D_DEVCAP_DXFMT_R8G8_SNORM,
1429 1, 1, 2, 0
1430 },
1431 {
1432 "SVGA3D_R16_FLOAT",
1433 SVGA3D_R16_FLOAT,
1434 SVGA3D_DEVCAP_DXFMT_R16_FLOAT,
1435 1, 1, 2, 0
1436 },
1437 {
1438 "SVGA3D_D16_UNORM",
1439 SVGA3D_D16_UNORM,
1440 SVGA3D_DEVCAP_DXFMT_D16_UNORM,
1441 1, 1, 2, 0
1442 },
1443 {
1444 "SVGA3D_A8_UNORM",
1445 SVGA3D_A8_UNORM,
1446 SVGA3D_DEVCAP_DXFMT_A8_UNORM,
1447 1, 1, 1, 0
1448 },
1449 {
1450 "SVGA3D_BC1_UNORM",
1451 SVGA3D_BC1_UNORM,
1452 SVGA3D_DEVCAP_DXFMT_BC1_UNORM,
1453 4, 4, 8, 0
1454 },
1455 {
1456 "SVGA3D_BC2_UNORM",
1457 SVGA3D_BC2_UNORM,
1458 SVGA3D_DEVCAP_DXFMT_BC2_UNORM,
1459 4, 4, 16, 0
1460 },
1461 {
1462 "SVGA3D_BC3_UNORM",
1463 SVGA3D_BC3_UNORM,
1464 SVGA3D_DEVCAP_DXFMT_BC3_UNORM,
1465 4, 4, 16, 0
1466 },
1467 {
1468 "SVGA3D_B5G6R5_UNORM",
1469 SVGA3D_B5G6R5_UNORM,
1470 SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM,
1471 1, 1, 2, 0
1472 },
1473 {
1474 "SVGA3D_B5G5R5A1_UNORM",
1475 SVGA3D_B5G5R5A1_UNORM,
1476 SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM,
1477 1, 1, 2, 0
1478 },
1479 {
1480 "SVGA3D_B8G8R8A8_UNORM",
1481 SVGA3D_B8G8R8A8_UNORM,
1482 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM,
1483 1, 1, 4, 0
1484 },
1485 {
1486 "SVGA3D_B8G8R8X8_UNORM",
1487 SVGA3D_B8G8R8X8_UNORM,
1488 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM,
1489 1, 1, 4, 0
1490 },
1491 {
1492 "SVGA3D_BC4_UNORM",
1493 SVGA3D_BC4_UNORM,
1494 SVGA3D_DEVCAP_DXFMT_BC4_UNORM,
1495 4, 4, 8, 0
1496 },
1497 {
1498 "SVGA3D_BC5_UNORM",
1499 SVGA3D_BC5_UNORM,
1500 SVGA3D_DEVCAP_DXFMT_BC5_UNORM,
1501 4, 4, 16, 0
1502 }
1503 };
1504
1505 static const SVGA3dSurfaceFormat compat_x8r8g8b8[] = {
1506 SVGA3D_X8R8G8B8, SVGA3D_A8R8G8B8, SVGA3D_B8G8R8X8_UNORM,
1507 SVGA3D_B8G8R8A8_UNORM, 0
1508 };
1509 static const SVGA3dSurfaceFormat compat_r8[] = {
1510 SVGA3D_R8_UNORM, SVGA3D_NV12, SVGA3D_YV12, 0
1511 };
1512 static const SVGA3dSurfaceFormat compat_g8r8[] = {
1513 SVGA3D_R8G8_UNORM, SVGA3D_NV12, 0
1514 };
1515 static const SVGA3dSurfaceFormat compat_r5g6b5[] = {
1516 SVGA3D_R5G6B5, SVGA3D_B5G6R5_UNORM, 0
1517 };
1518
1519 static const struct format_compat_entry format_compats[] = {
1520 {PIPE_FORMAT_B8G8R8X8_UNORM, compat_x8r8g8b8},
1521 {PIPE_FORMAT_B8G8R8A8_UNORM, compat_x8r8g8b8},
1522 {PIPE_FORMAT_R8_UNORM, compat_r8},
1523 {PIPE_FORMAT_R8G8_UNORM, compat_g8r8},
1524 {PIPE_FORMAT_B5G6R5_UNORM, compat_r5g6b5}
1525 };
1526
1527 /**
1528 * Debug only:
1529 * 1. check that format_cap_table[i] matches the i-th SVGA3D format.
1530 * 2. check that format_conversion_table[i].pformat == i.
1531 */
1532 static void
1533 check_format_tables(void)
1534 {
1535 static boolean first_call = TRUE;
1536
1537 if (first_call) {
1538 unsigned i;
1539
1540 STATIC_ASSERT(ARRAY_SIZE(format_cap_table) == SVGA3D_FORMAT_MAX);
1541 for (i = 0; i < ARRAY_SIZE(format_cap_table); i++) {
1542 assert(format_cap_table[i].format == i);
1543 }
1544
1545 STATIC_ASSERT(ARRAY_SIZE(format_conversion_table) == PIPE_FORMAT_COUNT);
1546 for (i = 0; i < ARRAY_SIZE(format_conversion_table); i++) {
1547 assert(format_conversion_table[i].pformat == i);
1548 }
1549
1550 first_call = FALSE;
1551 }
1552 }
1553
1554
1555 /**
1556 * Return string name of an SVGA3dDevCapIndex value.
1557 * For debugging.
1558 */
1559 static const char *
1560 svga_devcap_name(SVGA3dDevCapIndex cap)
1561 {
1562 static const struct debug_named_value devcap_names[] = {
1563 /* Note, we only list the DXFMT devcaps so far */
1564 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X8R8G8B8),
1565 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A8R8G8B8),
1566 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R5G6B5),
1567 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X1R5G5B5),
1568 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A1R5G5B5),
1569 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A4R4G4B4),
1570 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D32),
1571 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D16),
1572 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D24S8),
1573 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D15S1),
1574 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE8),
1575 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4),
1576 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE16),
1577 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8),
1578 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT1),
1579 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT2),
1580 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT3),
1581 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT4),
1582 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT5),
1583 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUMPU8V8),
1584 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5),
1585 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8),
1586 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1),
1587 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5),
1588 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8),
1589 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A2R10G10B10),
1590 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_V8U8),
1591 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8),
1592 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_CxV8U8),
1593 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X8L8V8U8),
1594 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A2W10V10U10),
1595 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ALPHA8),
1596 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R_S10E5),
1597 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R_S23E8),
1598 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_RG_S10E5),
1599 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_RG_S23E8),
1600 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUFFER),
1601 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D24X8),
1602 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_V16U16),
1603 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_G16R16),
1604 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A16B16G16R16),
1605 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_UYVY),
1606 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_YUY2),
1607 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_NV12),
1608 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_AYUV),
1609 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS),
1610 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT),
1611 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT),
1612 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS),
1613 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT),
1614 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT),
1615 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT),
1616 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS),
1617 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT),
1618 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM),
1619 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT),
1620 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS),
1621 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_UINT),
1622 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_SINT),
1623 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS),
1624 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT),
1625 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24_TYPELESS),
1626 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X32_TYPELESS_G8X24_UINT),
1627 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS),
1628 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT),
1629 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT),
1630 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS),
1631 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM),
1632 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB),
1633 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT),
1634 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT),
1635 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS),
1636 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_UINT),
1637 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_SINT),
1638 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS),
1639 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D32_FLOAT),
1640 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_UINT),
1641 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_SINT),
1642 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS),
1643 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT),
1644 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8_TYPELESS),
1645 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X24_TYPELESS_G8_UINT),
1646 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS),
1647 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM),
1648 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_UINT),
1649 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_SINT),
1650 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS),
1651 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_UNORM),
1652 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_UINT),
1653 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_SNORM),
1654 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_SINT),
1655 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS),
1656 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_UNORM),
1657 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_UINT),
1658 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_SNORM),
1659 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_SINT),
1660 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_P8),
1661 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP),
1662 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM),
1663 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM),
1664 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS),
1665 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB),
1666 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS),
1667 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB),
1668 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS),
1669 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB),
1670 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS),
1671 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ATI1),
1672 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC4_SNORM),
1673 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS),
1674 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ATI2),
1675 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC5_SNORM),
1676 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM),
1677 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS),
1678 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB),
1679 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS),
1680 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB),
1681 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_DF16),
1682 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_DF24),
1683 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT),
1684 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_YV12),
1685 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT),
1686 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT),
1687 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM),
1688 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT),
1689 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM),
1690 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM),
1691 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT),
1692 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM),
1693 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM),
1694 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_FLOAT),
1695 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM),
1696 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_FLOAT),
1697 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D16_UNORM),
1698 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A8_UNORM),
1699 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC1_UNORM),
1700 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC2_UNORM),
1701 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC3_UNORM),
1702 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM),
1703 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM),
1704 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM),
1705 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM),
1706 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC4_UNORM),
1707 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC5_UNORM),
1708 DEBUG_NAMED_VALUE_END,
1709 };
1710 return debug_dump_enum(devcap_names, cap);
1711 }
1712
1713
1714 /**
1715 * Return string for a bitmask of name of SVGA3D_DXFMT_x flags.
1716 * For debugging.
1717 */
1718 static const char *
1719 svga_devcap_format_flags(unsigned flags)
1720 {
1721 static const struct debug_named_value devcap_flags[] = {
1722 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_SUPPORTED),
1723 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_SHADER_SAMPLE),
1724 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_COLOR_RENDERTARGET),
1725 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_DEPTH_RENDERTARGET),
1726 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_BLENDABLE),
1727 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_MIPS),
1728 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_ARRAY),
1729 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_VOLUME),
1730 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_DX_VERTEX_BUFFER),
1731 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_MULTISAMPLE),
1732 DEBUG_NAMED_VALUE_END
1733 };
1734
1735 return debug_dump_flags(devcap_flags, flags);
1736 }
1737
1738
1739 /*
1740 * Get format capabilities from the host. It takes in consideration
1741 * deprecated/unsupported formats, and formats which are implicitely assumed to
1742 * be supported when the host does not provide an explicit capability entry.
1743 */
1744 void
1745 svga_get_format_cap(struct svga_screen *ss,
1746 SVGA3dSurfaceFormat format,
1747 SVGA3dSurfaceFormatCaps *caps)
1748 {
1749 struct svga_winsys_screen *sws = ss->sws;
1750 SVGA3dDevCapResult result;
1751 const struct format_cap *entry;
1752
1753 #ifdef DEBUG
1754 check_format_tables();
1755 #else
1756 (void) check_format_tables;
1757 #endif
1758
1759 assert(format < ARRAY_SIZE(format_cap_table));
1760 entry = &format_cap_table[format];
1761 assert(entry->format == format);
1762
1763 if (entry->devcap && sws->get_cap(sws, entry->devcap, &result)) {
1764 assert(format < SVGA3D_UYVY || entry->defaultOperations == 0);
1765 caps->value = result.u;
1766 } else {
1767 /* Implicitly advertised format -- use default caps */
1768 caps->value = entry->defaultOperations;
1769 }
1770 }
1771
1772
1773 /*
1774 * Get DX format capabilities from VGPU10 device.
1775 */
1776 static void
1777 svga_get_dx_format_cap(struct svga_screen *ss,
1778 SVGA3dSurfaceFormat format,
1779 SVGA3dDevCapResult *caps)
1780 {
1781 struct svga_winsys_screen *sws = ss->sws;
1782 const struct format_cap *entry;
1783
1784 #ifdef DEBUG
1785 check_format_tables();
1786 #else
1787 (void) check_format_tables;
1788 #endif
1789
1790 assert(sws->have_vgpu10);
1791 assert(format < ARRAY_SIZE(format_cap_table));
1792 entry = &format_cap_table[format];
1793 assert(entry->format == format);
1794 assert(entry->devcap > SVGA3D_DEVCAP_DXCONTEXT);
1795
1796 caps->u = 0;
1797 if (entry->devcap) {
1798 sws->get_cap(sws, entry->devcap, caps);
1799
1800 /* pre-SM41 capabable svga device supports SHADER_SAMPLE capability for
1801 * these formats but does not advertise the devcap.
1802 * So enable this bit here.
1803 */
1804 if (!sws->have_sm4_1 &&
1805 (format == SVGA3D_R32_FLOAT_X8X24 ||
1806 format == SVGA3D_R24_UNORM_X8)) {
1807 caps->u |= SVGA3D_DXFMT_SHADER_SAMPLE;
1808 }
1809 }
1810
1811 if (0) {
1812 debug_printf("Format %s, devcap %s = 0x%x (%s)\n",
1813 svga_format_name(format),
1814 svga_devcap_name(entry->devcap),
1815 caps->u,
1816 svga_devcap_format_flags(caps->u));
1817 }
1818 }
1819
1820
1821 void
1822 svga_format_size(SVGA3dSurfaceFormat format,
1823 unsigned *block_width,
1824 unsigned *block_height,
1825 unsigned *bytes_per_block)
1826 {
1827 assert(format < ARRAY_SIZE(format_cap_table));
1828 *block_width = format_cap_table[format].block_width;
1829 *block_height = format_cap_table[format].block_height;
1830 *bytes_per_block = format_cap_table[format].block_bytes;
1831 /* Make sure the table entry was valid */
1832 if (*block_width == 0)
1833 debug_printf("Bad table entry for %s\n", svga_format_name(format));
1834 assert(*block_width);
1835 assert(*block_height);
1836 assert(*bytes_per_block);
1837 }
1838
1839
1840 const char *
1841 svga_format_name(SVGA3dSurfaceFormat format)
1842 {
1843 assert(format < ARRAY_SIZE(format_cap_table));
1844 return format_cap_table[format].name;
1845 }
1846
1847
1848 /**
1849 * Is the given SVGA3dSurfaceFormat a signed or unsigned integer color format?
1850 */
1851 boolean
1852 svga_format_is_integer(SVGA3dSurfaceFormat format)
1853 {
1854 switch (format) {
1855 case SVGA3D_R32G32B32A32_SINT:
1856 case SVGA3D_R32G32B32_SINT:
1857 case SVGA3D_R32G32_SINT:
1858 case SVGA3D_R32_SINT:
1859 case SVGA3D_R16G16B16A16_SINT:
1860 case SVGA3D_R16G16_SINT:
1861 case SVGA3D_R16_SINT:
1862 case SVGA3D_R8G8B8A8_SINT:
1863 case SVGA3D_R8G8_SINT:
1864 case SVGA3D_R8_SINT:
1865 case SVGA3D_R32G32B32A32_UINT:
1866 case SVGA3D_R32G32B32_UINT:
1867 case SVGA3D_R32G32_UINT:
1868 case SVGA3D_R32_UINT:
1869 case SVGA3D_R16G16B16A16_UINT:
1870 case SVGA3D_R16G16_UINT:
1871 case SVGA3D_R16_UINT:
1872 case SVGA3D_R8G8B8A8_UINT:
1873 case SVGA3D_R8G8_UINT:
1874 case SVGA3D_R8_UINT:
1875 case SVGA3D_R10G10B10A2_UINT:
1876 return TRUE;
1877 default:
1878 return FALSE;
1879 }
1880 }
1881
1882 boolean
1883 svga_format_support_gen_mips(enum pipe_format format)
1884 {
1885 assert(format < ARRAY_SIZE(format_conversion_table));
1886 return ((format_conversion_table[format].flags & TF_GEN_MIPS) > 0);
1887 }
1888
1889
1890 /**
1891 * Given a texture format, return the expected data type returned from
1892 * the texture sampler. For example, UNORM8 formats return floating point
1893 * values while SINT formats returned signed integer values.
1894 * Note: this function could be moved into the gallum u_format.[ch] code
1895 * if it's useful to anyone else.
1896 */
1897 enum tgsi_return_type
1898 svga_get_texture_datatype(enum pipe_format format)
1899 {
1900 const struct util_format_description *desc = util_format_description(format);
1901 enum tgsi_return_type t;
1902
1903 if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN ) {
1904 if (util_format_is_depth_or_stencil(format)) {
1905 t = TGSI_RETURN_TYPE_FLOAT; /* XXX revisit this */
1906 }
1907 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_FLOAT) {
1908 t = TGSI_RETURN_TYPE_FLOAT;
1909 }
1910 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1911 t = desc->channel[0].normalized ? TGSI_RETURN_TYPE_UNORM : TGSI_RETURN_TYPE_UINT;
1912 }
1913 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
1914 t = desc->channel[0].normalized ? TGSI_RETURN_TYPE_SNORM : TGSI_RETURN_TYPE_SINT;
1915 }
1916 else {
1917 assert(!"Unexpected channel type in svga_get_texture_datatype()");
1918 t = TGSI_RETURN_TYPE_FLOAT;
1919 }
1920 }
1921 else {
1922 /* compressed format, shared exponent format, etc. */
1923 switch (format) {
1924 case PIPE_FORMAT_DXT1_RGB:
1925 case PIPE_FORMAT_DXT1_RGBA:
1926 case PIPE_FORMAT_DXT3_RGBA:
1927 case PIPE_FORMAT_DXT5_RGBA:
1928 case PIPE_FORMAT_DXT1_SRGB:
1929 case PIPE_FORMAT_DXT1_SRGBA:
1930 case PIPE_FORMAT_DXT3_SRGBA:
1931 case PIPE_FORMAT_DXT5_SRGBA:
1932 case PIPE_FORMAT_RGTC1_UNORM:
1933 case PIPE_FORMAT_RGTC2_UNORM:
1934 case PIPE_FORMAT_LATC1_UNORM:
1935 case PIPE_FORMAT_LATC2_UNORM:
1936 case PIPE_FORMAT_ETC1_RGB8:
1937 t = TGSI_RETURN_TYPE_UNORM;
1938 break;
1939 case PIPE_FORMAT_RGTC1_SNORM:
1940 case PIPE_FORMAT_RGTC2_SNORM:
1941 case PIPE_FORMAT_LATC1_SNORM:
1942 case PIPE_FORMAT_LATC2_SNORM:
1943 case PIPE_FORMAT_R10G10B10X2_SNORM:
1944 t = TGSI_RETURN_TYPE_SNORM;
1945 break;
1946 case PIPE_FORMAT_R11G11B10_FLOAT:
1947 case PIPE_FORMAT_R9G9B9E5_FLOAT:
1948 t = TGSI_RETURN_TYPE_FLOAT;
1949 break;
1950 default:
1951 assert(!"Unexpected channel type in svga_get_texture_datatype()");
1952 t = TGSI_RETURN_TYPE_FLOAT;
1953 }
1954 }
1955
1956 return t;
1957 }
1958
1959
1960 /**
1961 * Given an svga context, return true iff there are currently any integer color
1962 * buffers attached to the framebuffer.
1963 */
1964 boolean
1965 svga_has_any_integer_cbufs(const struct svga_context *svga)
1966 {
1967 unsigned i;
1968 for (i = 0; i < PIPE_MAX_COLOR_BUFS; ++i) {
1969 struct pipe_surface *cbuf = svga->curr.framebuffer.cbufs[i];
1970
1971 if (cbuf && util_format_is_pure_integer(cbuf->format)) {
1972 return TRUE;
1973 }
1974 }
1975 return FALSE;
1976 }
1977
1978
1979 /**
1980 * Given an SVGA format, return the corresponding typeless format.
1981 * If there is no typeless format, return the format unchanged.
1982 */
1983 SVGA3dSurfaceFormat
1984 svga_typeless_format(SVGA3dSurfaceFormat format)
1985 {
1986 switch (format) {
1987 case SVGA3D_R32G32B32A32_UINT:
1988 case SVGA3D_R32G32B32A32_SINT:
1989 case SVGA3D_R32G32B32A32_FLOAT:
1990 return SVGA3D_R32G32B32A32_TYPELESS;
1991 case SVGA3D_R32G32B32_FLOAT:
1992 case SVGA3D_R32G32B32_UINT:
1993 case SVGA3D_R32G32B32_SINT:
1994 return SVGA3D_R32G32B32_TYPELESS;
1995 case SVGA3D_R16G16B16A16_UINT:
1996 case SVGA3D_R16G16B16A16_UNORM:
1997 case SVGA3D_R16G16B16A16_SNORM:
1998 case SVGA3D_R16G16B16A16_SINT:
1999 case SVGA3D_R16G16B16A16_FLOAT:
2000 return SVGA3D_R16G16B16A16_TYPELESS;
2001 case SVGA3D_R32G32_UINT:
2002 case SVGA3D_R32G32_SINT:
2003 case SVGA3D_R32G32_FLOAT:
2004 return SVGA3D_R32G32_TYPELESS;
2005 case SVGA3D_D32_FLOAT_S8X24_UINT:
2006 case SVGA3D_X32_G8X24_UINT:
2007 case SVGA3D_R32G8X24_TYPELESS:
2008 return SVGA3D_R32G8X24_TYPELESS;
2009 case SVGA3D_R10G10B10A2_UINT:
2010 case SVGA3D_R10G10B10A2_UNORM:
2011 return SVGA3D_R10G10B10A2_TYPELESS;
2012 case SVGA3D_R8G8B8A8_UNORM:
2013 case SVGA3D_R8G8B8A8_SNORM:
2014 case SVGA3D_R8G8B8A8_UNORM_SRGB:
2015 case SVGA3D_R8G8B8A8_UINT:
2016 case SVGA3D_R8G8B8A8_SINT:
2017 case SVGA3D_R8G8B8A8_TYPELESS:
2018 return SVGA3D_R8G8B8A8_TYPELESS;
2019 case SVGA3D_R16G16_UINT:
2020 case SVGA3D_R16G16_SINT:
2021 case SVGA3D_R16G16_UNORM:
2022 case SVGA3D_R16G16_SNORM:
2023 case SVGA3D_R16G16_FLOAT:
2024 return SVGA3D_R16G16_TYPELESS;
2025 case SVGA3D_D32_FLOAT:
2026 case SVGA3D_R32_FLOAT:
2027 case SVGA3D_R32_UINT:
2028 case SVGA3D_R32_SINT:
2029 case SVGA3D_R32_TYPELESS:
2030 return SVGA3D_R32_TYPELESS;
2031 case SVGA3D_D24_UNORM_S8_UINT:
2032 case SVGA3D_R24G8_TYPELESS:
2033 return SVGA3D_R24G8_TYPELESS;
2034 case SVGA3D_X24_G8_UINT:
2035 return SVGA3D_R24_UNORM_X8;
2036 case SVGA3D_R8G8_UNORM:
2037 case SVGA3D_R8G8_SNORM:
2038 case SVGA3D_R8G8_UINT:
2039 case SVGA3D_R8G8_SINT:
2040 return SVGA3D_R8G8_TYPELESS;
2041 case SVGA3D_D16_UNORM:
2042 case SVGA3D_R16_UNORM:
2043 case SVGA3D_R16_UINT:
2044 case SVGA3D_R16_SNORM:
2045 case SVGA3D_R16_SINT:
2046 case SVGA3D_R16_FLOAT:
2047 case SVGA3D_R16_TYPELESS:
2048 return SVGA3D_R16_TYPELESS;
2049 case SVGA3D_R8_UNORM:
2050 case SVGA3D_R8_UINT:
2051 case SVGA3D_R8_SNORM:
2052 case SVGA3D_R8_SINT:
2053 return SVGA3D_R8_TYPELESS;
2054 case SVGA3D_B8G8R8A8_UNORM_SRGB:
2055 case SVGA3D_B8G8R8A8_UNORM:
2056 case SVGA3D_B8G8R8A8_TYPELESS:
2057 return SVGA3D_B8G8R8A8_TYPELESS;
2058 case SVGA3D_B8G8R8X8_UNORM_SRGB:
2059 case SVGA3D_B8G8R8X8_UNORM:
2060 case SVGA3D_B8G8R8X8_TYPELESS:
2061 return SVGA3D_B8G8R8X8_TYPELESS;
2062 case SVGA3D_BC1_UNORM:
2063 case SVGA3D_BC1_UNORM_SRGB:
2064 case SVGA3D_BC1_TYPELESS:
2065 return SVGA3D_BC1_TYPELESS;
2066 case SVGA3D_BC2_UNORM:
2067 case SVGA3D_BC2_UNORM_SRGB:
2068 case SVGA3D_BC2_TYPELESS:
2069 return SVGA3D_BC2_TYPELESS;
2070 case SVGA3D_BC3_UNORM:
2071 case SVGA3D_BC3_UNORM_SRGB:
2072 case SVGA3D_BC3_TYPELESS:
2073 return SVGA3D_BC3_TYPELESS;
2074 case SVGA3D_BC4_UNORM:
2075 case SVGA3D_BC4_SNORM:
2076 return SVGA3D_BC4_TYPELESS;
2077 case SVGA3D_BC5_UNORM:
2078 case SVGA3D_BC5_SNORM:
2079 return SVGA3D_BC5_TYPELESS;
2080
2081 /* Special cases (no corresponding _TYPELESS formats) */
2082 case SVGA3D_A8_UNORM:
2083 case SVGA3D_B5G5R5A1_UNORM:
2084 case SVGA3D_B5G6R5_UNORM:
2085 case SVGA3D_R11G11B10_FLOAT:
2086 case SVGA3D_R9G9B9E5_SHAREDEXP:
2087 return format;
2088 default:
2089 debug_printf("Unexpected format %s in %s\n",
2090 svga_format_name(format), __FUNCTION__);
2091 return format;
2092 }
2093 }
2094
2095
2096 /**
2097 * Given a surface format, return the corresponding format to use for
2098 * a texture sampler. In most cases, it's the format unchanged, but there
2099 * are some special cases.
2100 */
2101 SVGA3dSurfaceFormat
2102 svga_sampler_format(SVGA3dSurfaceFormat format)
2103 {
2104 switch (format) {
2105 case SVGA3D_D16_UNORM:
2106 return SVGA3D_R16_UNORM;
2107 case SVGA3D_D24_UNORM_S8_UINT:
2108 return SVGA3D_R24_UNORM_X8;
2109 case SVGA3D_D32_FLOAT:
2110 return SVGA3D_R32_FLOAT;
2111 case SVGA3D_D32_FLOAT_S8X24_UINT:
2112 return SVGA3D_R32_FLOAT_X8X24;
2113 default:
2114 return format;
2115 }
2116 }
2117
2118
2119 /**
2120 * Is the given format an uncompressed snorm format?
2121 */
2122 bool
2123 svga_format_is_uncompressed_snorm(SVGA3dSurfaceFormat format)
2124 {
2125 switch (format) {
2126 case SVGA3D_R8G8B8A8_SNORM:
2127 case SVGA3D_R8G8_SNORM:
2128 case SVGA3D_R8_SNORM:
2129 case SVGA3D_R16G16B16A16_SNORM:
2130 case SVGA3D_R16G16_SNORM:
2131 case SVGA3D_R16_SNORM:
2132 return true;
2133 default:
2134 return false;
2135 }
2136 }
2137
2138
2139 bool
2140 svga_format_is_typeless(SVGA3dSurfaceFormat format)
2141 {
2142 switch (format) {
2143 case SVGA3D_R32G32B32A32_TYPELESS:
2144 case SVGA3D_R32G32B32_TYPELESS:
2145 case SVGA3D_R16G16B16A16_TYPELESS:
2146 case SVGA3D_R32G32_TYPELESS:
2147 case SVGA3D_R32G8X24_TYPELESS:
2148 case SVGA3D_R10G10B10A2_TYPELESS:
2149 case SVGA3D_R8G8B8A8_TYPELESS:
2150 case SVGA3D_R16G16_TYPELESS:
2151 case SVGA3D_R32_TYPELESS:
2152 case SVGA3D_R24G8_TYPELESS:
2153 case SVGA3D_R8G8_TYPELESS:
2154 case SVGA3D_R16_TYPELESS:
2155 case SVGA3D_R8_TYPELESS:
2156 case SVGA3D_BC1_TYPELESS:
2157 case SVGA3D_BC2_TYPELESS:
2158 case SVGA3D_BC3_TYPELESS:
2159 case SVGA3D_BC4_TYPELESS:
2160 case SVGA3D_BC5_TYPELESS:
2161 case SVGA3D_B8G8R8A8_TYPELESS:
2162 case SVGA3D_B8G8R8X8_TYPELESS:
2163 return true;
2164 default:
2165 return false;
2166 }
2167 }
2168
2169
2170 /**
2171 * \brief Can we import a surface with a given SVGA3D format as a texture?
2172 *
2173 * \param ss[in] pointer to the svga screen.
2174 * \param pformat[in] pipe format of the local texture.
2175 * \param sformat[in] svga3d format of the imported surface.
2176 * \param bind[in] bind flags of the imported texture.
2177 * \param verbose[in] Print out incompatibilities in debug mode.
2178 */
2179 bool
2180 svga_format_is_shareable(const struct svga_screen *ss,
2181 enum pipe_format pformat,
2182 SVGA3dSurfaceFormat sformat,
2183 unsigned bind,
2184 bool verbose)
2185 {
2186 SVGA3dSurfaceFormat default_format =
2187 svga_translate_format(ss, pformat, bind);
2188 int i;
2189
2190 if (default_format == SVGA3D_FORMAT_INVALID)
2191 return false;
2192 if (default_format == sformat)
2193 return true;
2194
2195 for (i = 0; i < ARRAY_SIZE(format_compats); ++i) {
2196 if (format_compats[i].pformat == pformat) {
2197 const SVGA3dSurfaceFormat *compat_format =
2198 format_compats[i].compat_format;
2199 while (*compat_format != 0) {
2200 if (*compat_format == sformat)
2201 return true;
2202 compat_format++;
2203 }
2204 }
2205 }
2206
2207 if (verbose) {
2208 debug_printf("Incompatible imported surface format.\n");
2209 debug_printf("Texture format: \"%s\". Imported format: \"%s\".\n",
2210 svga_format_name(default_format),
2211 svga_format_name(sformat));
2212 }
2213
2214 return false;
2215 }
2216
2217
2218 /**
2219 * Return the sRGB format which corresponds to the given (linear) format.
2220 * If there's no such sRGB format, return the format as-is.
2221 */
2222 SVGA3dSurfaceFormat
2223 svga_linear_to_srgb(SVGA3dSurfaceFormat format)
2224 {
2225 switch (format) {
2226 case SVGA3D_R8G8B8A8_UNORM:
2227 return SVGA3D_R8G8B8A8_UNORM_SRGB;
2228 case SVGA3D_BC1_UNORM:
2229 return SVGA3D_BC1_UNORM_SRGB;
2230 case SVGA3D_BC2_UNORM:
2231 return SVGA3D_BC2_UNORM_SRGB;
2232 case SVGA3D_BC3_UNORM:
2233 return SVGA3D_BC3_UNORM_SRGB;
2234 case SVGA3D_B8G8R8A8_UNORM:
2235 return SVGA3D_B8G8R8A8_UNORM_SRGB;
2236 case SVGA3D_B8G8R8X8_UNORM:
2237 return SVGA3D_B8G8R8X8_UNORM_SRGB;
2238 default:
2239 return format;
2240 }
2241 }
2242
2243
2244 /**
2245 * Implement pipe_screen::is_format_supported().
2246 * \param bindings bitmask of PIPE_BIND_x flags
2247 */
2248 boolean
2249 svga_is_format_supported(struct pipe_screen *screen,
2250 enum pipe_format format,
2251 enum pipe_texture_target target,
2252 unsigned sample_count,
2253 unsigned storage_sample_count,
2254 unsigned bindings)
2255 {
2256 struct svga_screen *ss = svga_screen(screen);
2257 SVGA3dSurfaceFormat svga_format;
2258 SVGA3dSurfaceFormatCaps caps;
2259 SVGA3dSurfaceFormatCaps mask;
2260
2261 assert(bindings);
2262 assert(!ss->sws->have_vgpu10);
2263
2264 /* Multisamples is not supported in VGPU9 device */
2265 if (sample_count > 1)
2266 return FALSE;
2267
2268 svga_format = svga_translate_format(ss, format, bindings);
2269 if (svga_format == SVGA3D_FORMAT_INVALID) {
2270 return FALSE;
2271 }
2272
2273 if (util_format_is_srgb(format) &&
2274 (bindings & PIPE_BIND_DISPLAY_TARGET)) {
2275 /* We only support sRGB rendering with vgpu10 */
2276 return FALSE;
2277 }
2278
2279 /*
2280 * Override host capabilities, so that we end up with the same
2281 * visuals for all virtual hardware implementations.
2282 */
2283 if (bindings & PIPE_BIND_DISPLAY_TARGET) {
2284 switch (svga_format) {
2285 case SVGA3D_A8R8G8B8:
2286 case SVGA3D_X8R8G8B8:
2287 case SVGA3D_R5G6B5:
2288 break;
2289
2290 /* VGPU10 formats */
2291 case SVGA3D_B8G8R8A8_UNORM:
2292 case SVGA3D_B8G8R8X8_UNORM:
2293 case SVGA3D_B5G6R5_UNORM:
2294 case SVGA3D_B8G8R8X8_UNORM_SRGB:
2295 case SVGA3D_B8G8R8A8_UNORM_SRGB:
2296 case SVGA3D_R8G8B8A8_UNORM_SRGB:
2297 break;
2298
2299 /* Often unsupported/problematic. This means we end up with the same
2300 * visuals for all virtual hardware implementations.
2301 */
2302 case SVGA3D_A4R4G4B4:
2303 case SVGA3D_A1R5G5B5:
2304 return FALSE;
2305
2306 default:
2307 return FALSE;
2308 }
2309 }
2310
2311 /*
2312 * Query the host capabilities.
2313 */
2314 svga_get_format_cap(ss, svga_format, &caps);
2315
2316 if (bindings & PIPE_BIND_RENDER_TARGET) {
2317 /* Check that the color surface is blendable, unless it's an
2318 * integer format.
2319 */
2320 if (!svga_format_is_integer(svga_format) &&
2321 (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
2322 return FALSE;
2323 }
2324 }
2325
2326 mask.value = 0;
2327 if (bindings & PIPE_BIND_RENDER_TARGET)
2328 mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
2329
2330 if (bindings & PIPE_BIND_DEPTH_STENCIL)
2331 mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
2332
2333 if (bindings & PIPE_BIND_SAMPLER_VIEW)
2334 mask.value |= SVGA3DFORMAT_OP_TEXTURE;
2335
2336 if (target == PIPE_TEXTURE_CUBE)
2337 mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
2338 else if (target == PIPE_TEXTURE_3D)
2339 mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
2340
2341 return (caps.value & mask.value) == mask.value;
2342 }
2343
2344
2345 /**
2346 * Implement pipe_screen::is_format_supported() for VGPU10 device.
2347 * \param bindings bitmask of PIPE_BIND_x flags
2348 */
2349 boolean
2350 svga_is_dx_format_supported(struct pipe_screen *screen,
2351 enum pipe_format format,
2352 enum pipe_texture_target target,
2353 unsigned sample_count,
2354 unsigned storage_sample_count,
2355 unsigned bindings)
2356 {
2357 struct svga_screen *ss = svga_screen(screen);
2358 SVGA3dSurfaceFormat svga_format;
2359 SVGA3dDevCapResult caps;
2360 unsigned int mask = 0;
2361
2362 assert(bindings);
2363 assert(ss->sws->have_vgpu10);
2364
2365 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
2366 return false;
2367
2368 if (sample_count > 1) {
2369 /* In ms_samples, if bit N is set it means that we support
2370 * multisample with N+1 samples per pixel.
2371 */
2372 if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
2373 return FALSE;
2374 }
2375 mask |= SVGA3D_DXFMT_MULTISAMPLE;
2376 }
2377
2378 /*
2379 * For VGPU10 vertex formats, skip querying host capabilities
2380 */
2381
2382 if (bindings & PIPE_BIND_VERTEX_BUFFER) {
2383 SVGA3dSurfaceFormat svga_format;
2384 unsigned flags;
2385 svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
2386 return svga_format != SVGA3D_FORMAT_INVALID;
2387 }
2388
2389 svga_format = svga_translate_format(ss, format, bindings);
2390 if (svga_format == SVGA3D_FORMAT_INVALID) {
2391 return FALSE;
2392 }
2393
2394 /*
2395 * Override host capabilities, so that we end up with the same
2396 * visuals for all virtual hardware implementations.
2397 */
2398 if (bindings & PIPE_BIND_DISPLAY_TARGET) {
2399 switch (svga_format) {
2400 case SVGA3D_A8R8G8B8:
2401 case SVGA3D_X8R8G8B8:
2402 case SVGA3D_R5G6B5:
2403 break;
2404
2405 /* VGPU10 formats */
2406 case SVGA3D_B8G8R8A8_UNORM:
2407 case SVGA3D_B8G8R8X8_UNORM:
2408 case SVGA3D_B5G6R5_UNORM:
2409 case SVGA3D_B8G8R8X8_UNORM_SRGB:
2410 case SVGA3D_B8G8R8A8_UNORM_SRGB:
2411 case SVGA3D_R8G8B8A8_UNORM_SRGB:
2412 break;
2413
2414 /* Often unsupported/problematic. This means we end up with the same
2415 * visuals for all virtual hardware implementations.
2416 */
2417 case SVGA3D_A4R4G4B4:
2418 case SVGA3D_A1R5G5B5:
2419 return FALSE;
2420
2421 default:
2422 return FALSE;
2423 }
2424 }
2425
2426 /*
2427 * Query the host capabilities.
2428 */
2429 svga_get_dx_format_cap(ss, svga_format, &caps);
2430
2431 if (bindings & PIPE_BIND_RENDER_TARGET) {
2432 /* Check that the color surface is blendable, unless it's an
2433 * integer format.
2434 */
2435 if (!(svga_format_is_integer(svga_format) ||
2436 (caps.u & SVGA3D_DXFMT_BLENDABLE))) {
2437 return FALSE;
2438 }
2439 mask |= SVGA3D_DXFMT_COLOR_RENDERTARGET;
2440 }
2441
2442 if (bindings & PIPE_BIND_DEPTH_STENCIL)
2443 mask |= SVGA3D_DXFMT_DEPTH_RENDERTARGET;
2444
2445 if (target == PIPE_TEXTURE_3D)
2446 mask |= SVGA3D_DXFMT_VOLUME;
2447
2448 /* Is the format supported for rendering */
2449 if ((caps.u & mask) != mask)
2450 return FALSE;
2451
2452 if (bindings & PIPE_BIND_SAMPLER_VIEW) {
2453 SVGA3dSurfaceFormat sampler_format;
2454
2455 /* Get the sampler view format */
2456 sampler_format = svga_sampler_format(svga_format);
2457 if (sampler_format != svga_format) {
2458 caps.u = 0;
2459 svga_get_dx_format_cap(ss, sampler_format, &caps);
2460 mask &= (SVGA3D_DXFMT_VOLUME | SVGA3D_DXFMT_MULTISAMPLE);
2461 mask |= SVGA3D_DXFMT_SHADER_SAMPLE;
2462 if ((caps.u & mask) != mask)
2463 return FALSE;
2464 }
2465 }
2466
2467 return TRUE;
2468 }