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svga: add new gallium formats to the format conversion table
[mesa.git] / src / gallium / drivers / svga / svga_format.c
1 /**********************************************************
2 * Copyright 2011 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26
27 #include "pipe/p_format.h"
28 #include "util/u_debug.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31
32 #include "svga_winsys.h"
33 #include "svga_screen.h"
34 #include "svga_format.h"
35
36
37 /** Describes mapping from gallium formats to SVGA vertex/pixel formats */
38 struct vgpu10_format_entry
39 {
40 enum pipe_format pformat;
41 SVGA3dSurfaceFormat vertex_format;
42 SVGA3dSurfaceFormat pixel_format;
43 SVGA3dSurfaceFormat view_format; /* view format for texture buffer */
44 unsigned flags;
45 };
46
47 struct format_compat_entry
48 {
49 enum pipe_format pformat;
50 const SVGA3dSurfaceFormat *compat_format;
51 };
52
53
54 /**
55 * Table mapping Gallium formats to SVGA3d vertex/pixel formats.
56 * Note: the table is ordered according to PIPE_FORMAT_x order.
57 */
58 static const struct vgpu10_format_entry format_conversion_table[] =
59 {
60 /* Gallium format SVGA3D vertex format SVGA3D pixel format SVGA3D texbuf view format Flags */
61 { PIPE_FORMAT_NONE, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
62 { PIPE_FORMAT_B8G8R8A8_UNORM, SVGA3D_B8G8R8A8_UNORM, SVGA3D_B8G8R8A8_UNORM, SVGA3D_B8G8R8A8_UNORM, TF_GEN_MIPS },
63 { PIPE_FORMAT_B8G8R8X8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8X8_UNORM, SVGA3D_B8G8R8X8_UNORM, TF_GEN_MIPS },
64 { PIPE_FORMAT_A8R8G8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
65 { PIPE_FORMAT_X8R8G8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
66 { PIPE_FORMAT_B5G5R5A1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_B5G5R5A1_UNORM, SVGA3D_B5G5R5A1_UNORM, TF_GEN_MIPS },
67 { PIPE_FORMAT_B4G4R4A4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
68 { PIPE_FORMAT_B5G6R5_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_B5G6R5_UNORM, SVGA3D_B5G6R5_UNORM, TF_GEN_MIPS },
69 { PIPE_FORMAT_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, TF_GEN_MIPS },
70 { PIPE_FORMAT_L8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UNORM, TF_XXX1 },
71 { PIPE_FORMAT_A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_A8_UNORM, SVGA3D_R8_UNORM, TF_GEN_MIPS | TF_000X},
72 { PIPE_FORMAT_I8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UNORM, TF_XXXX },
73 { PIPE_FORMAT_L8A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8G8_UNORM, TF_XXXY },
74 { PIPE_FORMAT_L16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UNORM, TF_XXX1 },
75 { PIPE_FORMAT_UYVY, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
76 { PIPE_FORMAT_YUYV, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
77 { PIPE_FORMAT_Z16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_D16_UNORM, SVGA3D_D16_UNORM, 0 },
78 { PIPE_FORMAT_Z32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
79 { PIPE_FORMAT_Z32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_D32_FLOAT, SVGA3D_D32_FLOAT, 0 },
80 { PIPE_FORMAT_Z24_UNORM_S8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_D24_UNORM_S8_UINT, SVGA3D_D24_UNORM_S8_UINT, 0 },
81 { PIPE_FORMAT_S8_UINT_Z24_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
82 { PIPE_FORMAT_Z24X8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_D24_UNORM_S8_UINT, SVGA3D_D24_UNORM_S8_UINT, 0 },
83 { PIPE_FORMAT_X8Z24_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
84 { PIPE_FORMAT_S8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
85 { PIPE_FORMAT_R64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
86 { PIPE_FORMAT_R64G64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
87 { PIPE_FORMAT_R64G64B64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
88 { PIPE_FORMAT_R64G64B64A64_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
89 { PIPE_FORMAT_R32_FLOAT, SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, TF_GEN_MIPS },
90 { PIPE_FORMAT_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, TF_GEN_MIPS },
91 { PIPE_FORMAT_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, TF_GEN_MIPS },
92 { PIPE_FORMAT_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, TF_GEN_MIPS },
93 { PIPE_FORMAT_R32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
94 { PIPE_FORMAT_R32G32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
95 { PIPE_FORMAT_R32G32B32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
96 { PIPE_FORMAT_R32G32B32A32_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
97 { PIPE_FORMAT_R32_USCALED, SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
98 { PIPE_FORMAT_R32G32_USCALED, SVGA3D_R32G32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
99 { PIPE_FORMAT_R32G32B32_USCALED, SVGA3D_R32G32B32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
100 { PIPE_FORMAT_R32G32B32A32_USCALED, SVGA3D_R32G32B32A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
101 { PIPE_FORMAT_R32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
102 { PIPE_FORMAT_R32G32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
103 { PIPE_FORMAT_R32G32B32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
104 { PIPE_FORMAT_R32G32B32A32_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
105 { PIPE_FORMAT_R32_SSCALED, SVGA3D_R32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
106 { PIPE_FORMAT_R32G32_SSCALED, SVGA3D_R32G32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
107 { PIPE_FORMAT_R32G32B32_SSCALED, SVGA3D_R32G32B32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
108 { PIPE_FORMAT_R32G32B32A32_SSCALED, SVGA3D_R32G32B32A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
109 { PIPE_FORMAT_R16_UNORM, SVGA3D_R16_UNORM, SVGA3D_R16_UNORM, SVGA3D_R16_UNORM, TF_GEN_MIPS },
110 { PIPE_FORMAT_R16G16_UNORM, SVGA3D_R16G16_UNORM, SVGA3D_R16G16_UNORM, SVGA3D_R16G16_UNORM, TF_GEN_MIPS },
111 { PIPE_FORMAT_R16G16B16_UNORM, SVGA3D_R16G16B16A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
112 { PIPE_FORMAT_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, TF_GEN_MIPS },
113 { PIPE_FORMAT_R16_USCALED, SVGA3D_R16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
114 { PIPE_FORMAT_R16G16_USCALED, SVGA3D_R16G16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
115 { PIPE_FORMAT_R16G16B16_USCALED, SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_U_TO_F_CAST },
116 { PIPE_FORMAT_R16G16B16A16_USCALED, SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
117 { PIPE_FORMAT_R16_SNORM, SVGA3D_R16_SNORM, SVGA3D_R16_SNORM, SVGA3D_R16_SNORM, 0 },
118 { PIPE_FORMAT_R16G16_SNORM, SVGA3D_R16G16_SNORM, SVGA3D_R16G16_SNORM, SVGA3D_R16G16_SNORM, 0 },
119 { PIPE_FORMAT_R16G16B16_SNORM, SVGA3D_R16G16B16A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
120 { PIPE_FORMAT_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, 0 },
121 { PIPE_FORMAT_R16_SSCALED, SVGA3D_R16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
122 { PIPE_FORMAT_R16G16_SSCALED, SVGA3D_R16G16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
123 { PIPE_FORMAT_R16G16B16_SSCALED, SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_I_TO_F_CAST },
124 { PIPE_FORMAT_R16G16B16A16_SSCALED, SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
125 { PIPE_FORMAT_R8_UNORM, SVGA3D_R8_UNORM, SVGA3D_R8_UNORM, SVGA3D_R8_UNORM, TF_GEN_MIPS },
126 { PIPE_FORMAT_R8G8_UNORM, SVGA3D_R8G8_UNORM, SVGA3D_R8G8_UNORM, SVGA3D_R8G8_UNORM, TF_GEN_MIPS },
127 { PIPE_FORMAT_R8G8B8_UNORM, SVGA3D_R8G8B8A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
128 { PIPE_FORMAT_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, TF_GEN_MIPS },
129 { PIPE_FORMAT_X8B8G8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
130 { PIPE_FORMAT_R8_USCALED, SVGA3D_R8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
131 { PIPE_FORMAT_R8G8_USCALED, SVGA3D_R8G8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
132 { PIPE_FORMAT_R8G8B8_USCALED, SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_U_TO_F_CAST },
133 { PIPE_FORMAT_R8G8B8A8_USCALED, SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
134 { 73, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
135 { PIPE_FORMAT_R8_SNORM, SVGA3D_R8_SNORM, SVGA3D_R8_SNORM, SVGA3D_R8_SNORM, 0 },
136 { PIPE_FORMAT_R8G8_SNORM, SVGA3D_R8G8_SNORM, SVGA3D_R8G8_SNORM, SVGA3D_R8G8_SNORM, 0 },
137 { PIPE_FORMAT_R8G8B8_SNORM, SVGA3D_R8G8B8A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
138 { PIPE_FORMAT_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, 0 },
139 { 78, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
140 { 79, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
141 { 80, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
142 { 81, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
143 { PIPE_FORMAT_R8_SSCALED, SVGA3D_R8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
144 { PIPE_FORMAT_R8G8_SSCALED, SVGA3D_R8G8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
145 { PIPE_FORMAT_R8G8B8_SSCALED, SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_I_TO_F_CAST },
146 { PIPE_FORMAT_R8G8B8A8_SSCALED, SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
147 { 86, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
148 { PIPE_FORMAT_R32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
149 { PIPE_FORMAT_R32G32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
150 { PIPE_FORMAT_R32G32B32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
151 { PIPE_FORMAT_R32G32B32A32_FIXED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
152 { PIPE_FORMAT_R16_FLOAT, SVGA3D_R16_FLOAT, SVGA3D_R16_FLOAT, SVGA3D_R16_FLOAT, TF_GEN_MIPS },
153 { PIPE_FORMAT_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, TF_GEN_MIPS },
154 { PIPE_FORMAT_R16G16B16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
155 { PIPE_FORMAT_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, TF_GEN_MIPS },
156 { PIPE_FORMAT_L8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
157 { PIPE_FORMAT_L8A8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
158 { PIPE_FORMAT_R8G8B8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
159 { PIPE_FORMAT_A8B8G8R8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
160 { PIPE_FORMAT_X8B8G8R8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
161 { PIPE_FORMAT_B8G8R8A8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8A8_UNORM_SRGB, SVGA3D_FORMAT_INVALID, TF_GEN_MIPS },
162 { PIPE_FORMAT_B8G8R8X8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8X8_UNORM_SRGB, SVGA3D_FORMAT_INVALID, TF_GEN_MIPS },
163 { PIPE_FORMAT_A8R8G8B8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
164 { PIPE_FORMAT_X8R8G8B8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
165 { PIPE_FORMAT_R8G8B8A8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_R8G8B8A8_UNORM_SRGB, SVGA3D_FORMAT_INVALID, TF_GEN_MIPS },
166 { PIPE_FORMAT_DXT1_RGB, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM, SVGA3D_FORMAT_INVALID, 0 },
167 { PIPE_FORMAT_DXT1_RGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM, SVGA3D_FORMAT_INVALID, 0 },
168 { PIPE_FORMAT_DXT3_RGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC2_UNORM, SVGA3D_FORMAT_INVALID, 0 },
169 { PIPE_FORMAT_DXT5_RGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC3_UNORM, SVGA3D_FORMAT_INVALID, 0 },
170 { PIPE_FORMAT_DXT1_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM_SRGB, SVGA3D_FORMAT_INVALID, 0 },
171 { PIPE_FORMAT_DXT1_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM_SRGB, SVGA3D_FORMAT_INVALID, 0 },
172 { PIPE_FORMAT_DXT3_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC2_UNORM_SRGB, SVGA3D_FORMAT_INVALID, 0 },
173 { PIPE_FORMAT_DXT5_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_BC3_UNORM_SRGB, SVGA3D_FORMAT_INVALID, 0 },
174 { PIPE_FORMAT_RGTC1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC4_UNORM, SVGA3D_FORMAT_INVALID, 0 },
175 { PIPE_FORMAT_RGTC1_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC4_SNORM, SVGA3D_FORMAT_INVALID, 0 },
176 { PIPE_FORMAT_RGTC2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC5_UNORM, SVGA3D_FORMAT_INVALID, 0 },
177 { PIPE_FORMAT_RGTC2_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_BC5_SNORM, SVGA3D_FORMAT_INVALID, 0 },
178 { PIPE_FORMAT_R8G8_B8G8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
179 { PIPE_FORMAT_G8R8_G8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
180 { PIPE_FORMAT_R8SG8SB8UX8U_NORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
181 { PIPE_FORMAT_R5SG5SB6U_NORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
182 { PIPE_FORMAT_A8B8G8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
183 { PIPE_FORMAT_B5G5R5X1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
184 { PIPE_FORMAT_R10G10B10A2_USCALED, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_USCALED },
185 { PIPE_FORMAT_R11G11B10_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_R11G11B10_FLOAT, SVGA3D_R11G11B10_FLOAT, TF_GEN_MIPS },
186 { PIPE_FORMAT_R9G9B9E5_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_R9G9B9E5_SHAREDEXP, SVGA3D_FORMAT_INVALID, 0 },
187 { PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_D32_FLOAT_S8X24_UINT, SVGA3D_FORMAT_INVALID, 0 },
188 { PIPE_FORMAT_R1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
189 { PIPE_FORMAT_R10G10B10X2_USCALED, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
190 { PIPE_FORMAT_R10G10B10X2_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
191 { PIPE_FORMAT_L4A4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
192 { PIPE_FORMAT_B10G10R10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA },
193 { PIPE_FORMAT_R10SG10SB10SA2U_NORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
194 { PIPE_FORMAT_R8G8Bx_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
195 { PIPE_FORMAT_R8G8B8X8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
196 { PIPE_FORMAT_B4G4R4X4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
197 { PIPE_FORMAT_X24S8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
198 { PIPE_FORMAT_S8X24_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
199 { PIPE_FORMAT_X32_S8X24_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
200 { PIPE_FORMAT_B2G3R3_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
201 { PIPE_FORMAT_L16A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16G16_UNORM, TF_XXXY },
202 { PIPE_FORMAT_A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UNORM, TF_000X },
203 { PIPE_FORMAT_I16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UNORM, TF_XXXX },
204 { PIPE_FORMAT_LATC1_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
205 { PIPE_FORMAT_LATC1_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
206 { PIPE_FORMAT_LATC2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
207 { PIPE_FORMAT_LATC2_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
208 { PIPE_FORMAT_A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
209 { PIPE_FORMAT_L8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
210 { PIPE_FORMAT_L8A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
211 { PIPE_FORMAT_I8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
212 { PIPE_FORMAT_A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
213 { PIPE_FORMAT_L16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
214 { PIPE_FORMAT_L16A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
215 { PIPE_FORMAT_I16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
216 { PIPE_FORMAT_A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_FLOAT, TF_000X },
217 { PIPE_FORMAT_L16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_FLOAT, TF_XXX1 },
218 { PIPE_FORMAT_L16A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16G16_FLOAT, TF_XXXY },
219 { PIPE_FORMAT_I16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_FLOAT, TF_XXXX },
220 { PIPE_FORMAT_A32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_FLOAT, TF_000X },
221 { PIPE_FORMAT_L32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_FLOAT, TF_XXX1 },
222 { PIPE_FORMAT_L32A32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32G32_FLOAT, TF_XXXY },
223 { PIPE_FORMAT_I32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_FLOAT, TF_XXXX },
224 { PIPE_FORMAT_YV12, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
225 { PIPE_FORMAT_YV16, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
226 { PIPE_FORMAT_IYUV, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
227 { PIPE_FORMAT_NV12, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
228 { PIPE_FORMAT_NV21, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
229 { PIPE_FORMAT_A4R4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
230 { PIPE_FORMAT_R4A4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
231 { PIPE_FORMAT_R8A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
232 { PIPE_FORMAT_A8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
233 { PIPE_FORMAT_R10G10B10A2_SSCALED, SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_SSCALED },
234 { PIPE_FORMAT_R10G10B10A2_SNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_SNORM },
235 { PIPE_FORMAT_B10G10R10A2_USCALED, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_USCALED },
236 { PIPE_FORMAT_B10G10R10A2_SSCALED, SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_SSCALED },
237 { PIPE_FORMAT_B10G10R10A2_SNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_SNORM },
238 { PIPE_FORMAT_R8_UINT, SVGA3D_R8_UINT, SVGA3D_R8_UINT, SVGA3D_R8_UINT, 0 },
239 { PIPE_FORMAT_R8G8_UINT, SVGA3D_R8G8_UINT, SVGA3D_R8G8_UINT, SVGA3D_R8G8_UINT, 0 },
240 { PIPE_FORMAT_R8G8B8_UINT, SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
241 { PIPE_FORMAT_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, 0 },
242 { PIPE_FORMAT_R8_SINT, SVGA3D_R8_SINT, SVGA3D_R8_SINT, SVGA3D_R8_SINT, 0 },
243 { PIPE_FORMAT_R8G8_SINT, SVGA3D_R8G8_SINT, SVGA3D_R8G8_SINT, SVGA3D_R8G8_SINT, 0 },
244 { PIPE_FORMAT_R8G8B8_SINT, SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
245 { PIPE_FORMAT_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, 0 },
246 { PIPE_FORMAT_R16_UINT, SVGA3D_R16_UINT, SVGA3D_R16_UINT, SVGA3D_R16_UINT, 0 },
247 { PIPE_FORMAT_R16G16_UINT, SVGA3D_R16G16_UINT, SVGA3D_R16G16_UINT, SVGA3D_R16G16_UINT, 0 },
248 { PIPE_FORMAT_R16G16B16_UINT, SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
249 { PIPE_FORMAT_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, 0 },
250 { PIPE_FORMAT_R16_SINT, SVGA3D_R16_SINT, SVGA3D_R16_SINT, SVGA3D_R16_SINT, 0 },
251 { PIPE_FORMAT_R16G16_SINT, SVGA3D_R16G16_SINT, SVGA3D_R16G16_SINT, SVGA3D_R16G16_SINT, 0 },
252 { PIPE_FORMAT_R16G16B16_SINT, SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
253 { PIPE_FORMAT_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, 0 },
254 { PIPE_FORMAT_R32_UINT, SVGA3D_R32_UINT, SVGA3D_R32_UINT, SVGA3D_R32_UINT, 0 },
255 { PIPE_FORMAT_R32G32_UINT, SVGA3D_R32G32_UINT, SVGA3D_R32G32_UINT, SVGA3D_R32G32_UINT, 0 },
256 { PIPE_FORMAT_R32G32B32_UINT, SVGA3D_R32G32B32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
257 { PIPE_FORMAT_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, 0 },
258 { PIPE_FORMAT_R32_SINT, SVGA3D_R32_SINT, SVGA3D_R32_SINT, SVGA3D_R32_SINT, 0 },
259 { PIPE_FORMAT_R32G32_SINT, SVGA3D_R32G32_SINT, SVGA3D_R32G32_SINT, SVGA3D_R32G32_SINT, 0 },
260 { PIPE_FORMAT_R32G32B32_SINT, SVGA3D_R32G32B32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
261 { PIPE_FORMAT_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, 0 },
262 { PIPE_FORMAT_A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UINT, TF_000X },
263 { PIPE_FORMAT_I8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UINT, TF_XXXX },
264 { PIPE_FORMAT_L8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UINT, TF_XXX1 },
265 { PIPE_FORMAT_L8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8G8_UINT, TF_XXXY },
266 { PIPE_FORMAT_A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_SINT, TF_000X },
267 { PIPE_FORMAT_I8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_SINT, TF_XXXX },
268 { PIPE_FORMAT_L8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_SINT, TF_XXX1 },
269 { PIPE_FORMAT_L8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8G8_SINT, TF_XXXY },
270 { PIPE_FORMAT_A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UINT, TF_000X },
271 { PIPE_FORMAT_I16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UINT, TF_XXXX },
272 { PIPE_FORMAT_L16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UINT, TF_XXX1 },
273 { PIPE_FORMAT_L16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16G16_UINT, TF_XXXY },
274 { PIPE_FORMAT_A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_SINT, TF_000X },
275 { PIPE_FORMAT_I16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_SINT, TF_XXXX },
276 { PIPE_FORMAT_L16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_SINT, TF_XXX1 },
277 { PIPE_FORMAT_L16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16G16_SINT, TF_XXXY },
278 { PIPE_FORMAT_A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_UINT, TF_000X },
279 { PIPE_FORMAT_I32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_UINT, TF_XXXX },
280 { PIPE_FORMAT_L32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_UINT, TF_XXX1 },
281 { PIPE_FORMAT_L32A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32G32_UINT, TF_XXXY },
282 { PIPE_FORMAT_A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_SINT, TF_000X },
283 { PIPE_FORMAT_I32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_SINT, TF_XXXX },
284 { PIPE_FORMAT_L32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_SINT, TF_XXX1 },
285 { PIPE_FORMAT_L32A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32G32_SINT, TF_XXXY },
286 { PIPE_FORMAT_B10G10R10A2_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
287 { PIPE_FORMAT_ETC1_RGB8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
288 { PIPE_FORMAT_R8G8_R8B8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
289 { PIPE_FORMAT_G8R8_B8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
290 { PIPE_FORMAT_R8G8B8X8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
291 { PIPE_FORMAT_R8G8B8X8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
292 { PIPE_FORMAT_R8G8B8X8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
293 { PIPE_FORMAT_R8G8B8X8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
294 { PIPE_FORMAT_B10G10R10X2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
295 { PIPE_FORMAT_R16G16B16X16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
296 { PIPE_FORMAT_R16G16B16X16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
297 { PIPE_FORMAT_R16G16B16X16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
298 { PIPE_FORMAT_R16G16B16X16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
299 { PIPE_FORMAT_R16G16B16X16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
300 { PIPE_FORMAT_R32G32B32X32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
301 { PIPE_FORMAT_R32G32B32X32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
302 { PIPE_FORMAT_R32G32B32X32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
303 { PIPE_FORMAT_R8A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
304 { PIPE_FORMAT_R16A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
305 { PIPE_FORMAT_R16A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
306 { PIPE_FORMAT_R16A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
307 { PIPE_FORMAT_R32A32_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
308 { PIPE_FORMAT_R8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
309 { PIPE_FORMAT_R8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
310 { PIPE_FORMAT_R16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
311 { PIPE_FORMAT_R16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
312 { PIPE_FORMAT_R32A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
313 { PIPE_FORMAT_R32A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
314 { PIPE_FORMAT_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, 0 },
315 { PIPE_FORMAT_B5G6R5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
316 { PIPE_FORMAT_BPTC_RGBA_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
317 { PIPE_FORMAT_BPTC_SRGBA, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
318 { PIPE_FORMAT_BPTC_RGB_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
319 { PIPE_FORMAT_BPTC_RGB_UFLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
320 { PIPE_FORMAT_A8L8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
321 { PIPE_FORMAT_A8L8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
322 { PIPE_FORMAT_A8L8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
323 { PIPE_FORMAT_A16L16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
324 { PIPE_FORMAT_G8R8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
325 { PIPE_FORMAT_G8R8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
326 { PIPE_FORMAT_G16R16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
327 { PIPE_FORMAT_G16R16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
328 { PIPE_FORMAT_A8B8G8R8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
329 { PIPE_FORMAT_X8B8G8R8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
330 { PIPE_FORMAT_ETC2_RGB8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
331 { PIPE_FORMAT_ETC2_SRGB8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
332 { PIPE_FORMAT_ETC2_RGB8A1, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
333 { PIPE_FORMAT_ETC2_SRGB8A1, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
334 { PIPE_FORMAT_ETC2_RGBA8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
335 { PIPE_FORMAT_ETC2_SRGBA8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
336 { PIPE_FORMAT_ETC2_R11_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
337 { PIPE_FORMAT_ETC2_R11_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
338 { PIPE_FORMAT_ETC2_RG11_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
339 { PIPE_FORMAT_ETC2_RG11_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
340 { PIPE_FORMAT_ASTC_4x4, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
341 { PIPE_FORMAT_ASTC_5x4, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
342 { PIPE_FORMAT_ASTC_5x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
343 { PIPE_FORMAT_ASTC_6x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
344 { PIPE_FORMAT_ASTC_6x6, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
345 { PIPE_FORMAT_ASTC_8x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
346 { PIPE_FORMAT_ASTC_8x6, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
347 { PIPE_FORMAT_ASTC_8x8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
348 { PIPE_FORMAT_ASTC_10x5, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
349 { PIPE_FORMAT_ASTC_10x6, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
350 { PIPE_FORMAT_ASTC_10x8, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
351 { PIPE_FORMAT_ASTC_10x10, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
352 { PIPE_FORMAT_ASTC_12x10, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
353 { PIPE_FORMAT_ASTC_12x12, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
354 { PIPE_FORMAT_ASTC_4x4_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
355 { PIPE_FORMAT_ASTC_5x4_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
356 { PIPE_FORMAT_ASTC_5x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
357 { PIPE_FORMAT_ASTC_6x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
358 { PIPE_FORMAT_ASTC_6x6_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
359 { PIPE_FORMAT_ASTC_8x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
360 { PIPE_FORMAT_ASTC_8x6_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
361 { PIPE_FORMAT_ASTC_8x8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
362 { PIPE_FORMAT_ASTC_10x5_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
363 { PIPE_FORMAT_ASTC_10x6_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
364 { PIPE_FORMAT_ASTC_10x8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
365 { PIPE_FORMAT_ASTC_10x10_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
366 { PIPE_FORMAT_ASTC_12x10_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
367 { PIPE_FORMAT_ASTC_12x12_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
368 { PIPE_FORMAT_P016, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
369 { PIPE_FORMAT_R10G10B10X2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
370 { PIPE_FORMAT_A1B5G5R5_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
371 { PIPE_FORMAT_X1B5G5R5_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
372 { PIPE_FORMAT_A4B4G4R4_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
373 { PIPE_FORMAT_R8_SRGB, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
374 { PIPE_FORMAT_A8L8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
375 { PIPE_FORMAT_G8R8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
376 { PIPE_FORMAT_A8B8G8R8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
377 { PIPE_FORMAT_X8B8G8R8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
378 };
379
380
381 /**
382 * Translate a gallium vertex format to a vgpu10 vertex format.
383 * Also, return any special vertex format flags.
384 */
385 void
386 svga_translate_vertex_format_vgpu10(enum pipe_format format,
387 SVGA3dSurfaceFormat *svga_format,
388 unsigned *vf_flags)
389 {
390 assert(format < ARRAY_SIZE(format_conversion_table));
391 if (format >= ARRAY_SIZE(format_conversion_table)) {
392 format = PIPE_FORMAT_NONE;
393 }
394 *svga_format = format_conversion_table[format].vertex_format;
395 *vf_flags = format_conversion_table[format].flags;
396 }
397
398
399 /**
400 * Translate a gallium pixel format to a vgpu10 format
401 * to be used in a shader resource view for a texture buffer.
402 * Also return any special texture format flags such as
403 * any special swizzle mask.
404 */
405 void
406 svga_translate_texture_buffer_view_format(enum pipe_format format,
407 SVGA3dSurfaceFormat *svga_format,
408 unsigned *tf_flags)
409 {
410 assert(format < ARRAY_SIZE(format_conversion_table));
411 if (format >= ARRAY_SIZE(format_conversion_table)) {
412 format = PIPE_FORMAT_NONE;
413 }
414 *svga_format = format_conversion_table[format].view_format;
415 *tf_flags = format_conversion_table[format].flags;
416 }
417
418
419 /**
420 * Translate a gallium scanout format to a svga format valid
421 * for screen target surface.
422 */
423 static SVGA3dSurfaceFormat
424 svga_translate_screen_target_format_vgpu10(enum pipe_format format)
425 {
426 switch (format) {
427 case PIPE_FORMAT_B8G8R8A8_UNORM:
428 return SVGA3D_B8G8R8A8_UNORM;
429 case PIPE_FORMAT_B8G8R8X8_UNORM:
430 return SVGA3D_B8G8R8X8_UNORM;
431 case PIPE_FORMAT_B5G6R5_UNORM:
432 return SVGA3D_R5G6B5;
433 case PIPE_FORMAT_B5G5R5A1_UNORM:
434 return SVGA3D_A1R5G5B5;
435 default:
436 debug_printf("Invalid format %s specified for screen target\n",
437 svga_format_name(format));
438 return SVGA3D_FORMAT_INVALID;
439 }
440 }
441
442 /*
443 * Translate from gallium format to SVGA3D format.
444 */
445 SVGA3dSurfaceFormat
446 svga_translate_format(const struct svga_screen *ss,
447 enum pipe_format format,
448 unsigned bind)
449 {
450 if (ss->sws->have_vgpu10) {
451 if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) {
452 return format_conversion_table[format].vertex_format;
453 }
454 else if (bind & PIPE_BIND_SCANOUT) {
455 return svga_translate_screen_target_format_vgpu10(format);
456 }
457 else {
458 return format_conversion_table[format].pixel_format;
459 }
460 }
461
462 switch(format) {
463 case PIPE_FORMAT_B8G8R8A8_UNORM:
464 return SVGA3D_A8R8G8B8;
465 case PIPE_FORMAT_B8G8R8X8_UNORM:
466 return SVGA3D_X8R8G8B8;
467
468 /* sRGB required for GL2.1 */
469 case PIPE_FORMAT_B8G8R8A8_SRGB:
470 return SVGA3D_A8R8G8B8;
471 case PIPE_FORMAT_DXT1_SRGB:
472 case PIPE_FORMAT_DXT1_SRGBA:
473 return SVGA3D_DXT1;
474 case PIPE_FORMAT_DXT3_SRGBA:
475 return SVGA3D_DXT3;
476 case PIPE_FORMAT_DXT5_SRGBA:
477 return SVGA3D_DXT5;
478
479 case PIPE_FORMAT_B5G6R5_UNORM:
480 return SVGA3D_R5G6B5;
481 case PIPE_FORMAT_B5G5R5A1_UNORM:
482 return SVGA3D_A1R5G5B5;
483 case PIPE_FORMAT_B4G4R4A4_UNORM:
484 return SVGA3D_A4R4G4B4;
485
486 case PIPE_FORMAT_R16G16B16A16_UNORM:
487 return SVGA3D_A16B16G16R16;
488
489 case PIPE_FORMAT_Z16_UNORM:
490 assert(!ss->sws->have_vgpu10);
491 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.z16 : SVGA3D_Z_D16;
492 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
493 assert(!ss->sws->have_vgpu10);
494 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.s8z24 : SVGA3D_Z_D24S8;
495 case PIPE_FORMAT_X8Z24_UNORM:
496 assert(!ss->sws->have_vgpu10);
497 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.x8z24 : SVGA3D_Z_D24X8;
498
499 case PIPE_FORMAT_A8_UNORM:
500 return SVGA3D_ALPHA8;
501 case PIPE_FORMAT_L8_UNORM:
502 return SVGA3D_LUMINANCE8;
503
504 case PIPE_FORMAT_DXT1_RGB:
505 case PIPE_FORMAT_DXT1_RGBA:
506 return SVGA3D_DXT1;
507 case PIPE_FORMAT_DXT3_RGBA:
508 return SVGA3D_DXT3;
509 case PIPE_FORMAT_DXT5_RGBA:
510 return SVGA3D_DXT5;
511
512 /* Float formats (only 1, 2 and 4-component formats supported) */
513 case PIPE_FORMAT_R32_FLOAT:
514 return SVGA3D_R_S23E8;
515 case PIPE_FORMAT_R32G32_FLOAT:
516 return SVGA3D_RG_S23E8;
517 case PIPE_FORMAT_R32G32B32A32_FLOAT:
518 return SVGA3D_ARGB_S23E8;
519 case PIPE_FORMAT_R16_FLOAT:
520 return SVGA3D_R_S10E5;
521 case PIPE_FORMAT_R16G16_FLOAT:
522 return SVGA3D_RG_S10E5;
523 case PIPE_FORMAT_R16G16B16A16_FLOAT:
524 return SVGA3D_ARGB_S10E5;
525
526 case PIPE_FORMAT_Z32_UNORM:
527 /* SVGA3D_Z_D32 is not yet unsupported */
528 /* fall-through */
529 default:
530 return SVGA3D_FORMAT_INVALID;
531 }
532 }
533
534
535 /*
536 * Format capability description entry.
537 */
538 struct format_cap {
539 const char *name;
540
541 SVGA3dSurfaceFormat format;
542
543 /*
544 * Capability index corresponding to the format.
545 */
546 SVGA3dDevCapIndex devcap;
547
548 /* size of each pixel/block */
549 unsigned block_width, block_height, block_bytes;
550
551 /*
552 * Mask of supported SVGA3dFormatOp operations, to be inferred when the
553 * capability is not explicitly present.
554 */
555 uint32 defaultOperations;
556 };
557
558
559 /*
560 * Format capability description table.
561 *
562 * Ordered by increasing SVGA3dSurfaceFormat value, but with gaps.
563 */
564 static const struct format_cap format_cap_table[] = {
565 {
566 "SVGA3D_FORMAT_INVALID",
567 SVGA3D_FORMAT_INVALID, 0, 0, 0, 0, 0
568 },
569 {
570 "SVGA3D_X8R8G8B8",
571 SVGA3D_X8R8G8B8,
572 SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8,
573 1, 1, 4,
574 SVGA3DFORMAT_OP_TEXTURE |
575 SVGA3DFORMAT_OP_CUBETEXTURE |
576 SVGA3DFORMAT_OP_VOLUMETEXTURE |
577 SVGA3DFORMAT_OP_DISPLAYMODE |
578 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
579 },
580 {
581 "SVGA3D_A8R8G8B8",
582 SVGA3D_A8R8G8B8,
583 SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8,
584 1, 1, 4,
585 SVGA3DFORMAT_OP_TEXTURE |
586 SVGA3DFORMAT_OP_CUBETEXTURE |
587 SVGA3DFORMAT_OP_VOLUMETEXTURE |
588 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
589 },
590 {
591 "SVGA3D_R5G6B5",
592 SVGA3D_R5G6B5,
593 SVGA3D_DEVCAP_SURFACEFMT_R5G6B5,
594 1, 1, 2,
595 SVGA3DFORMAT_OP_TEXTURE |
596 SVGA3DFORMAT_OP_CUBETEXTURE |
597 SVGA3DFORMAT_OP_VOLUMETEXTURE |
598 SVGA3DFORMAT_OP_DISPLAYMODE |
599 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
600 },
601 {
602 "SVGA3D_X1R5G5B5",
603 SVGA3D_X1R5G5B5,
604 SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5,
605 1, 1, 2,
606 SVGA3DFORMAT_OP_TEXTURE |
607 SVGA3DFORMAT_OP_CUBETEXTURE |
608 SVGA3DFORMAT_OP_VOLUMETEXTURE |
609 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
610 },
611 {
612 "SVGA3D_A1R5G5B5",
613 SVGA3D_A1R5G5B5,
614 SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5,
615 1, 1, 2,
616 SVGA3DFORMAT_OP_TEXTURE |
617 SVGA3DFORMAT_OP_CUBETEXTURE |
618 SVGA3DFORMAT_OP_VOLUMETEXTURE |
619 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
620 },
621 {
622 "SVGA3D_A4R4G4B4",
623 SVGA3D_A4R4G4B4,
624 SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4,
625 1, 1, 2,
626 SVGA3DFORMAT_OP_TEXTURE |
627 SVGA3DFORMAT_OP_CUBETEXTURE |
628 SVGA3DFORMAT_OP_VOLUMETEXTURE |
629 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
630 },
631 {
632 /*
633 * SVGA3D_Z_D32 is not yet supported, and has no corresponding
634 * SVGA3D_DEVCAP_xxx.
635 */
636 "SVGA3D_Z_D32",
637 SVGA3D_Z_D32, 0, 0, 0, 0, 0
638 },
639 {
640 "SVGA3D_Z_D16",
641 SVGA3D_Z_D16,
642 SVGA3D_DEVCAP_SURFACEFMT_Z_D16,
643 1, 1, 2,
644 SVGA3DFORMAT_OP_ZSTENCIL
645 },
646 {
647 "SVGA3D_Z_D24S8",
648 SVGA3D_Z_D24S8,
649 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8,
650 1, 1, 4,
651 SVGA3DFORMAT_OP_ZSTENCIL
652 },
653 {
654 "SVGA3D_Z_D15S1",
655 SVGA3D_Z_D15S1,
656 SVGA3D_DEVCAP_MAX,
657 1, 1, 2,
658 SVGA3DFORMAT_OP_ZSTENCIL
659 },
660 {
661 "SVGA3D_LUMINANCE8",
662 SVGA3D_LUMINANCE8,
663 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8,
664 1, 1, 1,
665 SVGA3DFORMAT_OP_TEXTURE |
666 SVGA3DFORMAT_OP_CUBETEXTURE |
667 SVGA3DFORMAT_OP_VOLUMETEXTURE
668 },
669 {
670 /*
671 * SVGA3D_LUMINANCE4_ALPHA4 is not supported, and has no corresponding
672 * SVGA3D_DEVCAP_xxx.
673 */
674 "SVGA3D_LUMINANCE4_ALPHA4",
675 SVGA3D_LUMINANCE4_ALPHA4, 0, 0, 0, 0, 0
676 },
677 {
678 "SVGA3D_LUMINANCE16",
679 SVGA3D_LUMINANCE16,
680 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16,
681 1, 1, 2,
682 SVGA3DFORMAT_OP_TEXTURE |
683 SVGA3DFORMAT_OP_CUBETEXTURE |
684 SVGA3DFORMAT_OP_VOLUMETEXTURE
685 },
686 {
687 "SVGA3D_LUMINANCE8_ALPHA8",
688 SVGA3D_LUMINANCE8_ALPHA8,
689 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8,
690 1, 1, 2,
691 SVGA3DFORMAT_OP_TEXTURE |
692 SVGA3DFORMAT_OP_CUBETEXTURE |
693 SVGA3DFORMAT_OP_VOLUMETEXTURE
694 },
695 {
696 "SVGA3D_DXT1",
697 SVGA3D_DXT1,
698 SVGA3D_DEVCAP_SURFACEFMT_DXT1,
699 4, 4, 8,
700 SVGA3DFORMAT_OP_TEXTURE |
701 SVGA3DFORMAT_OP_CUBETEXTURE
702 },
703 {
704 "SVGA3D_DXT2",
705 SVGA3D_DXT2,
706 SVGA3D_DEVCAP_SURFACEFMT_DXT2,
707 4, 4, 8,
708 SVGA3DFORMAT_OP_TEXTURE |
709 SVGA3DFORMAT_OP_CUBETEXTURE
710 },
711 {
712 "SVGA3D_DXT3",
713 SVGA3D_DXT3,
714 SVGA3D_DEVCAP_SURFACEFMT_DXT3,
715 4, 4, 16,
716 SVGA3DFORMAT_OP_TEXTURE |
717 SVGA3DFORMAT_OP_CUBETEXTURE
718 },
719 {
720 "SVGA3D_DXT4",
721 SVGA3D_DXT4,
722 SVGA3D_DEVCAP_SURFACEFMT_DXT4,
723 4, 4, 16,
724 SVGA3DFORMAT_OP_TEXTURE |
725 SVGA3DFORMAT_OP_CUBETEXTURE
726 },
727 {
728 "SVGA3D_DXT5",
729 SVGA3D_DXT5,
730 SVGA3D_DEVCAP_SURFACEFMT_DXT5,
731 4, 4, 8,
732 SVGA3DFORMAT_OP_TEXTURE |
733 SVGA3DFORMAT_OP_CUBETEXTURE
734 },
735 {
736 "SVGA3D_BUMPU8V8",
737 SVGA3D_BUMPU8V8,
738 SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8,
739 1, 1, 2,
740 SVGA3DFORMAT_OP_TEXTURE |
741 SVGA3DFORMAT_OP_CUBETEXTURE |
742 SVGA3DFORMAT_OP_VOLUMETEXTURE
743 },
744 {
745 /*
746 * SVGA3D_BUMPL6V5U5 is unsupported; it has no corresponding
747 * SVGA3D_DEVCAP_xxx.
748 */
749 "SVGA3D_BUMPL6V5U5",
750 SVGA3D_BUMPL6V5U5, 0, 0, 0, 0, 0
751 },
752 {
753 "SVGA3D_BUMPX8L8V8U8",
754 SVGA3D_BUMPX8L8V8U8,
755 SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8,
756 1, 1, 4,
757 SVGA3DFORMAT_OP_TEXTURE |
758 SVGA3DFORMAT_OP_CUBETEXTURE
759 },
760 {
761 "SVGA3D_FORMAT_DEAD1",
762 SVGA3D_FORMAT_DEAD1, 0, 0, 0, 0, 0
763 },
764 {
765 "SVGA3D_ARGB_S10E5",
766 SVGA3D_ARGB_S10E5,
767 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5,
768 1, 1, 2,
769 SVGA3DFORMAT_OP_TEXTURE |
770 SVGA3DFORMAT_OP_CUBETEXTURE |
771 SVGA3DFORMAT_OP_VOLUMETEXTURE |
772 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
773 },
774 {
775 "SVGA3D_ARGB_S23E8",
776 SVGA3D_ARGB_S23E8,
777 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8,
778 1, 1, 4,
779 SVGA3DFORMAT_OP_TEXTURE |
780 SVGA3DFORMAT_OP_CUBETEXTURE |
781 SVGA3DFORMAT_OP_VOLUMETEXTURE |
782 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
783 },
784 {
785 "SVGA3D_A2R10G10B10",
786 SVGA3D_A2R10G10B10,
787 SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10,
788 1, 1, 4,
789 SVGA3DFORMAT_OP_TEXTURE |
790 SVGA3DFORMAT_OP_CUBETEXTURE |
791 SVGA3DFORMAT_OP_VOLUMETEXTURE |
792 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
793 },
794 {
795 /*
796 * SVGA3D_V8U8 is unsupported; it has no corresponding
797 * SVGA3D_DEVCAP_xxx. SVGA3D_BUMPU8V8 should be used instead.
798 */
799 "SVGA3D_V8U8",
800 SVGA3D_V8U8, 0, 0, 0, 0, 0
801 },
802 {
803 "SVGA3D_Q8W8V8U8",
804 SVGA3D_Q8W8V8U8,
805 SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8,
806 1, 1, 4,
807 SVGA3DFORMAT_OP_TEXTURE |
808 SVGA3DFORMAT_OP_CUBETEXTURE
809 },
810 {
811 "SVGA3D_CxV8U8",
812 SVGA3D_CxV8U8,
813 SVGA3D_DEVCAP_SURFACEFMT_CxV8U8,
814 1, 1, 2,
815 SVGA3DFORMAT_OP_TEXTURE
816 },
817 {
818 /*
819 * SVGA3D_X8L8V8U8 is unsupported; it has no corresponding
820 * SVGA3D_DEVCAP_xxx. SVGA3D_BUMPX8L8V8U8 should be used instead.
821 */
822 "SVGA3D_X8L8V8U8",
823 SVGA3D_X8L8V8U8, 0, 0, 0, 0, 0
824 },
825 {
826 "SVGA3D_A2W10V10U10",
827 SVGA3D_A2W10V10U10,
828 SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10,
829 1, 1, 4,
830 SVGA3DFORMAT_OP_TEXTURE
831 },
832 {
833 "SVGA3D_ALPHA8",
834 SVGA3D_ALPHA8,
835 SVGA3D_DEVCAP_SURFACEFMT_ALPHA8,
836 1, 1, 1,
837 SVGA3DFORMAT_OP_TEXTURE |
838 SVGA3DFORMAT_OP_CUBETEXTURE |
839 SVGA3DFORMAT_OP_VOLUMETEXTURE
840 },
841 {
842 "SVGA3D_R_S10E5",
843 SVGA3D_R_S10E5,
844 SVGA3D_DEVCAP_SURFACEFMT_R_S10E5,
845 1, 1, 2,
846 SVGA3DFORMAT_OP_TEXTURE |
847 SVGA3DFORMAT_OP_VOLUMETEXTURE |
848 SVGA3DFORMAT_OP_CUBETEXTURE |
849 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
850 },
851 {
852 "SVGA3D_R_S23E8",
853 SVGA3D_R_S23E8,
854 SVGA3D_DEVCAP_SURFACEFMT_R_S23E8,
855 1, 1, 4,
856 SVGA3DFORMAT_OP_TEXTURE |
857 SVGA3DFORMAT_OP_VOLUMETEXTURE |
858 SVGA3DFORMAT_OP_CUBETEXTURE |
859 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
860 },
861 {
862 "SVGA3D_RG_S10E5",
863 SVGA3D_RG_S10E5,
864 SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5,
865 1, 1, 2,
866 SVGA3DFORMAT_OP_TEXTURE |
867 SVGA3DFORMAT_OP_VOLUMETEXTURE |
868 SVGA3DFORMAT_OP_CUBETEXTURE |
869 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
870 },
871 {
872 "SVGA3D_RG_S23E8",
873 SVGA3D_RG_S23E8,
874 SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8,
875 1, 1, 4,
876 SVGA3DFORMAT_OP_TEXTURE |
877 SVGA3DFORMAT_OP_VOLUMETEXTURE |
878 SVGA3DFORMAT_OP_CUBETEXTURE |
879 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
880 },
881 {
882 /*
883 * SVGA3D_BUFFER is a placeholder format for index/vertex buffers.
884 */
885 "SVGA3D_BUFFER",
886 SVGA3D_BUFFER, 0, 1, 1, 1, 0
887 },
888 {
889 "SVGA3D_Z_D24X8",
890 SVGA3D_Z_D24X8,
891 SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8,
892 1, 1, 4,
893 SVGA3DFORMAT_OP_ZSTENCIL
894 },
895 {
896 "SVGA3D_V16U16",
897 SVGA3D_V16U16,
898 SVGA3D_DEVCAP_SURFACEFMT_V16U16,
899 1, 1, 4,
900 SVGA3DFORMAT_OP_TEXTURE |
901 SVGA3DFORMAT_OP_CUBETEXTURE |
902 SVGA3DFORMAT_OP_VOLUMETEXTURE
903 },
904 {
905 "SVGA3D_G16R16",
906 SVGA3D_G16R16,
907 SVGA3D_DEVCAP_SURFACEFMT_G16R16,
908 1, 1, 4,
909 SVGA3DFORMAT_OP_TEXTURE |
910 SVGA3DFORMAT_OP_CUBETEXTURE |
911 SVGA3DFORMAT_OP_VOLUMETEXTURE |
912 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
913 },
914 {
915 "SVGA3D_A16B16G16R16",
916 SVGA3D_A16B16G16R16,
917 SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16,
918 1, 1, 8,
919 SVGA3DFORMAT_OP_TEXTURE |
920 SVGA3DFORMAT_OP_CUBETEXTURE |
921 SVGA3DFORMAT_OP_VOLUMETEXTURE |
922 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
923 },
924 {
925 "SVGA3D_UYVY",
926 SVGA3D_UYVY,
927 SVGA3D_DEVCAP_SURFACEFMT_UYVY,
928 0, 0, 0, 0
929 },
930 {
931 "SVGA3D_YUY2",
932 SVGA3D_YUY2,
933 SVGA3D_DEVCAP_SURFACEFMT_YUY2,
934 0, 0, 0, 0
935 },
936 {
937 "SVGA3D_NV12",
938 SVGA3D_NV12,
939 SVGA3D_DEVCAP_SURFACEFMT_NV12,
940 0, 0, 0, 0
941 },
942 {
943 "SVGA3D_AYUV",
944 SVGA3D_AYUV,
945 SVGA3D_DEVCAP_SURFACEFMT_AYUV,
946 0, 0, 0, 0
947 },
948 {
949 "SVGA3D_R32G32B32A32_TYPELESS",
950 SVGA3D_R32G32B32A32_TYPELESS,
951 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS,
952 1, 1, 16, 0
953 },
954 {
955 "SVGA3D_R32G32B32A32_UINT",
956 SVGA3D_R32G32B32A32_UINT,
957 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT,
958 1, 1, 16, 0
959 },
960 {
961 "SVGA3D_R32G32B32A32_SINT",
962 SVGA3D_R32G32B32A32_SINT,
963 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT,
964 1, 1, 16, 0
965 },
966 {
967 "SVGA3D_R32G32B32_TYPELESS",
968 SVGA3D_R32G32B32_TYPELESS,
969 SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS,
970 1, 1, 12, 0
971 },
972 {
973 "SVGA3D_R32G32B32_FLOAT",
974 SVGA3D_R32G32B32_FLOAT,
975 SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT,
976 1, 1, 12, 0
977 },
978 {
979 "SVGA3D_R32G32B32_UINT",
980 SVGA3D_R32G32B32_UINT,
981 SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT,
982 1, 1, 12, 0
983 },
984 {
985 "SVGA3D_R32G32B32_SINT",
986 SVGA3D_R32G32B32_SINT,
987 SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT,
988 1, 1, 12, 0
989 },
990 {
991 "SVGA3D_R16G16B16A16_TYPELESS",
992 SVGA3D_R16G16B16A16_TYPELESS,
993 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS,
994 1, 1, 8, 0
995 },
996 {
997 "SVGA3D_R16G16B16A16_UINT",
998 SVGA3D_R16G16B16A16_UINT,
999 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT,
1000 1, 1, 8, 0
1001 },
1002 {
1003 "SVGA3D_R16G16B16A16_SNORM",
1004 SVGA3D_R16G16B16A16_SNORM,
1005 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM,
1006 1, 1, 8, 0
1007 },
1008 {
1009 "SVGA3D_R16G16B16A16_SINT",
1010 SVGA3D_R16G16B16A16_SINT,
1011 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT,
1012 1, 1, 8, 0
1013 },
1014 {
1015 "SVGA3D_R32G32_TYPELESS",
1016 SVGA3D_R32G32_TYPELESS,
1017 SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS,
1018 1, 1, 8, 0
1019 },
1020 {
1021 "SVGA3D_R32G32_UINT",
1022 SVGA3D_R32G32_UINT,
1023 SVGA3D_DEVCAP_DXFMT_R32G32_UINT,
1024 1, 1, 8, 0
1025 },
1026 {
1027 "SVGA3D_R32G32_SINT",
1028 SVGA3D_R32G32_SINT,
1029 SVGA3D_DEVCAP_DXFMT_R32G32_SINT,
1030 1, 1, 8,
1031 0
1032 },
1033 {
1034 "SVGA3D_R32G8X24_TYPELESS",
1035 SVGA3D_R32G8X24_TYPELESS,
1036 SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS,
1037 1, 1, 8, 0
1038 },
1039 {
1040 "SVGA3D_D32_FLOAT_S8X24_UINT",
1041 SVGA3D_D32_FLOAT_S8X24_UINT,
1042 SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT,
1043 1, 1, 8, 0
1044 },
1045 {
1046 "SVGA3D_R32_FLOAT_X8X24",
1047 SVGA3D_R32_FLOAT_X8X24,
1048 SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24,
1049 1, 1, 8, 0
1050 },
1051 {
1052 "SVGA3D_X32_G8X24_UINT",
1053 SVGA3D_X32_G8X24_UINT,
1054 SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT,
1055 1, 1, 4, 0
1056 },
1057 {
1058 "SVGA3D_R10G10B10A2_TYPELESS",
1059 SVGA3D_R10G10B10A2_TYPELESS,
1060 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS,
1061 1, 1, 4, 0
1062 },
1063 {
1064 "SVGA3D_R10G10B10A2_UINT",
1065 SVGA3D_R10G10B10A2_UINT,
1066 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT,
1067 1, 1, 4, 0
1068 },
1069 {
1070 "SVGA3D_R11G11B10_FLOAT",
1071 SVGA3D_R11G11B10_FLOAT,
1072 SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT,
1073 1, 1, 4, 0
1074 },
1075 {
1076 "SVGA3D_R8G8B8A8_TYPELESS",
1077 SVGA3D_R8G8B8A8_TYPELESS,
1078 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS,
1079 1, 1, 4, 0
1080 },
1081 {
1082 "SVGA3D_R8G8B8A8_UNORM",
1083 SVGA3D_R8G8B8A8_UNORM,
1084 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM,
1085 1, 1, 4, 0
1086 },
1087 {
1088 "SVGA3D_R8G8B8A8_UNORM_SRGB",
1089 SVGA3D_R8G8B8A8_UNORM_SRGB,
1090 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB,
1091 1, 1, 4, 0
1092 },
1093 {
1094 "SVGA3D_R8G8B8A8_UINT",
1095 SVGA3D_R8G8B8A8_UINT,
1096 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT,
1097 1, 1, 4, 0
1098 },
1099 {
1100 "SVGA3D_R8G8B8A8_SINT",
1101 SVGA3D_R8G8B8A8_SINT,
1102 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT,
1103 1, 1, 4, 0
1104 },
1105 {
1106 "SVGA3D_R16G16_TYPELESS",
1107 SVGA3D_R16G16_TYPELESS,
1108 SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS,
1109 1, 1, 4, 0
1110 },
1111 {
1112 "SVGA3D_R16G16_UINT",
1113 SVGA3D_R16G16_UINT,
1114 SVGA3D_DEVCAP_DXFMT_R16G16_UINT,
1115 1, 1, 4, 0
1116 },
1117 {
1118 "SVGA3D_R16G16_SINT",
1119 SVGA3D_R16G16_SINT,
1120 SVGA3D_DEVCAP_DXFMT_R16G16_SINT,
1121 1, 1, 4, 0
1122 },
1123 {
1124 "SVGA3D_R32_TYPELESS",
1125 SVGA3D_R32_TYPELESS,
1126 SVGA3D_DEVCAP_DXFMT_R32_TYPELESS,
1127 1, 1, 4, 0
1128 },
1129 {
1130 "SVGA3D_D32_FLOAT",
1131 SVGA3D_D32_FLOAT,
1132 SVGA3D_DEVCAP_DXFMT_D32_FLOAT,
1133 1, 1, 4, 0
1134 },
1135 {
1136 "SVGA3D_R32_UINT",
1137 SVGA3D_R32_UINT,
1138 SVGA3D_DEVCAP_DXFMT_R32_UINT,
1139 1, 1, 4, 0
1140 },
1141 {
1142 "SVGA3D_R32_SINT",
1143 SVGA3D_R32_SINT,
1144 SVGA3D_DEVCAP_DXFMT_R32_SINT,
1145 1, 1, 4, 0
1146 },
1147 {
1148 "SVGA3D_R24G8_TYPELESS",
1149 SVGA3D_R24G8_TYPELESS,
1150 SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS,
1151 1, 1, 4, 0
1152 },
1153 {
1154 "SVGA3D_D24_UNORM_S8_UINT",
1155 SVGA3D_D24_UNORM_S8_UINT,
1156 SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT,
1157 1, 1, 4, 0
1158 },
1159 {
1160 "SVGA3D_R24_UNORM_X8",
1161 SVGA3D_R24_UNORM_X8,
1162 SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8,
1163 1, 1, 4, 0
1164 },
1165 {
1166 "SVGA3D_X24_G8_UINT",
1167 SVGA3D_X24_G8_UINT,
1168 SVGA3D_DEVCAP_DXFMT_X24_G8_UINT,
1169 1, 1, 4, 0
1170 },
1171 {
1172 "SVGA3D_R8G8_TYPELESS",
1173 SVGA3D_R8G8_TYPELESS,
1174 SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS,
1175 1, 1, 2, 0
1176 },
1177 {
1178 "SVGA3D_R8G8_UNORM",
1179 SVGA3D_R8G8_UNORM,
1180 SVGA3D_DEVCAP_DXFMT_R8G8_UNORM,
1181 1, 1, 2, 0
1182 },
1183 {
1184 "SVGA3D_R8G8_UINT",
1185 SVGA3D_R8G8_UINT,
1186 SVGA3D_DEVCAP_DXFMT_R8G8_UINT,
1187 1, 1, 2, 0
1188 },
1189 {
1190 "SVGA3D_R8G8_SINT",
1191 SVGA3D_R8G8_SINT,
1192 SVGA3D_DEVCAP_DXFMT_R8G8_SINT,
1193 1, 1, 2, 0
1194 },
1195 {
1196 "SVGA3D_R16_TYPELESS",
1197 SVGA3D_R16_TYPELESS,
1198 SVGA3D_DEVCAP_DXFMT_R16_TYPELESS,
1199 1, 1, 2, 0
1200 },
1201 {
1202 "SVGA3D_R16_UNORM",
1203 SVGA3D_R16_UNORM,
1204 SVGA3D_DEVCAP_DXFMT_R16_UNORM,
1205 1, 1, 2, 0
1206 },
1207 {
1208 "SVGA3D_R16_UINT",
1209 SVGA3D_R16_UINT,
1210 SVGA3D_DEVCAP_DXFMT_R16_UINT,
1211 1, 1, 2, 0
1212 },
1213 {
1214 "SVGA3D_R16_SNORM",
1215 SVGA3D_R16_SNORM,
1216 SVGA3D_DEVCAP_DXFMT_R16_SNORM,
1217 1, 1, 2, 0
1218 },
1219 {
1220 "SVGA3D_R16_SINT",
1221 SVGA3D_R16_SINT,
1222 SVGA3D_DEVCAP_DXFMT_R16_SINT,
1223 1, 1, 2, 0
1224 },
1225 {
1226 "SVGA3D_R8_TYPELESS",
1227 SVGA3D_R8_TYPELESS,
1228 SVGA3D_DEVCAP_DXFMT_R8_TYPELESS,
1229 1, 1, 1, 0
1230 },
1231 {
1232 "SVGA3D_R8_UNORM",
1233 SVGA3D_R8_UNORM,
1234 SVGA3D_DEVCAP_DXFMT_R8_UNORM,
1235 1, 1, 1, 0
1236 },
1237 {
1238 "SVGA3D_R8_UINT",
1239 SVGA3D_R8_UINT,
1240 SVGA3D_DEVCAP_DXFMT_R8_UINT,
1241 1, 1, 1, 0
1242 },
1243 {
1244 "SVGA3D_R8_SNORM",
1245 SVGA3D_R8_SNORM,
1246 SVGA3D_DEVCAP_DXFMT_R8_SNORM,
1247 1, 1, 1, 0
1248 },
1249 {
1250 "SVGA3D_R8_SINT",
1251 SVGA3D_R8_SINT,
1252 SVGA3D_DEVCAP_DXFMT_R8_SINT,
1253 1, 1, 1, 0
1254 },
1255 {
1256 "SVGA3D_P8",
1257 SVGA3D_P8, 0, 0, 0, 0, 0
1258 },
1259 {
1260 "SVGA3D_R9G9B9E5_SHAREDEXP",
1261 SVGA3D_R9G9B9E5_SHAREDEXP,
1262 SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP,
1263 1, 1, 4, 0
1264 },
1265 {
1266 "SVGA3D_R8G8_B8G8_UNORM",
1267 SVGA3D_R8G8_B8G8_UNORM, 0, 0, 0, 0, 0
1268 },
1269 {
1270 "SVGA3D_G8R8_G8B8_UNORM",
1271 SVGA3D_G8R8_G8B8_UNORM, 0, 0, 0, 0, 0
1272 },
1273 {
1274 "SVGA3D_BC1_TYPELESS",
1275 SVGA3D_BC1_TYPELESS,
1276 SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS,
1277 4, 4, 8, 0
1278 },
1279 {
1280 "SVGA3D_BC1_UNORM_SRGB",
1281 SVGA3D_BC1_UNORM_SRGB,
1282 SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB,
1283 4, 4, 8, 0
1284 },
1285 {
1286 "SVGA3D_BC2_TYPELESS",
1287 SVGA3D_BC2_TYPELESS,
1288 SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS,
1289 4, 4, 16, 0
1290 },
1291 {
1292 "SVGA3D_BC2_UNORM_SRGB",
1293 SVGA3D_BC2_UNORM_SRGB,
1294 SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB,
1295 4, 4, 16, 0
1296 },
1297 {
1298 "SVGA3D_BC3_TYPELESS",
1299 SVGA3D_BC3_TYPELESS,
1300 SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS,
1301 4, 4, 16, 0
1302 },
1303 {
1304 "SVGA3D_BC3_UNORM_SRGB",
1305 SVGA3D_BC3_UNORM_SRGB,
1306 SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB,
1307 4, 4, 16, 0
1308 },
1309 {
1310 "SVGA3D_BC4_TYPELESS",
1311 SVGA3D_BC4_TYPELESS,
1312 SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS,
1313 4, 4, 8, 0
1314 },
1315 {
1316 "SVGA3D_ATI1",
1317 SVGA3D_ATI1, 0, 0, 0, 0, 0
1318 },
1319 {
1320 "SVGA3D_BC4_SNORM",
1321 SVGA3D_BC4_SNORM,
1322 SVGA3D_DEVCAP_DXFMT_BC4_SNORM,
1323 4, 4, 8, 0
1324 },
1325 {
1326 "SVGA3D_BC5_TYPELESS",
1327 SVGA3D_BC5_TYPELESS,
1328 SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS,
1329 4, 4, 16, 0
1330 },
1331 {
1332 "SVGA3D_ATI2",
1333 SVGA3D_ATI2, 0, 0, 0, 0, 0
1334 },
1335 {
1336 "SVGA3D_BC5_SNORM",
1337 SVGA3D_BC5_SNORM,
1338 SVGA3D_DEVCAP_DXFMT_BC5_SNORM,
1339 4, 4, 16, 0
1340 },
1341 {
1342 "SVGA3D_R10G10B10_XR_BIAS_A2_UNORM",
1343 SVGA3D_R10G10B10_XR_BIAS_A2_UNORM, 0, 0, 0, 0, 0
1344 },
1345 {
1346 "SVGA3D_B8G8R8A8_TYPELESS",
1347 SVGA3D_B8G8R8A8_TYPELESS,
1348 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS,
1349 1, 1, 4, 0
1350 },
1351 {
1352 "SVGA3D_B8G8R8A8_UNORM_SRGB",
1353 SVGA3D_B8G8R8A8_UNORM_SRGB,
1354 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB,
1355 1, 1, 4, 0
1356 },
1357 {
1358 "SVGA3D_B8G8R8X8_TYPELESS",
1359 SVGA3D_B8G8R8X8_TYPELESS,
1360 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS,
1361 1, 1, 4, 0
1362 },
1363 {
1364 "SVGA3D_B8G8R8X8_UNORM_SRGB",
1365 SVGA3D_B8G8R8X8_UNORM_SRGB,
1366 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB,
1367 1, 1, 4, 0
1368 },
1369 {
1370 "SVGA3D_Z_DF16",
1371 SVGA3D_Z_DF16,
1372 SVGA3D_DEVCAP_SURFACEFMT_Z_DF16,
1373 1, 1, 2, 0
1374 },
1375 {
1376 "SVGA3D_Z_DF24",
1377 SVGA3D_Z_DF24,
1378 SVGA3D_DEVCAP_SURFACEFMT_Z_DF24,
1379 1, 1, 4, 0
1380 },
1381 {
1382 "SVGA3D_Z_D24S8_INT",
1383 SVGA3D_Z_D24S8_INT,
1384 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT,
1385 1, 1, 4, 0
1386 },
1387 {
1388 "SVGA3D_YV12",
1389 SVGA3D_YV12, 0, 0, 0, 0, 0
1390 },
1391 {
1392 "SVGA3D_R32G32B32A32_FLOAT",
1393 SVGA3D_R32G32B32A32_FLOAT,
1394 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT,
1395 1, 1, 16, 0
1396 },
1397 {
1398 "SVGA3D_R16G16B16A16_FLOAT",
1399 SVGA3D_R16G16B16A16_FLOAT,
1400 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT,
1401 1, 1, 8, 0
1402 },
1403 {
1404 "SVGA3D_R16G16B16A16_UNORM",
1405 SVGA3D_R16G16B16A16_UNORM,
1406 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM,
1407 1, 1, 8, 0
1408 },
1409 {
1410 "SVGA3D_R32G32_FLOAT",
1411 SVGA3D_R32G32_FLOAT,
1412 SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT,
1413 1, 1, 8, 0
1414 },
1415 {
1416 "SVGA3D_R10G10B10A2_UNORM",
1417 SVGA3D_R10G10B10A2_UNORM,
1418 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM,
1419 1, 1, 4, 0
1420 },
1421 {
1422 "SVGA3D_R8G8B8A8_SNORM",
1423 SVGA3D_R8G8B8A8_SNORM,
1424 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM,
1425 1, 1, 4, 0
1426 },
1427 {
1428 "SVGA3D_R16G16_FLOAT",
1429 SVGA3D_R16G16_FLOAT,
1430 SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT,
1431 1, 1, 4, 0
1432 },
1433 {
1434 "SVGA3D_R16G16_UNORM",
1435 SVGA3D_R16G16_UNORM,
1436 SVGA3D_DEVCAP_DXFMT_R16G16_UNORM,
1437 1, 1, 4, 0
1438 },
1439 {
1440 "SVGA3D_R16G16_SNORM",
1441 SVGA3D_R16G16_SNORM,
1442 SVGA3D_DEVCAP_DXFMT_R16G16_SNORM,
1443 1, 1, 4, 0
1444 },
1445 {
1446 "SVGA3D_R32_FLOAT",
1447 SVGA3D_R32_FLOAT,
1448 SVGA3D_DEVCAP_DXFMT_R32_FLOAT,
1449 1, 1, 4, 0
1450 },
1451 {
1452 "SVGA3D_R8G8_SNORM",
1453 SVGA3D_R8G8_SNORM,
1454 SVGA3D_DEVCAP_DXFMT_R8G8_SNORM,
1455 1, 1, 2, 0
1456 },
1457 {
1458 "SVGA3D_R16_FLOAT",
1459 SVGA3D_R16_FLOAT,
1460 SVGA3D_DEVCAP_DXFMT_R16_FLOAT,
1461 1, 1, 2, 0
1462 },
1463 {
1464 "SVGA3D_D16_UNORM",
1465 SVGA3D_D16_UNORM,
1466 SVGA3D_DEVCAP_DXFMT_D16_UNORM,
1467 1, 1, 2, 0
1468 },
1469 {
1470 "SVGA3D_A8_UNORM",
1471 SVGA3D_A8_UNORM,
1472 SVGA3D_DEVCAP_DXFMT_A8_UNORM,
1473 1, 1, 1, 0
1474 },
1475 {
1476 "SVGA3D_BC1_UNORM",
1477 SVGA3D_BC1_UNORM,
1478 SVGA3D_DEVCAP_DXFMT_BC1_UNORM,
1479 4, 4, 8, 0
1480 },
1481 {
1482 "SVGA3D_BC2_UNORM",
1483 SVGA3D_BC2_UNORM,
1484 SVGA3D_DEVCAP_DXFMT_BC2_UNORM,
1485 4, 4, 16, 0
1486 },
1487 {
1488 "SVGA3D_BC3_UNORM",
1489 SVGA3D_BC3_UNORM,
1490 SVGA3D_DEVCAP_DXFMT_BC3_UNORM,
1491 4, 4, 16, 0
1492 },
1493 {
1494 "SVGA3D_B5G6R5_UNORM",
1495 SVGA3D_B5G6R5_UNORM,
1496 SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM,
1497 1, 1, 2, 0
1498 },
1499 {
1500 "SVGA3D_B5G5R5A1_UNORM",
1501 SVGA3D_B5G5R5A1_UNORM,
1502 SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM,
1503 1, 1, 2, 0
1504 },
1505 {
1506 "SVGA3D_B8G8R8A8_UNORM",
1507 SVGA3D_B8G8R8A8_UNORM,
1508 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM,
1509 1, 1, 4, 0
1510 },
1511 {
1512 "SVGA3D_B8G8R8X8_UNORM",
1513 SVGA3D_B8G8R8X8_UNORM,
1514 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM,
1515 1, 1, 4, 0
1516 },
1517 {
1518 "SVGA3D_BC4_UNORM",
1519 SVGA3D_BC4_UNORM,
1520 SVGA3D_DEVCAP_DXFMT_BC4_UNORM,
1521 4, 4, 8, 0
1522 },
1523 {
1524 "SVGA3D_BC5_UNORM",
1525 SVGA3D_BC5_UNORM,
1526 SVGA3D_DEVCAP_DXFMT_BC5_UNORM,
1527 4, 4, 16, 0
1528 }
1529 };
1530
1531 static const SVGA3dSurfaceFormat compat_x8r8g8b8[] = {
1532 SVGA3D_X8R8G8B8, SVGA3D_A8R8G8B8, SVGA3D_B8G8R8X8_UNORM,
1533 SVGA3D_B8G8R8A8_UNORM, 0
1534 };
1535 static const SVGA3dSurfaceFormat compat_r8[] = {
1536 SVGA3D_R8_UNORM, SVGA3D_NV12, SVGA3D_YV12, 0
1537 };
1538 static const SVGA3dSurfaceFormat compat_g8r8[] = {
1539 SVGA3D_R8G8_UNORM, SVGA3D_NV12, 0
1540 };
1541 static const SVGA3dSurfaceFormat compat_r5g6b5[] = {
1542 SVGA3D_R5G6B5, SVGA3D_B5G6R5_UNORM, 0
1543 };
1544
1545 static const struct format_compat_entry format_compats[] = {
1546 {PIPE_FORMAT_B8G8R8X8_UNORM, compat_x8r8g8b8},
1547 {PIPE_FORMAT_B8G8R8A8_UNORM, compat_x8r8g8b8},
1548 {PIPE_FORMAT_R8_UNORM, compat_r8},
1549 {PIPE_FORMAT_R8G8_UNORM, compat_g8r8},
1550 {PIPE_FORMAT_B5G6R5_UNORM, compat_r5g6b5}
1551 };
1552
1553 /**
1554 * Debug only:
1555 * 1. check that format_cap_table[i] matches the i-th SVGA3D format.
1556 * 2. check that format_conversion_table[i].pformat == i.
1557 */
1558 static void
1559 check_format_tables(void)
1560 {
1561 static boolean first_call = TRUE;
1562
1563 if (first_call) {
1564 unsigned i;
1565
1566 STATIC_ASSERT(ARRAY_SIZE(format_cap_table) == SVGA3D_FORMAT_MAX);
1567 for (i = 0; i < ARRAY_SIZE(format_cap_table); i++) {
1568 assert(format_cap_table[i].format == i);
1569 }
1570
1571 STATIC_ASSERT(ARRAY_SIZE(format_conversion_table) == PIPE_FORMAT_COUNT);
1572 for (i = 0; i < ARRAY_SIZE(format_conversion_table); i++) {
1573 assert(format_conversion_table[i].pformat == i);
1574 }
1575
1576 first_call = FALSE;
1577 }
1578 }
1579
1580
1581 /**
1582 * Return string name of an SVGA3dDevCapIndex value.
1583 * For debugging.
1584 */
1585 static const char *
1586 svga_devcap_name(SVGA3dDevCapIndex cap)
1587 {
1588 static const struct debug_named_value devcap_names[] = {
1589 /* Note, we only list the DXFMT devcaps so far */
1590 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X8R8G8B8),
1591 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A8R8G8B8),
1592 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R5G6B5),
1593 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X1R5G5B5),
1594 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A1R5G5B5),
1595 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A4R4G4B4),
1596 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D32),
1597 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D16),
1598 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D24S8),
1599 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D15S1),
1600 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE8),
1601 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4),
1602 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE16),
1603 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8),
1604 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT1),
1605 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT2),
1606 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT3),
1607 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT4),
1608 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT5),
1609 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUMPU8V8),
1610 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5),
1611 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8),
1612 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1),
1613 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5),
1614 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8),
1615 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A2R10G10B10),
1616 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_V8U8),
1617 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8),
1618 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_CxV8U8),
1619 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X8L8V8U8),
1620 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A2W10V10U10),
1621 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ALPHA8),
1622 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R_S10E5),
1623 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R_S23E8),
1624 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_RG_S10E5),
1625 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_RG_S23E8),
1626 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUFFER),
1627 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D24X8),
1628 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_V16U16),
1629 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_G16R16),
1630 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A16B16G16R16),
1631 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_UYVY),
1632 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_YUY2),
1633 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_NV12),
1634 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_AYUV),
1635 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS),
1636 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT),
1637 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT),
1638 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS),
1639 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT),
1640 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT),
1641 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT),
1642 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS),
1643 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT),
1644 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM),
1645 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT),
1646 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS),
1647 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_UINT),
1648 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_SINT),
1649 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS),
1650 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT),
1651 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24),
1652 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT),
1653 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS),
1654 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT),
1655 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT),
1656 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS),
1657 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM),
1658 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB),
1659 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT),
1660 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT),
1661 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS),
1662 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_UINT),
1663 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_SINT),
1664 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS),
1665 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D32_FLOAT),
1666 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_UINT),
1667 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_SINT),
1668 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS),
1669 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT),
1670 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8),
1671 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X24_G8_UINT),
1672 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS),
1673 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM),
1674 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_UINT),
1675 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_SINT),
1676 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS),
1677 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_UNORM),
1678 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_UINT),
1679 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_SNORM),
1680 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_SINT),
1681 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS),
1682 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_UNORM),
1683 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_UINT),
1684 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_SNORM),
1685 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_SINT),
1686 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_P8),
1687 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP),
1688 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM),
1689 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM),
1690 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS),
1691 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB),
1692 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS),
1693 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB),
1694 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS),
1695 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB),
1696 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS),
1697 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ATI1),
1698 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC4_SNORM),
1699 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS),
1700 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ATI2),
1701 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC5_SNORM),
1702 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM),
1703 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS),
1704 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB),
1705 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS),
1706 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB),
1707 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_DF16),
1708 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_DF24),
1709 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT),
1710 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_YV12),
1711 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT),
1712 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT),
1713 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM),
1714 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT),
1715 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM),
1716 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM),
1717 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT),
1718 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM),
1719 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM),
1720 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_FLOAT),
1721 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM),
1722 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_FLOAT),
1723 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D16_UNORM),
1724 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A8_UNORM),
1725 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC1_UNORM),
1726 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC2_UNORM),
1727 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC3_UNORM),
1728 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM),
1729 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM),
1730 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM),
1731 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM),
1732 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC4_UNORM),
1733 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC5_UNORM),
1734 DEBUG_NAMED_VALUE_END,
1735 };
1736 return debug_dump_enum(devcap_names, cap);
1737 }
1738
1739
1740 /**
1741 * Return string for a bitmask of name of SVGA3D_DXFMT_x flags.
1742 * For debugging.
1743 */
1744 static const char *
1745 svga_devcap_format_flags(unsigned flags)
1746 {
1747 static const struct debug_named_value devcap_flags[] = {
1748 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_SUPPORTED),
1749 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_SHADER_SAMPLE),
1750 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_COLOR_RENDERTARGET),
1751 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_DEPTH_RENDERTARGET),
1752 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_BLENDABLE),
1753 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_MIPS),
1754 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_ARRAY),
1755 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_VOLUME),
1756 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_DX_VERTEX_BUFFER),
1757 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_MULTISAMPLE),
1758 DEBUG_NAMED_VALUE_END
1759 };
1760
1761 return debug_dump_flags(devcap_flags, flags);
1762 }
1763
1764
1765 /*
1766 * Get format capabilities from the host. It takes in consideration
1767 * deprecated/unsupported formats, and formats which are implicitely assumed to
1768 * be supported when the host does not provide an explicit capability entry.
1769 */
1770 void
1771 svga_get_format_cap(struct svga_screen *ss,
1772 SVGA3dSurfaceFormat format,
1773 SVGA3dSurfaceFormatCaps *caps)
1774 {
1775 struct svga_winsys_screen *sws = ss->sws;
1776 SVGA3dDevCapResult result;
1777 const struct format_cap *entry;
1778
1779 #ifdef DEBUG
1780 check_format_tables();
1781 #else
1782 (void) check_format_tables;
1783 #endif
1784
1785 assert(format < ARRAY_SIZE(format_cap_table));
1786 entry = &format_cap_table[format];
1787 assert(entry->format == format);
1788
1789 if (entry->devcap && sws->get_cap(sws, entry->devcap, &result)) {
1790 assert(format < SVGA3D_UYVY || entry->defaultOperations == 0);
1791 caps->value = result.u;
1792 } else {
1793 /* Implicitly advertised format -- use default caps */
1794 caps->value = entry->defaultOperations;
1795 }
1796 }
1797
1798
1799 /*
1800 * Get DX format capabilities from VGPU10 device.
1801 */
1802 static void
1803 svga_get_dx_format_cap(struct svga_screen *ss,
1804 SVGA3dSurfaceFormat format,
1805 SVGA3dDevCapResult *caps)
1806 {
1807 struct svga_winsys_screen *sws = ss->sws;
1808 const struct format_cap *entry;
1809
1810 #ifdef DEBUG
1811 check_format_tables();
1812 #else
1813 (void) check_format_tables;
1814 #endif
1815
1816 assert(sws->have_vgpu10);
1817 assert(format < ARRAY_SIZE(format_cap_table));
1818 entry = &format_cap_table[format];
1819 assert(entry->format == format);
1820 assert(entry->devcap > SVGA3D_DEVCAP_DXCONTEXT);
1821
1822 caps->u = 0;
1823 if (entry->devcap) {
1824 sws->get_cap(sws, entry->devcap, caps);
1825
1826 /* pre-SM41 capabable svga device supports SHADER_SAMPLE capability for
1827 * these formats but does not advertise the devcap.
1828 * So enable this bit here.
1829 */
1830 if (!sws->have_sm4_1 &&
1831 (format == SVGA3D_R32_FLOAT_X8X24 ||
1832 format == SVGA3D_R24_UNORM_X8)) {
1833 caps->u |= SVGA3D_DXFMT_SHADER_SAMPLE;
1834 }
1835 }
1836
1837 if (0) {
1838 debug_printf("Format %s, devcap %s = 0x%x (%s)\n",
1839 svga_format_name(format),
1840 svga_devcap_name(entry->devcap),
1841 caps->u,
1842 svga_devcap_format_flags(caps->u));
1843 }
1844 }
1845
1846
1847 void
1848 svga_format_size(SVGA3dSurfaceFormat format,
1849 unsigned *block_width,
1850 unsigned *block_height,
1851 unsigned *bytes_per_block)
1852 {
1853 assert(format < ARRAY_SIZE(format_cap_table));
1854 *block_width = format_cap_table[format].block_width;
1855 *block_height = format_cap_table[format].block_height;
1856 *bytes_per_block = format_cap_table[format].block_bytes;
1857 /* Make sure the table entry was valid */
1858 if (*block_width == 0)
1859 debug_printf("Bad table entry for %s\n", svga_format_name(format));
1860 assert(*block_width);
1861 assert(*block_height);
1862 assert(*bytes_per_block);
1863 }
1864
1865
1866 const char *
1867 svga_format_name(SVGA3dSurfaceFormat format)
1868 {
1869 assert(format < ARRAY_SIZE(format_cap_table));
1870 return format_cap_table[format].name;
1871 }
1872
1873
1874 /**
1875 * Is the given SVGA3dSurfaceFormat a signed or unsigned integer color format?
1876 */
1877 boolean
1878 svga_format_is_integer(SVGA3dSurfaceFormat format)
1879 {
1880 switch (format) {
1881 case SVGA3D_R32G32B32A32_SINT:
1882 case SVGA3D_R32G32B32_SINT:
1883 case SVGA3D_R32G32_SINT:
1884 case SVGA3D_R32_SINT:
1885 case SVGA3D_R16G16B16A16_SINT:
1886 case SVGA3D_R16G16_SINT:
1887 case SVGA3D_R16_SINT:
1888 case SVGA3D_R8G8B8A8_SINT:
1889 case SVGA3D_R8G8_SINT:
1890 case SVGA3D_R8_SINT:
1891 case SVGA3D_R32G32B32A32_UINT:
1892 case SVGA3D_R32G32B32_UINT:
1893 case SVGA3D_R32G32_UINT:
1894 case SVGA3D_R32_UINT:
1895 case SVGA3D_R16G16B16A16_UINT:
1896 case SVGA3D_R16G16_UINT:
1897 case SVGA3D_R16_UINT:
1898 case SVGA3D_R8G8B8A8_UINT:
1899 case SVGA3D_R8G8_UINT:
1900 case SVGA3D_R8_UINT:
1901 case SVGA3D_R10G10B10A2_UINT:
1902 return TRUE;
1903 default:
1904 return FALSE;
1905 }
1906 }
1907
1908 boolean
1909 svga_format_support_gen_mips(enum pipe_format format)
1910 {
1911 assert(format < ARRAY_SIZE(format_conversion_table));
1912 return ((format_conversion_table[format].flags & TF_GEN_MIPS) > 0);
1913 }
1914
1915
1916 /**
1917 * Given a texture format, return the expected data type returned from
1918 * the texture sampler. For example, UNORM8 formats return floating point
1919 * values while SINT formats returned signed integer values.
1920 * Note: this function could be moved into the gallum u_format.[ch] code
1921 * if it's useful to anyone else.
1922 */
1923 enum tgsi_return_type
1924 svga_get_texture_datatype(enum pipe_format format)
1925 {
1926 const struct util_format_description *desc = util_format_description(format);
1927 enum tgsi_return_type t;
1928
1929 if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN ) {
1930 if (util_format_is_depth_or_stencil(format)) {
1931 t = TGSI_RETURN_TYPE_FLOAT; /* XXX revisit this */
1932 }
1933 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_FLOAT) {
1934 t = TGSI_RETURN_TYPE_FLOAT;
1935 }
1936 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1937 t = desc->channel[0].normalized ? TGSI_RETURN_TYPE_UNORM : TGSI_RETURN_TYPE_UINT;
1938 }
1939 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
1940 t = desc->channel[0].normalized ? TGSI_RETURN_TYPE_SNORM : TGSI_RETURN_TYPE_SINT;
1941 }
1942 else {
1943 assert(!"Unexpected channel type in svga_get_texture_datatype()");
1944 t = TGSI_RETURN_TYPE_FLOAT;
1945 }
1946 }
1947 else {
1948 /* compressed format, shared exponent format, etc. */
1949 switch (format) {
1950 case PIPE_FORMAT_DXT1_RGB:
1951 case PIPE_FORMAT_DXT1_RGBA:
1952 case PIPE_FORMAT_DXT3_RGBA:
1953 case PIPE_FORMAT_DXT5_RGBA:
1954 case PIPE_FORMAT_DXT1_SRGB:
1955 case PIPE_FORMAT_DXT1_SRGBA:
1956 case PIPE_FORMAT_DXT3_SRGBA:
1957 case PIPE_FORMAT_DXT5_SRGBA:
1958 case PIPE_FORMAT_RGTC1_UNORM:
1959 case PIPE_FORMAT_RGTC2_UNORM:
1960 case PIPE_FORMAT_LATC1_UNORM:
1961 case PIPE_FORMAT_LATC2_UNORM:
1962 case PIPE_FORMAT_ETC1_RGB8:
1963 t = TGSI_RETURN_TYPE_UNORM;
1964 break;
1965 case PIPE_FORMAT_RGTC1_SNORM:
1966 case PIPE_FORMAT_RGTC2_SNORM:
1967 case PIPE_FORMAT_LATC1_SNORM:
1968 case PIPE_FORMAT_LATC2_SNORM:
1969 case PIPE_FORMAT_R10G10B10X2_SNORM:
1970 t = TGSI_RETURN_TYPE_SNORM;
1971 break;
1972 case PIPE_FORMAT_R11G11B10_FLOAT:
1973 case PIPE_FORMAT_R9G9B9E5_FLOAT:
1974 t = TGSI_RETURN_TYPE_FLOAT;
1975 break;
1976 default:
1977 assert(!"Unexpected channel type in svga_get_texture_datatype()");
1978 t = TGSI_RETURN_TYPE_FLOAT;
1979 }
1980 }
1981
1982 return t;
1983 }
1984
1985
1986 /**
1987 * Given an svga context, return true iff there are currently any integer color
1988 * buffers attached to the framebuffer.
1989 */
1990 boolean
1991 svga_has_any_integer_cbufs(const struct svga_context *svga)
1992 {
1993 unsigned i;
1994 for (i = 0; i < PIPE_MAX_COLOR_BUFS; ++i) {
1995 struct pipe_surface *cbuf = svga->curr.framebuffer.cbufs[i];
1996
1997 if (cbuf && util_format_is_pure_integer(cbuf->format)) {
1998 return TRUE;
1999 }
2000 }
2001 return FALSE;
2002 }
2003
2004
2005 /**
2006 * Given an SVGA format, return the corresponding typeless format.
2007 * If there is no typeless format, return the format unchanged.
2008 */
2009 SVGA3dSurfaceFormat
2010 svga_typeless_format(SVGA3dSurfaceFormat format)
2011 {
2012 switch (format) {
2013 case SVGA3D_R32G32B32A32_UINT:
2014 case SVGA3D_R32G32B32A32_SINT:
2015 case SVGA3D_R32G32B32A32_FLOAT:
2016 return SVGA3D_R32G32B32A32_TYPELESS;
2017 case SVGA3D_R32G32B32_FLOAT:
2018 case SVGA3D_R32G32B32_UINT:
2019 case SVGA3D_R32G32B32_SINT:
2020 return SVGA3D_R32G32B32_TYPELESS;
2021 case SVGA3D_R16G16B16A16_UINT:
2022 case SVGA3D_R16G16B16A16_UNORM:
2023 case SVGA3D_R16G16B16A16_SNORM:
2024 case SVGA3D_R16G16B16A16_SINT:
2025 case SVGA3D_R16G16B16A16_FLOAT:
2026 return SVGA3D_R16G16B16A16_TYPELESS;
2027 case SVGA3D_R32G32_UINT:
2028 case SVGA3D_R32G32_SINT:
2029 case SVGA3D_R32G32_FLOAT:
2030 return SVGA3D_R32G32_TYPELESS;
2031 case SVGA3D_D32_FLOAT_S8X24_UINT:
2032 case SVGA3D_X32_G8X24_UINT:
2033 case SVGA3D_R32G8X24_TYPELESS:
2034 return SVGA3D_R32G8X24_TYPELESS;
2035 case SVGA3D_R10G10B10A2_UINT:
2036 case SVGA3D_R10G10B10A2_UNORM:
2037 return SVGA3D_R10G10B10A2_TYPELESS;
2038 case SVGA3D_R8G8B8A8_UNORM:
2039 case SVGA3D_R8G8B8A8_SNORM:
2040 case SVGA3D_R8G8B8A8_UNORM_SRGB:
2041 case SVGA3D_R8G8B8A8_UINT:
2042 case SVGA3D_R8G8B8A8_SINT:
2043 case SVGA3D_R8G8B8A8_TYPELESS:
2044 return SVGA3D_R8G8B8A8_TYPELESS;
2045 case SVGA3D_R16G16_UINT:
2046 case SVGA3D_R16G16_SINT:
2047 case SVGA3D_R16G16_UNORM:
2048 case SVGA3D_R16G16_SNORM:
2049 case SVGA3D_R16G16_FLOAT:
2050 return SVGA3D_R16G16_TYPELESS;
2051 case SVGA3D_D32_FLOAT:
2052 case SVGA3D_R32_FLOAT:
2053 case SVGA3D_R32_UINT:
2054 case SVGA3D_R32_SINT:
2055 case SVGA3D_R32_TYPELESS:
2056 return SVGA3D_R32_TYPELESS;
2057 case SVGA3D_D24_UNORM_S8_UINT:
2058 case SVGA3D_R24G8_TYPELESS:
2059 return SVGA3D_R24G8_TYPELESS;
2060 case SVGA3D_X24_G8_UINT:
2061 return SVGA3D_R24_UNORM_X8;
2062 case SVGA3D_R8G8_UNORM:
2063 case SVGA3D_R8G8_SNORM:
2064 case SVGA3D_R8G8_UINT:
2065 case SVGA3D_R8G8_SINT:
2066 return SVGA3D_R8G8_TYPELESS;
2067 case SVGA3D_D16_UNORM:
2068 case SVGA3D_R16_UNORM:
2069 case SVGA3D_R16_UINT:
2070 case SVGA3D_R16_SNORM:
2071 case SVGA3D_R16_SINT:
2072 case SVGA3D_R16_FLOAT:
2073 case SVGA3D_R16_TYPELESS:
2074 return SVGA3D_R16_TYPELESS;
2075 case SVGA3D_R8_UNORM:
2076 case SVGA3D_R8_UINT:
2077 case SVGA3D_R8_SNORM:
2078 case SVGA3D_R8_SINT:
2079 return SVGA3D_R8_TYPELESS;
2080 case SVGA3D_B8G8R8A8_UNORM_SRGB:
2081 case SVGA3D_B8G8R8A8_UNORM:
2082 case SVGA3D_B8G8R8A8_TYPELESS:
2083 return SVGA3D_B8G8R8A8_TYPELESS;
2084 case SVGA3D_B8G8R8X8_UNORM_SRGB:
2085 case SVGA3D_B8G8R8X8_UNORM:
2086 case SVGA3D_B8G8R8X8_TYPELESS:
2087 return SVGA3D_B8G8R8X8_TYPELESS;
2088 case SVGA3D_BC1_UNORM:
2089 case SVGA3D_BC1_UNORM_SRGB:
2090 case SVGA3D_BC1_TYPELESS:
2091 return SVGA3D_BC1_TYPELESS;
2092 case SVGA3D_BC2_UNORM:
2093 case SVGA3D_BC2_UNORM_SRGB:
2094 case SVGA3D_BC2_TYPELESS:
2095 return SVGA3D_BC2_TYPELESS;
2096 case SVGA3D_BC3_UNORM:
2097 case SVGA3D_BC3_UNORM_SRGB:
2098 case SVGA3D_BC3_TYPELESS:
2099 return SVGA3D_BC3_TYPELESS;
2100 case SVGA3D_BC4_UNORM:
2101 case SVGA3D_BC4_SNORM:
2102 return SVGA3D_BC4_TYPELESS;
2103 case SVGA3D_BC5_UNORM:
2104 case SVGA3D_BC5_SNORM:
2105 return SVGA3D_BC5_TYPELESS;
2106
2107 /* Special cases (no corresponding _TYPELESS formats) */
2108 case SVGA3D_A8_UNORM:
2109 case SVGA3D_B5G5R5A1_UNORM:
2110 case SVGA3D_B5G6R5_UNORM:
2111 case SVGA3D_R11G11B10_FLOAT:
2112 case SVGA3D_R9G9B9E5_SHAREDEXP:
2113 return format;
2114 default:
2115 debug_printf("Unexpected format %s in %s\n",
2116 svga_format_name(format), __FUNCTION__);
2117 return format;
2118 }
2119 }
2120
2121
2122 /**
2123 * Given a surface format, return the corresponding format to use for
2124 * a texture sampler. In most cases, it's the format unchanged, but there
2125 * are some special cases.
2126 */
2127 SVGA3dSurfaceFormat
2128 svga_sampler_format(SVGA3dSurfaceFormat format)
2129 {
2130 switch (format) {
2131 case SVGA3D_D16_UNORM:
2132 return SVGA3D_R16_UNORM;
2133 case SVGA3D_D24_UNORM_S8_UINT:
2134 return SVGA3D_R24_UNORM_X8;
2135 case SVGA3D_D32_FLOAT:
2136 return SVGA3D_R32_FLOAT;
2137 case SVGA3D_D32_FLOAT_S8X24_UINT:
2138 return SVGA3D_R32_FLOAT_X8X24;
2139 default:
2140 return format;
2141 }
2142 }
2143
2144
2145 /**
2146 * Is the given format an uncompressed snorm format?
2147 */
2148 bool
2149 svga_format_is_uncompressed_snorm(SVGA3dSurfaceFormat format)
2150 {
2151 switch (format) {
2152 case SVGA3D_R8G8B8A8_SNORM:
2153 case SVGA3D_R8G8_SNORM:
2154 case SVGA3D_R8_SNORM:
2155 case SVGA3D_R16G16B16A16_SNORM:
2156 case SVGA3D_R16G16_SNORM:
2157 case SVGA3D_R16_SNORM:
2158 return true;
2159 default:
2160 return false;
2161 }
2162 }
2163
2164
2165 bool
2166 svga_format_is_typeless(SVGA3dSurfaceFormat format)
2167 {
2168 switch (format) {
2169 case SVGA3D_R32G32B32A32_TYPELESS:
2170 case SVGA3D_R32G32B32_TYPELESS:
2171 case SVGA3D_R16G16B16A16_TYPELESS:
2172 case SVGA3D_R32G32_TYPELESS:
2173 case SVGA3D_R32G8X24_TYPELESS:
2174 case SVGA3D_R10G10B10A2_TYPELESS:
2175 case SVGA3D_R8G8B8A8_TYPELESS:
2176 case SVGA3D_R16G16_TYPELESS:
2177 case SVGA3D_R32_TYPELESS:
2178 case SVGA3D_R24G8_TYPELESS:
2179 case SVGA3D_R8G8_TYPELESS:
2180 case SVGA3D_R16_TYPELESS:
2181 case SVGA3D_R8_TYPELESS:
2182 case SVGA3D_BC1_TYPELESS:
2183 case SVGA3D_BC2_TYPELESS:
2184 case SVGA3D_BC3_TYPELESS:
2185 case SVGA3D_BC4_TYPELESS:
2186 case SVGA3D_BC5_TYPELESS:
2187 case SVGA3D_B8G8R8A8_TYPELESS:
2188 case SVGA3D_B8G8R8X8_TYPELESS:
2189 return true;
2190 default:
2191 return false;
2192 }
2193 }
2194
2195
2196 /**
2197 * \brief Can we import a surface with a given SVGA3D format as a texture?
2198 *
2199 * \param ss[in] pointer to the svga screen.
2200 * \param pformat[in] pipe format of the local texture.
2201 * \param sformat[in] svga3d format of the imported surface.
2202 * \param bind[in] bind flags of the imported texture.
2203 * \param verbose[in] Print out incompatibilities in debug mode.
2204 */
2205 bool
2206 svga_format_is_shareable(const struct svga_screen *ss,
2207 enum pipe_format pformat,
2208 SVGA3dSurfaceFormat sformat,
2209 unsigned bind,
2210 bool verbose)
2211 {
2212 SVGA3dSurfaceFormat default_format =
2213 svga_translate_format(ss, pformat, bind);
2214 int i;
2215
2216 if (default_format == SVGA3D_FORMAT_INVALID)
2217 return false;
2218 if (default_format == sformat)
2219 return true;
2220
2221 for (i = 0; i < ARRAY_SIZE(format_compats); ++i) {
2222 if (format_compats[i].pformat == pformat) {
2223 const SVGA3dSurfaceFormat *compat_format =
2224 format_compats[i].compat_format;
2225 while (*compat_format != 0) {
2226 if (*compat_format == sformat)
2227 return true;
2228 compat_format++;
2229 }
2230 }
2231 }
2232
2233 if (verbose) {
2234 debug_printf("Incompatible imported surface format.\n");
2235 debug_printf("Texture format: \"%s\". Imported format: \"%s\".\n",
2236 svga_format_name(default_format),
2237 svga_format_name(sformat));
2238 }
2239
2240 return false;
2241 }
2242
2243
2244 /**
2245 * Return the sRGB format which corresponds to the given (linear) format.
2246 * If there's no such sRGB format, return the format as-is.
2247 */
2248 SVGA3dSurfaceFormat
2249 svga_linear_to_srgb(SVGA3dSurfaceFormat format)
2250 {
2251 switch (format) {
2252 case SVGA3D_R8G8B8A8_UNORM:
2253 return SVGA3D_R8G8B8A8_UNORM_SRGB;
2254 case SVGA3D_BC1_UNORM:
2255 return SVGA3D_BC1_UNORM_SRGB;
2256 case SVGA3D_BC2_UNORM:
2257 return SVGA3D_BC2_UNORM_SRGB;
2258 case SVGA3D_BC3_UNORM:
2259 return SVGA3D_BC3_UNORM_SRGB;
2260 case SVGA3D_B8G8R8A8_UNORM:
2261 return SVGA3D_B8G8R8A8_UNORM_SRGB;
2262 case SVGA3D_B8G8R8X8_UNORM:
2263 return SVGA3D_B8G8R8X8_UNORM_SRGB;
2264 default:
2265 return format;
2266 }
2267 }
2268
2269
2270 /**
2271 * Implement pipe_screen::is_format_supported().
2272 * \param bindings bitmask of PIPE_BIND_x flags
2273 */
2274 boolean
2275 svga_is_format_supported(struct pipe_screen *screen,
2276 enum pipe_format format,
2277 enum pipe_texture_target target,
2278 unsigned sample_count,
2279 unsigned storage_sample_count,
2280 unsigned bindings)
2281 {
2282 struct svga_screen *ss = svga_screen(screen);
2283 SVGA3dSurfaceFormat svga_format;
2284 SVGA3dSurfaceFormatCaps caps;
2285 SVGA3dSurfaceFormatCaps mask;
2286
2287 assert(bindings);
2288 assert(!ss->sws->have_vgpu10);
2289
2290 /* Multisamples is not supported in VGPU9 device */
2291 if (sample_count > 1)
2292 return FALSE;
2293
2294 svga_format = svga_translate_format(ss, format, bindings);
2295 if (svga_format == SVGA3D_FORMAT_INVALID) {
2296 return FALSE;
2297 }
2298
2299 if (util_format_is_srgb(format) &&
2300 (bindings & PIPE_BIND_DISPLAY_TARGET)) {
2301 /* We only support sRGB rendering with vgpu10 */
2302 return FALSE;
2303 }
2304
2305 /*
2306 * Override host capabilities, so that we end up with the same
2307 * visuals for all virtual hardware implementations.
2308 */
2309 if (bindings & PIPE_BIND_DISPLAY_TARGET) {
2310 switch (svga_format) {
2311 case SVGA3D_A8R8G8B8:
2312 case SVGA3D_X8R8G8B8:
2313 case SVGA3D_R5G6B5:
2314 break;
2315
2316 /* VGPU10 formats */
2317 case SVGA3D_B8G8R8A8_UNORM:
2318 case SVGA3D_B8G8R8X8_UNORM:
2319 case SVGA3D_B5G6R5_UNORM:
2320 case SVGA3D_B8G8R8X8_UNORM_SRGB:
2321 case SVGA3D_B8G8R8A8_UNORM_SRGB:
2322 case SVGA3D_R8G8B8A8_UNORM_SRGB:
2323 break;
2324
2325 /* Often unsupported/problematic. This means we end up with the same
2326 * visuals for all virtual hardware implementations.
2327 */
2328 case SVGA3D_A4R4G4B4:
2329 case SVGA3D_A1R5G5B5:
2330 return FALSE;
2331
2332 default:
2333 return FALSE;
2334 }
2335 }
2336
2337 /*
2338 * Query the host capabilities.
2339 */
2340 svga_get_format_cap(ss, svga_format, &caps);
2341
2342 if (bindings & PIPE_BIND_RENDER_TARGET) {
2343 /* Check that the color surface is blendable, unless it's an
2344 * integer format.
2345 */
2346 if (!svga_format_is_integer(svga_format) &&
2347 (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
2348 return FALSE;
2349 }
2350 }
2351
2352 mask.value = 0;
2353 if (bindings & PIPE_BIND_RENDER_TARGET)
2354 mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
2355
2356 if (bindings & PIPE_BIND_DEPTH_STENCIL)
2357 mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
2358
2359 if (bindings & PIPE_BIND_SAMPLER_VIEW)
2360 mask.value |= SVGA3DFORMAT_OP_TEXTURE;
2361
2362 if (target == PIPE_TEXTURE_CUBE)
2363 mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
2364 else if (target == PIPE_TEXTURE_3D)
2365 mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
2366
2367 return (caps.value & mask.value) == mask.value;
2368 }
2369
2370
2371 /**
2372 * Implement pipe_screen::is_format_supported() for VGPU10 device.
2373 * \param bindings bitmask of PIPE_BIND_x flags
2374 */
2375 boolean
2376 svga_is_dx_format_supported(struct pipe_screen *screen,
2377 enum pipe_format format,
2378 enum pipe_texture_target target,
2379 unsigned sample_count,
2380 unsigned storage_sample_count,
2381 unsigned bindings)
2382 {
2383 struct svga_screen *ss = svga_screen(screen);
2384 SVGA3dSurfaceFormat svga_format;
2385 SVGA3dDevCapResult caps;
2386 unsigned int mask = 0;
2387
2388 assert(bindings);
2389 assert(ss->sws->have_vgpu10);
2390
2391 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
2392 return false;
2393
2394 if (sample_count > 1) {
2395 /* In ms_samples, if bit N is set it means that we support
2396 * multisample with N+1 samples per pixel.
2397 */
2398 if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
2399 return FALSE;
2400 }
2401 mask |= SVGA3D_DXFMT_MULTISAMPLE;
2402 }
2403
2404 /*
2405 * For VGPU10 vertex formats, skip querying host capabilities
2406 */
2407
2408 if (bindings & PIPE_BIND_VERTEX_BUFFER) {
2409 SVGA3dSurfaceFormat svga_format;
2410 unsigned flags;
2411 svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
2412 return svga_format != SVGA3D_FORMAT_INVALID;
2413 }
2414
2415 svga_format = svga_translate_format(ss, format, bindings);
2416 if (svga_format == SVGA3D_FORMAT_INVALID) {
2417 return FALSE;
2418 }
2419
2420 /*
2421 * Override host capabilities, so that we end up with the same
2422 * visuals for all virtual hardware implementations.
2423 */
2424 if (bindings & PIPE_BIND_DISPLAY_TARGET) {
2425 switch (svga_format) {
2426 case SVGA3D_A8R8G8B8:
2427 case SVGA3D_X8R8G8B8:
2428 case SVGA3D_R5G6B5:
2429 break;
2430
2431 /* VGPU10 formats */
2432 case SVGA3D_B8G8R8A8_UNORM:
2433 case SVGA3D_B8G8R8X8_UNORM:
2434 case SVGA3D_B5G6R5_UNORM:
2435 case SVGA3D_B8G8R8X8_UNORM_SRGB:
2436 case SVGA3D_B8G8R8A8_UNORM_SRGB:
2437 case SVGA3D_R8G8B8A8_UNORM_SRGB:
2438 break;
2439
2440 /* Often unsupported/problematic. This means we end up with the same
2441 * visuals for all virtual hardware implementations.
2442 */
2443 case SVGA3D_A4R4G4B4:
2444 case SVGA3D_A1R5G5B5:
2445 return FALSE;
2446
2447 default:
2448 return FALSE;
2449 }
2450 }
2451
2452 /*
2453 * Query the host capabilities.
2454 */
2455 svga_get_dx_format_cap(ss, svga_format, &caps);
2456
2457 if (bindings & PIPE_BIND_RENDER_TARGET) {
2458 /* Check that the color surface is blendable, unless it's an
2459 * integer format.
2460 */
2461 if (!(svga_format_is_integer(svga_format) ||
2462 (caps.u & SVGA3D_DXFMT_BLENDABLE))) {
2463 return FALSE;
2464 }
2465 mask |= SVGA3D_DXFMT_COLOR_RENDERTARGET;
2466 }
2467
2468 if (bindings & PIPE_BIND_DEPTH_STENCIL)
2469 mask |= SVGA3D_DXFMT_DEPTH_RENDERTARGET;
2470
2471 switch (target) {
2472 case PIPE_TEXTURE_3D:
2473 mask |= SVGA3D_DXFMT_VOLUME;
2474 break;
2475 case PIPE_TEXTURE_1D_ARRAY:
2476 case PIPE_TEXTURE_2D_ARRAY:
2477 case PIPE_TEXTURE_CUBE_ARRAY:
2478 mask |= SVGA3D_DXFMT_ARRAY;
2479 break;
2480 default:
2481 break;
2482 }
2483
2484 /* Is the format supported for rendering */
2485 if ((caps.u & mask) != mask)
2486 return FALSE;
2487
2488 if (bindings & PIPE_BIND_SAMPLER_VIEW) {
2489 SVGA3dSurfaceFormat sampler_format;
2490
2491 /* Get the sampler view format */
2492 sampler_format = svga_sampler_format(svga_format);
2493 if (sampler_format != svga_format) {
2494 caps.u = 0;
2495 svga_get_dx_format_cap(ss, sampler_format, &caps);
2496 mask &= SVGA3D_DXFMT_VOLUME;
2497 mask |= SVGA3D_DXFMT_SHADER_SAMPLE;
2498 if ((caps.u & mask) != mask)
2499 return FALSE;
2500 }
2501 }
2502
2503 return TRUE;
2504 }