1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
26 #include "pipe/p_defines.h"
27 #include "util/u_bitmask.h"
28 #include "util/u_inlines.h"
29 #include "util/u_math.h"
30 #include "util/u_memory.h"
32 #include "svga_context.h"
33 #include "svga_hw_reg.h"
37 static inline unsigned
38 svga_translate_compare_func(unsigned func
)
41 case PIPE_FUNC_NEVER
: return SVGA3D_CMP_NEVER
;
42 case PIPE_FUNC_LESS
: return SVGA3D_CMP_LESS
;
43 case PIPE_FUNC_LEQUAL
: return SVGA3D_CMP_LESSEQUAL
;
44 case PIPE_FUNC_GREATER
: return SVGA3D_CMP_GREATER
;
45 case PIPE_FUNC_GEQUAL
: return SVGA3D_CMP_GREATEREQUAL
;
46 case PIPE_FUNC_NOTEQUAL
: return SVGA3D_CMP_NOTEQUAL
;
47 case PIPE_FUNC_EQUAL
: return SVGA3D_CMP_EQUAL
;
48 case PIPE_FUNC_ALWAYS
: return SVGA3D_CMP_ALWAYS
;
51 return SVGA3D_CMP_ALWAYS
;
55 static inline unsigned
56 svga_translate_stencil_op(unsigned op
)
59 case PIPE_STENCIL_OP_KEEP
: return SVGA3D_STENCILOP_KEEP
;
60 case PIPE_STENCIL_OP_ZERO
: return SVGA3D_STENCILOP_ZERO
;
61 case PIPE_STENCIL_OP_REPLACE
: return SVGA3D_STENCILOP_REPLACE
;
62 case PIPE_STENCIL_OP_INCR
: return SVGA3D_STENCILOP_INCRSAT
;
63 case PIPE_STENCIL_OP_DECR
: return SVGA3D_STENCILOP_DECRSAT
;
64 case PIPE_STENCIL_OP_INCR_WRAP
: return SVGA3D_STENCILOP_INCR
;
65 case PIPE_STENCIL_OP_DECR_WRAP
: return SVGA3D_STENCILOP_DECR
;
66 case PIPE_STENCIL_OP_INVERT
: return SVGA3D_STENCILOP_INVERT
;
69 return SVGA3D_STENCILOP_KEEP
;
75 * Define a vgpu10 depth/stencil state object for the given
76 * svga depth/stencil state.
79 define_depth_stencil_state_object(struct svga_context
*svga
,
80 struct svga_depth_stencil_state
*ds
)
84 assert(svga_have_vgpu10(svga
));
86 ds
->id
= util_bitmask_add(svga
->ds_object_id_bm
);
88 /* spot check that these comparision tokens are the same */
89 STATIC_ASSERT(SVGA3D_COMPARISON_NEVER
== SVGA3D_CMP_NEVER
);
90 STATIC_ASSERT(SVGA3D_COMPARISON_LESS
== SVGA3D_CMP_LESS
);
91 STATIC_ASSERT(SVGA3D_COMPARISON_NOT_EQUAL
== SVGA3D_CMP_NOTEQUAL
);
93 /* Loop in case command buffer is full and we need to flush and retry */
94 for (try = 0; try < 2; try++) {
97 /* Note: we use the ds->stencil[0].enabled value for both the front
98 * and back-face enables. If single-side stencil is used, we'll have
99 * set the back state the same as the front state.
101 ret
= SVGA3D_vgpu10_DefineDepthStencilState(svga
->swc
,
108 ds
->stencil
[0].enabled
, /*f|b*/
109 ds
->stencil
[0].enabled
, /*f*/
110 ds
->stencil
[0].enabled
, /*b*/
112 ds
->stencil_writemask
,
115 ds
->stencil
[0].zfail
,
120 ds
->stencil
[1].zfail
,
122 ds
->stencil
[1].func
);
125 svga_context_flush(svga
, NULL
);
131 svga_create_depth_stencil_state(struct pipe_context
*pipe
,
132 const struct pipe_depth_stencil_alpha_state
*templ
)
134 struct svga_context
*svga
= svga_context(pipe
);
135 struct svga_depth_stencil_state
*ds
= CALLOC_STRUCT(svga_depth_stencil_state
);
140 /* Don't try to figure out CW/CCW correspondence with
141 * stencil[0]/[1] at this point. Presumably this can change as
142 * back/front face are modified.
144 ds
->stencil
[0].enabled
= templ
->stencil
[0].enabled
;
145 if (ds
->stencil
[0].enabled
) {
146 ds
->stencil
[0].func
= svga_translate_compare_func(templ
->stencil
[0].func
);
147 ds
->stencil
[0].fail
= svga_translate_stencil_op(templ
->stencil
[0].fail_op
);
148 ds
->stencil
[0].zfail
= svga_translate_stencil_op(templ
->stencil
[0].zfail_op
);
149 ds
->stencil
[0].pass
= svga_translate_stencil_op(templ
->stencil
[0].zpass_op
);
151 /* SVGA3D has one ref/mask/writemask triple shared between front &
152 * back face stencil. We really need two:
154 ds
->stencil_mask
= templ
->stencil
[0].valuemask
& 0xff;
155 ds
->stencil_writemask
= templ
->stencil
[0].writemask
& 0xff;
158 ds
->stencil
[0].func
= SVGA3D_CMP_ALWAYS
;
159 ds
->stencil
[0].fail
= SVGA3D_STENCILOP_KEEP
;
160 ds
->stencil
[0].zfail
= SVGA3D_STENCILOP_KEEP
;
161 ds
->stencil
[0].pass
= SVGA3D_STENCILOP_KEEP
;
164 ds
->stencil
[1].enabled
= templ
->stencil
[1].enabled
;
165 if (templ
->stencil
[1].enabled
) {
166 assert(templ
->stencil
[0].enabled
);
167 /* two-sided stencil */
168 ds
->stencil
[1].func
= svga_translate_compare_func(templ
->stencil
[1].func
);
169 ds
->stencil
[1].fail
= svga_translate_stencil_op(templ
->stencil
[1].fail_op
);
170 ds
->stencil
[1].zfail
= svga_translate_stencil_op(templ
->stencil
[1].zfail_op
);
171 ds
->stencil
[1].pass
= svga_translate_stencil_op(templ
->stencil
[1].zpass_op
);
173 ds
->stencil_mask
= templ
->stencil
[1].valuemask
& 0xff;
174 ds
->stencil_writemask
= templ
->stencil
[1].writemask
& 0xff;
176 if (templ
->stencil
[1].valuemask
!= templ
->stencil
[0].valuemask
) {
177 pipe_debug_message(&svga
->debug
.callback
, CONFORMANCE
,
178 "two-sided stencil mask not supported "
179 "(front=0x%x, back=0x%x)",
180 templ
->stencil
[0].valuemask
,
181 templ
->stencil
[1].valuemask
);
183 if (templ
->stencil
[1].writemask
!= templ
->stencil
[0].writemask
) {
184 pipe_debug_message(&svga
->debug
.callback
, CONFORMANCE
,
185 "two-sided stencil writemask not supported "
186 "(front=0x%x, back=0x%x)",
187 templ
->stencil
[0].writemask
,
188 templ
->stencil
[1].writemask
);
192 /* back face state is same as front-face state */
193 ds
->stencil
[1].func
= ds
->stencil
[0].func
;
194 ds
->stencil
[1].fail
= ds
->stencil
[0].fail
;
195 ds
->stencil
[1].zfail
= ds
->stencil
[0].zfail
;
196 ds
->stencil
[1].pass
= ds
->stencil
[0].pass
;
200 ds
->zenable
= templ
->depth
.enabled
;
202 ds
->zfunc
= svga_translate_compare_func(templ
->depth
.func
);
203 ds
->zwriteenable
= templ
->depth
.writemask
;
206 ds
->zfunc
= SVGA3D_CMP_ALWAYS
;
209 ds
->alphatestenable
= templ
->alpha
.enabled
;
210 if (ds
->alphatestenable
) {
211 ds
->alphafunc
= svga_translate_compare_func(templ
->alpha
.func
);
212 ds
->alpharef
= templ
->alpha
.ref_value
;
215 ds
->alphafunc
= SVGA3D_CMP_ALWAYS
;
218 if (svga_have_vgpu10(svga
)) {
219 define_depth_stencil_state_object(svga
, ds
);
222 svga
->hud
.num_depthstencil_objects
++;
224 SVGA_STATS_COUNT_INC(svga_screen(svga
->pipe
.screen
)->sws
,
225 SVGA_STATS_COUNT_DEPTHSTENCILSTATE
);
232 svga_bind_depth_stencil_state(struct pipe_context
*pipe
, void *depth_stencil
)
234 struct svga_context
*svga
= svga_context(pipe
);
236 if (svga_have_vgpu10(svga
)) {
237 /* flush any previously queued drawing before changing state */
238 svga_hwtnl_flush_retry(svga
);
241 svga
->curr
.depth
= (const struct svga_depth_stencil_state
*)depth_stencil
;
242 svga
->dirty
|= SVGA_NEW_DEPTH_STENCIL_ALPHA
;
247 svga_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth_stencil
)
249 struct svga_context
*svga
= svga_context(pipe
);
250 struct svga_depth_stencil_state
*ds
=
251 (struct svga_depth_stencil_state
*) depth_stencil
;
253 if (svga_have_vgpu10(svga
)) {
256 svga_hwtnl_flush_retry(svga
);
258 assert(ds
->id
!= SVGA3D_INVALID_ID
);
260 ret
= SVGA3D_vgpu10_DestroyDepthStencilState(svga
->swc
, ds
->id
);
261 if (ret
!= PIPE_OK
) {
262 svga_context_flush(svga
, NULL
);
263 ret
= SVGA3D_vgpu10_DestroyDepthStencilState(svga
->swc
, ds
->id
);
264 assert(ret
== PIPE_OK
);
267 if (ds
->id
== svga
->state
.hw_draw
.depth_stencil_id
)
268 svga
->state
.hw_draw
.depth_stencil_id
= SVGA3D_INVALID_ID
;
270 util_bitmask_clear(svga
->ds_object_id_bm
, ds
->id
);
271 ds
->id
= SVGA3D_INVALID_ID
;
275 svga
->hud
.num_depthstencil_objects
--;
280 svga_set_stencil_ref(struct pipe_context
*pipe
,
281 const struct pipe_stencil_ref
*stencil_ref
)
283 struct svga_context
*svga
= svga_context(pipe
);
285 if (svga_have_vgpu10(svga
)) {
286 /* flush any previously queued drawing before changing state */
287 svga_hwtnl_flush_retry(svga
);
290 svga
->curr
.stencil_ref
= *stencil_ref
;
292 svga
->dirty
|= SVGA_NEW_STENCIL_REF
;
297 svga_set_sample_mask(struct pipe_context
*pipe
,
298 unsigned sample_mask
)
300 struct svga_context
*svga
= svga_context(pipe
);
302 svga
->curr
.sample_mask
= sample_mask
;
304 svga
->dirty
|= SVGA_NEW_BLEND
; /* See emit_rss_vgpu10() */
309 svga_set_min_samples(struct pipe_context
*pipe
, unsigned min_samples
)
311 /* This specifies the minimum number of times the fragment shader
312 * must run when doing per-sample shading for a MSAA render target.
313 * For our SVGA3D device, the FS is automatically run in per-sample
314 * mode if it uses the sample ID or sample position registers.
320 svga_init_depth_stencil_functions(struct svga_context
*svga
)
322 svga
->pipe
.create_depth_stencil_alpha_state
= svga_create_depth_stencil_state
;
323 svga
->pipe
.bind_depth_stencil_alpha_state
= svga_bind_depth_stencil_state
;
324 svga
->pipe
.delete_depth_stencil_alpha_state
= svga_delete_depth_stencil_state
;
326 svga
->pipe
.set_stencil_ref
= svga_set_stencil_ref
;
327 svga
->pipe
.set_sample_mask
= svga_set_sample_mask
;
328 svga
->pipe
.set_min_samples
= svga_set_min_samples
;