u_blitter: add a msaa parameter to util_blitter_clear
[mesa.git] / src / gallium / drivers / svga / svga_pipe_rasterizer.c
1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
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11 *
12 * The above copyright notice and this permission notice shall be
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14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
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24 **********************************************************/
25
26 #include "pipe/p_defines.h"
27 #include "draw/draw_context.h"
28 #include "util/u_bitmask.h"
29 #include "util/u_inlines.h"
30 #include "util/u_math.h"
31 #include "util/u_memory.h"
32
33 #include "svga_cmd.h"
34 #include "svga_context.h"
35 #include "svga_hw_reg.h"
36 #include "svga_screen.h"
37
38
39 /* Hardware frontwinding is always set up as SVGA3D_FRONTWINDING_CW.
40 */
41 static SVGA3dFace
42 svga_translate_cullmode(unsigned mode, unsigned front_ccw)
43 {
44 const int hw_front_ccw = 0; /* hardware is always CW */
45 switch (mode) {
46 case PIPE_FACE_NONE:
47 return SVGA3D_FACE_NONE;
48 case PIPE_FACE_FRONT:
49 return front_ccw == hw_front_ccw ? SVGA3D_FACE_FRONT : SVGA3D_FACE_BACK;
50 case PIPE_FACE_BACK:
51 return front_ccw == hw_front_ccw ? SVGA3D_FACE_BACK : SVGA3D_FACE_FRONT;
52 case PIPE_FACE_FRONT_AND_BACK:
53 return SVGA3D_FACE_FRONT_BACK;
54 default:
55 assert(0);
56 return SVGA3D_FACE_NONE;
57 }
58 }
59
60 static SVGA3dShadeMode
61 svga_translate_flatshade(unsigned mode)
62 {
63 return mode ? SVGA3D_SHADEMODE_FLAT : SVGA3D_SHADEMODE_SMOOTH;
64 }
65
66
67 static unsigned
68 translate_fill_mode(unsigned fill)
69 {
70 switch (fill) {
71 case PIPE_POLYGON_MODE_POINT:
72 return SVGA3D_FILLMODE_POINT;
73 case PIPE_POLYGON_MODE_LINE:
74 return SVGA3D_FILLMODE_LINE;
75 case PIPE_POLYGON_MODE_FILL:
76 return SVGA3D_FILLMODE_FILL;
77 default:
78 assert(!"Bad fill mode");
79 return SVGA3D_FILLMODE_FILL;
80 }
81 }
82
83
84 static unsigned
85 translate_cull_mode(unsigned cull)
86 {
87 switch (cull) {
88 case PIPE_FACE_NONE:
89 return SVGA3D_CULL_NONE;
90 case PIPE_FACE_FRONT:
91 return SVGA3D_CULL_FRONT;
92 case PIPE_FACE_BACK:
93 return SVGA3D_CULL_BACK;
94 case PIPE_FACE_FRONT_AND_BACK:
95 /* NOTE: we simply no-op polygon drawing in svga_draw_vbo() */
96 return SVGA3D_CULL_NONE;
97 default:
98 assert(!"Bad cull mode");
99 return SVGA3D_CULL_NONE;
100 }
101 }
102
103
104 static void
105 define_rasterizer_object(struct svga_context *svga,
106 struct svga_rasterizer_state *rast)
107 {
108 struct svga_screen *svgascreen = svga_screen(svga->pipe.screen);
109 unsigned fill_mode = translate_fill_mode(rast->templ.fill_front);
110 const unsigned cull_mode = translate_cull_mode(rast->templ.cull_face);
111 const int depth_bias = rast->templ.offset_units;
112 const float slope_scaled_depth_bias = rast->templ.offset_scale;
113 /* PIPE_CAP_POLYGON_OFFSET_CLAMP not supported: */
114 const float depth_bias_clamp = 0.0;
115 const float line_width = rast->templ.line_width > 0.0f ?
116 rast->templ.line_width : 1.0f;
117 const uint8 line_factor = rast->templ.line_stipple_enable ?
118 rast->templ.line_stipple_factor : 0;
119 const uint16 line_pattern = rast->templ.line_stipple_enable ?
120 rast->templ.line_stipple_pattern : 0;
121 unsigned try;
122
123 rast->id = util_bitmask_add(svga->rast_object_id_bm);
124
125 if (rast->templ.fill_front != rast->templ.fill_back) {
126 /* The VGPU10 device can't handle different front/back fill modes.
127 * We'll handle that with a swtnl/draw fallback. But we need to
128 * make sure we always fill triangles in that case.
129 */
130 fill_mode = SVGA3D_FILLMODE_FILL;
131 }
132
133 for (try = 0; try < 2; try++) {
134 const uint8 pv_last = !rast->templ.flatshade_first &&
135 svgascreen->haveProvokingVertex;
136 enum pipe_error ret =
137 SVGA3D_vgpu10_DefineRasterizerState(svga->swc,
138 rast->id,
139 fill_mode,
140 cull_mode,
141 rast->templ.front_ccw,
142 depth_bias,
143 depth_bias_clamp,
144 slope_scaled_depth_bias,
145 rast->templ.depth_clip_near,
146 rast->templ.scissor,
147 rast->templ.multisample,
148 rast->templ.line_smooth,
149 line_width,
150 rast->templ.line_stipple_enable,
151 line_factor,
152 line_pattern,
153 pv_last);
154 if (ret == PIPE_OK)
155 return;
156 svga_context_flush(svga, NULL);
157 }
158 }
159
160
161 static void *
162 svga_create_rasterizer_state(struct pipe_context *pipe,
163 const struct pipe_rasterizer_state *templ)
164 {
165 struct svga_context *svga = svga_context(pipe);
166 struct svga_rasterizer_state *rast = CALLOC_STRUCT(svga_rasterizer_state);
167 struct svga_screen *screen = svga_screen(pipe->screen);
168
169 if (!rast)
170 return NULL;
171
172 /* need this for draw module. */
173 rast->templ = *templ;
174
175 rast->shademode = svga_translate_flatshade(templ->flatshade);
176 rast->cullmode = svga_translate_cullmode(templ->cull_face, templ->front_ccw);
177 rast->scissortestenable = templ->scissor;
178 rast->multisampleantialias = templ->multisample;
179 rast->antialiasedlineenable = templ->line_smooth;
180 rast->lastpixel = templ->line_last_pixel;
181 rast->pointsprite = templ->point_quad_rasterization;
182
183 if (rast->templ.multisample) {
184 /* The OpenGL 3.0 spec says points are always drawn as circles when
185 * MSAA is enabled. Note that our implementation isn't 100% correct,
186 * though. Our smooth point implementation involves drawing a square,
187 * computing fragment distance from point center, then attenuating
188 * the fragment alpha value. We should not attenuate alpha if msaa
189 * is enabled. We should kill fragments entirely outside the circle
190 * and let the GPU compute per-fragment coverage.
191 * But as-is, our implementation gives acceptable results and passes
192 * Piglit's MSAA point smooth test.
193 */
194 rast->templ.point_smooth = TRUE;
195 }
196
197 if (templ->point_smooth) {
198 /* For smooth points we need to generate fragments for at least
199 * a 2x2 region. Otherwise the quad we draw may be too small and
200 * we may generate no fragments at all.
201 */
202 rast->pointsize = MAX2(2.0f, templ->point_size);
203 }
204 else {
205 rast->pointsize = templ->point_size;
206 }
207
208 rast->hw_fillmode = PIPE_POLYGON_MODE_FILL;
209
210 /* Use swtnl + decomposition implement these:
211 */
212
213 if (templ->line_width <= screen->maxLineWidth) {
214 /* pass line width to device */
215 rast->linewidth = MAX2(1.0F, templ->line_width);
216 }
217 else if (svga->debug.no_line_width) {
218 /* nothing */
219 }
220 else {
221 /* use 'draw' pipeline for wide line */
222 rast->need_pipeline |= SVGA_PIPELINE_FLAG_LINES;
223 rast->need_pipeline_lines_str = "line width";
224 }
225
226 if (templ->line_stipple_enable) {
227 if (screen->haveLineStipple || svga->debug.force_hw_line_stipple) {
228 SVGA3dLinePattern lp;
229 lp.repeat = templ->line_stipple_factor + 1;
230 lp.pattern = templ->line_stipple_pattern;
231 rast->linepattern = lp.uintValue;
232 }
233 else {
234 /* use 'draw' module to decompose into short line segments */
235 rast->need_pipeline |= SVGA_PIPELINE_FLAG_LINES;
236 rast->need_pipeline_lines_str = "line stipple";
237 }
238 }
239
240 if (!svga_have_vgpu10(svga) && templ->point_smooth) {
241 rast->need_pipeline |= SVGA_PIPELINE_FLAG_POINTS;
242 rast->need_pipeline_points_str = "smooth points";
243 }
244
245 if (templ->line_smooth && !screen->haveLineSmooth) {
246 /*
247 * XXX: Enabling the pipeline slows down performance immensely, so ignore
248 * line smooth state, where there is very little visual improvement.
249 * Smooth lines will still be drawn for wide lines.
250 */
251 #if 0
252 rast->need_pipeline |= SVGA_PIPELINE_FLAG_LINES;
253 rast->need_pipeline_lines_str = "smooth lines";
254 #endif
255 }
256
257 {
258 int fill_front = templ->fill_front;
259 int fill_back = templ->fill_back;
260 int fill = PIPE_POLYGON_MODE_FILL;
261 boolean offset_front = util_get_offset(templ, fill_front);
262 boolean offset_back = util_get_offset(templ, fill_back);
263 boolean offset = FALSE;
264
265 switch (templ->cull_face) {
266 case PIPE_FACE_FRONT_AND_BACK:
267 offset = FALSE;
268 fill = PIPE_POLYGON_MODE_FILL;
269 break;
270
271 case PIPE_FACE_FRONT:
272 offset = offset_back;
273 fill = fill_back;
274 break;
275
276 case PIPE_FACE_BACK:
277 offset = offset_front;
278 fill = fill_front;
279 break;
280
281 case PIPE_FACE_NONE:
282 if (fill_front != fill_back || offset_front != offset_back) {
283 /* Always need the draw module to work out different
284 * front/back fill modes:
285 */
286 rast->need_pipeline |= SVGA_PIPELINE_FLAG_TRIS;
287 rast->need_pipeline_tris_str = "different front/back fillmodes";
288 fill = PIPE_POLYGON_MODE_FILL;
289 }
290 else {
291 offset = offset_front;
292 fill = fill_front;
293 }
294 break;
295
296 default:
297 assert(0);
298 break;
299 }
300
301 /* Unfilled primitive modes aren't implemented on all virtual
302 * hardware. We can do some unfilled processing with index
303 * translation, but otherwise need the draw module:
304 */
305 if (fill != PIPE_POLYGON_MODE_FILL &&
306 (templ->flatshade ||
307 templ->light_twoside ||
308 offset)) {
309 fill = PIPE_POLYGON_MODE_FILL;
310 rast->need_pipeline |= SVGA_PIPELINE_FLAG_TRIS;
311 rast->need_pipeline_tris_str = "unfilled primitives with no index manipulation";
312 }
313
314 /* If we are decomposing to lines, and lines need the pipeline,
315 * then we also need the pipeline for tris.
316 */
317 if (fill == PIPE_POLYGON_MODE_LINE &&
318 (rast->need_pipeline & SVGA_PIPELINE_FLAG_LINES)) {
319 fill = PIPE_POLYGON_MODE_FILL;
320 rast->need_pipeline |= SVGA_PIPELINE_FLAG_TRIS;
321 rast->need_pipeline_tris_str = "decomposing lines";
322 }
323
324 /* Similarly for points:
325 */
326 if (fill == PIPE_POLYGON_MODE_POINT &&
327 (rast->need_pipeline & SVGA_PIPELINE_FLAG_POINTS)) {
328 fill = PIPE_POLYGON_MODE_FILL;
329 rast->need_pipeline |= SVGA_PIPELINE_FLAG_TRIS;
330 rast->need_pipeline_tris_str = "decomposing points";
331 }
332
333 if (offset) {
334 rast->slopescaledepthbias = templ->offset_scale;
335 rast->depthbias = templ->offset_units;
336 }
337
338 rast->hw_fillmode = fill;
339 }
340
341 if (rast->need_pipeline & SVGA_PIPELINE_FLAG_TRIS) {
342 /* Turn off stuff which will get done in the draw module:
343 */
344 rast->hw_fillmode = PIPE_POLYGON_MODE_FILL;
345 rast->slopescaledepthbias = 0;
346 rast->depthbias = 0;
347 }
348
349 if (0 && rast->need_pipeline) {
350 debug_printf("svga: rast need_pipeline = 0x%x\n", rast->need_pipeline);
351 debug_printf(" pnts: %s \n", rast->need_pipeline_points_str);
352 debug_printf(" lins: %s \n", rast->need_pipeline_lines_str);
353 debug_printf(" tris: %s \n", rast->need_pipeline_tris_str);
354 }
355
356 if (svga_have_vgpu10(svga)) {
357 define_rasterizer_object(svga, rast);
358 }
359
360 if (templ->poly_smooth) {
361 pipe_debug_message(&svga->debug.callback, CONFORMANCE,
362 "GL_POLYGON_SMOOTH not supported");
363 }
364
365 svga->hud.num_rasterizer_objects++;
366 SVGA_STATS_COUNT_INC(svga_screen(svga->pipe.screen)->sws,
367 SVGA_STATS_COUNT_RASTERIZERSTATE);
368
369 return rast;
370 }
371
372
373 static void
374 svga_bind_rasterizer_state(struct pipe_context *pipe, void *state)
375 {
376 struct svga_context *svga = svga_context(pipe);
377 struct svga_rasterizer_state *raster = (struct svga_rasterizer_state *)state;
378
379 if (!raster || !svga->curr.rast) {
380 svga->dirty |= SVGA_NEW_STIPPLE | SVGA_NEW_DEPTH_STENCIL_ALPHA;
381 }
382 else {
383 if (raster->templ.poly_stipple_enable !=
384 svga->curr.rast->templ.poly_stipple_enable) {
385 svga->dirty |= SVGA_NEW_STIPPLE;
386 }
387 if (raster->templ.rasterizer_discard !=
388 svga->curr.rast->templ.rasterizer_discard) {
389 svga->dirty |= SVGA_NEW_DEPTH_STENCIL_ALPHA;
390 }
391 }
392
393 svga->curr.rast = raster;
394
395 svga->dirty |= SVGA_NEW_RAST;
396 }
397
398
399 static void
400 svga_delete_rasterizer_state(struct pipe_context *pipe, void *state)
401 {
402 struct svga_context *svga = svga_context(pipe);
403 struct svga_rasterizer_state *raster =
404 (struct svga_rasterizer_state *) state;
405
406 if (svga_have_vgpu10(svga)) {
407 enum pipe_error ret =
408 SVGA3D_vgpu10_DestroyRasterizerState(svga->swc, raster->id);
409 if (ret != PIPE_OK) {
410 svga_context_flush(svga, NULL);
411 ret = SVGA3D_vgpu10_DestroyRasterizerState(svga->swc, raster->id);
412 }
413
414 if (raster->id == svga->state.hw_draw.rasterizer_id)
415 svga->state.hw_draw.rasterizer_id = SVGA3D_INVALID_ID;
416
417 util_bitmask_clear(svga->rast_object_id_bm, raster->id);
418 }
419
420 FREE(state);
421 svga->hud.num_rasterizer_objects--;
422 }
423
424
425 void
426 svga_init_rasterizer_functions(struct svga_context *svga)
427 {
428 svga->pipe.create_rasterizer_state = svga_create_rasterizer_state;
429 svga->pipe.bind_rasterizer_state = svga_bind_rasterizer_state;
430 svga->pipe.delete_rasterizer_state = svga_delete_rasterizer_state;
431 }