1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
28 #include "pipe/p_state.h"
29 #include "pipe/p_defines.h"
30 #include "util/u_inlines.h"
31 #include "os/os_thread.h"
32 #include "util/u_math.h"
33 #include "util/u_memory.h"
35 #include "svga_context.h"
36 #include "svga_screen.h"
37 #include "svga_resource_buffer.h"
38 #include "svga_resource_buffer_upload.h"
39 #include "svga_winsys.h"
40 #include "svga_debug.h"
44 * Vertex and index buffers need hardware backing. Constant buffers
45 * do not. No other types of buffers currently supported.
48 svga_buffer_needs_hw_storage(unsigned usage
)
50 return usage
& (PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
);
55 * Map a range of a buffer.
57 * Unlike texture DMAs (which are written immediately to the command buffer and
58 * therefore inherently serialized with other context operations), for buffers
59 * we try to coalesce multiple range mappings (i.e, multiple calls to this
60 * function) into a single DMA command, for better efficiency in command
61 * processing. This means we need to exercise extra care here to ensure that
62 * the end result is exactly the same as if one DMA was used for every mapped
66 svga_buffer_map_range( struct pipe_context
*pipe
,
67 struct pipe_resource
*buf
,
72 struct svga_context
*svga
= svga_context(pipe
);
73 struct svga_screen
*ss
= svga_screen(pipe
->screen
);
74 struct svga_winsys_screen
*sws
= ss
->sws
;
75 struct svga_buffer
*sbuf
= svga_buffer( buf
);
78 if (usage
& PIPE_TRANSFER_WRITE
) {
79 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
81 * Finish writing any pending DMA commands, and tell the host to discard
82 * the buffer contents on the next DMA operation.
85 if (sbuf
->dma
.pending
) {
86 svga_buffer_upload_flush(svga
, sbuf
);
89 * Instead of flushing the context command buffer, simply discard
90 * the current hwbuf, and start a new one.
93 svga_buffer_destroy_hw_storage(ss
, sbuf
);
96 sbuf
->map
.num_ranges
= 0;
97 sbuf
->dma
.flags
.discard
= TRUE
;
100 if (usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) {
101 if (!sbuf
->map
.num_ranges
) {
103 * No pending ranges to upload so far, so we can tell the host to
104 * not synchronize on the next DMA command.
107 sbuf
->dma
.flags
.unsynchronized
= TRUE
;
111 * Synchronizing, so finish writing any pending DMA command, and
112 * ensure the next DMA will be done in order.
115 if (sbuf
->dma
.pending
) {
116 svga_buffer_upload_flush(svga
, sbuf
);
120 * We have a pending DMA upload from a hardware buffer, therefore
121 * we need to ensure that the host finishes processing that DMA
122 * command before the state tracker can start overwriting the
125 * XXX: This could be avoided by tying the hardware buffer to
126 * the transfer (just as done with textures), which would allow
127 * overlapping DMAs commands to be queued on the same context
128 * buffer. However, due to the likelihood of software vertex
129 * processing, it is more convenient to hold on to the hardware
130 * buffer, allowing to quickly access the contents from the CPU
131 * without having to do a DMA download from the host.
134 if (usage
& PIPE_TRANSFER_DONTBLOCK
) {
136 * Flushing the command buffer here will most likely cause
137 * the map of the hwbuf below to block, so preemptively
138 * return NULL here if DONTBLOCK is set to prevent unnecessary
139 * command buffer flushes.
145 svga_context_flush(svga
, NULL
);
149 sbuf
->dma
.flags
.unsynchronized
= FALSE
;
153 if (!sbuf
->swbuf
&& !sbuf
->hwbuf
) {
154 if (svga_buffer_create_hw_storage(ss
, sbuf
) != PIPE_OK
) {
156 * We can't create a hardware buffer big enough, so create a malloc
160 debug_printf("%s: failed to allocate %u KB of DMA, "
161 "splitting DMA transfers\n",
163 (sbuf
->b
.b
.width0
+ 1023)/1024);
166 sbuf
->swbuf
= align_malloc(sbuf
->b
.b
.width0
, 16);
171 /* User/malloc buffer */
174 else if (sbuf
->hwbuf
) {
175 map
= sws
->buffer_map(sws
, sbuf
->hwbuf
, usage
);
184 if (usage
& PIPE_TRANSFER_WRITE
) {
185 assert(sbuf
->map
.count
<= 1);
186 sbuf
->map
.writing
= TRUE
;
187 if (usage
& PIPE_TRANSFER_FLUSH_EXPLICIT
)
188 sbuf
->map
.flush_explicit
= TRUE
;
198 svga_buffer_flush_mapped_range( struct pipe_context
*pipe
,
199 struct pipe_resource
*buf
,
200 unsigned offset
, unsigned length
)
202 struct svga_buffer
*sbuf
= svga_buffer( buf
);
203 struct svga_screen
*ss
= svga_screen(pipe
->screen
);
205 pipe_mutex_lock(ss
->swc_mutex
);
206 assert(sbuf
->map
.writing
);
207 if(sbuf
->map
.writing
) {
208 assert(sbuf
->map
.flush_explicit
);
209 svga_buffer_add_range(sbuf
, offset
, offset
+ length
);
211 pipe_mutex_unlock(ss
->swc_mutex
);
215 svga_buffer_unmap( struct pipe_context
*pipe
,
216 struct pipe_resource
*buf
)
218 struct svga_screen
*ss
= svga_screen(pipe
->screen
);
219 struct svga_winsys_screen
*sws
= ss
->sws
;
220 struct svga_buffer
*sbuf
= svga_buffer( buf
);
222 pipe_mutex_lock(ss
->swc_mutex
);
224 assert(sbuf
->map
.count
);
229 sws
->buffer_unmap(sws
, sbuf
->hwbuf
);
231 if (sbuf
->map
.writing
) {
232 if (!sbuf
->map
.flush_explicit
) {
234 * Mapped range not flushed explicitly, so flush the whole buffer,
235 * and tell the host to discard the contents when processing the DMA
239 SVGA_DBG(DEBUG_DMA
, "flushing the whole buffer\n");
241 sbuf
->dma
.flags
.discard
= TRUE
;
243 svga_buffer_add_range(sbuf
, 0, sbuf
->b
.b
.width0
);
246 sbuf
->map
.writing
= FALSE
;
247 sbuf
->map
.flush_explicit
= FALSE
;
250 pipe_mutex_unlock(ss
->swc_mutex
);
256 svga_buffer_destroy( struct pipe_screen
*screen
,
257 struct pipe_resource
*buf
)
259 struct svga_screen
*ss
= svga_screen(screen
);
260 struct svga_buffer
*sbuf
= svga_buffer( buf
);
262 assert(!p_atomic_read(&buf
->reference
.count
));
264 assert(!sbuf
->dma
.pending
);
267 svga_buffer_destroy_host_surface(ss
, sbuf
);
269 if(sbuf
->uploaded
.buffer
)
270 pipe_resource_reference(&sbuf
->uploaded
.buffer
, NULL
);
273 svga_buffer_destroy_hw_storage(ss
, sbuf
);
275 if(sbuf
->swbuf
&& !sbuf
->user
)
276 align_free(sbuf
->swbuf
);
282 /* Keep the original code more or less intact, implement transfers in
283 * terms of the old functions.
286 svga_buffer_transfer_map( struct pipe_context
*pipe
,
287 struct pipe_transfer
*transfer
)
289 uint8_t *map
= svga_buffer_map_range( pipe
,
297 /* map_buffer() returned a pointer to the beginning of the buffer,
298 * but transfers are expected to return a pointer to just the
299 * region specified in the box.
301 return map
+ transfer
->box
.x
;
306 static void svga_buffer_transfer_flush_region( struct pipe_context
*pipe
,
307 struct pipe_transfer
*transfer
,
308 const struct pipe_box
*box
)
310 assert(box
->x
+ box
->width
<= transfer
->box
.width
);
312 svga_buffer_flush_mapped_range(pipe
,
314 transfer
->box
.x
+ box
->x
,
318 static void svga_buffer_transfer_unmap( struct pipe_context
*pipe
,
319 struct pipe_transfer
*transfer
)
321 svga_buffer_unmap(pipe
,
331 struct u_resource_vtbl svga_buffer_vtbl
=
333 u_default_resource_get_handle
, /* get_handle */
334 svga_buffer_destroy
, /* resource_destroy */
335 u_default_get_transfer
, /* get_transfer */
336 u_default_transfer_destroy
, /* transfer_destroy */
337 svga_buffer_transfer_map
, /* transfer_map */
338 svga_buffer_transfer_flush_region
, /* transfer_flush_region */
339 svga_buffer_transfer_unmap
, /* transfer_unmap */
340 u_default_transfer_inline_write
/* transfer_inline_write */
345 struct pipe_resource
*
346 svga_buffer_create(struct pipe_screen
*screen
,
347 const struct pipe_resource
*template)
349 struct svga_screen
*ss
= svga_screen(screen
);
350 struct svga_buffer
*sbuf
;
352 sbuf
= CALLOC_STRUCT(svga_buffer
);
356 sbuf
->b
.b
= *template;
357 sbuf
->b
.vtbl
= &svga_buffer_vtbl
;
358 pipe_reference_init(&sbuf
->b
.b
.reference
, 1);
359 sbuf
->b
.b
.screen
= screen
;
361 if(svga_buffer_needs_hw_storage(template->bind
)) {
362 if(svga_buffer_create_host_surface(ss
, sbuf
) != PIPE_OK
)
366 sbuf
->swbuf
= align_malloc(template->width0
, 64);
371 debug_reference(&sbuf
->b
.b
.reference
,
372 (debug_reference_descriptor
)debug_describe_resource
, 0);
382 struct pipe_resource
*
383 svga_user_buffer_create(struct pipe_screen
*screen
,
388 struct svga_buffer
*sbuf
;
390 sbuf
= CALLOC_STRUCT(svga_buffer
);
394 pipe_reference_init(&sbuf
->b
.b
.reference
, 1);
395 sbuf
->b
.vtbl
= &svga_buffer_vtbl
;
396 sbuf
->b
.b
.screen
= screen
;
397 sbuf
->b
.b
.format
= PIPE_FORMAT_R8_UNORM
; /* ?? */
398 sbuf
->b
.b
.usage
= PIPE_USAGE_IMMUTABLE
;
399 sbuf
->b
.b
.bind
= bind
;
400 sbuf
->b
.b
.width0
= bytes
;
401 sbuf
->b
.b
.height0
= 1;
402 sbuf
->b
.b
.depth0
= 1;
403 sbuf
->b
.b
.array_size
= 1;
408 debug_reference(&sbuf
->b
.b
.reference
,
409 (debug_reference_descriptor
)debug_describe_resource
, 0);