1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
27 #include "os/os_thread.h"
28 #include "pipe/p_state.h"
29 #include "pipe/p_defines.h"
30 #include "util/u_inlines.h"
31 #include "util/u_math.h"
32 #include "util/u_memory.h"
33 #include "util/u_double_list.h"
36 #include "svga_context.h"
37 #include "svga_debug.h"
38 #include "svga_resource_buffer.h"
39 #include "svga_resource_buffer_upload.h"
40 #include "svga_screen.h"
41 #include "svga_winsys.h"
44 * Describes a complete SVGA_3D_CMD_UPDATE_GB_IMAGE command
47 struct svga_3d_update_gb_image
{
48 SVGA3dCmdHeader header
;
49 SVGA3dCmdUpdateGBImage body
;
52 struct svga_3d_invalidate_gb_image
{
53 SVGA3dCmdHeader header
;
54 SVGA3dCmdInvalidateGBImage body
;
59 * Allocate a winsys_buffer (ie. DMA, aka GMR memory).
61 * It will flush and retry in case the first attempt to create a DMA buffer
62 * fails, so it should not be called from any function involved in flushing
65 struct svga_winsys_buffer
*
66 svga_winsys_buffer_create( struct svga_context
*svga
,
71 struct svga_screen
*svgascreen
= svga_screen(svga
->pipe
.screen
);
72 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
73 struct svga_winsys_buffer
*buf
;
76 buf
= sws
->buffer_create(sws
, alignment
, usage
, size
);
78 SVGA_DBG(DEBUG_DMA
|DEBUG_PERF
, "flushing context to find %d bytes GMR\n",
81 /* Try flushing all pending DMAs */
82 svga_context_flush(svga
, NULL
);
83 buf
= sws
->buffer_create(sws
, alignment
, usage
, size
);
91 * Destroy HW storage if separate from the host surface.
92 * In the GB case, the HW storage is associated with the host surface
93 * and is therefore a No-op.
96 svga_buffer_destroy_hw_storage(struct svga_screen
*ss
, struct svga_buffer
*sbuf
)
98 struct svga_winsys_screen
*sws
= ss
->sws
;
100 assert(!sbuf
->map
.count
);
103 sws
->buffer_destroy(sws
, sbuf
->hwbuf
);
111 * Allocate DMA'ble or Updatable storage for the buffer.
113 * Called before mapping a buffer.
116 svga_buffer_create_hw_storage(struct svga_screen
*ss
,
117 struct svga_buffer
*sbuf
)
121 if (ss
->sws
->have_gb_objects
) {
122 assert(sbuf
->handle
|| !sbuf
->dma
.pending
);
123 return svga_buffer_create_host_surface(ss
, sbuf
);
126 struct svga_winsys_screen
*sws
= ss
->sws
;
127 unsigned alignment
= 16;
129 unsigned size
= sbuf
->b
.b
.width0
;
131 sbuf
->hwbuf
= sws
->buffer_create(sws
, alignment
, usage
, size
);
133 return PIPE_ERROR_OUT_OF_MEMORY
;
135 assert(!sbuf
->dma
.pending
);
144 svga_buffer_create_host_surface(struct svga_screen
*ss
,
145 struct svga_buffer
*sbuf
)
152 sbuf
->key
.format
= SVGA3D_BUFFER
;
153 if (sbuf
->b
.b
.bind
& PIPE_BIND_VERTEX_BUFFER
)
154 sbuf
->key
.flags
|= SVGA3D_SURFACE_HINT_VERTEXBUFFER
;
155 if (sbuf
->b
.b
.bind
& PIPE_BIND_INDEX_BUFFER
)
156 sbuf
->key
.flags
|= SVGA3D_SURFACE_HINT_INDEXBUFFER
;
158 sbuf
->key
.size
.width
= sbuf
->b
.b
.width0
;
159 sbuf
->key
.size
.height
= 1;
160 sbuf
->key
.size
.depth
= 1;
162 sbuf
->key
.numFaces
= 1;
163 sbuf
->key
.numMipLevels
= 1;
164 sbuf
->key
.cachable
= 1;
166 SVGA_DBG(DEBUG_DMA
, "surface_create for buffer sz %d\n", sbuf
->b
.b
.width0
);
168 sbuf
->handle
= svga_screen_surface_create(ss
, &sbuf
->key
);
170 return PIPE_ERROR_OUT_OF_MEMORY
;
172 /* Always set the discard flag on the first time the buffer is written
173 * as svga_screen_surface_create might have passed a recycled host
176 sbuf
->dma
.flags
.discard
= TRUE
;
178 SVGA_DBG(DEBUG_DMA
, " --> got sid %p sz %d (buffer)\n", sbuf
->handle
, sbuf
->b
.b
.width0
);
186 svga_buffer_destroy_host_surface(struct svga_screen
*ss
,
187 struct svga_buffer
*sbuf
)
190 SVGA_DBG(DEBUG_DMA
, " ungrab sid %p sz %d\n", sbuf
->handle
, sbuf
->b
.b
.width0
);
191 svga_screen_surface_destroy(ss
, &sbuf
->key
, &sbuf
->handle
);
197 * Insert a number of preliminary UPDATE_GB_IMAGE commands in the
198 * command buffer, equal to the current number of mapped ranges.
199 * The UPDATE_GB_IMAGE commands will be patched with the
200 * actual ranges just before flush.
202 static enum pipe_error
203 svga_buffer_upload_gb_command(struct svga_context
*svga
,
204 struct svga_buffer
*sbuf
)
206 struct svga_winsys_context
*swc
= svga
->swc
;
207 SVGA3dCmdUpdateGBImage
*cmd
;
208 struct svga_3d_update_gb_image
*ccmd
= NULL
;
209 uint32 numBoxes
= sbuf
->map
.num_ranges
;
210 struct pipe_resource
*dummy
;
214 assert(sbuf
->dma
.updates
== NULL
);
216 if (sbuf
->dma
.flags
.discard
) {
217 struct svga_3d_invalidate_gb_image
*cicmd
= NULL
;
218 SVGA3dCmdInvalidateGBImage
*icmd
;
220 /* Allocate FIFO space for one INVALIDATE_GB_IMAGE command followed by
221 * 'numBoxes' UPDATE_GB_IMAGE commands. Allocate all at once rather
222 * than with separate commands because we need to properly deal with
223 * filling the command buffer.
225 icmd
= SVGA3D_FIFOReserve(swc
,
226 SVGA_3D_CMD_INVALIDATE_GB_IMAGE
,
227 sizeof *icmd
+ numBoxes
* sizeof *ccmd
,
230 return PIPE_ERROR_OUT_OF_MEMORY
;
232 cicmd
= container_of(icmd
, cicmd
, body
);
233 cicmd
->header
.size
= sizeof *icmd
;
234 swc
->surface_relocation(swc
, &icmd
->image
.sid
, NULL
, sbuf
->handle
,
236 SVGA_RELOC_INTERNAL
|
238 icmd
->image
.face
= 0;
239 icmd
->image
.mipmap
= 0;
241 /* initialize the first UPDATE_GB_IMAGE command */
242 ccmd
= (struct svga_3d_update_gb_image
*) &icmd
[1];
243 ccmd
->header
.id
= SVGA_3D_CMD_UPDATE_GB_IMAGE
;
247 /* Allocate FIFO space for 'numBoxes' UPDATE_GB_IMAGE commands */
248 cmd
= SVGA3D_FIFOReserve(swc
,
249 SVGA_3D_CMD_UPDATE_GB_IMAGE
,
250 sizeof *cmd
+ (numBoxes
- 1) * sizeof *ccmd
,
253 return PIPE_ERROR_OUT_OF_MEMORY
;
255 ccmd
= container_of(cmd
, ccmd
, body
);
258 /* Init the first UPDATE_GB_IMAGE command */
259 ccmd
->header
.size
= sizeof *cmd
;
260 swc
->surface_relocation(swc
, &cmd
->image
.sid
, NULL
, sbuf
->handle
,
261 SVGA_RELOC_WRITE
| SVGA_RELOC_INTERNAL
);
263 cmd
->image
.mipmap
= 0;
265 /* Save pointer to the first UPDATE_GB_IMAGE command so that we can
266 * fill in the box info below.
268 sbuf
->dma
.updates
= ccmd
;
271 * Copy the relocation info, face and mipmap to all
272 * subsequent commands. NOTE: For winsyses that actually
273 * patch the image.sid member at flush time, this will fail
274 * miserably. For those we need to add as many relocations
275 * as there are copy boxes.
278 for (i
= 1; i
< numBoxes
; ++i
) {
279 memcpy(++ccmd
, sbuf
->dma
.updates
, sizeof *ccmd
);
282 /* Increment reference count */
283 sbuf
->dma
.svga
= svga
;
285 pipe_resource_reference(&dummy
, &sbuf
->b
.b
);
286 SVGA_FIFOCommitAll(swc
);
288 sbuf
->dma
.flags
.discard
= FALSE
;
295 * Variant of SVGA3D_BufferDMA which leaves the copy box temporarily in blank.
297 static enum pipe_error
298 svga_buffer_upload_command(struct svga_context
*svga
,
299 struct svga_buffer
*sbuf
)
301 struct svga_winsys_context
*swc
= svga
->swc
;
302 struct svga_winsys_buffer
*guest
= sbuf
->hwbuf
;
303 struct svga_winsys_surface
*host
= sbuf
->handle
;
304 SVGA3dTransferType transfer
= SVGA3D_WRITE_HOST_VRAM
;
305 SVGA3dCmdSurfaceDMA
*cmd
;
306 uint32 numBoxes
= sbuf
->map
.num_ranges
;
307 SVGA3dCopyBox
*boxes
;
308 SVGA3dCmdSurfaceDMASuffix
*pSuffix
;
309 unsigned region_flags
;
310 unsigned surface_flags
;
311 struct pipe_resource
*dummy
;
313 if (svga_have_gb_objects(svga
))
314 return svga_buffer_upload_gb_command(svga
, sbuf
);
316 if (transfer
== SVGA3D_WRITE_HOST_VRAM
) {
317 region_flags
= SVGA_RELOC_READ
;
318 surface_flags
= SVGA_RELOC_WRITE
;
320 else if (transfer
== SVGA3D_READ_HOST_VRAM
) {
321 region_flags
= SVGA_RELOC_WRITE
;
322 surface_flags
= SVGA_RELOC_READ
;
326 return PIPE_ERROR_BAD_INPUT
;
331 cmd
= SVGA3D_FIFOReserve(swc
,
332 SVGA_3D_CMD_SURFACE_DMA
,
333 sizeof *cmd
+ numBoxes
* sizeof *boxes
+ sizeof *pSuffix
,
336 return PIPE_ERROR_OUT_OF_MEMORY
;
338 swc
->region_relocation(swc
, &cmd
->guest
.ptr
, guest
, 0, region_flags
);
339 cmd
->guest
.pitch
= 0;
341 swc
->surface_relocation(swc
, &cmd
->host
.sid
, NULL
, host
, surface_flags
);
343 cmd
->host
.mipmap
= 0;
345 cmd
->transfer
= transfer
;
347 sbuf
->dma
.boxes
= (SVGA3dCopyBox
*)&cmd
[1];
348 sbuf
->dma
.svga
= svga
;
350 /* Increment reference count */
352 pipe_resource_reference(&dummy
, &sbuf
->b
.b
);
354 pSuffix
= (SVGA3dCmdSurfaceDMASuffix
*)((uint8_t*)cmd
+ sizeof *cmd
+ numBoxes
* sizeof *boxes
);
355 pSuffix
->suffixSize
= sizeof *pSuffix
;
356 pSuffix
->maximumOffset
= sbuf
->b
.b
.width0
;
357 pSuffix
->flags
= sbuf
->dma
.flags
;
359 SVGA_FIFOCommitAll(swc
);
361 sbuf
->dma
.flags
.discard
= FALSE
;
368 * Patch up the upload DMA command reserved by svga_buffer_upload_command
369 * with the final ranges.
372 svga_buffer_upload_flush(struct svga_context
*svga
,
373 struct svga_buffer
*sbuf
)
376 struct pipe_resource
*dummy
;
378 if (!sbuf
->dma
.pending
) {
379 //debug_printf("no dma pending on buffer\n");
383 assert(sbuf
->handle
);
384 assert(sbuf
->map
.num_ranges
);
385 assert(sbuf
->dma
.svga
== svga
);
388 * Patch the DMA/update command with the final copy box.
390 if (svga_have_gb_objects(svga
)) {
391 struct svga_3d_update_gb_image
*update
= sbuf
->dma
.updates
;
394 for (i
= 0; i
< sbuf
->map
.num_ranges
; ++i
, ++update
) {
395 SVGA3dBox
*box
= &update
->body
.box
;
397 SVGA_DBG(DEBUG_DMA
, " bytes %u - %u\n",
398 sbuf
->map
.ranges
[i
].start
, sbuf
->map
.ranges
[i
].end
);
400 box
->x
= sbuf
->map
.ranges
[i
].start
;
403 box
->w
= sbuf
->map
.ranges
[i
].end
- sbuf
->map
.ranges
[i
].start
;
407 assert(box
->x
<= sbuf
->b
.b
.width0
);
408 assert(box
->x
+ box
->w
<= sbuf
->b
.b
.width0
);
413 assert(sbuf
->dma
.boxes
);
414 SVGA_DBG(DEBUG_DMA
, "dma to sid %p\n", sbuf
->handle
);
416 for (i
= 0; i
< sbuf
->map
.num_ranges
; ++i
) {
417 SVGA3dCopyBox
*box
= sbuf
->dma
.boxes
+ i
;
419 SVGA_DBG(DEBUG_DMA
, " bytes %u - %u\n",
420 sbuf
->map
.ranges
[i
].start
, sbuf
->map
.ranges
[i
].end
);
422 box
->x
= sbuf
->map
.ranges
[i
].start
;
425 box
->w
= sbuf
->map
.ranges
[i
].end
- sbuf
->map
.ranges
[i
].start
;
428 box
->srcx
= sbuf
->map
.ranges
[i
].start
;
432 assert(box
->x
<= sbuf
->b
.b
.width0
);
433 assert(box
->x
+ box
->w
<= sbuf
->b
.b
.width0
);
437 /* Reset sbuf for next use/upload */
439 sbuf
->map
.num_ranges
= 0;
441 assert(sbuf
->head
.prev
&& sbuf
->head
.next
);
442 LIST_DEL(&sbuf
->head
); /* remove from svga->dirty_buffers list */
444 sbuf
->head
.next
= sbuf
->head
.prev
= NULL
;
446 sbuf
->dma
.pending
= FALSE
;
447 sbuf
->dma
.flags
.discard
= FALSE
;
448 sbuf
->dma
.flags
.unsynchronized
= FALSE
;
450 sbuf
->dma
.svga
= NULL
;
451 sbuf
->dma
.boxes
= NULL
;
452 sbuf
->dma
.updates
= NULL
;
454 /* Decrement reference count (and potentially destroy) */
456 pipe_resource_reference(&dummy
, NULL
);
461 * Note a dirty range.
463 * This function only notes the range down. It doesn't actually emit a DMA
464 * upload command. That only happens when a context tries to refer to this
465 * buffer, and the DMA upload command is added to that context's command
468 * We try to lump as many contiguous DMA transfers together as possible.
471 svga_buffer_add_range(struct svga_buffer
*sbuf
,
476 unsigned nearest_range
;
477 unsigned nearest_dist
;
481 if (sbuf
->map
.num_ranges
< SVGA_BUFFER_MAX_RANGES
) {
482 nearest_range
= sbuf
->map
.num_ranges
;
485 nearest_range
= SVGA_BUFFER_MAX_RANGES
- 1;
490 * Try to grow one of the ranges.
493 for (i
= 0; i
< sbuf
->map
.num_ranges
; ++i
) {
498 left_dist
= start
- sbuf
->map
.ranges
[i
].end
;
499 right_dist
= sbuf
->map
.ranges
[i
].start
- end
;
500 dist
= MAX2(left_dist
, right_dist
);
504 * Ranges are contiguous or overlapping -- extend this one and return.
506 * Note that it is not this function's task to prevent overlapping
507 * ranges, as the GMR was already given so it is too late to do
508 * anything. If the ranges overlap here it must surely be because
509 * PIPE_TRANSFER_UNSYNCHRONIZED was set.
512 sbuf
->map
.ranges
[i
].start
= MIN2(sbuf
->map
.ranges
[i
].start
, start
);
513 sbuf
->map
.ranges
[i
].end
= MAX2(sbuf
->map
.ranges
[i
].end
, end
);
518 * Discontiguous ranges -- keep track of the nearest range.
521 if (dist
< nearest_dist
) {
529 * We cannot add a new range to an existing DMA command, so patch-up the
530 * pending DMA upload and start clean.
533 svga_buffer_upload_flush(sbuf
->dma
.svga
, sbuf
);
535 assert(!sbuf
->dma
.pending
);
536 assert(!sbuf
->dma
.svga
);
537 assert(!sbuf
->dma
.boxes
);
539 if (sbuf
->map
.num_ranges
< SVGA_BUFFER_MAX_RANGES
) {
544 sbuf
->map
.ranges
[sbuf
->map
.num_ranges
].start
= start
;
545 sbuf
->map
.ranges
[sbuf
->map
.num_ranges
].end
= end
;
546 ++sbuf
->map
.num_ranges
;
549 * Everything else failed, so just extend the nearest range.
551 * It is OK to do this because we always keep a local copy of the
552 * host buffer data, for SW TNL, and the host never modifies the buffer.
555 assert(nearest_range
< SVGA_BUFFER_MAX_RANGES
);
556 assert(nearest_range
< sbuf
->map
.num_ranges
);
557 sbuf
->map
.ranges
[nearest_range
].start
= MIN2(sbuf
->map
.ranges
[nearest_range
].start
, start
);
558 sbuf
->map
.ranges
[nearest_range
].end
= MAX2(sbuf
->map
.ranges
[nearest_range
].end
, end
);
565 * Copy the contents of the malloc buffer to a hardware buffer.
567 static enum pipe_error
568 svga_buffer_update_hw(struct svga_context
*svga
, struct svga_buffer
*sbuf
)
571 if (!svga_buffer_has_hw_storage(sbuf
)) {
572 struct svga_screen
*ss
= svga_screen(sbuf
->b
.b
.screen
);
581 ret
= svga_buffer_create_hw_storage(svga_screen(sbuf
->b
.b
.screen
),
586 pipe_mutex_lock(ss
->swc_mutex
);
587 map
= svga_buffer_hw_storage_map(svga
, sbuf
, PIPE_TRANSFER_WRITE
, &retry
);
591 pipe_mutex_unlock(ss
->swc_mutex
);
592 svga_buffer_destroy_hw_storage(ss
, sbuf
);
596 memcpy(map
, sbuf
->swbuf
, sbuf
->b
.b
.width0
);
597 svga_buffer_hw_storage_unmap(svga
, sbuf
);
599 /* This user/malloc buffer is now indistinguishable from a gpu buffer */
600 assert(!sbuf
->map
.count
);
601 if (!sbuf
->map
.count
) {
605 align_free(sbuf
->swbuf
);
609 pipe_mutex_unlock(ss
->swc_mutex
);
617 * Upload the buffer to the host in a piecewise fashion.
619 * Used when the buffer is too big to fit in the GMR aperture.
620 * This function should never get called in the guest-backed case
621 * since we always have a full-sized hardware storage backing the
624 static enum pipe_error
625 svga_buffer_upload_piecewise(struct svga_screen
*ss
,
626 struct svga_context
*svga
,
627 struct svga_buffer
*sbuf
)
629 struct svga_winsys_screen
*sws
= ss
->sws
;
630 const unsigned alignment
= sizeof(void *);
631 const unsigned usage
= 0;
634 assert(sbuf
->map
.num_ranges
);
635 assert(!sbuf
->dma
.pending
);
636 assert(!svga_have_gb_objects(svga
));
638 SVGA_DBG(DEBUG_DMA
, "dma to sid %p\n", sbuf
->handle
);
640 for (i
= 0; i
< sbuf
->map
.num_ranges
; ++i
) {
641 struct svga_buffer_range
*range
= &sbuf
->map
.ranges
[i
];
642 unsigned offset
= range
->start
;
643 unsigned size
= range
->end
- range
->start
;
645 while (offset
< range
->end
) {
646 struct svga_winsys_buffer
*hwbuf
;
650 if (offset
+ size
> range
->end
)
651 size
= range
->end
- offset
;
653 hwbuf
= sws
->buffer_create(sws
, alignment
, usage
, size
);
657 return PIPE_ERROR_OUT_OF_MEMORY
;
658 hwbuf
= sws
->buffer_create(sws
, alignment
, usage
, size
);
661 SVGA_DBG(DEBUG_DMA
, " bytes %u - %u\n",
662 offset
, offset
+ size
);
664 map
= sws
->buffer_map(sws
, hwbuf
,
665 PIPE_TRANSFER_WRITE
|
666 PIPE_TRANSFER_DISCARD_RANGE
);
669 memcpy(map
, (const char *) sbuf
->swbuf
+ offset
, size
);
670 sws
->buffer_unmap(sws
, hwbuf
);
673 ret
= SVGA3D_BufferDMA(svga
->swc
,
675 SVGA3D_WRITE_HOST_VRAM
,
676 size
, 0, offset
, sbuf
->dma
.flags
);
677 if (ret
!= PIPE_OK
) {
678 svga_context_flush(svga
, NULL
);
679 ret
= SVGA3D_BufferDMA(svga
->swc
,
681 SVGA3D_WRITE_HOST_VRAM
,
682 size
, 0, offset
, sbuf
->dma
.flags
);
683 assert(ret
== PIPE_OK
);
686 sbuf
->dma
.flags
.discard
= FALSE
;
688 sws
->buffer_destroy(sws
, hwbuf
);
694 sbuf
->map
.num_ranges
= 0;
701 * Get (or create/upload) the winsys surface handle so that we can
702 * refer to this buffer in fifo commands.
703 * This function will create the host surface, and in the GB case also the
704 * hardware storage. In the non-GB case, the hardware storage will be created
705 * if there are mapped ranges and the data is currently in a malloc'ed buffer.
707 struct svga_winsys_surface
*
708 svga_buffer_handle(struct svga_context
*svga
,
709 struct pipe_resource
*buf
)
711 struct pipe_screen
*screen
= svga
->pipe
.screen
;
712 struct svga_screen
*ss
= svga_screen(screen
);
713 struct svga_buffer
*sbuf
;
719 sbuf
= svga_buffer(buf
);
724 /* This call will set sbuf->handle */
725 if (svga_have_gb_objects(svga
)) {
726 ret
= svga_buffer_update_hw(svga
, sbuf
);
728 ret
= svga_buffer_create_host_surface(ss
, sbuf
);
734 assert(sbuf
->handle
);
736 if (sbuf
->map
.num_ranges
) {
737 if (!sbuf
->dma
.pending
) {
739 * No pending DMA upload yet, so insert a DMA upload command now.
743 * Migrate the data from swbuf -> hwbuf if necessary.
745 ret
= svga_buffer_update_hw(svga
, sbuf
);
746 if (ret
== PIPE_OK
) {
748 * Queue a dma command.
751 ret
= svga_buffer_upload_command(svga
, sbuf
);
752 if (ret
== PIPE_ERROR_OUT_OF_MEMORY
) {
753 svga_context_flush(svga
, NULL
);
754 ret
= svga_buffer_upload_command(svga
, sbuf
);
755 assert(ret
== PIPE_OK
);
757 if (ret
== PIPE_OK
) {
758 sbuf
->dma
.pending
= TRUE
;
759 assert(!sbuf
->head
.prev
&& !sbuf
->head
.next
);
760 LIST_ADDTAIL(&sbuf
->head
, &svga
->dirty_buffers
);
763 else if (ret
== PIPE_ERROR_OUT_OF_MEMORY
) {
765 * The buffer is too big to fit in the GMR aperture, so break it in
768 ret
= svga_buffer_upload_piecewise(ss
, svga
, sbuf
);
771 if (ret
!= PIPE_OK
) {
773 * Something unexpected happened above. There is very little that
774 * we can do other than proceeding while ignoring the dirty ranges.
777 sbuf
->map
.num_ranges
= 0;
782 * There a pending dma already. Make sure it is from this context.
784 assert(sbuf
->dma
.svga
== svga
);
788 assert(!sbuf
->map
.num_ranges
|| sbuf
->dma
.pending
);
796 svga_context_flush_buffers(struct svga_context
*svga
)
798 struct list_head
*curr
, *next
;
799 struct svga_buffer
*sbuf
;
801 curr
= svga
->dirty_buffers
.next
;
803 while(curr
!= &svga
->dirty_buffers
) {
804 sbuf
= LIST_ENTRY(struct svga_buffer
, curr
, head
);
806 assert(p_atomic_read(&sbuf
->b
.b
.reference
.count
) != 0);
807 assert(sbuf
->dma
.pending
);
809 svga_buffer_upload_flush(svga
, sbuf
);