1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
27 #include "os/os_thread.h"
28 #include "pipe/p_state.h"
29 #include "pipe/p_defines.h"
30 #include "util/u_inlines.h"
31 #include "util/u_math.h"
32 #include "util/u_memory.h"
35 #include "svga_context.h"
36 #include "svga_debug.h"
37 #include "svga_resource_buffer.h"
38 #include "svga_resource_buffer_upload.h"
39 #include "svga_screen.h"
40 #include "svga_winsys.h"
43 * Describes a complete SVGA_3D_CMD_UPDATE_GB_IMAGE command
46 struct svga_3d_update_gb_image
{
47 SVGA3dCmdHeader header
;
48 SVGA3dCmdUpdateGBImage body
;
51 struct svga_3d_invalidate_gb_image
{
52 SVGA3dCmdHeader header
;
53 SVGA3dCmdInvalidateGBImage body
;
58 * Allocate a winsys_buffer (ie. DMA, aka GMR memory).
60 * It will flush and retry in case the first attempt to create a DMA buffer
61 * fails, so it should not be called from any function involved in flushing
64 struct svga_winsys_buffer
*
65 svga_winsys_buffer_create( struct svga_context
*svga
,
70 struct svga_screen
*svgascreen
= svga_screen(svga
->pipe
.screen
);
71 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
72 struct svga_winsys_buffer
*buf
;
75 buf
= sws
->buffer_create(sws
, alignment
, usage
, size
);
77 SVGA_DBG(DEBUG_DMA
|DEBUG_PERF
, "flushing context to find %d bytes GMR\n",
80 /* Try flushing all pending DMAs */
81 svga_context_flush(svga
, NULL
);
82 buf
= sws
->buffer_create(sws
, alignment
, usage
, size
);
90 * Destroy HW storage if separate from the host surface.
91 * In the GB case, the HW storage is associated with the host surface
92 * and is therefore a No-op.
95 svga_buffer_destroy_hw_storage(struct svga_screen
*ss
, struct svga_buffer
*sbuf
)
97 struct svga_winsys_screen
*sws
= ss
->sws
;
99 assert(sbuf
->map
.count
== 0);
102 sws
->buffer_destroy(sws
, sbuf
->hwbuf
);
110 * Allocate DMA'ble or Updatable storage for the buffer.
112 * Called before mapping a buffer.
115 svga_buffer_create_hw_storage(struct svga_screen
*ss
,
116 struct svga_buffer
*sbuf
)
120 if (ss
->sws
->have_gb_objects
) {
121 assert(sbuf
->handle
|| !sbuf
->dma
.pending
);
122 return svga_buffer_create_host_surface(ss
, sbuf
);
125 struct svga_winsys_screen
*sws
= ss
->sws
;
126 unsigned alignment
= 16;
128 unsigned size
= sbuf
->b
.b
.width0
;
130 sbuf
->hwbuf
= sws
->buffer_create(sws
, alignment
, usage
, size
);
132 return PIPE_ERROR_OUT_OF_MEMORY
;
134 assert(!sbuf
->dma
.pending
);
143 svga_buffer_create_host_surface(struct svga_screen
*ss
,
144 struct svga_buffer
*sbuf
)
151 sbuf
->key
.format
= SVGA3D_BUFFER
;
152 if (sbuf
->bind_flags
& PIPE_BIND_VERTEX_BUFFER
) {
153 sbuf
->key
.flags
|= SVGA3D_SURFACE_HINT_VERTEXBUFFER
;
154 sbuf
->key
.flags
|= SVGA3D_SURFACE_BIND_VERTEX_BUFFER
;
156 if (sbuf
->bind_flags
& PIPE_BIND_INDEX_BUFFER
) {
157 sbuf
->key
.flags
|= SVGA3D_SURFACE_HINT_INDEXBUFFER
;
158 sbuf
->key
.flags
|= SVGA3D_SURFACE_BIND_INDEX_BUFFER
;
160 if (sbuf
->bind_flags
& PIPE_BIND_CONSTANT_BUFFER
)
161 sbuf
->key
.flags
|= SVGA3D_SURFACE_BIND_CONSTANT_BUFFER
;
163 if (sbuf
->bind_flags
& PIPE_BIND_STREAM_OUTPUT
)
164 sbuf
->key
.flags
|= SVGA3D_SURFACE_BIND_STREAM_OUTPUT
;
166 if (sbuf
->bind_flags
& PIPE_BIND_SAMPLER_VIEW
)
167 sbuf
->key
.flags
|= SVGA3D_SURFACE_BIND_SHADER_RESOURCE
;
169 sbuf
->key
.size
.width
= sbuf
->b
.b
.width0
;
170 sbuf
->key
.size
.height
= 1;
171 sbuf
->key
.size
.depth
= 1;
173 sbuf
->key
.numFaces
= 1;
174 sbuf
->key
.numMipLevels
= 1;
175 sbuf
->key
.cachable
= 1;
176 sbuf
->key
.arraySize
= 1;
178 SVGA_DBG(DEBUG_DMA
, "surface_create for buffer sz %d\n",
181 sbuf
->handle
= svga_screen_surface_create(ss
, sbuf
->b
.b
.bind
,
182 sbuf
->b
.b
.usage
, &sbuf
->key
);
184 return PIPE_ERROR_OUT_OF_MEMORY
;
186 /* Always set the discard flag on the first time the buffer is written
187 * as svga_screen_surface_create might have passed a recycled host
190 sbuf
->dma
.flags
.discard
= TRUE
;
192 SVGA_DBG(DEBUG_DMA
, " --> got sid %p sz %d (buffer)\n",
193 sbuf
->handle
, sbuf
->b
.b
.width0
);
201 svga_buffer_destroy_host_surface(struct svga_screen
*ss
,
202 struct svga_buffer
*sbuf
)
205 SVGA_DBG(DEBUG_DMA
, " ungrab sid %p sz %d\n",
206 sbuf
->handle
, sbuf
->b
.b
.width0
);
207 svga_screen_surface_destroy(ss
, &sbuf
->key
, &sbuf
->handle
);
213 * Insert a number of preliminary UPDATE_GB_IMAGE commands in the
214 * command buffer, equal to the current number of mapped ranges.
215 * The UPDATE_GB_IMAGE commands will be patched with the
216 * actual ranges just before flush.
218 static enum pipe_error
219 svga_buffer_upload_gb_command(struct svga_context
*svga
,
220 struct svga_buffer
*sbuf
)
222 struct svga_winsys_context
*swc
= svga
->swc
;
223 SVGA3dCmdUpdateGBImage
*update_cmd
;
224 struct svga_3d_update_gb_image
*whole_update_cmd
= NULL
;
225 const uint32 numBoxes
= sbuf
->map
.num_ranges
;
226 struct pipe_resource
*dummy
;
229 assert(svga_have_gb_objects(svga
));
231 assert(sbuf
->dma
.updates
== NULL
);
233 if (sbuf
->dma
.flags
.discard
) {
234 struct svga_3d_invalidate_gb_image
*cicmd
= NULL
;
235 SVGA3dCmdInvalidateGBImage
*invalidate_cmd
;
236 const unsigned total_commands_size
=
237 sizeof(*invalidate_cmd
) + numBoxes
* sizeof(*whole_update_cmd
);
239 /* Allocate FIFO space for one INVALIDATE_GB_IMAGE command followed by
240 * 'numBoxes' UPDATE_GB_IMAGE commands. Allocate all at once rather
241 * than with separate commands because we need to properly deal with
242 * filling the command buffer.
244 invalidate_cmd
= SVGA3D_FIFOReserve(swc
,
245 SVGA_3D_CMD_INVALIDATE_GB_IMAGE
,
246 total_commands_size
, 1 + numBoxes
);
248 return PIPE_ERROR_OUT_OF_MEMORY
;
250 cicmd
= container_of(invalidate_cmd
, cicmd
, body
);
251 cicmd
->header
.size
= sizeof(*invalidate_cmd
);
252 swc
->surface_relocation(swc
, &invalidate_cmd
->image
.sid
, NULL
, sbuf
->handle
,
254 SVGA_RELOC_INTERNAL
|
256 invalidate_cmd
->image
.face
= 0;
257 invalidate_cmd
->image
.mipmap
= 0;
259 /* The whole_update_command is a SVGA3dCmdHeader plus the
260 * SVGA3dCmdUpdateGBImage command.
262 whole_update_cmd
= (struct svga_3d_update_gb_image
*) &invalidate_cmd
[1];
263 /* initialize the first UPDATE_GB_IMAGE command */
264 whole_update_cmd
->header
.id
= SVGA_3D_CMD_UPDATE_GB_IMAGE
;
265 update_cmd
= &whole_update_cmd
->body
;
268 /* Allocate FIFO space for 'numBoxes' UPDATE_GB_IMAGE commands */
269 const unsigned total_commands_size
=
270 sizeof(*update_cmd
) + (numBoxes
- 1) * sizeof(*whole_update_cmd
);
272 update_cmd
= SVGA3D_FIFOReserve(swc
,
273 SVGA_3D_CMD_UPDATE_GB_IMAGE
,
274 total_commands_size
, numBoxes
);
276 return PIPE_ERROR_OUT_OF_MEMORY
;
278 /* The whole_update_command is a SVGA3dCmdHeader plus the
279 * SVGA3dCmdUpdateGBImage command.
281 whole_update_cmd
= container_of(update_cmd
, whole_update_cmd
, body
);
284 /* Init the first UPDATE_GB_IMAGE command */
285 whole_update_cmd
->header
.size
= sizeof(*update_cmd
);
286 swc
->surface_relocation(swc
, &update_cmd
->image
.sid
, NULL
, sbuf
->handle
,
287 SVGA_RELOC_WRITE
| SVGA_RELOC_INTERNAL
);
288 update_cmd
->image
.face
= 0;
289 update_cmd
->image
.mipmap
= 0;
291 /* Save pointer to the first UPDATE_GB_IMAGE command so that we can
292 * fill in the box info below.
294 sbuf
->dma
.updates
= whole_update_cmd
;
297 * Copy the face, mipmap, etc. info to all subsequent commands.
298 * Also do the surface relocation for each subsequent command.
300 for (i
= 1; i
< numBoxes
; ++i
) {
302 memcpy(whole_update_cmd
, sbuf
->dma
.updates
, sizeof(*whole_update_cmd
));
304 swc
->surface_relocation(swc
, &whole_update_cmd
->body
.image
.sid
, NULL
,
306 SVGA_RELOC_WRITE
| SVGA_RELOC_INTERNAL
);
309 /* Increment reference count */
310 sbuf
->dma
.svga
= svga
;
312 pipe_resource_reference(&dummy
, &sbuf
->b
.b
);
313 SVGA_FIFOCommitAll(swc
);
315 swc
->hints
|= SVGA_HINT_FLAG_CAN_PRE_FLUSH
;
316 sbuf
->dma
.flags
.discard
= FALSE
;
318 svga
->hud
.num_resource_updates
++;
325 * Issue DMA commands to transfer guest memory to the host.
326 * Note that the memory segments (offset, size) will be patched in
327 * later in the svga_buffer_upload_flush() function.
329 static enum pipe_error
330 svga_buffer_upload_hb_command(struct svga_context
*svga
,
331 struct svga_buffer
*sbuf
)
333 struct svga_winsys_context
*swc
= svga
->swc
;
334 struct svga_winsys_buffer
*guest
= sbuf
->hwbuf
;
335 struct svga_winsys_surface
*host
= sbuf
->handle
;
336 const SVGA3dTransferType transfer
= SVGA3D_WRITE_HOST_VRAM
;
337 SVGA3dCmdSurfaceDMA
*cmd
;
338 const uint32 numBoxes
= sbuf
->map
.num_ranges
;
339 SVGA3dCopyBox
*boxes
;
340 SVGA3dCmdSurfaceDMASuffix
*pSuffix
;
341 unsigned region_flags
;
342 unsigned surface_flags
;
343 struct pipe_resource
*dummy
;
345 assert(!svga_have_gb_objects(svga
));
347 if (transfer
== SVGA3D_WRITE_HOST_VRAM
) {
348 region_flags
= SVGA_RELOC_READ
;
349 surface_flags
= SVGA_RELOC_WRITE
;
351 else if (transfer
== SVGA3D_READ_HOST_VRAM
) {
352 region_flags
= SVGA_RELOC_WRITE
;
353 surface_flags
= SVGA_RELOC_READ
;
357 return PIPE_ERROR_BAD_INPUT
;
362 cmd
= SVGA3D_FIFOReserve(swc
,
363 SVGA_3D_CMD_SURFACE_DMA
,
364 sizeof *cmd
+ numBoxes
* sizeof *boxes
+ sizeof *pSuffix
,
367 return PIPE_ERROR_OUT_OF_MEMORY
;
369 swc
->region_relocation(swc
, &cmd
->guest
.ptr
, guest
, 0, region_flags
);
370 cmd
->guest
.pitch
= 0;
372 swc
->surface_relocation(swc
, &cmd
->host
.sid
, NULL
, host
, surface_flags
);
374 cmd
->host
.mipmap
= 0;
376 cmd
->transfer
= transfer
;
378 sbuf
->dma
.boxes
= (SVGA3dCopyBox
*)&cmd
[1];
379 sbuf
->dma
.svga
= svga
;
381 /* Increment reference count */
383 pipe_resource_reference(&dummy
, &sbuf
->b
.b
);
385 pSuffix
= (SVGA3dCmdSurfaceDMASuffix
*)((uint8_t*)cmd
+ sizeof *cmd
+ numBoxes
* sizeof *boxes
);
386 pSuffix
->suffixSize
= sizeof *pSuffix
;
387 pSuffix
->maximumOffset
= sbuf
->b
.b
.width0
;
388 pSuffix
->flags
= sbuf
->dma
.flags
;
390 SVGA_FIFOCommitAll(swc
);
392 swc
->hints
|= SVGA_HINT_FLAG_CAN_PRE_FLUSH
;
393 sbuf
->dma
.flags
.discard
= FALSE
;
395 svga
->hud
.num_buffer_uploads
++;
402 * Issue commands to transfer guest memory to the host.
404 static enum pipe_error
405 svga_buffer_upload_command(struct svga_context
*svga
, struct svga_buffer
*sbuf
)
407 if (svga_have_gb_objects(svga
)) {
408 return svga_buffer_upload_gb_command(svga
, sbuf
);
410 return svga_buffer_upload_hb_command(svga
, sbuf
);
416 * Patch up the upload DMA command reserved by svga_buffer_upload_command
417 * with the final ranges.
420 svga_buffer_upload_flush(struct svga_context
*svga
,
421 struct svga_buffer
*sbuf
)
424 struct pipe_resource
*dummy
;
426 if (!sbuf
->dma
.pending
) {
427 //debug_printf("no dma pending on buffer\n");
431 assert(sbuf
->handle
);
432 assert(sbuf
->map
.num_ranges
);
433 assert(sbuf
->dma
.svga
== svga
);
436 * Patch the DMA/update command with the final copy box.
438 if (svga_have_gb_objects(svga
)) {
439 struct svga_3d_update_gb_image
*update
= sbuf
->dma
.updates
;
442 for (i
= 0; i
< sbuf
->map
.num_ranges
; ++i
, ++update
) {
443 SVGA3dBox
*box
= &update
->body
.box
;
445 SVGA_DBG(DEBUG_DMA
, " bytes %u - %u\n",
446 sbuf
->map
.ranges
[i
].start
, sbuf
->map
.ranges
[i
].end
);
448 box
->x
= sbuf
->map
.ranges
[i
].start
;
451 box
->w
= sbuf
->map
.ranges
[i
].end
- sbuf
->map
.ranges
[i
].start
;
455 assert(box
->x
<= sbuf
->b
.b
.width0
);
456 assert(box
->x
+ box
->w
<= sbuf
->b
.b
.width0
);
458 svga
->hud
.num_bytes_uploaded
+= box
->w
;
459 svga
->hud
.num_buffer_uploads
++;
464 assert(sbuf
->dma
.boxes
);
465 SVGA_DBG(DEBUG_DMA
, "dma to sid %p\n", sbuf
->handle
);
467 for (i
= 0; i
< sbuf
->map
.num_ranges
; ++i
) {
468 SVGA3dCopyBox
*box
= sbuf
->dma
.boxes
+ i
;
470 SVGA_DBG(DEBUG_DMA
, " bytes %u - %u\n",
471 sbuf
->map
.ranges
[i
].start
, sbuf
->map
.ranges
[i
].end
);
473 box
->x
= sbuf
->map
.ranges
[i
].start
;
476 box
->w
= sbuf
->map
.ranges
[i
].end
- sbuf
->map
.ranges
[i
].start
;
479 box
->srcx
= sbuf
->map
.ranges
[i
].start
;
483 assert(box
->x
<= sbuf
->b
.b
.width0
);
484 assert(box
->x
+ box
->w
<= sbuf
->b
.b
.width0
);
486 svga
->hud
.num_bytes_uploaded
+= box
->w
;
487 svga
->hud
.num_buffer_uploads
++;
491 /* Reset sbuf for next use/upload */
493 sbuf
->map
.num_ranges
= 0;
495 assert(sbuf
->head
.prev
&& sbuf
->head
.next
);
496 LIST_DEL(&sbuf
->head
); /* remove from svga->dirty_buffers list */
498 sbuf
->head
.next
= sbuf
->head
.prev
= NULL
;
500 sbuf
->dma
.pending
= FALSE
;
501 sbuf
->dma
.flags
.discard
= FALSE
;
502 sbuf
->dma
.flags
.unsynchronized
= FALSE
;
504 sbuf
->dma
.svga
= NULL
;
505 sbuf
->dma
.boxes
= NULL
;
506 sbuf
->dma
.updates
= NULL
;
508 /* Decrement reference count (and potentially destroy) */
510 pipe_resource_reference(&dummy
, NULL
);
515 * Note a dirty range.
517 * This function only notes the range down. It doesn't actually emit a DMA
518 * upload command. That only happens when a context tries to refer to this
519 * buffer, and the DMA upload command is added to that context's command
522 * We try to lump as many contiguous DMA transfers together as possible.
525 svga_buffer_add_range(struct svga_buffer
*sbuf
, unsigned start
, unsigned end
)
528 unsigned nearest_range
;
529 unsigned nearest_dist
;
533 if (sbuf
->map
.num_ranges
< SVGA_BUFFER_MAX_RANGES
) {
534 nearest_range
= sbuf
->map
.num_ranges
;
537 nearest_range
= SVGA_BUFFER_MAX_RANGES
- 1;
542 * Try to grow one of the ranges.
544 for (i
= 0; i
< sbuf
->map
.num_ranges
; ++i
) {
545 const int left_dist
= start
- sbuf
->map
.ranges
[i
].end
;
546 const int right_dist
= sbuf
->map
.ranges
[i
].start
- end
;
547 const int dist
= MAX2(left_dist
, right_dist
);
551 * Ranges are contiguous or overlapping -- extend this one and return.
553 * Note that it is not this function's task to prevent overlapping
554 * ranges, as the GMR was already given so it is too late to do
555 * anything. If the ranges overlap here it must surely be because
556 * PIPE_TRANSFER_UNSYNCHRONIZED was set.
558 sbuf
->map
.ranges
[i
].start
= MIN2(sbuf
->map
.ranges
[i
].start
, start
);
559 sbuf
->map
.ranges
[i
].end
= MAX2(sbuf
->map
.ranges
[i
].end
, end
);
564 * Discontiguous ranges -- keep track of the nearest range.
566 if (dist
< nearest_dist
) {
574 * We cannot add a new range to an existing DMA command, so patch-up the
575 * pending DMA upload and start clean.
578 svga_buffer_upload_flush(sbuf
->dma
.svga
, sbuf
);
580 assert(!sbuf
->dma
.pending
);
581 assert(!sbuf
->dma
.svga
);
582 assert(!sbuf
->dma
.boxes
);
584 if (sbuf
->map
.num_ranges
< SVGA_BUFFER_MAX_RANGES
) {
589 sbuf
->map
.ranges
[sbuf
->map
.num_ranges
].start
= start
;
590 sbuf
->map
.ranges
[sbuf
->map
.num_ranges
].end
= end
;
591 ++sbuf
->map
.num_ranges
;
594 * Everything else failed, so just extend the nearest range.
596 * It is OK to do this because we always keep a local copy of the
597 * host buffer data, for SW TNL, and the host never modifies the buffer.
600 assert(nearest_range
< SVGA_BUFFER_MAX_RANGES
);
601 assert(nearest_range
< sbuf
->map
.num_ranges
);
602 sbuf
->map
.ranges
[nearest_range
].start
=
603 MIN2(sbuf
->map
.ranges
[nearest_range
].start
, start
);
604 sbuf
->map
.ranges
[nearest_range
].end
=
605 MAX2(sbuf
->map
.ranges
[nearest_range
].end
, end
);
612 * Copy the contents of the malloc buffer to a hardware buffer.
614 static enum pipe_error
615 svga_buffer_update_hw(struct svga_context
*svga
, struct svga_buffer
*sbuf
)
618 if (!svga_buffer_has_hw_storage(sbuf
)) {
619 struct svga_screen
*ss
= svga_screen(sbuf
->b
.b
.screen
);
628 ret
= svga_buffer_create_hw_storage(svga_screen(sbuf
->b
.b
.screen
), sbuf
);
632 pipe_mutex_lock(ss
->swc_mutex
);
633 map
= svga_buffer_hw_storage_map(svga
, sbuf
, PIPE_TRANSFER_WRITE
, &retry
);
637 pipe_mutex_unlock(ss
->swc_mutex
);
638 svga_buffer_destroy_hw_storage(ss
, sbuf
);
642 memcpy(map
, sbuf
->swbuf
, sbuf
->b
.b
.width0
);
643 svga_buffer_hw_storage_unmap(svga
, sbuf
);
645 /* This user/malloc buffer is now indistinguishable from a gpu buffer */
646 assert(sbuf
->map
.count
== 0);
647 if (sbuf
->map
.count
== 0) {
651 align_free(sbuf
->swbuf
);
655 pipe_mutex_unlock(ss
->swc_mutex
);
663 * Upload the buffer to the host in a piecewise fashion.
665 * Used when the buffer is too big to fit in the GMR aperture.
666 * This function should never get called in the guest-backed case
667 * since we always have a full-sized hardware storage backing the
670 static enum pipe_error
671 svga_buffer_upload_piecewise(struct svga_screen
*ss
,
672 struct svga_context
*svga
,
673 struct svga_buffer
*sbuf
)
675 struct svga_winsys_screen
*sws
= ss
->sws
;
676 const unsigned alignment
= sizeof(void *);
677 const unsigned usage
= 0;
680 assert(sbuf
->map
.num_ranges
);
681 assert(!sbuf
->dma
.pending
);
682 assert(!svga_have_gb_objects(svga
));
684 SVGA_DBG(DEBUG_DMA
, "dma to sid %p\n", sbuf
->handle
);
686 for (i
= 0; i
< sbuf
->map
.num_ranges
; ++i
) {
687 const struct svga_buffer_range
*range
= &sbuf
->map
.ranges
[i
];
688 unsigned offset
= range
->start
;
689 unsigned size
= range
->end
- range
->start
;
691 while (offset
< range
->end
) {
692 struct svga_winsys_buffer
*hwbuf
;
696 if (offset
+ size
> range
->end
)
697 size
= range
->end
- offset
;
699 hwbuf
= sws
->buffer_create(sws
, alignment
, usage
, size
);
703 return PIPE_ERROR_OUT_OF_MEMORY
;
704 hwbuf
= sws
->buffer_create(sws
, alignment
, usage
, size
);
707 SVGA_DBG(DEBUG_DMA
, " bytes %u - %u\n",
708 offset
, offset
+ size
);
710 map
= sws
->buffer_map(sws
, hwbuf
,
711 PIPE_TRANSFER_WRITE
|
712 PIPE_TRANSFER_DISCARD_RANGE
);
715 memcpy(map
, (const char *) sbuf
->swbuf
+ offset
, size
);
716 sws
->buffer_unmap(sws
, hwbuf
);
719 ret
= SVGA3D_BufferDMA(svga
->swc
,
721 SVGA3D_WRITE_HOST_VRAM
,
722 size
, 0, offset
, sbuf
->dma
.flags
);
723 if (ret
!= PIPE_OK
) {
724 svga_context_flush(svga
, NULL
);
725 ret
= SVGA3D_BufferDMA(svga
->swc
,
727 SVGA3D_WRITE_HOST_VRAM
,
728 size
, 0, offset
, sbuf
->dma
.flags
);
729 assert(ret
== PIPE_OK
);
732 sbuf
->dma
.flags
.discard
= FALSE
;
734 sws
->buffer_destroy(sws
, hwbuf
);
740 sbuf
->map
.num_ranges
= 0;
747 * Get (or create/upload) the winsys surface handle so that we can
748 * refer to this buffer in fifo commands.
749 * This function will create the host surface, and in the GB case also the
750 * hardware storage. In the non-GB case, the hardware storage will be created
751 * if there are mapped ranges and the data is currently in a malloc'ed buffer.
753 struct svga_winsys_surface
*
754 svga_buffer_handle(struct svga_context
*svga
, struct pipe_resource
*buf
)
756 struct pipe_screen
*screen
= svga
->pipe
.screen
;
757 struct svga_screen
*ss
= svga_screen(screen
);
758 struct svga_buffer
*sbuf
;
764 sbuf
= svga_buffer(buf
);
769 /* This call will set sbuf->handle */
770 if (svga_have_gb_objects(svga
)) {
771 ret
= svga_buffer_update_hw(svga
, sbuf
);
773 ret
= svga_buffer_create_host_surface(ss
, sbuf
);
779 assert(sbuf
->handle
);
781 if (sbuf
->map
.num_ranges
) {
782 if (!sbuf
->dma
.pending
) {
783 /* No pending DMA/update commands yet. */
785 /* Migrate the data from swbuf -> hwbuf if necessary */
786 ret
= svga_buffer_update_hw(svga
, sbuf
);
787 if (ret
== PIPE_OK
) {
788 /* Emit DMA or UpdateGBImage commands */
789 ret
= svga_buffer_upload_command(svga
, sbuf
);
790 if (ret
== PIPE_ERROR_OUT_OF_MEMORY
) {
791 svga_context_flush(svga
, NULL
);
792 ret
= svga_buffer_upload_command(svga
, sbuf
);
793 assert(ret
== PIPE_OK
);
795 if (ret
== PIPE_OK
) {
796 sbuf
->dma
.pending
= TRUE
;
797 assert(!sbuf
->head
.prev
&& !sbuf
->head
.next
);
798 LIST_ADDTAIL(&sbuf
->head
, &svga
->dirty_buffers
);
801 else if (ret
== PIPE_ERROR_OUT_OF_MEMORY
) {
803 * The buffer is too big to fit in the GMR aperture, so break it in
806 ret
= svga_buffer_upload_piecewise(ss
, svga
, sbuf
);
809 if (ret
!= PIPE_OK
) {
811 * Something unexpected happened above. There is very little that
812 * we can do other than proceeding while ignoring the dirty ranges.
815 sbuf
->map
.num_ranges
= 0;
820 * There a pending dma already. Make sure it is from this context.
822 assert(sbuf
->dma
.svga
== svga
);
826 assert(sbuf
->map
.num_ranges
== 0 || sbuf
->dma
.pending
);
834 svga_context_flush_buffers(struct svga_context
*svga
)
836 struct list_head
*curr
, *next
;
838 curr
= svga
->dirty_buffers
.next
;
840 while (curr
!= &svga
->dirty_buffers
) {
841 struct svga_buffer
*sbuf
= LIST_ENTRY(struct svga_buffer
, curr
, head
);
843 assert(p_atomic_read(&sbuf
->b
.b
.reference
.count
) != 0);
844 assert(sbuf
->dma
.pending
);
846 svga_buffer_upload_flush(svga
, sbuf
);