1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
27 #include "os/os_thread.h"
28 #include "pipe/p_state.h"
29 #include "pipe/p_defines.h"
30 #include "util/u_inlines.h"
31 #include "util/u_math.h"
32 #include "util/u_memory.h"
35 #include "svga_context.h"
36 #include "svga_debug.h"
37 #include "svga_resource_buffer.h"
38 #include "svga_resource_buffer_upload.h"
39 #include "svga_screen.h"
40 #include "svga_winsys.h"
43 * Describes a complete SVGA_3D_CMD_UPDATE_GB_IMAGE command
46 struct svga_3d_update_gb_image
{
47 SVGA3dCmdHeader header
;
48 SVGA3dCmdUpdateGBImage body
;
51 struct svga_3d_invalidate_gb_image
{
52 SVGA3dCmdHeader header
;
53 SVGA3dCmdInvalidateGBImage body
;
58 * Allocate a winsys_buffer (ie. DMA, aka GMR memory).
60 * It will flush and retry in case the first attempt to create a DMA buffer
61 * fails, so it should not be called from any function involved in flushing
64 struct svga_winsys_buffer
*
65 svga_winsys_buffer_create( struct svga_context
*svga
,
70 struct svga_screen
*svgascreen
= svga_screen(svga
->pipe
.screen
);
71 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
72 struct svga_winsys_buffer
*buf
;
75 buf
= sws
->buffer_create(sws
, alignment
, usage
, size
);
77 SVGA_DBG(DEBUG_DMA
|DEBUG_PERF
, "flushing context to find %d bytes GMR\n",
80 /* Try flushing all pending DMAs */
81 svga_context_flush(svga
, NULL
);
82 buf
= sws
->buffer_create(sws
, alignment
, usage
, size
);
90 * Destroy HW storage if separate from the host surface.
91 * In the GB case, the HW storage is associated with the host surface
92 * and is therefore a No-op.
95 svga_buffer_destroy_hw_storage(struct svga_screen
*ss
, struct svga_buffer
*sbuf
)
97 struct svga_winsys_screen
*sws
= ss
->sws
;
99 assert(!sbuf
->map
.count
);
102 sws
->buffer_destroy(sws
, sbuf
->hwbuf
);
110 * Allocate DMA'ble or Updatable storage for the buffer.
112 * Called before mapping a buffer.
115 svga_buffer_create_hw_storage(struct svga_screen
*ss
,
116 struct svga_buffer
*sbuf
)
120 if (ss
->sws
->have_gb_objects
) {
121 assert(sbuf
->handle
|| !sbuf
->dma
.pending
);
122 return svga_buffer_create_host_surface(ss
, sbuf
);
125 struct svga_winsys_screen
*sws
= ss
->sws
;
126 unsigned alignment
= 16;
128 unsigned size
= sbuf
->b
.b
.width0
;
130 sbuf
->hwbuf
= sws
->buffer_create(sws
, alignment
, usage
, size
);
132 return PIPE_ERROR_OUT_OF_MEMORY
;
134 assert(!sbuf
->dma
.pending
);
143 svga_buffer_create_host_surface(struct svga_screen
*ss
,
144 struct svga_buffer
*sbuf
)
151 sbuf
->key
.format
= SVGA3D_BUFFER
;
152 if (sbuf
->bind_flags
& PIPE_BIND_VERTEX_BUFFER
) {
153 sbuf
->key
.flags
|= SVGA3D_SURFACE_HINT_VERTEXBUFFER
;
154 sbuf
->key
.flags
|= SVGA3D_SURFACE_BIND_VERTEX_BUFFER
;
156 if (sbuf
->bind_flags
& PIPE_BIND_INDEX_BUFFER
) {
157 sbuf
->key
.flags
|= SVGA3D_SURFACE_HINT_INDEXBUFFER
;
158 sbuf
->key
.flags
|= SVGA3D_SURFACE_BIND_INDEX_BUFFER
;
160 if (sbuf
->bind_flags
& PIPE_BIND_CONSTANT_BUFFER
)
161 sbuf
->key
.flags
|= SVGA3D_SURFACE_BIND_CONSTANT_BUFFER
;
163 if (sbuf
->bind_flags
& PIPE_BIND_STREAM_OUTPUT
)
164 sbuf
->key
.flags
|= SVGA3D_SURFACE_BIND_STREAM_OUTPUT
;
166 if (sbuf
->bind_flags
& PIPE_BIND_SAMPLER_VIEW
)
167 sbuf
->key
.flags
|= SVGA3D_SURFACE_BIND_SHADER_RESOURCE
;
169 sbuf
->key
.size
.width
= sbuf
->b
.b
.width0
;
170 sbuf
->key
.size
.height
= 1;
171 sbuf
->key
.size
.depth
= 1;
173 sbuf
->key
.numFaces
= 1;
174 sbuf
->key
.numMipLevels
= 1;
175 sbuf
->key
.cachable
= 1;
176 sbuf
->key
.arraySize
= 1;
178 SVGA_DBG(DEBUG_DMA
, "surface_create for buffer sz %d\n", sbuf
->b
.b
.width0
);
180 sbuf
->handle
= svga_screen_surface_create(ss
, sbuf
->b
.b
.bind
,
181 sbuf
->b
.b
.usage
, &sbuf
->key
);
183 return PIPE_ERROR_OUT_OF_MEMORY
;
185 /* Always set the discard flag on the first time the buffer is written
186 * as svga_screen_surface_create might have passed a recycled host
189 sbuf
->dma
.flags
.discard
= TRUE
;
191 SVGA_DBG(DEBUG_DMA
, " --> got sid %p sz %d (buffer)\n", sbuf
->handle
, sbuf
->b
.b
.width0
);
199 svga_buffer_destroy_host_surface(struct svga_screen
*ss
,
200 struct svga_buffer
*sbuf
)
203 SVGA_DBG(DEBUG_DMA
, " ungrab sid %p sz %d\n", sbuf
->handle
, sbuf
->b
.b
.width0
);
204 svga_screen_surface_destroy(ss
, &sbuf
->key
, &sbuf
->handle
);
210 * Insert a number of preliminary UPDATE_GB_IMAGE commands in the
211 * command buffer, equal to the current number of mapped ranges.
212 * The UPDATE_GB_IMAGE commands will be patched with the
213 * actual ranges just before flush.
215 static enum pipe_error
216 svga_buffer_upload_gb_command(struct svga_context
*svga
,
217 struct svga_buffer
*sbuf
)
219 struct svga_winsys_context
*swc
= svga
->swc
;
220 SVGA3dCmdUpdateGBImage
*update_cmd
;
221 struct svga_3d_update_gb_image
*whole_update_cmd
= NULL
;
222 uint32 numBoxes
= sbuf
->map
.num_ranges
;
223 struct pipe_resource
*dummy
;
226 assert(svga_have_gb_objects(svga
));
228 assert(sbuf
->dma
.updates
== NULL
);
230 if (sbuf
->dma
.flags
.discard
) {
231 struct svga_3d_invalidate_gb_image
*cicmd
= NULL
;
232 SVGA3dCmdInvalidateGBImage
*invalidate_cmd
;
233 const unsigned total_commands_size
=
234 sizeof(*invalidate_cmd
) + numBoxes
* sizeof(*whole_update_cmd
);
236 /* Allocate FIFO space for one INVALIDATE_GB_IMAGE command followed by
237 * 'numBoxes' UPDATE_GB_IMAGE commands. Allocate all at once rather
238 * than with separate commands because we need to properly deal with
239 * filling the command buffer.
241 invalidate_cmd
= SVGA3D_FIFOReserve(swc
,
242 SVGA_3D_CMD_INVALIDATE_GB_IMAGE
,
243 total_commands_size
, 1 + numBoxes
);
245 return PIPE_ERROR_OUT_OF_MEMORY
;
247 cicmd
= container_of(invalidate_cmd
, cicmd
, body
);
248 cicmd
->header
.size
= sizeof(*invalidate_cmd
);
249 swc
->surface_relocation(swc
, &invalidate_cmd
->image
.sid
, NULL
, sbuf
->handle
,
251 SVGA_RELOC_INTERNAL
|
253 invalidate_cmd
->image
.face
= 0;
254 invalidate_cmd
->image
.mipmap
= 0;
256 /* The whole_update_command is a SVGA3dCmdHeader plus the
257 * SVGA3dCmdUpdateGBImage command.
259 whole_update_cmd
= (struct svga_3d_update_gb_image
*) &invalidate_cmd
[1];
260 /* initialize the first UPDATE_GB_IMAGE command */
261 whole_update_cmd
->header
.id
= SVGA_3D_CMD_UPDATE_GB_IMAGE
;
262 update_cmd
= &whole_update_cmd
->body
;
265 /* Allocate FIFO space for 'numBoxes' UPDATE_GB_IMAGE commands */
266 const unsigned total_commands_size
=
267 sizeof(*update_cmd
) + (numBoxes
- 1) * sizeof(*whole_update_cmd
);
269 update_cmd
= SVGA3D_FIFOReserve(swc
,
270 SVGA_3D_CMD_UPDATE_GB_IMAGE
,
271 total_commands_size
, numBoxes
);
273 return PIPE_ERROR_OUT_OF_MEMORY
;
275 /* The whole_update_command is a SVGA3dCmdHeader plus the
276 * SVGA3dCmdUpdateGBImage command.
278 whole_update_cmd
= container_of(update_cmd
, whole_update_cmd
, body
);
281 /* Init the first UPDATE_GB_IMAGE command */
282 whole_update_cmd
->header
.size
= sizeof(*update_cmd
);
283 swc
->surface_relocation(swc
, &update_cmd
->image
.sid
, NULL
, sbuf
->handle
,
284 SVGA_RELOC_WRITE
| SVGA_RELOC_INTERNAL
);
285 update_cmd
->image
.face
= 0;
286 update_cmd
->image
.mipmap
= 0;
288 /* Save pointer to the first UPDATE_GB_IMAGE command so that we can
289 * fill in the box info below.
291 sbuf
->dma
.updates
= whole_update_cmd
;
294 * Copy the face, mipmap, etc. info to all subsequent commands.
295 * Also do the surface relocation for each subsequent command.
297 for (i
= 1; i
< numBoxes
; ++i
) {
299 memcpy(whole_update_cmd
, sbuf
->dma
.updates
, sizeof(*whole_update_cmd
));
301 swc
->surface_relocation(swc
, &whole_update_cmd
->body
.image
.sid
, NULL
,
303 SVGA_RELOC_WRITE
| SVGA_RELOC_INTERNAL
);
306 /* Increment reference count */
307 sbuf
->dma
.svga
= svga
;
309 pipe_resource_reference(&dummy
, &sbuf
->b
.b
);
310 SVGA_FIFOCommitAll(swc
);
312 swc
->hints
|= SVGA_HINT_FLAG_CAN_PRE_FLUSH
;
313 sbuf
->dma
.flags
.discard
= FALSE
;
315 svga
->hud
.num_resource_updates
++;
322 * Issue DMA commands to transfer guest memory to the host.
323 * Note that the memory segments (offset, size) will be patched in
324 * later in the svga_buffer_upload_flush() function.
326 static enum pipe_error
327 svga_buffer_upload_hb_command(struct svga_context
*svga
,
328 struct svga_buffer
*sbuf
)
330 struct svga_winsys_context
*swc
= svga
->swc
;
331 struct svga_winsys_buffer
*guest
= sbuf
->hwbuf
;
332 struct svga_winsys_surface
*host
= sbuf
->handle
;
333 SVGA3dTransferType transfer
= SVGA3D_WRITE_HOST_VRAM
;
334 SVGA3dCmdSurfaceDMA
*cmd
;
335 uint32 numBoxes
= sbuf
->map
.num_ranges
;
336 SVGA3dCopyBox
*boxes
;
337 SVGA3dCmdSurfaceDMASuffix
*pSuffix
;
338 unsigned region_flags
;
339 unsigned surface_flags
;
340 struct pipe_resource
*dummy
;
342 assert(!svga_have_gb_objects(svga
));
344 if (transfer
== SVGA3D_WRITE_HOST_VRAM
) {
345 region_flags
= SVGA_RELOC_READ
;
346 surface_flags
= SVGA_RELOC_WRITE
;
348 else if (transfer
== SVGA3D_READ_HOST_VRAM
) {
349 region_flags
= SVGA_RELOC_WRITE
;
350 surface_flags
= SVGA_RELOC_READ
;
354 return PIPE_ERROR_BAD_INPUT
;
359 cmd
= SVGA3D_FIFOReserve(swc
,
360 SVGA_3D_CMD_SURFACE_DMA
,
361 sizeof *cmd
+ numBoxes
* sizeof *boxes
+ sizeof *pSuffix
,
364 return PIPE_ERROR_OUT_OF_MEMORY
;
366 swc
->region_relocation(swc
, &cmd
->guest
.ptr
, guest
, 0, region_flags
);
367 cmd
->guest
.pitch
= 0;
369 swc
->surface_relocation(swc
, &cmd
->host
.sid
, NULL
, host
, surface_flags
);
371 cmd
->host
.mipmap
= 0;
373 cmd
->transfer
= transfer
;
375 sbuf
->dma
.boxes
= (SVGA3dCopyBox
*)&cmd
[1];
376 sbuf
->dma
.svga
= svga
;
378 /* Increment reference count */
380 pipe_resource_reference(&dummy
, &sbuf
->b
.b
);
382 pSuffix
= (SVGA3dCmdSurfaceDMASuffix
*)((uint8_t*)cmd
+ sizeof *cmd
+ numBoxes
* sizeof *boxes
);
383 pSuffix
->suffixSize
= sizeof *pSuffix
;
384 pSuffix
->maximumOffset
= sbuf
->b
.b
.width0
;
385 pSuffix
->flags
= sbuf
->dma
.flags
;
387 SVGA_FIFOCommitAll(swc
);
389 swc
->hints
|= SVGA_HINT_FLAG_CAN_PRE_FLUSH
;
390 sbuf
->dma
.flags
.discard
= FALSE
;
392 svga
->hud
.num_buffer_uploads
++;
399 * Issue commands to transfer guest memory to the host.
401 static enum pipe_error
402 svga_buffer_upload_command(struct svga_context
*svga
, struct svga_buffer
*sbuf
)
404 if (svga_have_gb_objects(svga
)) {
405 return svga_buffer_upload_gb_command(svga
, sbuf
);
407 return svga_buffer_upload_hb_command(svga
, sbuf
);
413 * Patch up the upload DMA command reserved by svga_buffer_upload_command
414 * with the final ranges.
417 svga_buffer_upload_flush(struct svga_context
*svga
,
418 struct svga_buffer
*sbuf
)
421 struct pipe_resource
*dummy
;
423 if (!sbuf
->dma
.pending
) {
424 //debug_printf("no dma pending on buffer\n");
428 assert(sbuf
->handle
);
429 assert(sbuf
->map
.num_ranges
);
430 assert(sbuf
->dma
.svga
== svga
);
433 * Patch the DMA/update command with the final copy box.
435 if (svga_have_gb_objects(svga
)) {
436 struct svga_3d_update_gb_image
*update
= sbuf
->dma
.updates
;
439 for (i
= 0; i
< sbuf
->map
.num_ranges
; ++i
, ++update
) {
440 SVGA3dBox
*box
= &update
->body
.box
;
442 SVGA_DBG(DEBUG_DMA
, " bytes %u - %u\n",
443 sbuf
->map
.ranges
[i
].start
, sbuf
->map
.ranges
[i
].end
);
445 box
->x
= sbuf
->map
.ranges
[i
].start
;
448 box
->w
= sbuf
->map
.ranges
[i
].end
- sbuf
->map
.ranges
[i
].start
;
452 assert(box
->x
<= sbuf
->b
.b
.width0
);
453 assert(box
->x
+ box
->w
<= sbuf
->b
.b
.width0
);
455 svga
->hud
.num_bytes_uploaded
+= box
->w
;
456 svga
->hud
.num_buffer_uploads
++;
461 assert(sbuf
->dma
.boxes
);
462 SVGA_DBG(DEBUG_DMA
, "dma to sid %p\n", sbuf
->handle
);
464 for (i
= 0; i
< sbuf
->map
.num_ranges
; ++i
) {
465 SVGA3dCopyBox
*box
= sbuf
->dma
.boxes
+ i
;
467 SVGA_DBG(DEBUG_DMA
, " bytes %u - %u\n",
468 sbuf
->map
.ranges
[i
].start
, sbuf
->map
.ranges
[i
].end
);
470 box
->x
= sbuf
->map
.ranges
[i
].start
;
473 box
->w
= sbuf
->map
.ranges
[i
].end
- sbuf
->map
.ranges
[i
].start
;
476 box
->srcx
= sbuf
->map
.ranges
[i
].start
;
480 assert(box
->x
<= sbuf
->b
.b
.width0
);
481 assert(box
->x
+ box
->w
<= sbuf
->b
.b
.width0
);
483 svga
->hud
.num_bytes_uploaded
+= box
->w
;
484 svga
->hud
.num_buffer_uploads
++;
488 /* Reset sbuf for next use/upload */
490 sbuf
->map
.num_ranges
= 0;
492 assert(sbuf
->head
.prev
&& sbuf
->head
.next
);
493 LIST_DEL(&sbuf
->head
); /* remove from svga->dirty_buffers list */
495 sbuf
->head
.next
= sbuf
->head
.prev
= NULL
;
497 sbuf
->dma
.pending
= FALSE
;
498 sbuf
->dma
.flags
.discard
= FALSE
;
499 sbuf
->dma
.flags
.unsynchronized
= FALSE
;
501 sbuf
->dma
.svga
= NULL
;
502 sbuf
->dma
.boxes
= NULL
;
503 sbuf
->dma
.updates
= NULL
;
505 /* Decrement reference count (and potentially destroy) */
507 pipe_resource_reference(&dummy
, NULL
);
512 * Note a dirty range.
514 * This function only notes the range down. It doesn't actually emit a DMA
515 * upload command. That only happens when a context tries to refer to this
516 * buffer, and the DMA upload command is added to that context's command
519 * We try to lump as many contiguous DMA transfers together as possible.
522 svga_buffer_add_range(struct svga_buffer
*sbuf
,
527 unsigned nearest_range
;
528 unsigned nearest_dist
;
532 if (sbuf
->map
.num_ranges
< SVGA_BUFFER_MAX_RANGES
) {
533 nearest_range
= sbuf
->map
.num_ranges
;
536 nearest_range
= SVGA_BUFFER_MAX_RANGES
- 1;
541 * Try to grow one of the ranges.
544 for (i
= 0; i
< sbuf
->map
.num_ranges
; ++i
) {
549 left_dist
= start
- sbuf
->map
.ranges
[i
].end
;
550 right_dist
= sbuf
->map
.ranges
[i
].start
- end
;
551 dist
= MAX2(left_dist
, right_dist
);
555 * Ranges are contiguous or overlapping -- extend this one and return.
557 * Note that it is not this function's task to prevent overlapping
558 * ranges, as the GMR was already given so it is too late to do
559 * anything. If the ranges overlap here it must surely be because
560 * PIPE_TRANSFER_UNSYNCHRONIZED was set.
563 sbuf
->map
.ranges
[i
].start
= MIN2(sbuf
->map
.ranges
[i
].start
, start
);
564 sbuf
->map
.ranges
[i
].end
= MAX2(sbuf
->map
.ranges
[i
].end
, end
);
569 * Discontiguous ranges -- keep track of the nearest range.
572 if (dist
< nearest_dist
) {
580 * We cannot add a new range to an existing DMA command, so patch-up the
581 * pending DMA upload and start clean.
584 svga_buffer_upload_flush(sbuf
->dma
.svga
, sbuf
);
586 assert(!sbuf
->dma
.pending
);
587 assert(!sbuf
->dma
.svga
);
588 assert(!sbuf
->dma
.boxes
);
590 if (sbuf
->map
.num_ranges
< SVGA_BUFFER_MAX_RANGES
) {
595 sbuf
->map
.ranges
[sbuf
->map
.num_ranges
].start
= start
;
596 sbuf
->map
.ranges
[sbuf
->map
.num_ranges
].end
= end
;
597 ++sbuf
->map
.num_ranges
;
600 * Everything else failed, so just extend the nearest range.
602 * It is OK to do this because we always keep a local copy of the
603 * host buffer data, for SW TNL, and the host never modifies the buffer.
606 assert(nearest_range
< SVGA_BUFFER_MAX_RANGES
);
607 assert(nearest_range
< sbuf
->map
.num_ranges
);
608 sbuf
->map
.ranges
[nearest_range
].start
= MIN2(sbuf
->map
.ranges
[nearest_range
].start
, start
);
609 sbuf
->map
.ranges
[nearest_range
].end
= MAX2(sbuf
->map
.ranges
[nearest_range
].end
, end
);
616 * Copy the contents of the malloc buffer to a hardware buffer.
618 static enum pipe_error
619 svga_buffer_update_hw(struct svga_context
*svga
, struct svga_buffer
*sbuf
)
622 if (!svga_buffer_has_hw_storage(sbuf
)) {
623 struct svga_screen
*ss
= svga_screen(sbuf
->b
.b
.screen
);
632 ret
= svga_buffer_create_hw_storage(svga_screen(sbuf
->b
.b
.screen
),
637 pipe_mutex_lock(ss
->swc_mutex
);
638 map
= svga_buffer_hw_storage_map(svga
, sbuf
, PIPE_TRANSFER_WRITE
, &retry
);
642 pipe_mutex_unlock(ss
->swc_mutex
);
643 svga_buffer_destroy_hw_storage(ss
, sbuf
);
647 memcpy(map
, sbuf
->swbuf
, sbuf
->b
.b
.width0
);
648 svga_buffer_hw_storage_unmap(svga
, sbuf
);
650 /* This user/malloc buffer is now indistinguishable from a gpu buffer */
651 assert(!sbuf
->map
.count
);
652 if (!sbuf
->map
.count
) {
656 align_free(sbuf
->swbuf
);
660 pipe_mutex_unlock(ss
->swc_mutex
);
668 * Upload the buffer to the host in a piecewise fashion.
670 * Used when the buffer is too big to fit in the GMR aperture.
671 * This function should never get called in the guest-backed case
672 * since we always have a full-sized hardware storage backing the
675 static enum pipe_error
676 svga_buffer_upload_piecewise(struct svga_screen
*ss
,
677 struct svga_context
*svga
,
678 struct svga_buffer
*sbuf
)
680 struct svga_winsys_screen
*sws
= ss
->sws
;
681 const unsigned alignment
= sizeof(void *);
682 const unsigned usage
= 0;
685 assert(sbuf
->map
.num_ranges
);
686 assert(!sbuf
->dma
.pending
);
687 assert(!svga_have_gb_objects(svga
));
689 SVGA_DBG(DEBUG_DMA
, "dma to sid %p\n", sbuf
->handle
);
691 for (i
= 0; i
< sbuf
->map
.num_ranges
; ++i
) {
692 const struct svga_buffer_range
*range
= &sbuf
->map
.ranges
[i
];
693 unsigned offset
= range
->start
;
694 unsigned size
= range
->end
- range
->start
;
696 while (offset
< range
->end
) {
697 struct svga_winsys_buffer
*hwbuf
;
701 if (offset
+ size
> range
->end
)
702 size
= range
->end
- offset
;
704 hwbuf
= sws
->buffer_create(sws
, alignment
, usage
, size
);
708 return PIPE_ERROR_OUT_OF_MEMORY
;
709 hwbuf
= sws
->buffer_create(sws
, alignment
, usage
, size
);
712 SVGA_DBG(DEBUG_DMA
, " bytes %u - %u\n",
713 offset
, offset
+ size
);
715 map
= sws
->buffer_map(sws
, hwbuf
,
716 PIPE_TRANSFER_WRITE
|
717 PIPE_TRANSFER_DISCARD_RANGE
);
720 memcpy(map
, (const char *) sbuf
->swbuf
+ offset
, size
);
721 sws
->buffer_unmap(sws
, hwbuf
);
724 ret
= SVGA3D_BufferDMA(svga
->swc
,
726 SVGA3D_WRITE_HOST_VRAM
,
727 size
, 0, offset
, sbuf
->dma
.flags
);
728 if (ret
!= PIPE_OK
) {
729 svga_context_flush(svga
, NULL
);
730 ret
= SVGA3D_BufferDMA(svga
->swc
,
732 SVGA3D_WRITE_HOST_VRAM
,
733 size
, 0, offset
, sbuf
->dma
.flags
);
734 assert(ret
== PIPE_OK
);
737 sbuf
->dma
.flags
.discard
= FALSE
;
739 sws
->buffer_destroy(sws
, hwbuf
);
745 sbuf
->map
.num_ranges
= 0;
752 * Get (or create/upload) the winsys surface handle so that we can
753 * refer to this buffer in fifo commands.
754 * This function will create the host surface, and in the GB case also the
755 * hardware storage. In the non-GB case, the hardware storage will be created
756 * if there are mapped ranges and the data is currently in a malloc'ed buffer.
758 struct svga_winsys_surface
*
759 svga_buffer_handle(struct svga_context
*svga
,
760 struct pipe_resource
*buf
)
762 struct pipe_screen
*screen
= svga
->pipe
.screen
;
763 struct svga_screen
*ss
= svga_screen(screen
);
764 struct svga_buffer
*sbuf
;
770 sbuf
= svga_buffer(buf
);
775 /* This call will set sbuf->handle */
776 if (svga_have_gb_objects(svga
)) {
777 ret
= svga_buffer_update_hw(svga
, sbuf
);
779 ret
= svga_buffer_create_host_surface(ss
, sbuf
);
785 assert(sbuf
->handle
);
787 if (sbuf
->map
.num_ranges
) {
788 if (!sbuf
->dma
.pending
) {
790 * No pending DMA upload yet, so insert a DMA upload command now.
794 * Migrate the data from swbuf -> hwbuf if necessary.
796 ret
= svga_buffer_update_hw(svga
, sbuf
);
797 if (ret
== PIPE_OK
) {
799 * Queue a dma command.
802 ret
= svga_buffer_upload_command(svga
, sbuf
);
803 if (ret
== PIPE_ERROR_OUT_OF_MEMORY
) {
804 svga_context_flush(svga
, NULL
);
805 ret
= svga_buffer_upload_command(svga
, sbuf
);
806 assert(ret
== PIPE_OK
);
808 if (ret
== PIPE_OK
) {
809 sbuf
->dma
.pending
= TRUE
;
810 assert(!sbuf
->head
.prev
&& !sbuf
->head
.next
);
811 LIST_ADDTAIL(&sbuf
->head
, &svga
->dirty_buffers
);
814 else if (ret
== PIPE_ERROR_OUT_OF_MEMORY
) {
816 * The buffer is too big to fit in the GMR aperture, so break it in
819 ret
= svga_buffer_upload_piecewise(ss
, svga
, sbuf
);
822 if (ret
!= PIPE_OK
) {
824 * Something unexpected happened above. There is very little that
825 * we can do other than proceeding while ignoring the dirty ranges.
828 sbuf
->map
.num_ranges
= 0;
833 * There a pending dma already. Make sure it is from this context.
835 assert(sbuf
->dma
.svga
== svga
);
839 assert(!sbuf
->map
.num_ranges
|| sbuf
->dma
.pending
);
847 svga_context_flush_buffers(struct svga_context
*svga
)
849 struct list_head
*curr
, *next
;
850 struct svga_buffer
*sbuf
;
852 curr
= svga
->dirty_buffers
.next
;
854 while(curr
!= &svga
->dirty_buffers
) {
855 sbuf
= LIST_ENTRY(struct svga_buffer
, curr
, head
);
857 assert(p_atomic_read(&sbuf
->b
.b
.reference
.count
) != 0);
858 assert(sbuf
->dma
.pending
);
860 svga_buffer_upload_flush(svga
, sbuf
);