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[mesa.git] / src / gallium / drivers / svga / svga_resource_texture.c
1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26 #include "svga3d_reg.h"
27 #include "svga3d_surfacedefs.h"
28
29 #include "pipe/p_state.h"
30 #include "pipe/p_defines.h"
31 #include "os/os_thread.h"
32 #include "util/u_format.h"
33 #include "util/u_inlines.h"
34 #include "util/u_math.h"
35 #include "util/u_memory.h"
36 #include "util/u_resource.h"
37 #include "util/u_upload_mgr.h"
38
39 #include "svga_cmd.h"
40 #include "svga_format.h"
41 #include "svga_screen.h"
42 #include "svga_context.h"
43 #include "svga_resource_texture.h"
44 #include "svga_resource_buffer.h"
45 #include "svga_sampler_view.h"
46 #include "svga_winsys.h"
47 #include "svga_debug.h"
48
49
50 static void
51 svga_transfer_dma_band(struct svga_context *svga,
52 struct svga_transfer *st,
53 SVGA3dTransferType transfer,
54 unsigned x, unsigned y, unsigned z,
55 unsigned w, unsigned h, unsigned d,
56 unsigned srcx, unsigned srcy, unsigned srcz,
57 SVGA3dSurfaceDMAFlags flags)
58 {
59 struct svga_texture *texture = svga_texture(st->base.resource);
60 SVGA3dCopyBox box;
61 enum pipe_error ret;
62
63 assert(!st->use_direct_map);
64
65 box.x = x;
66 box.y = y;
67 box.z = z;
68 box.w = w;
69 box.h = h;
70 box.d = d;
71 box.srcx = srcx;
72 box.srcy = srcy;
73 box.srcz = srcz;
74
75 SVGA_DBG(DEBUG_DMA, "dma %s sid %p, face %u, (%u, %u, %u) - "
76 "(%u, %u, %u), %ubpp\n",
77 transfer == SVGA3D_WRITE_HOST_VRAM ? "to" : "from",
78 texture->handle,
79 st->slice,
80 x,
81 y,
82 z,
83 x + w,
84 y + h,
85 z + 1,
86 util_format_get_blocksize(texture->b.b.format) * 8 /
87 (util_format_get_blockwidth(texture->b.b.format)
88 * util_format_get_blockheight(texture->b.b.format)));
89
90 ret = SVGA3D_SurfaceDMA(svga->swc, st, transfer, &box, 1, flags);
91 if (ret != PIPE_OK) {
92 svga_context_flush(svga, NULL);
93 ret = SVGA3D_SurfaceDMA(svga->swc, st, transfer, &box, 1, flags);
94 assert(ret == PIPE_OK);
95 }
96 }
97
98
99 static void
100 svga_transfer_dma(struct svga_context *svga,
101 struct svga_transfer *st,
102 SVGA3dTransferType transfer,
103 SVGA3dSurfaceDMAFlags flags)
104 {
105 struct svga_texture *texture = svga_texture(st->base.resource);
106 struct svga_screen *screen = svga_screen(texture->b.b.screen);
107 struct svga_winsys_screen *sws = screen->sws;
108 struct pipe_fence_handle *fence = NULL;
109
110 assert(!st->use_direct_map);
111
112 if (transfer == SVGA3D_READ_HOST_VRAM) {
113 SVGA_DBG(DEBUG_PERF, "%s: readback transfer\n", __FUNCTION__);
114 }
115
116 /* Ensure any pending operations on host surfaces are queued on the command
117 * buffer first.
118 */
119 svga_surfaces_flush( svga );
120
121 if (!st->swbuf) {
122 /* Do the DMA transfer in a single go */
123 svga_transfer_dma_band(svga, st, transfer,
124 st->base.box.x, st->base.box.y, st->base.box.z,
125 st->base.box.width, st->base.box.height, st->base.box.depth,
126 0, 0, 0,
127 flags);
128
129 if (transfer == SVGA3D_READ_HOST_VRAM) {
130 svga_context_flush(svga, &fence);
131 sws->fence_finish(sws, fence, 0);
132 sws->fence_reference(sws, &fence, NULL);
133 }
134 }
135 else {
136 int y, h, srcy;
137 unsigned blockheight =
138 util_format_get_blockheight(st->base.resource->format);
139
140 h = st->hw_nblocksy * blockheight;
141 srcy = 0;
142
143 for (y = 0; y < st->base.box.height; y += h) {
144 unsigned offset, length;
145 void *hw, *sw;
146
147 if (y + h > st->base.box.height)
148 h = st->base.box.height - y;
149
150 /* Transfer band must be aligned to pixel block boundaries */
151 assert(y % blockheight == 0);
152 assert(h % blockheight == 0);
153
154 offset = y * st->base.stride / blockheight;
155 length = h * st->base.stride / blockheight;
156
157 sw = (uint8_t *) st->swbuf + offset;
158
159 if (transfer == SVGA3D_WRITE_HOST_VRAM) {
160 unsigned usage = PIPE_TRANSFER_WRITE;
161
162 /* Wait for the previous DMAs to complete */
163 /* TODO: keep one DMA (at half the size) in the background */
164 if (y) {
165 svga_context_flush(svga, NULL);
166 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
167 }
168
169 hw = sws->buffer_map(sws, st->hwbuf, usage);
170 assert(hw);
171 if (hw) {
172 memcpy(hw, sw, length);
173 sws->buffer_unmap(sws, st->hwbuf);
174 }
175 }
176
177 svga_transfer_dma_band(svga, st, transfer,
178 st->base.box.x, y, st->base.box.z,
179 st->base.box.width, h, st->base.box.depth,
180 0, srcy, 0, flags);
181
182 /*
183 * Prevent the texture contents to be discarded on the next band
184 * upload.
185 */
186 flags.discard = FALSE;
187
188 if (transfer == SVGA3D_READ_HOST_VRAM) {
189 svga_context_flush(svga, &fence);
190 sws->fence_finish(sws, fence, 0);
191
192 hw = sws->buffer_map(sws, st->hwbuf, PIPE_TRANSFER_READ);
193 assert(hw);
194 if (hw) {
195 memcpy(sw, hw, length);
196 sws->buffer_unmap(sws, st->hwbuf);
197 }
198 }
199 }
200 }
201 }
202
203
204
205 static boolean
206 svga_texture_get_handle(struct pipe_screen *screen,
207 struct pipe_resource *texture,
208 struct winsys_handle *whandle)
209 {
210 struct svga_winsys_screen *sws = svga_winsys_screen(texture->screen);
211 unsigned stride;
212
213 assert(svga_texture(texture)->key.cachable == 0);
214 svga_texture(texture)->key.cachable = 0;
215
216 stride = util_format_get_nblocksx(texture->format, texture->width0) *
217 util_format_get_blocksize(texture->format);
218
219 return sws->surface_get_handle(sws, svga_texture(texture)->handle,
220 stride, whandle);
221 }
222
223
224 static void
225 svga_texture_destroy(struct pipe_screen *screen,
226 struct pipe_resource *pt)
227 {
228 struct svga_screen *ss = svga_screen(screen);
229 struct svga_texture *tex = svga_texture(pt);
230
231 ss->texture_timestamp++;
232
233 svga_sampler_view_reference(&tex->cached_view, NULL);
234
235 /*
236 DBG("%s deleting %p\n", __FUNCTION__, (void *) tex);
237 */
238 SVGA_DBG(DEBUG_DMA, "unref sid %p (texture)\n", tex->handle);
239 svga_screen_surface_destroy(ss, &tex->key, &tex->handle);
240
241 ss->hud.total_resource_bytes -= tex->size;
242
243 FREE(tex->defined);
244 FREE(tex->rendered_to);
245 FREE(tex->dirty);
246 FREE(tex);
247
248 assert(ss->hud.num_resources > 0);
249 if (ss->hud.num_resources > 0)
250 ss->hud.num_resources--;
251 }
252
253
254 /**
255 * Determine if the resource was rendered to
256 */
257 static inline boolean
258 was_tex_rendered_to(struct pipe_resource *resource,
259 const struct pipe_transfer *transfer)
260 {
261 unsigned face;
262
263 if (resource->target == PIPE_TEXTURE_CUBE) {
264 assert(transfer->box.depth == 1);
265 face = transfer->box.z;
266 }
267 else {
268 face = 0;
269 }
270
271 return svga_was_texture_rendered_to(svga_texture(resource),
272 face, transfer->level);
273 }
274
275
276 /**
277 * Determine if we need to read back a texture image before mapping it.
278 */
279 static inline boolean
280 need_tex_readback(struct pipe_transfer *transfer)
281 {
282 struct svga_texture *t = svga_texture(transfer->resource);
283
284 if (transfer->usage & PIPE_TRANSFER_READ)
285 return TRUE;
286
287 if ((transfer->usage & PIPE_TRANSFER_WRITE) &&
288 ((transfer->usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) == 0)) {
289 return was_tex_rendered_to(transfer->resource, transfer);
290 }
291
292 return FALSE;
293 }
294
295
296 static enum pipe_error
297 readback_image_vgpu9(struct svga_context *svga,
298 struct svga_winsys_surface *surf,
299 unsigned slice,
300 unsigned level)
301 {
302 enum pipe_error ret;
303
304 ret = SVGA3D_ReadbackGBImage(svga->swc, surf, slice, level);
305 if (ret != PIPE_OK) {
306 svga_context_flush(svga, NULL);
307 ret = SVGA3D_ReadbackGBImage(svga->swc, surf, slice, level);
308 }
309 return ret;
310 }
311
312
313 static enum pipe_error
314 readback_image_vgpu10(struct svga_context *svga,
315 struct svga_winsys_surface *surf,
316 unsigned slice,
317 unsigned level,
318 unsigned numMipLevels)
319 {
320 enum pipe_error ret;
321 unsigned subResource;
322
323 subResource = slice * numMipLevels + level;
324 ret = SVGA3D_vgpu10_ReadbackSubResource(svga->swc, surf, subResource);
325 if (ret != PIPE_OK) {
326 svga_context_flush(svga, NULL);
327 ret = SVGA3D_vgpu10_ReadbackSubResource(svga->swc, surf, subResource);
328 }
329 return ret;
330 }
331
332
333 /**
334 * Use DMA for the transfer request
335 */
336 static void *
337 svga_texture_transfer_map_dma(struct svga_context *svga,
338 struct svga_transfer *st)
339 {
340 struct svga_winsys_screen *sws = svga_screen(svga->pipe.screen)->sws;
341 struct pipe_resource *texture = st->base.resource;
342 unsigned nblocksx, nblocksy;
343 unsigned d;
344 unsigned usage = st->base.usage;
345
346 /* we'll put the data into a tightly packed buffer */
347 nblocksx = util_format_get_nblocksx(texture->format, st->base.box.width);
348 nblocksy = util_format_get_nblocksy(texture->format, st->base.box.height);
349 d = st->base.box.depth;
350
351 st->base.stride = nblocksx*util_format_get_blocksize(texture->format);
352 st->base.layer_stride = st->base.stride * nblocksy;
353 st->hw_nblocksy = nblocksy;
354
355 st->hwbuf = svga_winsys_buffer_create(svga, 1, 0,
356 st->hw_nblocksy * st->base.stride * d);
357
358 while (!st->hwbuf && (st->hw_nblocksy /= 2)) {
359 st->hwbuf =
360 svga_winsys_buffer_create(svga, 1, 0,
361 st->hw_nblocksy * st->base.stride * d);
362 }
363
364 if (!st->hwbuf)
365 return NULL;
366
367 if (st->hw_nblocksy < nblocksy) {
368 /* We couldn't allocate a hardware buffer big enough for the transfer,
369 * so allocate regular malloc memory instead
370 */
371 if (0) {
372 debug_printf("%s: failed to allocate %u KB of DMA, "
373 "splitting into %u x %u KB DMA transfers\n",
374 __FUNCTION__,
375 (nblocksy * st->base.stride + 1023) / 1024,
376 (nblocksy + st->hw_nblocksy - 1) / st->hw_nblocksy,
377 (st->hw_nblocksy * st->base.stride + 1023) / 1024);
378 }
379
380 st->swbuf = MALLOC(nblocksy * st->base.stride * d);
381 if (!st->swbuf) {
382 sws->buffer_destroy(sws, st->hwbuf);
383 return NULL;
384 }
385 }
386
387 if (usage & PIPE_TRANSFER_READ) {
388 SVGA3dSurfaceDMAFlags flags;
389 memset(&flags, 0, sizeof flags);
390 svga_transfer_dma(svga, st, SVGA3D_READ_HOST_VRAM, flags);
391 }
392
393 if (st->swbuf) {
394 return st->swbuf;
395 }
396 else {
397 return sws->buffer_map(sws, st->hwbuf, usage);
398 }
399 }
400
401
402 /**
403 * Use direct map for the transfer request
404 */
405 static void *
406 svga_texture_transfer_map_direct(struct svga_context *svga,
407 struct svga_transfer *st)
408 {
409 struct svga_winsys_screen *sws = svga_screen(svga->pipe.screen)->sws;
410 struct pipe_transfer *transfer = &st->base;
411 struct pipe_resource *texture = transfer->resource;
412 struct svga_texture *tex = svga_texture(texture);
413 struct svga_winsys_surface *surf = tex->handle;
414 unsigned level = st->base.level;
415 unsigned w, h, nblocksx, nblocksy;
416 unsigned usage = st->base.usage;
417
418 if (need_tex_readback(transfer)) {
419 enum pipe_error ret;
420
421 svga_surfaces_flush(svga);
422
423 if (svga_have_vgpu10(svga)) {
424 ret = readback_image_vgpu10(svga, surf, st->slice, level,
425 tex->b.b.last_level + 1);
426 } else {
427 ret = readback_image_vgpu9(svga, surf, st->slice, level);
428 }
429
430 svga->hud.num_readbacks++;
431 SVGA_STATS_COUNT_INC(sws, SVGA_STATS_COUNT_TEXREADBACK);
432
433 assert(ret == PIPE_OK);
434 (void) ret;
435
436 svga_context_flush(svga, NULL);
437 /*
438 * Note: if PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE were specified
439 * we could potentially clear the flag for all faces/layers/mips.
440 */
441 svga_clear_texture_rendered_to(tex, st->slice, level);
442 }
443 else {
444 assert(usage & PIPE_TRANSFER_WRITE);
445 if ((usage & PIPE_TRANSFER_UNSYNCHRONIZED) == 0) {
446 if (svga_is_texture_dirty(tex, st->slice, level)) {
447 /*
448 * do a surface flush if the subresource has been modified
449 * in this command buffer.
450 */
451 svga_surfaces_flush(svga);
452 if (!sws->surface_is_flushed(sws, surf)) {
453 svga->hud.surface_write_flushes++;
454 SVGA_STATS_COUNT_INC(sws, SVGA_STATS_COUNT_SURFACEWRITEFLUSH);
455 svga_context_flush(svga, NULL);
456 }
457 }
458 }
459 }
460
461 /* we'll directly access the guest-backed surface */
462 w = u_minify(texture->width0, level);
463 h = u_minify(texture->height0, level);
464 nblocksx = util_format_get_nblocksx(texture->format, w);
465 nblocksy = util_format_get_nblocksy(texture->format, h);
466 st->hw_nblocksy = nblocksy;
467 st->base.stride = nblocksx*util_format_get_blocksize(texture->format);
468 st->base.layer_stride = st->base.stride * nblocksy;
469
470 /*
471 * Begin mapping code
472 */
473 {
474 SVGA3dSize baseLevelSize;
475 uint8_t *map;
476 boolean retry;
477 unsigned offset, mip_width, mip_height;
478
479 map = svga->swc->surface_map(svga->swc, surf, usage, &retry);
480 if (map == NULL && retry) {
481 /*
482 * At this point, the svga_surfaces_flush() should already have
483 * called in svga_texture_get_transfer().
484 */
485 svga->hud.surface_write_flushes++;
486 svga_context_flush(svga, NULL);
487 map = svga->swc->surface_map(svga->swc, surf, usage, &retry);
488 }
489
490 /*
491 * Make sure we return NULL if the map fails
492 */
493 if (!map) {
494 return NULL;
495 }
496
497 /**
498 * Compute the offset to the specific texture slice in the buffer.
499 */
500 baseLevelSize.width = tex->b.b.width0;
501 baseLevelSize.height = tex->b.b.height0;
502 baseLevelSize.depth = tex->b.b.depth0;
503
504 if ((tex->b.b.target == PIPE_TEXTURE_1D_ARRAY) ||
505 (tex->b.b.target == PIPE_TEXTURE_2D_ARRAY)) {
506 st->base.layer_stride =
507 svga3dsurface_get_image_offset(tex->key.format, baseLevelSize,
508 tex->b.b.last_level + 1, 1, 0);
509 }
510
511 offset = svga3dsurface_get_image_offset(tex->key.format, baseLevelSize,
512 tex->b.b.last_level + 1, /* numMips */
513 st->slice, level);
514 if (level > 0) {
515 assert(offset > 0);
516 }
517
518 mip_width = u_minify(tex->b.b.width0, level);
519 mip_height = u_minify(tex->b.b.height0, level);
520
521 offset += svga3dsurface_get_pixel_offset(tex->key.format,
522 mip_width, mip_height,
523 st->base.box.x,
524 st->base.box.y,
525 st->base.box.z);
526 return (void *) (map + offset);
527 }
528 }
529
530
531 /**
532 * Request a transfer map to the texture resource
533 */
534 static void *
535 svga_texture_transfer_map(struct pipe_context *pipe,
536 struct pipe_resource *texture,
537 unsigned level,
538 unsigned usage,
539 const struct pipe_box *box,
540 struct pipe_transfer **ptransfer)
541 {
542 struct svga_context *svga = svga_context(pipe);
543 struct svga_winsys_screen *sws = svga_screen(pipe->screen)->sws;
544 struct svga_texture *tex = svga_texture(texture);
545 struct svga_transfer *st;
546 struct svga_winsys_surface *surf = tex->handle;
547 boolean use_direct_map = svga_have_gb_objects(svga) &&
548 !svga_have_gb_dma(svga);
549 void *map = NULL;
550 int64_t begin = svga_get_time(svga);
551
552 SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_TEXTRANSFERMAP);
553
554 if (!surf)
555 goto done;
556
557 /* We can't map texture storage directly unless we have GB objects */
558 if (usage & PIPE_TRANSFER_MAP_DIRECTLY) {
559 if (svga_have_gb_objects(svga))
560 use_direct_map = TRUE;
561 else
562 goto done;
563 }
564
565 st = CALLOC_STRUCT(svga_transfer);
566 if (!st)
567 goto done;
568
569 st->base.level = level;
570 st->base.usage = usage;
571 st->base.box = *box;
572
573 switch (tex->b.b.target) {
574 case PIPE_TEXTURE_CUBE:
575 st->slice = st->base.box.z;
576 st->base.box.z = 0; /* so we don't apply double offsets below */
577 break;
578 case PIPE_TEXTURE_2D_ARRAY:
579 case PIPE_TEXTURE_1D_ARRAY:
580 st->slice = st->base.box.z;
581 st->base.box.z = 0; /* so we don't apply double offsets below */
582
583 /* Force direct map for transfering multiple slices */
584 if (st->base.box.depth > 1)
585 use_direct_map = svga_have_gb_objects(svga);
586
587 break;
588 default:
589 st->slice = 0;
590 break;
591 }
592
593 st->use_direct_map = use_direct_map;
594 pipe_resource_reference(&st->base.resource, texture);
595
596 /* If this is the first time mapping to the surface in this
597 * command buffer, clear the dirty masks of this surface.
598 */
599 if (sws->surface_is_flushed(sws, surf)) {
600 svga_clear_texture_dirty(tex);
601 }
602
603 if (!use_direct_map) {
604 /* upload to the DMA buffer */
605 map = svga_texture_transfer_map_dma(svga, st);
606 }
607 else {
608 boolean can_upload = svga_texture_transfer_map_can_upload(svga, st);
609 boolean was_rendered_to = was_tex_rendered_to(texture, &st->base);
610
611 /* If the texture was already rendered to and upload buffer
612 * is supported, then we will use upload buffer to
613 * avoid the need to read back the texture content; otherwise,
614 * we'll first try to map directly to the GB surface, if it is blocked,
615 * then we'll try the upload buffer.
616 */
617 if (was_rendered_to && can_upload) {
618 map = svga_texture_transfer_map_upload(svga, st);
619 }
620 else {
621 unsigned orig_usage = st->base.usage;
622
623 /* try direct map to the GB surface */
624 if (can_upload)
625 st->base.usage |= PIPE_TRANSFER_DONTBLOCK;
626 map = svga_texture_transfer_map_direct(svga, st);
627 st->base.usage = orig_usage;
628
629 if (!map && can_upload) {
630 /* if direct map with DONTBLOCK fails, then try upload to the
631 * texture upload buffer.
632 */
633 map = svga_texture_transfer_map_upload(svga, st);
634 }
635 }
636
637 /* if upload fails, then try direct map again without DONTBLOCK */
638 if (!map) {
639 map = svga_texture_transfer_map_direct(svga, st);
640 }
641 }
642
643 if (!map) {
644 FREE(st);
645 }
646 else {
647 *ptransfer = &st->base;
648 svga->hud.num_textures_mapped++;
649 if (usage & PIPE_TRANSFER_WRITE) {
650 /* record texture upload for HUD */
651 svga->hud.num_bytes_uploaded +=
652 st->base.layer_stride * st->base.box.depth;
653
654 /* mark this texture level as dirty */
655 svga_set_texture_dirty(tex, st->slice, level);
656 }
657 }
658
659 done:
660 svga->hud.map_buffer_time += (svga_get_time(svga) - begin);
661 SVGA_STATS_TIME_POP(sws);
662 (void) sws;
663
664 return map;
665 }
666
667 /**
668 * Unmap a GB texture surface.
669 */
670 static void
671 svga_texture_surface_unmap(struct svga_context *svga,
672 struct pipe_transfer *transfer)
673 {
674 struct svga_winsys_surface *surf = svga_texture(transfer->resource)->handle;
675 struct svga_winsys_context *swc = svga->swc;
676 boolean rebind;
677
678 assert(surf);
679
680 swc->surface_unmap(swc, surf, &rebind);
681 if (rebind) {
682 enum pipe_error ret;
683 ret = SVGA3D_BindGBSurface(swc, surf);
684 if (ret != PIPE_OK) {
685 /* flush and retry */
686 svga_context_flush(svga, NULL);
687 ret = SVGA3D_BindGBSurface(swc, surf);
688 assert(ret == PIPE_OK);
689 }
690 }
691 }
692
693
694 static enum pipe_error
695 update_image_vgpu9(struct svga_context *svga,
696 struct svga_winsys_surface *surf,
697 const SVGA3dBox *box,
698 unsigned slice,
699 unsigned level)
700 {
701 enum pipe_error ret;
702
703 ret = SVGA3D_UpdateGBImage(svga->swc, surf, box, slice, level);
704 if (ret != PIPE_OK) {
705 svga_context_flush(svga, NULL);
706 ret = SVGA3D_UpdateGBImage(svga->swc, surf, box, slice, level);
707 }
708 return ret;
709 }
710
711
712 static enum pipe_error
713 update_image_vgpu10(struct svga_context *svga,
714 struct svga_winsys_surface *surf,
715 const SVGA3dBox *box,
716 unsigned slice,
717 unsigned level,
718 unsigned numMipLevels)
719 {
720 enum pipe_error ret;
721 unsigned subResource;
722
723 subResource = slice * numMipLevels + level;
724 ret = SVGA3D_vgpu10_UpdateSubResource(svga->swc, surf, box, subResource);
725 if (ret != PIPE_OK) {
726 svga_context_flush(svga, NULL);
727 ret = SVGA3D_vgpu10_UpdateSubResource(svga->swc, surf, box, subResource);
728 }
729 return ret;
730 }
731
732
733 /**
734 * unmap DMA transfer request
735 */
736 static void
737 svga_texture_transfer_unmap_dma(struct svga_context *svga,
738 struct svga_transfer *st)
739 {
740 struct svga_winsys_screen *sws = svga_screen(svga->pipe.screen)->sws;
741
742 if (st->hwbuf)
743 sws->buffer_unmap(sws, st->hwbuf);
744
745 if (st->base.usage & PIPE_TRANSFER_WRITE) {
746 /* Use DMA to transfer texture data */
747 SVGA3dSurfaceDMAFlags flags;
748
749 memset(&flags, 0, sizeof flags);
750 if (st->base.usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
751 flags.discard = TRUE;
752 }
753 if (st->base.usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
754 flags.unsynchronized = TRUE;
755 }
756
757 svga_transfer_dma(svga, st, SVGA3D_WRITE_HOST_VRAM, flags);
758 }
759
760 FREE(st->swbuf);
761 sws->buffer_destroy(sws, st->hwbuf);
762 }
763
764
765 /**
766 * unmap direct map transfer request
767 */
768 static void
769 svga_texture_transfer_unmap_direct(struct svga_context *svga,
770 struct svga_transfer *st)
771 {
772 struct pipe_transfer *transfer = &st->base;
773 struct svga_texture *tex = svga_texture(transfer->resource);
774
775 svga_texture_surface_unmap(svga, transfer);
776
777 /* Now send an update command to update the content in the backend. */
778 if (st->base.usage & PIPE_TRANSFER_WRITE) {
779 struct svga_winsys_surface *surf = tex->handle;
780 SVGA3dBox box;
781 enum pipe_error ret;
782 unsigned nlayers = 1;
783
784 assert(svga_have_gb_objects(svga));
785
786 /* update the effected region */
787 box.x = transfer->box.x;
788 box.y = transfer->box.y;
789 box.w = transfer->box.width;
790 box.h = transfer->box.height;
791 box.d = transfer->box.depth;
792
793 switch (tex->b.b.target) {
794 case PIPE_TEXTURE_CUBE:
795 box.z = 0;
796 break;
797 case PIPE_TEXTURE_2D_ARRAY:
798 nlayers = box.d;
799 box.z = 0;
800 box.d = 1;
801 break;
802 case PIPE_TEXTURE_1D_ARRAY:
803 nlayers = box.d;
804 box.y = box.z = 0;
805 box.d = 1;
806 break;
807 default:
808 box.z = transfer->box.z;
809 break;
810 }
811
812 if (0)
813 debug_printf("%s %d, %d, %d %d x %d x %d\n",
814 __FUNCTION__,
815 box.x, box.y, box.z,
816 box.w, box.h, box.d);
817
818 if (svga_have_vgpu10(svga)) {
819 unsigned i;
820 for (i = 0; i < nlayers; i++) {
821 ret = update_image_vgpu10(svga, surf, &box,
822 st->slice + i, transfer->level,
823 tex->b.b.last_level + 1);
824 assert(ret == PIPE_OK);
825 }
826 } else {
827 assert(nlayers == 1);
828 ret = update_image_vgpu9(svga, surf, &box, st->slice, transfer->level);
829 assert(ret == PIPE_OK);
830 }
831 (void) ret;
832 }
833 }
834
835 static void
836 svga_texture_transfer_unmap(struct pipe_context *pipe,
837 struct pipe_transfer *transfer)
838 {
839 struct svga_context *svga = svga_context(pipe);
840 struct svga_screen *ss = svga_screen(pipe->screen);
841 struct svga_winsys_screen *sws = ss->sws;
842 struct svga_transfer *st = svga_transfer(transfer);
843 struct svga_texture *tex = svga_texture(transfer->resource);
844
845 SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_TEXTRANSFERUNMAP);
846
847 if (!st->use_direct_map) {
848 svga_texture_transfer_unmap_dma(svga, st);
849 }
850 else if (st->upload.buf) {
851 svga_texture_transfer_unmap_upload(svga, st);
852 }
853 else {
854 svga_texture_transfer_unmap_direct(svga, st);
855 }
856
857 if (st->base.usage & PIPE_TRANSFER_WRITE) {
858 svga->hud.num_resource_updates++;
859
860 /* Mark the texture level as dirty */
861 ss->texture_timestamp++;
862 svga_age_texture_view(tex, transfer->level);
863 if (transfer->resource->target == PIPE_TEXTURE_CUBE)
864 svga_define_texture_level(tex, st->slice, transfer->level);
865 else
866 svga_define_texture_level(tex, 0, transfer->level);
867 }
868
869 pipe_resource_reference(&st->base.resource, NULL);
870 FREE(st);
871 SVGA_STATS_TIME_POP(sws);
872 (void) sws;
873 }
874
875
876 /**
877 * Does format store depth values?
878 */
879 static inline boolean
880 format_has_depth(enum pipe_format format)
881 {
882 const struct util_format_description *desc = util_format_description(format);
883 return util_format_has_depth(desc);
884 }
885
886
887 struct u_resource_vtbl svga_texture_vtbl =
888 {
889 svga_texture_get_handle, /* get_handle */
890 svga_texture_destroy, /* resource_destroy */
891 svga_texture_transfer_map, /* transfer_map */
892 u_default_transfer_flush_region, /* transfer_flush_region */
893 svga_texture_transfer_unmap, /* transfer_unmap */
894 };
895
896
897 struct pipe_resource *
898 svga_texture_create(struct pipe_screen *screen,
899 const struct pipe_resource *template)
900 {
901 struct svga_screen *svgascreen = svga_screen(screen);
902 struct svga_texture *tex;
903 unsigned bindings = template->bind;
904
905 SVGA_STATS_TIME_PUSH(svgascreen->sws,
906 SVGA_STATS_TIME_CREATETEXTURE);
907
908 assert(template->last_level < SVGA_MAX_TEXTURE_LEVELS);
909 if (template->last_level >= SVGA_MAX_TEXTURE_LEVELS) {
910 goto fail_notex;
911 }
912
913 tex = CALLOC_STRUCT(svga_texture);
914 if (!tex) {
915 goto fail_notex;
916 }
917
918 tex->defined = CALLOC(template->depth0 * template->array_size,
919 sizeof(tex->defined[0]));
920 if (!tex->defined) {
921 FREE(tex);
922 goto fail_notex;
923 }
924
925 tex->rendered_to = CALLOC(template->depth0 * template->array_size,
926 sizeof(tex->rendered_to[0]));
927 if (!tex->rendered_to) {
928 goto fail;
929 }
930
931 tex->dirty = CALLOC(template->depth0 * template->array_size,
932 sizeof(tex->dirty[0]));
933 if (!tex->dirty) {
934 goto fail;
935 }
936
937 tex->b.b = *template;
938 tex->b.vtbl = &svga_texture_vtbl;
939 pipe_reference_init(&tex->b.b.reference, 1);
940 tex->b.b.screen = screen;
941
942 tex->key.flags = 0;
943 tex->key.size.width = template->width0;
944 tex->key.size.height = template->height0;
945 tex->key.size.depth = template->depth0;
946 tex->key.arraySize = 1;
947 tex->key.numFaces = 1;
948
949 /* single sample texture can be treated as non-multisamples texture */
950 tex->key.sampleCount = template->nr_samples > 1 ? template->nr_samples : 0;
951
952 if (template->nr_samples > 1) {
953 tex->key.flags |= SVGA3D_SURFACE_MASKABLE_ANTIALIAS;
954 }
955
956 if (svgascreen->sws->have_vgpu10) {
957 switch (template->target) {
958 case PIPE_TEXTURE_1D:
959 tex->key.flags |= SVGA3D_SURFACE_1D;
960 break;
961 case PIPE_TEXTURE_1D_ARRAY:
962 tex->key.flags |= SVGA3D_SURFACE_1D;
963 /* fall-through */
964 case PIPE_TEXTURE_2D_ARRAY:
965 tex->key.flags |= SVGA3D_SURFACE_ARRAY;
966 tex->key.arraySize = template->array_size;
967 break;
968 case PIPE_TEXTURE_3D:
969 tex->key.flags |= SVGA3D_SURFACE_VOLUME;
970 break;
971 case PIPE_TEXTURE_CUBE:
972 tex->key.flags |= (SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_ARRAY);
973 tex->key.numFaces = 6;
974 break;
975 default:
976 break;
977 }
978 }
979 else {
980 switch (template->target) {
981 case PIPE_TEXTURE_3D:
982 tex->key.flags |= SVGA3D_SURFACE_VOLUME;
983 break;
984 case PIPE_TEXTURE_CUBE:
985 tex->key.flags |= SVGA3D_SURFACE_CUBEMAP;
986 tex->key.numFaces = 6;
987 break;
988 default:
989 break;
990 }
991 }
992
993 tex->key.cachable = 1;
994
995 if ((bindings & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) &&
996 !(bindings & PIPE_BIND_SAMPLER_VIEW)) {
997 /* Also check if the format can be sampled from */
998 if (screen->is_format_supported(screen, template->format,
999 template->target,
1000 template->nr_samples,
1001 PIPE_BIND_SAMPLER_VIEW)) {
1002 bindings |= PIPE_BIND_SAMPLER_VIEW;
1003 }
1004 }
1005
1006 if (bindings & PIPE_BIND_SAMPLER_VIEW) {
1007 tex->key.flags |= SVGA3D_SURFACE_HINT_TEXTURE;
1008 tex->key.flags |= SVGA3D_SURFACE_BIND_SHADER_RESOURCE;
1009
1010 if (!(bindings & PIPE_BIND_RENDER_TARGET)) {
1011 /* Also check if the format is color renderable */
1012 if (screen->is_format_supported(screen, template->format,
1013 template->target,
1014 template->nr_samples,
1015 PIPE_BIND_RENDER_TARGET)) {
1016 bindings |= PIPE_BIND_RENDER_TARGET;
1017 }
1018 }
1019
1020 if (!(bindings & PIPE_BIND_DEPTH_STENCIL)) {
1021 /* Also check if the format is depth/stencil renderable */
1022 if (screen->is_format_supported(screen, template->format,
1023 template->target,
1024 template->nr_samples,
1025 PIPE_BIND_DEPTH_STENCIL)) {
1026 bindings |= PIPE_BIND_DEPTH_STENCIL;
1027 }
1028 }
1029 }
1030
1031 if (bindings & PIPE_BIND_DISPLAY_TARGET) {
1032 tex->key.cachable = 0;
1033 }
1034
1035 if (bindings & PIPE_BIND_SHARED) {
1036 tex->key.cachable = 0;
1037 }
1038
1039 if (bindings & (PIPE_BIND_SCANOUT | PIPE_BIND_CURSOR)) {
1040 tex->key.scanout = 1;
1041 tex->key.cachable = 0;
1042 }
1043
1044 /*
1045 * Note: Previously we never passed the
1046 * SVGA3D_SURFACE_HINT_RENDERTARGET hint. Mesa cannot
1047 * know beforehand whether a texture will be used as a rendertarget or not
1048 * and it always requests PIPE_BIND_RENDER_TARGET, therefore
1049 * passing the SVGA3D_SURFACE_HINT_RENDERTARGET here defeats its purpose.
1050 *
1051 * However, this was changed since other state trackers
1052 * (XA for example) uses it accurately and certain device versions
1053 * relies on it in certain situations to render correctly.
1054 */
1055 if ((bindings & PIPE_BIND_RENDER_TARGET) &&
1056 !util_format_is_s3tc(template->format)) {
1057 tex->key.flags |= SVGA3D_SURFACE_HINT_RENDERTARGET;
1058 tex->key.flags |= SVGA3D_SURFACE_BIND_RENDER_TARGET;
1059 }
1060
1061 if (bindings & PIPE_BIND_DEPTH_STENCIL) {
1062 tex->key.flags |= SVGA3D_SURFACE_HINT_DEPTHSTENCIL;
1063 tex->key.flags |= SVGA3D_SURFACE_BIND_DEPTH_STENCIL;
1064 }
1065
1066 tex->key.numMipLevels = template->last_level + 1;
1067
1068 tex->key.format = svga_translate_format(svgascreen, template->format,
1069 bindings);
1070 if (tex->key.format == SVGA3D_FORMAT_INVALID) {
1071 goto fail;
1072 }
1073
1074 /* The actual allocation is done with a typeless format. Typeless
1075 * formats can be reinterpreted as other formats. For example,
1076 * SVGA3D_R8G8B8A8_UNORM_TYPELESS can be interpreted as
1077 * SVGA3D_R8G8B8A8_UNORM_SRGB or SVGA3D_R8G8B8A8_UNORM.
1078 * Do not use typeless formats for SHARED, DISPLAY_TARGET or SCANOUT
1079 * buffers.
1080 */
1081 if (svgascreen->sws->have_vgpu10
1082 && ((bindings & (PIPE_BIND_SHARED |
1083 PIPE_BIND_DISPLAY_TARGET |
1084 PIPE_BIND_SCANOUT)) == 0)) {
1085 SVGA3dSurfaceFormat typeless = svga_typeless_format(tex->key.format);
1086 if (0) {
1087 debug_printf("Convert resource type %s -> %s (bind 0x%x)\n",
1088 svga_format_name(tex->key.format),
1089 svga_format_name(typeless),
1090 bindings);
1091 }
1092
1093 if (svga_format_is_uncompressed_snorm(tex->key.format)) {
1094 /* We can't normally render to snorm surfaces, but once we
1095 * substitute a typeless format, we can if the rendertarget view
1096 * is unorm. This can happen with GL_ARB_copy_image.
1097 */
1098 tex->key.flags |= SVGA3D_SURFACE_HINT_RENDERTARGET;
1099 tex->key.flags |= SVGA3D_SURFACE_BIND_RENDER_TARGET;
1100 }
1101
1102 tex->key.format = typeless;
1103 }
1104
1105 SVGA_DBG(DEBUG_DMA, "surface_create for texture\n", tex->handle);
1106 tex->handle = svga_screen_surface_create(svgascreen, bindings,
1107 tex->b.b.usage, &tex->key);
1108 if (!tex->handle) {
1109 goto fail;
1110 }
1111
1112 SVGA_DBG(DEBUG_DMA, " --> got sid %p (texture)\n", tex->handle);
1113
1114 debug_reference(&tex->b.b.reference,
1115 (debug_reference_descriptor)debug_describe_resource, 0);
1116
1117 tex->size = util_resource_size(template);
1118 svgascreen->hud.total_resource_bytes += tex->size;
1119 svgascreen->hud.num_resources++;
1120
1121 SVGA_STATS_TIME_POP(svgascreen->sws);
1122
1123 return &tex->b.b;
1124
1125 fail:
1126 if (tex->dirty)
1127 FREE(tex->dirty);
1128 if (tex->rendered_to)
1129 FREE(tex->rendered_to);
1130 if (tex->defined)
1131 FREE(tex->defined);
1132 FREE(tex);
1133 fail_notex:
1134 SVGA_STATS_TIME_POP(svgascreen->sws);
1135 return NULL;
1136 }
1137
1138
1139 struct pipe_resource *
1140 svga_texture_from_handle(struct pipe_screen *screen,
1141 const struct pipe_resource *template,
1142 struct winsys_handle *whandle)
1143 {
1144 struct svga_winsys_screen *sws = svga_winsys_screen(screen);
1145 struct svga_screen *ss = svga_screen(screen);
1146 struct svga_winsys_surface *srf;
1147 struct svga_texture *tex;
1148 enum SVGA3dSurfaceFormat format = 0;
1149 assert(screen);
1150
1151 /* Only supports one type */
1152 if ((template->target != PIPE_TEXTURE_2D &&
1153 template->target != PIPE_TEXTURE_RECT) ||
1154 template->last_level != 0 ||
1155 template->depth0 != 1) {
1156 return NULL;
1157 }
1158
1159 srf = sws->surface_from_handle(sws, whandle, &format);
1160
1161 if (!srf)
1162 return NULL;
1163
1164 if (svga_translate_format(svga_screen(screen), template->format,
1165 template->bind) != format) {
1166 unsigned f1 = svga_translate_format(svga_screen(screen),
1167 template->format, template->bind);
1168 unsigned f2 = format;
1169
1170 /* It's okay for XRGB and ARGB or depth with/out stencil to get mixed up.
1171 */
1172 if (f1 == SVGA3D_B8G8R8A8_UNORM)
1173 f1 = SVGA3D_A8R8G8B8;
1174 if (f1 == SVGA3D_B8G8R8X8_UNORM)
1175 f1 = SVGA3D_X8R8G8B8;
1176
1177 if ( !( (f1 == f2) ||
1178 (f1 == SVGA3D_X8R8G8B8 && f2 == SVGA3D_A8R8G8B8) ||
1179 (f1 == SVGA3D_X8R8G8B8 && f2 == SVGA3D_B8G8R8X8_UNORM) ||
1180 (f1 == SVGA3D_A8R8G8B8 && f2 == SVGA3D_X8R8G8B8) ||
1181 (f1 == SVGA3D_A8R8G8B8 && f2 == SVGA3D_B8G8R8A8_UNORM) ||
1182 (f1 == SVGA3D_Z_D24X8 && f2 == SVGA3D_Z_D24S8) ||
1183 (f1 == SVGA3D_Z_DF24 && f2 == SVGA3D_Z_D24S8_INT) ) ) {
1184 debug_printf("%s wrong format %s != %s\n", __FUNCTION__,
1185 svga_format_name(f1), svga_format_name(f2));
1186 return NULL;
1187 }
1188 }
1189
1190 tex = CALLOC_STRUCT(svga_texture);
1191 if (!tex)
1192 return NULL;
1193
1194 tex->defined = CALLOC(template->depth0 * template->array_size,
1195 sizeof(tex->defined[0]));
1196 if (!tex->defined) {
1197 FREE(tex);
1198 return NULL;
1199 }
1200
1201 tex->b.b = *template;
1202 tex->b.vtbl = &svga_texture_vtbl;
1203 pipe_reference_init(&tex->b.b.reference, 1);
1204 tex->b.b.screen = screen;
1205
1206 SVGA_DBG(DEBUG_DMA, "wrap surface sid %p\n", srf);
1207
1208 tex->key.cachable = 0;
1209 tex->key.format = format;
1210 tex->handle = srf;
1211
1212 tex->rendered_to = CALLOC(1, sizeof(tex->rendered_to[0]));
1213 if (!tex->rendered_to)
1214 goto fail;
1215
1216 tex->dirty = CALLOC(1, sizeof(tex->dirty[0]));
1217 if (!tex->dirty)
1218 goto fail;
1219
1220 tex->imported = TRUE;
1221
1222 ss->hud.num_resources++;
1223
1224 return &tex->b.b;
1225
1226 fail:
1227 if (tex->defined)
1228 FREE(tex->defined);
1229 if (tex->rendered_to)
1230 FREE(tex->rendered_to);
1231 if (tex->dirty)
1232 FREE(tex->dirty);
1233 FREE(tex);
1234 return NULL;
1235 }
1236
1237 boolean
1238 svga_texture_generate_mipmap(struct pipe_context *pipe,
1239 struct pipe_resource *pt,
1240 enum pipe_format format,
1241 unsigned base_level,
1242 unsigned last_level,
1243 unsigned first_layer,
1244 unsigned last_layer)
1245 {
1246 struct pipe_sampler_view templ, *psv;
1247 struct svga_pipe_sampler_view *sv;
1248 struct svga_context *svga = svga_context(pipe);
1249 struct svga_texture *tex = svga_texture(pt);
1250 enum pipe_error ret;
1251
1252 assert(svga_have_vgpu10(svga));
1253
1254 /* Only support 2D texture for now */
1255 if (pt->target != PIPE_TEXTURE_2D)
1256 return FALSE;
1257
1258 /* Fallback to the mipmap generation utility for those formats that
1259 * do not support hw generate mipmap
1260 */
1261 if (!svga_format_support_gen_mips(format))
1262 return FALSE;
1263
1264 /* Make sure the texture surface was created with
1265 * SVGA3D_SURFACE_BIND_RENDER_TARGET
1266 */
1267 if (!tex->handle || !(tex->key.flags & SVGA3D_SURFACE_BIND_RENDER_TARGET))
1268 return FALSE;
1269
1270 templ.format = format;
1271 templ.u.tex.first_layer = first_layer;
1272 templ.u.tex.last_layer = last_layer;
1273 templ.u.tex.first_level = base_level;
1274 templ.u.tex.last_level = last_level;
1275
1276 psv = pipe->create_sampler_view(pipe, pt, &templ);
1277 if (psv == NULL)
1278 return FALSE;
1279
1280 sv = svga_pipe_sampler_view(psv);
1281 ret = svga_validate_pipe_sampler_view(svga, sv);
1282 if (ret != PIPE_OK) {
1283 svga_context_flush(svga, NULL);
1284 ret = svga_validate_pipe_sampler_view(svga, sv);
1285 assert(ret == PIPE_OK);
1286 }
1287
1288 ret = SVGA3D_vgpu10_GenMips(svga->swc, sv->id, tex->handle);
1289 if (ret != PIPE_OK) {
1290 svga_context_flush(svga, NULL);
1291 ret = SVGA3D_vgpu10_GenMips(svga->swc, sv->id, tex->handle);
1292 }
1293 pipe_sampler_view_reference(&psv, NULL);
1294
1295 svga->hud.num_generate_mipmap++;
1296
1297 return TRUE;
1298 }
1299
1300
1301 /* texture upload buffer default size in bytes */
1302 #define TEX_UPLOAD_DEFAULT_SIZE (1024 * 1024)
1303
1304 /**
1305 * Create a texture upload buffer
1306 */
1307 boolean
1308 svga_texture_transfer_map_upload_create(struct svga_context *svga)
1309 {
1310 svga->tex_upload = u_upload_create(&svga->pipe, TEX_UPLOAD_DEFAULT_SIZE,
1311 0, PIPE_USAGE_STAGING);
1312 return svga->tex_upload != NULL;
1313 }
1314
1315
1316 /**
1317 * Destroy the texture upload buffer
1318 */
1319 void
1320 svga_texture_transfer_map_upload_destroy(struct svga_context *svga)
1321 {
1322 u_upload_destroy(svga->tex_upload);
1323 }
1324
1325
1326 /**
1327 * Returns true if this transfer map request can use the upload buffer.
1328 */
1329 boolean
1330 svga_texture_transfer_map_can_upload(struct svga_context *svga,
1331 struct svga_transfer *st)
1332 {
1333 struct pipe_resource *texture = st->base.resource;
1334
1335 if (svga_sws(svga)->have_transfer_from_buffer_cmd == FALSE)
1336 return FALSE;
1337
1338 if (st->base.usage & PIPE_TRANSFER_READ)
1339 return FALSE;
1340
1341 /* TransferFromBuffer command is not well supported with multi-samples surface */
1342 if (texture->nr_samples > 1)
1343 return FALSE;
1344
1345 if (util_format_is_compressed(texture->format)) {
1346 /* XXX Need to take a closer look to see why texture upload
1347 * with 3D texture with compressed format fails
1348 */
1349 if (texture->target == PIPE_TEXTURE_3D)
1350 return FALSE;
1351
1352 #ifdef DEBUG
1353 {
1354 struct svga_texture *tex = svga_texture(texture);
1355 unsigned blockw, blockh, bytesPerBlock;
1356
1357 svga_format_size(tex->key.format, &blockw, &blockh, &bytesPerBlock);
1358
1359 /* dest box must start on block boundary */
1360 assert((st->base.box.x % blockw) == 0);
1361 assert((st->base.box.y % blockh) == 0);
1362 }
1363 #endif
1364 }
1365 else if (texture->format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1366 return FALSE;
1367 }
1368
1369 return TRUE;
1370 }
1371
1372
1373 /**
1374 * Use upload buffer for the transfer map request.
1375 */
1376 void *
1377 svga_texture_transfer_map_upload(struct svga_context *svga,
1378 struct svga_transfer *st)
1379 {
1380 struct pipe_resource *texture = st->base.resource;
1381 struct pipe_resource *tex_buffer = NULL;
1382 void *tex_map;
1383 unsigned nblocksx, nblocksy;
1384 unsigned offset;
1385 unsigned upload_size;
1386
1387 assert(svga->tex_upload);
1388
1389 st->upload.box.x = st->base.box.x;
1390 st->upload.box.y = st->base.box.y;
1391 st->upload.box.z = st->base.box.z;
1392 st->upload.box.w = st->base.box.width;
1393 st->upload.box.h = st->base.box.height;
1394 st->upload.box.d = st->base.box.depth;
1395 st->upload.nlayers = 1;
1396
1397 switch (texture->target) {
1398 case PIPE_TEXTURE_CUBE:
1399 st->upload.box.z = 0;
1400 break;
1401 case PIPE_TEXTURE_2D_ARRAY:
1402 st->upload.nlayers = st->base.box.depth;
1403 st->upload.box.z = 0;
1404 st->upload.box.d = 1;
1405 break;
1406 case PIPE_TEXTURE_1D_ARRAY:
1407 st->upload.nlayers = st->base.box.depth;
1408 st->upload.box.y = st->upload.box.z = 0;
1409 st->upload.box.d = 1;
1410 break;
1411 default:
1412 break;
1413 }
1414
1415 nblocksx = util_format_get_nblocksx(texture->format, st->base.box.width);
1416 nblocksy = util_format_get_nblocksy(texture->format, st->base.box.height);
1417
1418 st->base.stride = nblocksx * util_format_get_blocksize(texture->format);
1419 st->base.layer_stride = st->base.stride * nblocksy;
1420
1421 /* In order to use the TransferFromBuffer command to update the
1422 * texture content from the buffer, the layer stride for a multi-layers
1423 * surface needs to be in multiples of 16 bytes.
1424 */
1425 if (st->upload.nlayers > 1 && st->base.layer_stride & 15)
1426 return NULL;
1427
1428 upload_size = st->base.layer_stride * st->base.box.depth;
1429 upload_size = align(upload_size, 16);
1430
1431 /* If the upload size exceeds the default buffer size, the
1432 * upload buffer manager code will try to allocate a new buffer
1433 * with the new buffer size.
1434 */
1435 u_upload_alloc(svga->tex_upload, 0, upload_size, 16,
1436 &offset, &tex_buffer, &tex_map);
1437
1438 if (!tex_map) {
1439 return NULL;
1440 }
1441
1442 st->upload.buf = tex_buffer;
1443 st->upload.map = tex_map;
1444 st->upload.offset = offset;
1445
1446 return tex_map;
1447 }
1448
1449
1450 /**
1451 * Unmap upload map transfer request
1452 */
1453 void
1454 svga_texture_transfer_unmap_upload(struct svga_context *svga,
1455 struct svga_transfer *st)
1456 {
1457 struct svga_winsys_surface *srcsurf;
1458 struct svga_winsys_surface *dstsurf;
1459 struct pipe_resource *texture = st->base.resource;
1460 struct svga_texture *tex = svga_texture(texture);
1461 enum pipe_error ret;
1462 unsigned subResource;
1463 unsigned numMipLevels;
1464 unsigned i, layer;
1465 unsigned offset = st->upload.offset;
1466
1467 assert(svga->tex_upload);
1468 assert(st->upload.buf);
1469
1470 /* unmap the texture upload buffer */
1471 u_upload_unmap(svga->tex_upload);
1472
1473 srcsurf = svga_buffer_handle(svga, st->upload.buf);
1474 dstsurf = svga_texture(texture)->handle;
1475 assert(dstsurf);
1476
1477 numMipLevels = texture->last_level + 1;
1478
1479 for (i = 0, layer = st->slice; i < st->upload.nlayers; i++, layer++) {
1480 subResource = layer * numMipLevels + st->base.level;
1481
1482 /* send a transferFromBuffer command to update the host texture surface */
1483 assert((offset & 15) == 0);
1484
1485 ret = SVGA3D_vgpu10_TransferFromBuffer(svga->swc, srcsurf,
1486 offset,
1487 st->base.stride,
1488 st->base.layer_stride,
1489 dstsurf, subResource,
1490 &st->upload.box);
1491 if (ret != PIPE_OK) {
1492 svga_context_flush(svga, NULL);
1493 ret = SVGA3D_vgpu10_TransferFromBuffer(svga->swc, srcsurf,
1494 offset,
1495 st->base.stride,
1496 st->base.layer_stride,
1497 dstsurf, subResource,
1498 &st->upload.box);
1499 assert(ret == PIPE_OK);
1500 }
1501 offset += st->base.layer_stride;
1502
1503 /* Set rendered-to flag */
1504 svga_set_texture_rendered_to(tex, layer, st->base.level);
1505 }
1506
1507 pipe_resource_reference(&st->upload.buf, NULL);
1508 }