1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
26 #include "svga3d_reg.h"
27 #include "svga3d_surfacedefs.h"
29 #include "pipe/p_state.h"
30 #include "pipe/p_defines.h"
31 #include "os/os_thread.h"
32 #include "util/u_format.h"
33 #include "util/u_inlines.h"
34 #include "util/u_math.h"
35 #include "util/u_memory.h"
36 #include "util/u_resource.h"
39 #include "svga_format.h"
40 #include "svga_screen.h"
41 #include "svga_context.h"
42 #include "svga_resource_texture.h"
43 #include "svga_resource_buffer.h"
44 #include "svga_sampler_view.h"
45 #include "svga_winsys.h"
46 #include "svga_debug.h"
50 svga_transfer_dma_band(struct svga_context
*svga
,
51 struct svga_transfer
*st
,
52 SVGA3dTransferType transfer
,
53 unsigned x
, unsigned y
, unsigned z
,
54 unsigned w
, unsigned h
, unsigned d
,
55 unsigned srcx
, unsigned srcy
, unsigned srcz
,
56 SVGA3dSurfaceDMAFlags flags
)
58 struct svga_texture
*texture
= svga_texture(st
->base
.resource
);
62 assert(!st
->use_direct_map
);
74 SVGA_DBG(DEBUG_DMA
, "dma %s sid %p, face %u, (%u, %u, %u) - "
75 "(%u, %u, %u), %ubpp\n",
76 transfer
== SVGA3D_WRITE_HOST_VRAM
? "to" : "from",
85 util_format_get_blocksize(texture
->b
.b
.format
) * 8 /
86 (util_format_get_blockwidth(texture
->b
.b
.format
)
87 * util_format_get_blockheight(texture
->b
.b
.format
)));
89 ret
= SVGA3D_SurfaceDMA(svga
->swc
, st
, transfer
, &box
, 1, flags
);
91 svga_context_flush(svga
, NULL
);
92 ret
= SVGA3D_SurfaceDMA(svga
->swc
, st
, transfer
, &box
, 1, flags
);
93 assert(ret
== PIPE_OK
);
99 svga_transfer_dma(struct svga_context
*svga
,
100 struct svga_transfer
*st
,
101 SVGA3dTransferType transfer
,
102 SVGA3dSurfaceDMAFlags flags
)
104 struct svga_texture
*texture
= svga_texture(st
->base
.resource
);
105 struct svga_screen
*screen
= svga_screen(texture
->b
.b
.screen
);
106 struct svga_winsys_screen
*sws
= screen
->sws
;
107 struct pipe_fence_handle
*fence
= NULL
;
109 assert(!st
->use_direct_map
);
111 if (transfer
== SVGA3D_READ_HOST_VRAM
) {
112 SVGA_DBG(DEBUG_PERF
, "%s: readback transfer\n", __FUNCTION__
);
115 /* Ensure any pending operations on host surfaces are queued on the command
118 svga_surfaces_flush( svga
);
121 /* Do the DMA transfer in a single go */
122 svga_transfer_dma_band(svga
, st
, transfer
,
123 st
->base
.box
.x
, st
->base
.box
.y
, st
->base
.box
.z
,
124 st
->base
.box
.width
, st
->base
.box
.height
, st
->base
.box
.depth
,
128 if (transfer
== SVGA3D_READ_HOST_VRAM
) {
129 svga_context_flush(svga
, &fence
);
130 sws
->fence_finish(sws
, fence
, 0);
131 sws
->fence_reference(sws
, &fence
, NULL
);
136 unsigned blockheight
=
137 util_format_get_blockheight(st
->base
.resource
->format
);
139 h
= st
->hw_nblocksy
* blockheight
;
142 for (y
= 0; y
< st
->base
.box
.height
; y
+= h
) {
143 unsigned offset
, length
;
146 if (y
+ h
> st
->base
.box
.height
)
147 h
= st
->base
.box
.height
- y
;
149 /* Transfer band must be aligned to pixel block boundaries */
150 assert(y
% blockheight
== 0);
151 assert(h
% blockheight
== 0);
153 offset
= y
* st
->base
.stride
/ blockheight
;
154 length
= h
* st
->base
.stride
/ blockheight
;
156 sw
= (uint8_t *) st
->swbuf
+ offset
;
158 if (transfer
== SVGA3D_WRITE_HOST_VRAM
) {
159 unsigned usage
= PIPE_TRANSFER_WRITE
;
161 /* Wait for the previous DMAs to complete */
162 /* TODO: keep one DMA (at half the size) in the background */
164 svga_context_flush(svga
, NULL
);
165 usage
|= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
;
168 hw
= sws
->buffer_map(sws
, st
->hwbuf
, usage
);
171 memcpy(hw
, sw
, length
);
172 sws
->buffer_unmap(sws
, st
->hwbuf
);
176 svga_transfer_dma_band(svga
, st
, transfer
,
177 st
->base
.box
.x
, y
, st
->base
.box
.z
,
178 st
->base
.box
.width
, h
, st
->base
.box
.depth
,
182 * Prevent the texture contents to be discarded on the next band
185 flags
.discard
= FALSE
;
187 if (transfer
== SVGA3D_READ_HOST_VRAM
) {
188 svga_context_flush(svga
, &fence
);
189 sws
->fence_finish(sws
, fence
, 0);
191 hw
= sws
->buffer_map(sws
, st
->hwbuf
, PIPE_TRANSFER_READ
);
194 memcpy(sw
, hw
, length
);
195 sws
->buffer_unmap(sws
, st
->hwbuf
);
204 svga_texture_get_handle(struct pipe_screen
*screen
,
205 struct pipe_resource
*texture
,
206 struct winsys_handle
*whandle
)
208 struct svga_winsys_screen
*sws
= svga_winsys_screen(texture
->screen
);
211 assert(svga_texture(texture
)->key
.cachable
== 0);
212 svga_texture(texture
)->key
.cachable
= 0;
214 stride
= util_format_get_nblocksx(texture
->format
, texture
->width0
) *
215 util_format_get_blocksize(texture
->format
);
217 return sws
->surface_get_handle(sws
, svga_texture(texture
)->handle
,
223 svga_texture_destroy(struct pipe_screen
*screen
,
224 struct pipe_resource
*pt
)
226 struct svga_screen
*ss
= svga_screen(screen
);
227 struct svga_texture
*tex
= svga_texture(pt
);
229 ss
->texture_timestamp
++;
231 svga_sampler_view_reference(&tex
->cached_view
, NULL
);
234 DBG("%s deleting %p\n", __FUNCTION__, (void *) tex);
236 SVGA_DBG(DEBUG_DMA
, "unref sid %p (texture)\n", tex
->handle
);
237 svga_screen_surface_destroy(ss
, &tex
->key
, &tex
->handle
);
239 ss
->hud
.total_resource_bytes
-= tex
->size
;
242 FREE(tex
->rendered_to
);
246 assert(ss
->hud
.num_resources
> 0);
247 if (ss
->hud
.num_resources
> 0)
248 ss
->hud
.num_resources
--;
253 * Determine if we need to read back a texture image before mapping it.
256 need_tex_readback(struct pipe_transfer
*transfer
)
258 struct svga_texture
*t
= svga_texture(transfer
->resource
);
260 if (transfer
->usage
& PIPE_TRANSFER_READ
)
263 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) &&
264 ((transfer
->usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) == 0)) {
267 if (transfer
->resource
->target
== PIPE_TEXTURE_CUBE
) {
268 assert(transfer
->box
.depth
== 1);
269 face
= transfer
->box
.z
;
274 if (svga_was_texture_rendered_to(t
, face
, transfer
->level
)) {
283 static enum pipe_error
284 readback_image_vgpu9(struct svga_context
*svga
,
285 struct svga_winsys_surface
*surf
,
291 ret
= SVGA3D_ReadbackGBImage(svga
->swc
, surf
, slice
, level
);
292 if (ret
!= PIPE_OK
) {
293 svga_context_flush(svga
, NULL
);
294 ret
= SVGA3D_ReadbackGBImage(svga
->swc
, surf
, slice
, level
);
300 static enum pipe_error
301 readback_image_vgpu10(struct svga_context
*svga
,
302 struct svga_winsys_surface
*surf
,
305 unsigned numMipLevels
)
308 unsigned subResource
;
310 subResource
= slice
* numMipLevels
+ level
;
311 ret
= SVGA3D_vgpu10_ReadbackSubResource(svga
->swc
, surf
, subResource
);
312 if (ret
!= PIPE_OK
) {
313 svga_context_flush(svga
, NULL
);
314 ret
= SVGA3D_vgpu10_ReadbackSubResource(svga
->swc
, surf
, subResource
);
321 svga_texture_transfer_map(struct pipe_context
*pipe
,
322 struct pipe_resource
*texture
,
325 const struct pipe_box
*box
,
326 struct pipe_transfer
**ptransfer
)
328 struct svga_context
*svga
= svga_context(pipe
);
329 struct svga_screen
*ss
= svga_screen(pipe
->screen
);
330 struct svga_winsys_screen
*sws
= ss
->sws
;
331 struct svga_texture
*tex
= svga_texture(texture
);
332 struct svga_transfer
*st
;
333 unsigned nblocksx
, nblocksy
;
334 boolean use_direct_map
= svga_have_gb_objects(svga
) &&
335 !svga_have_gb_dma(svga
);
337 void *returnVal
= NULL
;
338 int64_t begin
= svga_get_time(svga
);
340 SVGA_STATS_TIME_PUSH(sws
, SVGA_STATS_TIME_TEXTRANSFERMAP
);
342 /* We can't map texture storage directly unless we have GB objects */
343 if (usage
& PIPE_TRANSFER_MAP_DIRECTLY
) {
344 if (svga_have_gb_objects(svga
))
345 use_direct_map
= TRUE
;
350 st
= CALLOC_STRUCT(svga_transfer
);
354 st
->base
.level
= level
;
355 st
->base
.usage
= usage
;
358 switch (tex
->b
.b
.target
) {
359 case PIPE_TEXTURE_CUBE
:
360 st
->slice
= st
->base
.box
.z
;
361 st
->base
.box
.z
= 0; /* so we don't apply double offsets below */
363 case PIPE_TEXTURE_2D_ARRAY
:
364 case PIPE_TEXTURE_1D_ARRAY
:
365 st
->slice
= st
->base
.box
.z
;
366 st
->base
.box
.z
= 0; /* so we don't apply double offsets below */
368 /* Force direct map for transfering multiple slices */
369 if (st
->base
.box
.depth
> 1)
370 use_direct_map
= svga_have_gb_objects(svga
);
380 if (use_direct_map
) {
381 /* we'll directly access the guest-backed surface */
382 w
= u_minify(texture
->width0
, level
);
383 h
= u_minify(texture
->height0
, level
);
384 d
= u_minify(texture
->depth0
, level
);
387 /* we'll put the data into a tightly packed buffer */
392 nblocksx
= util_format_get_nblocksx(texture
->format
, w
);
393 nblocksy
= util_format_get_nblocksy(texture
->format
, h
);
396 pipe_resource_reference(&st
->base
.resource
, texture
);
398 st
->base
.stride
= nblocksx
*util_format_get_blocksize(texture
->format
);
399 st
->base
.layer_stride
= st
->base
.stride
* nblocksy
;
401 if (usage
& PIPE_TRANSFER_WRITE
) {
402 /* record texture upload for HUD */
403 svga
->hud
.num_bytes_uploaded
+=
404 nblocksx
* nblocksy
* d
* util_format_get_blocksize(texture
->format
);
407 if (!use_direct_map
) {
408 /* Use a DMA buffer */
409 st
->hw_nblocksy
= nblocksy
;
411 st
->hwbuf
= svga_winsys_buffer_create(svga
, 1, 0,
412 st
->hw_nblocksy
* st
->base
.stride
* d
);
413 while(!st
->hwbuf
&& (st
->hw_nblocksy
/= 2)) {
414 st
->hwbuf
= svga_winsys_buffer_create(svga
, 1, 0,
415 st
->hw_nblocksy
* st
->base
.stride
* d
);
423 if (st
->hw_nblocksy
< nblocksy
) {
424 /* We couldn't allocate a hardware buffer big enough for the transfer,
425 * so allocate regular malloc memory instead */
427 debug_printf("%s: failed to allocate %u KB of DMA, "
428 "splitting into %u x %u KB DMA transfers\n",
430 (nblocksy
*st
->base
.stride
+ 1023)/1024,
431 (nblocksy
+ st
->hw_nblocksy
- 1)/st
->hw_nblocksy
,
432 (st
->hw_nblocksy
*st
->base
.stride
+ 1023)/1024);
435 st
->swbuf
= MALLOC(nblocksy
* st
->base
.stride
* d
);
437 sws
->buffer_destroy(sws
, st
->hwbuf
);
443 if (usage
& PIPE_TRANSFER_READ
) {
444 SVGA3dSurfaceDMAFlags flags
;
445 memset(&flags
, 0, sizeof flags
);
446 svga_transfer_dma(svga
, st
, SVGA3D_READ_HOST_VRAM
, flags
);
449 struct pipe_transfer
*transfer
= &st
->base
;
450 struct svga_winsys_surface
*surf
= tex
->handle
;
457 /* If this is the first time mapping to the surface in this
458 * command buffer, clear the dirty masks of this surface.
460 if (sws
->surface_is_flushed(sws
, surf
)) {
461 svga_clear_texture_dirty(tex
);
464 if (need_tex_readback(transfer
)) {
467 svga_surfaces_flush(svga
);
469 if (svga_have_vgpu10(svga
)) {
470 ret
= readback_image_vgpu10(svga
, surf
, st
->slice
, transfer
->level
,
471 tex
->b
.b
.last_level
+ 1);
473 ret
= readback_image_vgpu9(svga
, surf
, st
->slice
, transfer
->level
);
476 svga
->hud
.num_readbacks
++;
477 SVGA_STATS_COUNT_INC(sws
, SVGA_STATS_COUNT_TEXREADBACK
);
479 assert(ret
== PIPE_OK
);
482 svga_context_flush(svga
, NULL
);
485 * Note: if PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE were specified
486 * we could potentially clear the flag for all faces/layers/mips.
488 svga_clear_texture_rendered_to(tex
, st
->slice
, transfer
->level
);
491 assert(transfer
->usage
& PIPE_TRANSFER_WRITE
);
492 if ((transfer
->usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) == 0) {
493 if (svga_is_texture_dirty(tex
, st
->slice
, transfer
->level
)) {
495 * do a surface flush if the subresource has been modified
496 * in this command buffer.
498 svga_surfaces_flush(svga
);
499 if (!sws
->surface_is_flushed(sws
, surf
)) {
500 svga
->hud
.surface_write_flushes
++;
501 SVGA_STATS_COUNT_INC(sws
, SVGA_STATS_COUNT_SURFACEWRITEFLUSH
);
502 svga_context_flush(svga
, NULL
);
507 if (transfer
->usage
& PIPE_TRANSFER_WRITE
) {
508 /* mark this texture level as dirty */
509 svga_set_texture_dirty(tex
, st
->slice
, transfer
->level
);
513 st
->use_direct_map
= use_direct_map
;
515 *ptransfer
= &st
->base
;
521 returnVal
= st
->swbuf
;
523 else if (!st
->use_direct_map
) {
524 returnVal
= sws
->buffer_map(sws
, st
->hwbuf
, usage
);
527 SVGA3dSize baseLevelSize
;
528 struct svga_texture
*tex
= svga_texture(texture
);
529 struct svga_winsys_surface
*surf
= tex
->handle
;
532 unsigned offset
, mip_width
, mip_height
;
533 unsigned xoffset
= st
->base
.box
.x
;
534 unsigned yoffset
= st
->base
.box
.y
;
535 unsigned zoffset
= st
->base
.box
.z
;
537 map
= svga
->swc
->surface_map(svga
->swc
, surf
, usage
, &retry
);
538 if (map
== NULL
&& retry
) {
540 * At this point, the svga_surfaces_flush() should already have
541 * called in svga_texture_get_transfer().
543 svga_context_flush(svga
, NULL
);
544 map
= svga
->swc
->surface_map(svga
->swc
, surf
, usage
, &retry
);
548 * Make sure we return NULL if the map fails
557 * Compute the offset to the specific texture slice in the buffer.
559 baseLevelSize
.width
= tex
->b
.b
.width0
;
560 baseLevelSize
.height
= tex
->b
.b
.height0
;
561 baseLevelSize
.depth
= tex
->b
.b
.depth0
;
563 if ((tex
->b
.b
.target
== PIPE_TEXTURE_1D_ARRAY
) ||
564 (tex
->b
.b
.target
== PIPE_TEXTURE_2D_ARRAY
)) {
565 st
->base
.layer_stride
=
566 svga3dsurface_get_image_offset(tex
->key
.format
, baseLevelSize
,
567 tex
->b
.b
.last_level
+ 1, 1, 0);
570 offset
= svga3dsurface_get_image_offset(tex
->key
.format
, baseLevelSize
,
571 tex
->b
.b
.last_level
+ 1, /* numMips */
577 mip_width
= u_minify(tex
->b
.b
.width0
, level
);
578 mip_height
= u_minify(tex
->b
.b
.height0
, level
);
580 offset
+= svga3dsurface_get_pixel_offset(tex
->key
.format
,
581 mip_width
, mip_height
,
582 xoffset
, yoffset
, zoffset
);
583 returnVal
= (void *) (map
+ offset
);
586 svga
->hud
.map_buffer_time
+= (svga_get_time(svga
) - begin
);
587 svga
->hud
.num_resources_mapped
++;
590 SVGA_STATS_TIME_POP(sws
);
596 * Unmap a GB texture surface.
599 svga_texture_surface_unmap(struct svga_context
*svga
,
600 struct pipe_transfer
*transfer
)
602 struct svga_winsys_surface
*surf
= svga_texture(transfer
->resource
)->handle
;
603 struct svga_winsys_context
*swc
= svga
->swc
;
608 swc
->surface_unmap(swc
, surf
, &rebind
);
611 ret
= SVGA3D_BindGBSurface(swc
, surf
);
612 if (ret
!= PIPE_OK
) {
613 /* flush and retry */
614 svga_context_flush(svga
, NULL
);
615 ret
= SVGA3D_BindGBSurface(swc
, surf
);
616 assert(ret
== PIPE_OK
);
622 static enum pipe_error
623 update_image_vgpu9(struct svga_context
*svga
,
624 struct svga_winsys_surface
*surf
,
625 const SVGA3dBox
*box
,
631 ret
= SVGA3D_UpdateGBImage(svga
->swc
, surf
, box
, slice
, level
);
632 if (ret
!= PIPE_OK
) {
633 svga_context_flush(svga
, NULL
);
634 ret
= SVGA3D_UpdateGBImage(svga
->swc
, surf
, box
, slice
, level
);
640 static enum pipe_error
641 update_image_vgpu10(struct svga_context
*svga
,
642 struct svga_winsys_surface
*surf
,
643 const SVGA3dBox
*box
,
646 unsigned numMipLevels
)
649 unsigned subResource
;
651 subResource
= slice
* numMipLevels
+ level
;
652 ret
= SVGA3D_vgpu10_UpdateSubResource(svga
->swc
, surf
, box
, subResource
);
653 if (ret
!= PIPE_OK
) {
654 svga_context_flush(svga
, NULL
);
655 ret
= SVGA3D_vgpu10_UpdateSubResource(svga
->swc
, surf
, box
, subResource
);
662 svga_texture_transfer_unmap(struct pipe_context
*pipe
,
663 struct pipe_transfer
*transfer
)
665 struct svga_context
*svga
= svga_context(pipe
);
666 struct svga_screen
*ss
= svga_screen(pipe
->screen
);
667 struct svga_winsys_screen
*sws
= ss
->sws
;
668 struct svga_transfer
*st
= svga_transfer(transfer
);
669 struct svga_texture
*tex
= svga_texture(transfer
->resource
);
671 SVGA_STATS_TIME_PUSH(sws
, SVGA_STATS_TIME_TEXTRANSFERUNMAP
);
674 if (st
->use_direct_map
) {
675 svga_texture_surface_unmap(svga
, transfer
);
678 sws
->buffer_unmap(sws
, st
->hwbuf
);
682 if (!st
->use_direct_map
&& (st
->base
.usage
& PIPE_TRANSFER_WRITE
)) {
683 /* Use DMA to transfer texture data */
684 SVGA3dSurfaceDMAFlags flags
;
686 memset(&flags
, 0, sizeof flags
);
687 if (transfer
->usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
688 flags
.discard
= TRUE
;
690 if (transfer
->usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) {
691 flags
.unsynchronized
= TRUE
;
694 svga_transfer_dma(svga
, st
, SVGA3D_WRITE_HOST_VRAM
, flags
);
695 } else if (transfer
->usage
& PIPE_TRANSFER_WRITE
) {
696 struct svga_winsys_surface
*surf
=
697 svga_texture(transfer
->resource
)->handle
;
700 unsigned nlayers
= 1;
702 assert(svga_have_gb_objects(svga
));
704 /* update the effected region */
705 box
.x
= transfer
->box
.x
;
706 box
.y
= transfer
->box
.y
;
707 box
.w
= transfer
->box
.width
;
708 box
.h
= transfer
->box
.height
;
709 box
.d
= transfer
->box
.depth
;
711 switch (tex
->b
.b
.target
) {
712 case PIPE_TEXTURE_CUBE
:
715 case PIPE_TEXTURE_2D_ARRAY
:
720 case PIPE_TEXTURE_1D_ARRAY
:
726 box
.z
= transfer
->box
.z
;
731 debug_printf("%s %d, %d, %d %d x %d x %d\n",
734 box
.w
, box
.h
, box
.d
);
736 if (svga_have_vgpu10(svga
)) {
738 for (i
= 0; i
< nlayers
; i
++) {
739 ret
= update_image_vgpu10(svga
, surf
, &box
,
740 st
->slice
+ i
, transfer
->level
,
741 tex
->b
.b
.last_level
+ 1);
742 assert(ret
== PIPE_OK
);
745 assert(nlayers
== 1);
746 ret
= update_image_vgpu9(svga
, surf
, &box
, st
->slice
, transfer
->level
);
747 assert(ret
== PIPE_OK
);
750 svga
->hud
.num_resource_updates
++;
755 ss
->texture_timestamp
++;
756 svga_age_texture_view(tex
, transfer
->level
);
757 if (transfer
->resource
->target
== PIPE_TEXTURE_CUBE
)
758 svga_define_texture_level(tex
, st
->slice
, transfer
->level
);
760 svga_define_texture_level(tex
, 0, transfer
->level
);
762 pipe_resource_reference(&st
->base
.resource
, NULL
);
765 if (!st
->use_direct_map
) {
766 sws
->buffer_destroy(sws
, st
->hwbuf
);
769 SVGA_STATS_TIME_POP(sws
);
774 * Does format store depth values?
776 static inline boolean
777 format_has_depth(enum pipe_format format
)
779 const struct util_format_description
*desc
= util_format_description(format
);
780 return util_format_has_depth(desc
);
784 struct u_resource_vtbl svga_texture_vtbl
=
786 svga_texture_get_handle
, /* get_handle */
787 svga_texture_destroy
, /* resource_destroy */
788 svga_texture_transfer_map
, /* transfer_map */
789 u_default_transfer_flush_region
, /* transfer_flush_region */
790 svga_texture_transfer_unmap
, /* transfer_unmap */
794 struct pipe_resource
*
795 svga_texture_create(struct pipe_screen
*screen
,
796 const struct pipe_resource
*template)
798 struct svga_screen
*svgascreen
= svga_screen(screen
);
799 struct svga_texture
*tex
;
800 unsigned bindings
= template->bind
;
802 SVGA_STATS_TIME_PUSH(svgascreen
->sws
,
803 SVGA_STATS_TIME_CREATETEXTURE
);
805 assert(template->last_level
< SVGA_MAX_TEXTURE_LEVELS
);
806 if (template->last_level
>= SVGA_MAX_TEXTURE_LEVELS
) {
810 tex
= CALLOC_STRUCT(svga_texture
);
815 tex
->defined
= CALLOC(template->depth0
* template->array_size
,
816 sizeof(tex
->defined
[0]));
822 tex
->rendered_to
= CALLOC(template->depth0
* template->array_size
,
823 sizeof(tex
->rendered_to
[0]));
824 if (!tex
->rendered_to
) {
828 tex
->dirty
= CALLOC(template->depth0
* template->array_size
,
829 sizeof(tex
->dirty
[0]));
834 tex
->b
.b
= *template;
835 tex
->b
.vtbl
= &svga_texture_vtbl
;
836 pipe_reference_init(&tex
->b
.b
.reference
, 1);
837 tex
->b
.b
.screen
= screen
;
840 tex
->key
.size
.width
= template->width0
;
841 tex
->key
.size
.height
= template->height0
;
842 tex
->key
.size
.depth
= template->depth0
;
843 tex
->key
.arraySize
= 1;
844 tex
->key
.numFaces
= 1;
845 tex
->key
.sampleCount
= template->nr_samples
;
847 if (template->nr_samples
> 1) {
848 tex
->key
.flags
|= SVGA3D_SURFACE_MASKABLE_ANTIALIAS
;
851 if (svgascreen
->sws
->have_vgpu10
) {
852 switch (template->target
) {
853 case PIPE_TEXTURE_1D
:
854 tex
->key
.flags
|= SVGA3D_SURFACE_1D
;
856 case PIPE_TEXTURE_1D_ARRAY
:
857 tex
->key
.flags
|= SVGA3D_SURFACE_1D
;
859 case PIPE_TEXTURE_2D_ARRAY
:
860 tex
->key
.flags
|= SVGA3D_SURFACE_ARRAY
;
861 tex
->key
.arraySize
= template->array_size
;
863 case PIPE_TEXTURE_3D
:
864 tex
->key
.flags
|= SVGA3D_SURFACE_VOLUME
;
866 case PIPE_TEXTURE_CUBE
:
867 tex
->key
.flags
|= (SVGA3D_SURFACE_CUBEMAP
| SVGA3D_SURFACE_ARRAY
);
868 tex
->key
.numFaces
= 6;
875 switch (template->target
) {
876 case PIPE_TEXTURE_3D
:
877 tex
->key
.flags
|= SVGA3D_SURFACE_VOLUME
;
879 case PIPE_TEXTURE_CUBE
:
880 tex
->key
.flags
|= SVGA3D_SURFACE_CUBEMAP
;
881 tex
->key
.numFaces
= 6;
888 tex
->key
.cachable
= 1;
890 if ((bindings
& (PIPE_BIND_RENDER_TARGET
| PIPE_BIND_DEPTH_STENCIL
)) &&
891 !(bindings
& PIPE_BIND_SAMPLER_VIEW
)) {
892 /* Also check if the format can be sampled from */
893 if (screen
->is_format_supported(screen
, template->format
,
895 template->nr_samples
,
896 PIPE_BIND_SAMPLER_VIEW
)) {
897 bindings
|= PIPE_BIND_SAMPLER_VIEW
;
901 if (bindings
& PIPE_BIND_SAMPLER_VIEW
) {
902 tex
->key
.flags
|= SVGA3D_SURFACE_HINT_TEXTURE
;
903 tex
->key
.flags
|= SVGA3D_SURFACE_BIND_SHADER_RESOURCE
;
905 if (!(bindings
& PIPE_BIND_RENDER_TARGET
)) {
906 /* Also check if the format is renderable */
907 if (screen
->is_format_supported(screen
, template->format
,
909 template->nr_samples
,
910 PIPE_BIND_RENDER_TARGET
)) {
911 bindings
|= PIPE_BIND_RENDER_TARGET
;
916 if (bindings
& PIPE_BIND_DISPLAY_TARGET
) {
917 tex
->key
.cachable
= 0;
920 if (bindings
& PIPE_BIND_SHARED
) {
921 tex
->key
.cachable
= 0;
924 if (bindings
& (PIPE_BIND_SCANOUT
| PIPE_BIND_CURSOR
)) {
925 tex
->key
.scanout
= 1;
926 tex
->key
.cachable
= 0;
930 * Note: Previously we never passed the
931 * SVGA3D_SURFACE_HINT_RENDERTARGET hint. Mesa cannot
932 * know beforehand whether a texture will be used as a rendertarget or not
933 * and it always requests PIPE_BIND_RENDER_TARGET, therefore
934 * passing the SVGA3D_SURFACE_HINT_RENDERTARGET here defeats its purpose.
936 * However, this was changed since other state trackers
937 * (XA for example) uses it accurately and certain device versions
938 * relies on it in certain situations to render correctly.
940 if ((bindings
& PIPE_BIND_RENDER_TARGET
) &&
941 !util_format_is_s3tc(template->format
)) {
942 tex
->key
.flags
|= SVGA3D_SURFACE_HINT_RENDERTARGET
;
943 tex
->key
.flags
|= SVGA3D_SURFACE_BIND_RENDER_TARGET
;
946 if (bindings
& PIPE_BIND_DEPTH_STENCIL
) {
947 tex
->key
.flags
|= SVGA3D_SURFACE_HINT_DEPTHSTENCIL
;
948 tex
->key
.flags
|= SVGA3D_SURFACE_BIND_DEPTH_STENCIL
;
951 tex
->key
.numMipLevels
= template->last_level
+ 1;
953 tex
->key
.format
= svga_translate_format(svgascreen
, template->format
,
955 if (tex
->key
.format
== SVGA3D_FORMAT_INVALID
) {
959 /* The actual allocation is done with a typeless format. Typeless
960 * formats can be reinterpreted as other formats. For example,
961 * SVGA3D_R8G8B8A8_UNORM_TYPELESS can be interpreted as
962 * SVGA3D_R8G8B8A8_UNORM_SRGB or SVGA3D_R8G8B8A8_UNORM.
963 * Do not use typeless formats for SHARED, DISPLAY_TARGET or SCANOUT
966 if (svgascreen
->sws
->have_vgpu10
967 && ((bindings
& (PIPE_BIND_SHARED
|
968 PIPE_BIND_DISPLAY_TARGET
|
969 PIPE_BIND_SCANOUT
)) == 0)) {
970 SVGA3dSurfaceFormat typeless
= svga_typeless_format(tex
->key
.format
);
972 debug_printf("Convert resource type %s -> %s (bind 0x%x)\n",
973 svga_format_name(tex
->key
.format
),
974 svga_format_name(typeless
),
978 if (svga_format_is_uncompressed_snorm(tex
->key
.format
)) {
979 /* We can't normally render to snorm surfaces, but once we
980 * substitute a typeless format, we can if the rendertarget view
981 * is unorm. This can happen with GL_ARB_copy_image.
983 tex
->key
.flags
|= SVGA3D_SURFACE_HINT_RENDERTARGET
;
984 tex
->key
.flags
|= SVGA3D_SURFACE_BIND_RENDER_TARGET
;
987 tex
->key
.format
= typeless
;
990 SVGA_DBG(DEBUG_DMA
, "surface_create for texture\n", tex
->handle
);
991 tex
->handle
= svga_screen_surface_create(svgascreen
, bindings
,
992 tex
->b
.b
.usage
, &tex
->key
);
997 SVGA_DBG(DEBUG_DMA
, " --> got sid %p (texture)\n", tex
->handle
);
999 debug_reference(&tex
->b
.b
.reference
,
1000 (debug_reference_descriptor
)debug_describe_resource
, 0);
1002 tex
->size
= util_resource_size(template);
1003 svgascreen
->hud
.total_resource_bytes
+= tex
->size
;
1004 svgascreen
->hud
.num_resources
++;
1006 SVGA_STATS_TIME_POP(svgascreen
->sws
);
1013 if (tex
->rendered_to
)
1014 FREE(tex
->rendered_to
);
1019 SVGA_STATS_TIME_POP(svgascreen
->sws
);
1024 struct pipe_resource
*
1025 svga_texture_from_handle(struct pipe_screen
*screen
,
1026 const struct pipe_resource
*template,
1027 struct winsys_handle
*whandle
)
1029 struct svga_winsys_screen
*sws
= svga_winsys_screen(screen
);
1030 struct svga_screen
*ss
= svga_screen(screen
);
1031 struct svga_winsys_surface
*srf
;
1032 struct svga_texture
*tex
;
1033 enum SVGA3dSurfaceFormat format
= 0;
1036 /* Only supports one type */
1037 if ((template->target
!= PIPE_TEXTURE_2D
&&
1038 template->target
!= PIPE_TEXTURE_RECT
) ||
1039 template->last_level
!= 0 ||
1040 template->depth0
!= 1) {
1044 srf
= sws
->surface_from_handle(sws
, whandle
, &format
);
1049 if (svga_translate_format(svga_screen(screen
), template->format
,
1050 template->bind
) != format
) {
1051 unsigned f1
= svga_translate_format(svga_screen(screen
),
1052 template->format
, template->bind
);
1053 unsigned f2
= format
;
1055 /* It's okay for XRGB and ARGB or depth with/out stencil to get mixed up.
1057 if (f1
== SVGA3D_B8G8R8A8_UNORM
)
1058 f1
= SVGA3D_A8R8G8B8
;
1059 if (f1
== SVGA3D_B8G8R8X8_UNORM
)
1060 f1
= SVGA3D_X8R8G8B8
;
1062 if ( !( (f1
== f2
) ||
1063 (f1
== SVGA3D_X8R8G8B8
&& f2
== SVGA3D_A8R8G8B8
) ||
1064 (f1
== SVGA3D_X8R8G8B8
&& f2
== SVGA3D_B8G8R8X8_UNORM
) ||
1065 (f1
== SVGA3D_A8R8G8B8
&& f2
== SVGA3D_X8R8G8B8
) ||
1066 (f1
== SVGA3D_A8R8G8B8
&& f2
== SVGA3D_B8G8R8A8_UNORM
) ||
1067 (f1
== SVGA3D_Z_D24X8
&& f2
== SVGA3D_Z_D24S8
) ||
1068 (f1
== SVGA3D_Z_DF24
&& f2
== SVGA3D_Z_D24S8_INT
) ) ) {
1069 debug_printf("%s wrong format %s != %s\n", __FUNCTION__
,
1070 svga_format_name(f1
), svga_format_name(f2
));
1075 tex
= CALLOC_STRUCT(svga_texture
);
1079 tex
->defined
= CALLOC(template->depth0
* template->array_size
,
1080 sizeof(tex
->defined
[0]));
1081 if (!tex
->defined
) {
1086 tex
->b
.b
= *template;
1087 tex
->b
.vtbl
= &svga_texture_vtbl
;
1088 pipe_reference_init(&tex
->b
.b
.reference
, 1);
1089 tex
->b
.b
.screen
= screen
;
1091 SVGA_DBG(DEBUG_DMA
, "wrap surface sid %p\n", srf
);
1093 tex
->key
.cachable
= 0;
1094 tex
->key
.format
= format
;
1097 tex
->rendered_to
= CALLOC(1, sizeof(tex
->rendered_to
[0]));
1098 if (!tex
->rendered_to
)
1101 tex
->dirty
= CALLOC(1, sizeof(tex
->dirty
[0]));
1105 tex
->imported
= TRUE
;
1107 ss
->hud
.num_resources
++;
1114 if (tex
->rendered_to
)
1115 FREE(tex
->rendered_to
);
1123 svga_texture_generate_mipmap(struct pipe_context
*pipe
,
1124 struct pipe_resource
*pt
,
1125 enum pipe_format format
,
1126 unsigned base_level
,
1127 unsigned last_level
,
1128 unsigned first_layer
,
1129 unsigned last_layer
)
1131 struct pipe_sampler_view templ
, *psv
;
1132 struct svga_pipe_sampler_view
*sv
;
1133 struct svga_context
*svga
= svga_context(pipe
);
1134 struct svga_texture
*tex
= svga_texture(pt
);
1135 enum pipe_error ret
;
1137 assert(svga_have_vgpu10(svga
));
1139 /* Only support 2D texture for now */
1140 if (pt
->target
!= PIPE_TEXTURE_2D
)
1143 /* Fallback to the mipmap generation utility for those formats that
1144 * do not support hw generate mipmap
1146 if (!svga_format_support_gen_mips(format
))
1149 /* Make sure the texture surface was created with
1150 * SVGA3D_SURFACE_BIND_RENDER_TARGET
1152 if (!tex
->handle
|| !(tex
->key
.flags
& SVGA3D_SURFACE_BIND_RENDER_TARGET
))
1155 templ
.format
= format
;
1156 templ
.u
.tex
.first_layer
= first_layer
;
1157 templ
.u
.tex
.last_layer
= last_layer
;
1158 templ
.u
.tex
.first_level
= base_level
;
1159 templ
.u
.tex
.last_level
= last_level
;
1161 psv
= pipe
->create_sampler_view(pipe
, pt
, &templ
);
1165 sv
= svga_pipe_sampler_view(psv
);
1166 ret
= svga_validate_pipe_sampler_view(svga
, sv
);
1167 if (ret
!= PIPE_OK
) {
1168 svga_context_flush(svga
, NULL
);
1169 ret
= svga_validate_pipe_sampler_view(svga
, sv
);
1170 assert(ret
== PIPE_OK
);
1173 ret
= SVGA3D_vgpu10_GenMips(svga
->swc
, sv
->id
, tex
->handle
);
1174 if (ret
!= PIPE_OK
) {
1175 svga_context_flush(svga
, NULL
);
1176 ret
= SVGA3D_vgpu10_GenMips(svga
->swc
, sv
->id
, tex
->handle
);
1178 pipe_sampler_view_reference(&psv
, NULL
);
1180 svga
->hud
.num_generate_mipmap
++;