src/gallium/drivers/svga/svga_screen.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
  27 #include "util/u_format.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_inlines.h"
  30 #include "util/u_string.h"
  31 #include "util/u_math.h"
  32
  33 #include "os/os_process.h"
  34
  35 #include "svga_winsys.h"
  36 #include "svga_public.h"
  37 #include "svga_context.h"
  38 #include "svga_format.h"
  39 #include "svga_msg.h"
  40 #include "svga_screen.h"
  41 #include "svga_tgsi.h"
  42 #include "svga_resource_texture.h"
  43 #include "svga_resource.h"
  44 #include "svga_debug.h"
  45
  46 #include "svga3d_shaderdefs.h"
  47 #include "VGPU10ShaderTokens.h"
  48
  49 /* NOTE: this constant may get moved into a svga3d*.h header file */
  50 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
  51
  52 #ifdef DEBUG
  53 int SVGA_DEBUG = 0;
  54
  55 static const struct debug_named_value svga_debug_flags[] = {
  56    { "dma",         DEBUG_DMA, NULL },
  57    { "tgsi",        DEBUG_TGSI, NULL },
  58    { "pipe",        DEBUG_PIPE, NULL },
  59    { "state",       DEBUG_STATE, NULL },
  60    { "screen",      DEBUG_SCREEN, NULL },
  61    { "tex",         DEBUG_TEX, NULL },
  62    { "swtnl",       DEBUG_SWTNL, NULL },
  63    { "const",       DEBUG_CONSTS, NULL },
  64    { "viewport",    DEBUG_VIEWPORT, NULL },
  65    { "views",       DEBUG_VIEWS, NULL },
  66    { "perf",        DEBUG_PERF, NULL },
  67    { "flush",       DEBUG_FLUSH, NULL },
  68    { "sync",        DEBUG_SYNC, NULL },
  69    { "cache",       DEBUG_CACHE, NULL },
  70    { "streamout",   DEBUG_STREAMOUT, NULL },
  71    { "query",       DEBUG_QUERY, NULL },
  72    { "samplers",    DEBUG_SAMPLERS, NULL },
  73    DEBUG_NAMED_VALUE_END
  74 };
  75 #endif
  76
  77 static const char *
  78 svga_get_vendor( struct pipe_screen *pscreen )
  79 {
  80    return "VMware, Inc.";
  81 }
  82
  83
  84 static const char *
  85 svga_get_name( struct pipe_screen *pscreen )
  86 {
  87    const char *build = "", *llvm = "", *mutex = "";
  88    static char name[100];
  89 #ifdef DEBUG
  90    /* Only return internal details in the DEBUG version:
  91     */
  92    build = "build: DEBUG;";
  93    mutex = "mutex: " PIPE_ATOMIC ";";
  94 #elif defined(VMX86_STATS)
  95    build = "build: OPT;";
  96 #else
  97    build = "build: RELEASE;";
  98 #endif
  99 #ifdef HAVE_LLVM
 100    llvm = "LLVM;";
 101 #endif
 102
 103    util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
 104    return name;
 105 }
 106
 107
 108 /** Helper for querying float-valued device cap */
 109 static float
 110 get_float_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
 111               float defaultVal)
 112 {
 113    SVGA3dDevCapResult result;
 114    if (sws->get_cap(sws, cap, &result))
 115       return result.f;
 116    else
 117       return defaultVal;
 118 }
 119
 120
 121 /** Helper for querying uint-valued device cap */
 122 static unsigned
 123 get_uint_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
 124              unsigned defaultVal)
 125 {
 126    SVGA3dDevCapResult result;
 127    if (sws->get_cap(sws, cap, &result))
 128       return result.u;
 129    else
 130       return defaultVal;
 131 }
 132
 133
 134 /** Helper for querying boolean-valued device cap */
 135 static boolean
 136 get_bool_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
 137              boolean defaultVal)
 138 {
 139    SVGA3dDevCapResult result;
 140    if (sws->get_cap(sws, cap, &result))
 141       return result.b;
 142    else
 143       return defaultVal;
 144 }
 145
 146
 147 static float
 148 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 149 {
 150    struct svga_screen *svgascreen = svga_screen(screen);
 151    struct svga_winsys_screen *sws = svgascreen->sws;
 152
 153    switch (param) {
 154    case PIPE_CAPF_MAX_LINE_WIDTH:
 155       return svgascreen->maxLineWidth;
 156    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 157       return svgascreen->maxLineWidthAA;
 158
 159    case PIPE_CAPF_MAX_POINT_WIDTH:
 160       /* fall-through */
 161    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 162       return svgascreen->maxPointSize;
 163
 164    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 165       return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
 166
 167    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 168       return 15.0;
 169
 170    }
 171
 172    debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
 173    return 0;
 174 }
 175
 176
 177 static int
 178 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
 179 {
 180    struct svga_screen *svgascreen = svga_screen(screen);
 181    struct svga_winsys_screen *sws = svgascreen->sws;
 182    SVGA3dDevCapResult result;
 183
 184    switch (param) {
 185    case PIPE_CAP_NPOT_TEXTURES:
 186    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 187    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 188       return 1;
 189    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 190       /*
 191        * "In virtually every OpenGL implementation and hardware,
 192        * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
 193        * http://www.opengl.org/wiki/Blending
 194        */
 195       return sws->have_vgpu10 ? 1 : 0;
 196    case PIPE_CAP_ANISOTROPIC_FILTER:
 197       return 1;
 198    case PIPE_CAP_POINT_SPRITE:
 199       return 1;
 200    case PIPE_CAP_TGSI_TEXCOORD:
 201       return 0;
 202    case PIPE_CAP_MAX_RENDER_TARGETS:
 203       return svgascreen->max_color_buffers;
 204    case PIPE_CAP_OCCLUSION_QUERY:
 205       return 1;
 206    case PIPE_CAP_QUERY_TIME_ELAPSED:
 207       return 0;
 208    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 209       return sws->have_vgpu10;
 210    case PIPE_CAP_TEXTURE_SWIZZLE:
 211       return 1;
 212    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 213       return 0;
 214    case PIPE_CAP_USER_VERTEX_BUFFERS:
 215       return 0;
 216    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 217       return 256;
 218
 219    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 220       {
 221          unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
 222          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
 223             levels = MIN2(util_logbase2(result.u) + 1, levels);
 224          else
 225             levels = 12 /* 2048x2048 */;
 226          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
 227             levels = MIN2(util_logbase2(result.u) + 1, levels);
 228          else
 229             levels = 12 /* 2048x2048 */;
 230          return levels;
 231       }
 232
 233    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 234       if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
 235          return 8;  /* max 128x128x128 */
 236       return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
 237
 238    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 239       /*
 240        * No mechanism to query the host, and at least limited to 2048x2048 on
 241        * certain hardware.
 242        */
 243       return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
 244                   12 /* 2048x2048 */);
 245
 246    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 247       return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
 248
 249    case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
 250       return 1;
 251
 252    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 253       return 1;
 254    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 255       return sws->have_vgpu10;
 256    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 257       return 0;
 258    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 259       return !sws->have_vgpu10;
 260
 261    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 262       return 1; /* The color outputs of vertex shaders are not clamped */
 263    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 264       return 0; /* The driver can't clamp vertex colors */
 265    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 266       return 0; /* The driver can't clamp fragment colors */
 267
 268    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 269       return 1; /* expected for GL_ARB_framebuffer_object */
 270
 271    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 272       return sws->have_vgpu10 ? 330 : 120;
 273
 274    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 275       return 0;
 276
 277    case PIPE_CAP_SM3:
 278       return 1;
 279
 280    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 281    case PIPE_CAP_INDEP_BLEND_ENABLE:
 282    case PIPE_CAP_CONDITIONAL_RENDER:
 283    case PIPE_CAP_QUERY_TIMESTAMP:
 284    case PIPE_CAP_TGSI_INSTANCEID:
 285    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 286    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 287    case PIPE_CAP_FAKE_SW_MSAA:
 288       return sws->have_vgpu10;
 289
 290    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 291       return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
 292    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 293       return sws->have_vgpu10 ? 4 : 0;
 294    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 295       return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
 296    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 297    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 298       return 0;
 299    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 300       return svgascreen->ms_samples ? 1 : 0;
 301
 302    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 303       /* convert bytes to texels for the case of the largest texel
 304        * size: float[4].
 305        */
 306       return SVGA3D_DX_MAX_RESOURCE_SIZE / (4 * sizeof(float));
 307
 308    case PIPE_CAP_MIN_TEXEL_OFFSET:
 309       return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
 310    case PIPE_CAP_MAX_TEXEL_OFFSET:
 311       return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
 312
 313    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 314    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 315       return 0;
 316
 317    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 318       return sws->have_vgpu10 ? 256 : 0;
 319    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 320       return sws->have_vgpu10 ? 1024 : 0;
 321
 322    case PIPE_CAP_PRIMITIVE_RESTART:
 323       return 1; /* may be a sw fallback, depending on restart index */
 324
 325    case PIPE_CAP_GENERATE_MIPMAP:
 326       return sws->have_generate_mipmap_cmd;
 327
 328    case PIPE_CAP_NATIVE_FENCE_FD:
 329       return sws->have_fence_fd;
 330
 331    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 332       return 1;
 333
 334    /* Unsupported features */
 335    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 336    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 337    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 338    case PIPE_CAP_INDEP_BLEND_FUNC:
 339    case PIPE_CAP_TEXTURE_BARRIER:
 340    case PIPE_CAP_MAX_VERTEX_STREAMS:
 341    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 342    case PIPE_CAP_COMPUTE:
 343    case PIPE_CAP_START_INSTANCE:
 344    case PIPE_CAP_CUBE_MAP_ARRAY:
 345    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 346    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 347    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 348    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 349    case PIPE_CAP_TEXTURE_GATHER_SM5:
 350    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 351    case PIPE_CAP_TEXTURE_QUERY_LOD:
 352    case PIPE_CAP_SAMPLE_SHADING:
 353    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 354    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 355    case PIPE_CAP_DRAW_INDIRECT:
 356    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 357    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 358    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 359    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 360    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 361    case PIPE_CAP_CLIP_HALFZ:
 362    case PIPE_CAP_VERTEXID_NOBASE:
 363    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 364    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 365    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 366    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 367    case PIPE_CAP_INVALIDATE_BUFFER:
 368    case PIPE_CAP_STRING_MARKER:
 369    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 370    case PIPE_CAP_QUERY_MEMORY_INFO:
 371    case PIPE_CAP_PCI_GROUP:
 372    case PIPE_CAP_PCI_BUS:
 373    case PIPE_CAP_PCI_DEVICE:
 374    case PIPE_CAP_PCI_FUNCTION:
 375    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 376       return 0;
 377    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 378       return 64;
 379    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 380    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 381    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 382       return 1;  /* need 4-byte alignment for all offsets and strides */
 383    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 384       return 2048;
 385    case PIPE_CAP_MAX_VIEWPORTS:
 386       return 1;
 387    case PIPE_CAP_ENDIANNESS:
 388       return PIPE_ENDIAN_LITTLE;
 389
 390    case PIPE_CAP_VENDOR_ID:
 391       return 0x15ad; /* VMware Inc. */
 392    case PIPE_CAP_DEVICE_ID:
 393       return 0x0405; /* assume SVGA II */
 394    case PIPE_CAP_ACCELERATED:
 395       return 0; /* XXX: */
 396    case PIPE_CAP_VIDEO_MEMORY:
 397       /* XXX: Query the host ? */
 398       return 1;
 399    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 400       return sws->have_vgpu10;
 401    case PIPE_CAP_CLEAR_TEXTURE:
 402       return sws->have_vgpu10;
 403    case PIPE_CAP_UMA:
 404    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 405    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 406    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 407    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 408    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 409    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 410    case PIPE_CAP_TGSI_TXQS:
 411    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 412    case PIPE_CAP_SHAREABLE_SHADERS:
 413    case PIPE_CAP_DRAW_PARAMETERS:
 414    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 415    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 416    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 417    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 418    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 419    case PIPE_CAP_CULL_DISTANCE:
 420    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 421    case PIPE_CAP_TGSI_VOTE:
 422    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 423    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 424    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 425    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 426    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 427    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 428    case PIPE_CAP_TGSI_FS_FBFETCH:
 429    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 430    case PIPE_CAP_DOUBLES:
 431    case PIPE_CAP_INT64:
 432    case PIPE_CAP_INT64_DIVMOD:
 433    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 434    case PIPE_CAP_TGSI_CLOCK:
 435    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 436    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 437    case PIPE_CAP_TGSI_BALLOT:
 438    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 439    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 440    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 441    case PIPE_CAP_POST_DEPTH_COVERAGE:
 442    case PIPE_CAP_BINDLESS_TEXTURE:
 443    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 444    case PIPE_CAP_QUERY_SO_OVERFLOW:
 445    case PIPE_CAP_MEMOBJ:
 446    case PIPE_CAP_LOAD_CONSTBUF:
 447    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 448    case PIPE_CAP_TILE_RASTER_ORDER:
 449    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 450    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 451    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 452    case PIPE_CAP_FENCE_SIGNAL:
 453    case PIPE_CAP_CONSTBUF0_FLAGS:
 454       return 0;
 455    }
 456
 457    debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
 458    return 0;
 459 }
 460
 461
 462 static int
 463 vgpu9_get_shader_param(struct pipe_screen *screen,
 464                        enum pipe_shader_type shader,
 465                        enum pipe_shader_cap param)
 466 {
 467    struct svga_screen *svgascreen = svga_screen(screen);
 468    struct svga_winsys_screen *sws = svgascreen->sws;
 469    unsigned val;
 470
 471    assert(!sws->have_vgpu10);
 472
 473    switch (shader)
 474    {
 475    case PIPE_SHADER_FRAGMENT:
 476       switch (param)
 477       {
 478       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 479       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 480          return get_uint_cap(sws,
 481                              SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
 482                              512);
 483       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 484       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 485          return 512;
 486       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 487          return SVGA3D_MAX_NESTING_LEVEL;
 488       case PIPE_SHADER_CAP_MAX_INPUTS:
 489          return 10;
 490       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 491          return svgascreen->max_color_buffers;
 492       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 493          return 224 * sizeof(float[4]);
 494       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 495          return 1;
 496       case PIPE_SHADER_CAP_MAX_TEMPS:
 497          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
 498          return MIN2(val, SVGA3D_TEMPREG_MAX);
 499       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 500          /*
 501           * Although PS 3.0 has some addressing abilities it can only represent
 502           * loops that can be statically determined and unrolled. Given we can
 503           * only handle a subset of the cases that the state tracker already
 504           * does it is better to defer loop unrolling to the state tracker.
 505           */
 506          return 0;
 507       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 508          return 0;
 509       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 510          return 0;
 511       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 512       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 513       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 514          return 0;
 515       case PIPE_SHADER_CAP_SUBROUTINES:
 516          return 0;
 517       case PIPE_SHADER_CAP_INT64_ATOMICS:
 518       case PIPE_SHADER_CAP_INTEGERS:
 519          return 0;
 520       case PIPE_SHADER_CAP_FP16:
 521          return 0;
 522       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 523       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 524          return 16;
 525       case PIPE_SHADER_CAP_PREFERRED_IR:
 526          return PIPE_SHADER_IR_TGSI;
 527       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 528          return 0;
 529       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 530       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 531       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 532       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 533       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 534       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 535       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 536       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 537       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 538       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 539       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 540          return 0;
 541       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 542          return 32;
 543       }
 544       /* If we get here, we failed to handle a cap above */
 545       debug_printf("Unexpected fragment shader query %u\n", param);
 546       return 0;
 547    case PIPE_SHADER_VERTEX:
 548       switch (param)
 549       {
 550       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 551       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 552          return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
 553                              512);
 554       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 555       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 556          /* XXX: until we have vertex texture support */
 557          return 0;
 558       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 559          return SVGA3D_MAX_NESTING_LEVEL;
 560       case PIPE_SHADER_CAP_MAX_INPUTS:
 561          return 16;
 562       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 563          return 10;
 564       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 565          return 256 * sizeof(float[4]);
 566       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 567          return 1;
 568       case PIPE_SHADER_CAP_MAX_TEMPS:
 569          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
 570          return MIN2(val, SVGA3D_TEMPREG_MAX);
 571       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 572          return 0;
 573       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 574          return 0;
 575       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 576       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 577          return 1;
 578       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 579          return 0;
 580       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 581          return 1;
 582       case PIPE_SHADER_CAP_SUBROUTINES:
 583          return 0;
 584       case PIPE_SHADER_CAP_INT64_ATOMICS:
 585       case PIPE_SHADER_CAP_INTEGERS:
 586          return 0;
 587       case PIPE_SHADER_CAP_FP16:
 588          return 0;
 589       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 590       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 591          return 0;
 592       case PIPE_SHADER_CAP_PREFERRED_IR:
 593          return PIPE_SHADER_IR_TGSI;
 594       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 595          return 0;
 596       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 597       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 598       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 599       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 600       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 601       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 602       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 603       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 604       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 605       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 606       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 607          return 0;
 608       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 609          return 32;
 610       }
 611       /* If we get here, we failed to handle a cap above */
 612       debug_printf("Unexpected vertex shader query %u\n", param);
 613       return 0;
 614    case PIPE_SHADER_GEOMETRY:
 615    case PIPE_SHADER_COMPUTE:
 616    case PIPE_SHADER_TESS_CTRL:
 617    case PIPE_SHADER_TESS_EVAL:
 618       /* no support for geometry, tess or compute shaders at this time */
 619       return 0;
 620    default:
 621       debug_printf("Unexpected shader type (%u) query\n", shader);
 622       return 0;
 623    }
 624    return 0;
 625 }
 626
 627
 628 static int
 629 vgpu10_get_shader_param(struct pipe_screen *screen,
 630                         enum pipe_shader_type shader,
 631                         enum pipe_shader_cap param)
 632 {
 633    struct svga_screen *svgascreen = svga_screen(screen);
 634    struct svga_winsys_screen *sws = svgascreen->sws;
 635
 636    assert(sws->have_vgpu10);
 637    (void) sws;  /* silence unused var warnings in non-debug builds */
 638
 639    /* Only VS, GS, FS supported */
 640    if (shader != PIPE_SHADER_VERTEX &&
 641        shader != PIPE_SHADER_GEOMETRY &&
 642        shader != PIPE_SHADER_FRAGMENT) {
 643       return 0;
 644    }
 645
 646    /* NOTE: we do not query the device for any caps/limits at this time */
 647
 648    /* Generally the same limits for vertex, geometry and fragment shaders */
 649    switch (param) {
 650    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 651    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 652    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 653    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 654       return 64 * 1024;
 655    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 656       return 64;
 657    case PIPE_SHADER_CAP_MAX_INPUTS:
 658       if (shader == PIPE_SHADER_FRAGMENT)
 659          return VGPU10_MAX_FS_INPUTS;
 660       else if (shader == PIPE_SHADER_GEOMETRY)
 661          return VGPU10_MAX_GS_INPUTS;
 662       else
 663          return VGPU10_MAX_VS_INPUTS;
 664    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 665       if (shader == PIPE_SHADER_FRAGMENT)
 666          return VGPU10_MAX_FS_OUTPUTS;
 667       else if (shader == PIPE_SHADER_GEOMETRY)
 668          return VGPU10_MAX_GS_OUTPUTS;
 669       else
 670          return VGPU10_MAX_VS_OUTPUTS;
 671    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 672       return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
 673    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 674       return svgascreen->max_const_buffers;
 675    case PIPE_SHADER_CAP_MAX_TEMPS:
 676       return VGPU10_MAX_TEMPS;
 677    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 678    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 679    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 680    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 681       return TRUE; /* XXX verify */
 682    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 683    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 684    case PIPE_SHADER_CAP_SUBROUTINES:
 685    case PIPE_SHADER_CAP_INTEGERS:
 686       return TRUE;
 687    case PIPE_SHADER_CAP_FP16:
 688       return FALSE;
 689    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 690    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 691       return SVGA3D_DX_MAX_SAMPLERS;
 692    case PIPE_SHADER_CAP_PREFERRED_IR:
 693       return PIPE_SHADER_IR_TGSI;
 694    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 695       return 0;
 696    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 697    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 698    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 699    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 700    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 701    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 702    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 703    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 704    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 705    case PIPE_SHADER_CAP_INT64_ATOMICS:
 706    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 707    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 708       return 0;
 709    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 710       return 32;
 711    default:
 712       debug_printf("Unexpected vgpu10 shader query %u\n", param);
 713       return 0;
 714    }
 715    return 0;
 716 }
 717
 718
 719 static int
 720 svga_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
 721                       enum pipe_shader_cap param)
 722 {
 723    struct svga_screen *svgascreen = svga_screen(screen);
 724    struct svga_winsys_screen *sws = svgascreen->sws;
 725    if (sws->have_vgpu10) {
 726       return vgpu10_get_shader_param(screen, shader, param);
 727    }
 728    else {
 729       return vgpu9_get_shader_param(screen, shader, param);
 730    }
 731 }
 732
 733
 734 static void
 735 svga_fence_reference(struct pipe_screen *screen,
 736                      struct pipe_fence_handle **ptr,
 737                      struct pipe_fence_handle *fence)
 738 {
 739    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 740    sws->fence_reference(sws, ptr, fence);
 741 }
 742
 743
 744 static boolean
 745 svga_fence_finish(struct pipe_screen *screen,
 746                   struct pipe_context *ctx,
 747                   struct pipe_fence_handle *fence,
 748                   uint64_t timeout)
 749 {
 750    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 751    boolean retVal;
 752
 753    SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
 754
 755    if (!timeout) {
 756       retVal = sws->fence_signalled(sws, fence, 0) == 0;
 757    }
 758    else {
 759       SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
 760                __FUNCTION__, fence);
 761
 762       retVal = sws->fence_finish(sws, fence, timeout, 0) == 0;
 763    }
 764
 765    SVGA_STATS_TIME_POP(sws);
 766
 767    return retVal;
 768 }
 769
 770
 771 static int
 772 svga_fence_get_fd(struct pipe_screen *screen,
 773                   struct pipe_fence_handle *fence)
 774 {
 775    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 776
 777    return sws->fence_get_fd(sws, fence, TRUE);
 778 }
 779
 780
 781 static int
 782 svga_get_driver_query_info(struct pipe_screen *screen,
 783                            unsigned index,
 784                            struct pipe_driver_query_info *info)
 785 {
 786 #define QUERY(NAME, ENUM, UNITS) \
 787    {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
 788
 789    static const struct pipe_driver_query_info queries[] = {
 790       /* per-frame counters */
 791       QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
 792             PIPE_DRIVER_QUERY_TYPE_UINT64),
 793       QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
 794             PIPE_DRIVER_QUERY_TYPE_UINT64),
 795       QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
 796             PIPE_DRIVER_QUERY_TYPE_UINT64),
 797       QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
 798             PIPE_DRIVER_QUERY_TYPE_UINT64),
 799       QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
 800             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 801       QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
 802             PIPE_DRIVER_QUERY_TYPE_UINT64),
 803       QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
 804             PIPE_DRIVER_QUERY_TYPE_UINT64),
 805       QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
 806             PIPE_DRIVER_QUERY_TYPE_BYTES),
 807       QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
 808             PIPE_DRIVER_QUERY_TYPE_BYTES),
 809       QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
 810             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 811       QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
 812             PIPE_DRIVER_QUERY_TYPE_UINT64),
 813       QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
 814             PIPE_DRIVER_QUERY_TYPE_UINT64),
 815       QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
 816             PIPE_DRIVER_QUERY_TYPE_UINT64),
 817       QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
 818             PIPE_DRIVER_QUERY_TYPE_UINT64),
 819       QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
 820             PIPE_DRIVER_QUERY_TYPE_UINT64),
 821       QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
 822             PIPE_DRIVER_QUERY_TYPE_UINT64),
 823
 824       /* running total counters */
 825       QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
 826             PIPE_DRIVER_QUERY_TYPE_BYTES),
 827       QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
 828             PIPE_DRIVER_QUERY_TYPE_UINT64),
 829       QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
 830             PIPE_DRIVER_QUERY_TYPE_UINT64),
 831       QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
 832             PIPE_DRIVER_QUERY_TYPE_UINT64),
 833       QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
 834             PIPE_DRIVER_QUERY_TYPE_UINT64),
 835       QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
 836             PIPE_DRIVER_QUERY_TYPE_UINT64),
 837       QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS,
 838             PIPE_DRIVER_QUERY_TYPE_UINT64),
 839       QUERY("num-commands-per-draw", SVGA_QUERY_NUM_COMMANDS_PER_DRAW,
 840             PIPE_DRIVER_QUERY_TYPE_FLOAT),
 841    };
 842 #undef QUERY
 843
 844    if (!info)
 845       return ARRAY_SIZE(queries);
 846
 847    if (index >= ARRAY_SIZE(queries))
 848       return 0;
 849
 850    *info = queries[index];
 851    return 1;
 852 }
 853
 854
 855 static void
 856 init_logging(struct pipe_screen *screen)
 857 {
 858    static const char *log_prefix = "Mesa: ";
 859    char host_log[1000];
 860
 861    /* Log Version to Host */
 862    util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 863                  "%s%s", log_prefix, svga_get_name(screen));
 864    svga_host_log(host_log);
 865
 866    util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 867                  "%s%s"
 868 #ifdef MESA_GIT_SHA1
 869                  " (" MESA_GIT_SHA1 ")"
 870 #endif
 871                  , log_prefix, PACKAGE_VERSION);
 872    svga_host_log(host_log);
 873
 874    /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
 875     * line (program name and arguments).
 876     */
 877    if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE)) {
 878       char cmdline[1000];
 879       if (os_get_command_line(cmdline, sizeof(cmdline))) {
 880          util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 881                        "%s%s", log_prefix, cmdline);
 882          svga_host_log(host_log);
 883       }
 884    }
 885 }
 886
 887
 888 static void
 889 svga_destroy_screen( struct pipe_screen *screen )
 890 {
 891    struct svga_screen *svgascreen = svga_screen(screen);
 892
 893    svga_screen_cache_cleanup(svgascreen);
 894
 895    mtx_destroy(&svgascreen->swc_mutex);
 896    mtx_destroy(&svgascreen->tex_mutex);
 897
 898    svgascreen->sws->destroy(svgascreen->sws);
 899
 900    FREE(svgascreen);
 901 }
 902
 903
 904 /**
 905  * Create a new svga_screen object
 906  */
 907 struct pipe_screen *
 908 svga_screen_create(struct svga_winsys_screen *sws)
 909 {
 910    struct svga_screen *svgascreen;
 911    struct pipe_screen *screen;
 912
 913 #ifdef DEBUG
 914    SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
 915 #endif
 916
 917    svgascreen = CALLOC_STRUCT(svga_screen);
 918    if (!svgascreen)
 919       goto error1;
 920
 921    svgascreen->debug.force_level_surface_view =
 922       debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
 923    svgascreen->debug.force_surface_view =
 924       debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
 925    svgascreen->debug.force_sampler_view =
 926       debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
 927    svgascreen->debug.no_surface_view =
 928       debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
 929    svgascreen->debug.no_sampler_view =
 930       debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
 931    svgascreen->debug.no_cache_index_buffers =
 932       debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
 933
 934    screen = &svgascreen->screen;
 935
 936    screen->destroy = svga_destroy_screen;
 937    screen->get_name = svga_get_name;
 938    screen->get_vendor = svga_get_vendor;
 939    screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
 940    screen->get_param = svga_get_param;
 941    screen->get_shader_param = svga_get_shader_param;
 942    screen->get_paramf = svga_get_paramf;
 943    screen->get_timestamp = NULL;
 944    screen->is_format_supported = svga_is_format_supported;
 945    screen->context_create = svga_context_create;
 946    screen->fence_reference = svga_fence_reference;
 947    screen->fence_finish = svga_fence_finish;
 948    screen->fence_get_fd = svga_fence_get_fd;
 949
 950    screen->get_driver_query_info = svga_get_driver_query_info;
 951    svgascreen->sws = sws;
 952
 953    svga_init_screen_resource_functions(svgascreen);
 954
 955    if (sws->get_hw_version) {
 956       svgascreen->hw_version = sws->get_hw_version(sws);
 957    } else {
 958       svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
 959    }
 960
 961    if (svgascreen->hw_version < SVGA3D_HWVERSION_WS8_B1) {
 962       /* too old for 3D acceleration */
 963       debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
 964                    svgascreen->hw_version);
 965       goto error2;
 966    }
 967
 968    /*
 969     * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
 970     * when sampled from, where as the DF16, DF24, and D24S8_INT do not.  So
 971     * we prefer the later when available.
 972     *
 973     * This mimics hardware vendors extensions for D3D depth sampling. See also
 974     * http://aras-p.info/texts/D3D9GPUHacks.html
 975     */
 976
 977    {
 978       boolean has_df16, has_df24, has_d24s8_int;
 979       SVGA3dSurfaceFormatCaps caps;
 980       SVGA3dSurfaceFormatCaps mask;
 981       mask.value = 0;
 982       mask.zStencil = 1;
 983       mask.texture = 1;
 984
 985       svgascreen->depth.z16 = SVGA3D_Z_D16;
 986       svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
 987       svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
 988
 989       svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
 990       has_df16 = (caps.value & mask.value) == mask.value;
 991
 992       svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
 993       has_df24 = (caps.value & mask.value) == mask.value;
 994
 995       svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
 996       has_d24s8_int = (caps.value & mask.value) == mask.value;
 997
 998       /* XXX: We might want some other logic here.
 999        * Like if we only have d24s8_int we should
1000        * emulate the other formats with that.
1001        */
1002       if (has_df16) {
1003          svgascreen->depth.z16 = SVGA3D_Z_DF16;
1004       }
1005       if (has_df24) {
1006          svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1007       }
1008       if (has_d24s8_int) {
1009          svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1010       }
1011    }
1012
1013    /* Query device caps
1014     */
1015    if (sws->have_vgpu10) {
1016       svgascreen->haveProvokingVertex
1017          = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1018       svgascreen->haveLineSmooth = TRUE;
1019       svgascreen->maxPointSize = 80.0F;
1020       svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1021
1022       /* Multisample samples per pixel */
1023       if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
1024          svgascreen->ms_samples =
1025             get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
1026       }
1027
1028       /* We only support 4x, 8x, 16x MSAA */
1029       svgascreen->ms_samples &= ((1 << (4-1)) |
1030                                  (1 << (8-1)) |
1031                                  (1 << (16-1)));
1032
1033       /* Maximum number of constant buffers */
1034       svgascreen->max_const_buffers =
1035          get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1036       assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1037    }
1038    else {
1039       /* VGPU9 */
1040       unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1041                                      SVGA3DVSVERSION_NONE);
1042       unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1043                                      SVGA3DPSVERSION_NONE);
1044
1045       /* we require Shader model 3.0 or later */
1046       if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1047          goto error2;
1048       }
1049
1050       svgascreen->haveProvokingVertex = FALSE;
1051
1052       svgascreen->haveLineSmooth =
1053          get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1054
1055       svgascreen->maxPointSize =
1056          get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1057       /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1058       svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1059
1060       /* The SVGA3D device always supports 4 targets at this time, regardless
1061        * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1062        */
1063       svgascreen->max_color_buffers = 4;
1064
1065       /* Only support one constant buffer
1066        */
1067       svgascreen->max_const_buffers = 1;
1068
1069       /* No multisampling */
1070       svgascreen->ms_samples = 0;
1071    }
1072
1073    /* common VGPU9 / VGPU10 caps */
1074    svgascreen->haveLineStipple =
1075       get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1076
1077    svgascreen->maxLineWidth =
1078       MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f));
1079
1080    svgascreen->maxLineWidthAA =
1081       MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f));
1082
1083    if (0) {
1084       debug_printf("svga: haveProvokingVertex %u\n",
1085                    svgascreen->haveProvokingVertex);
1086       debug_printf("svga: haveLineStip %u  "
1087                    "haveLineSmooth %u  maxLineWidth %.2f  maxLineWidthAA %.2f\n",
1088                    svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1089                    svgascreen->maxLineWidth, svgascreen->maxLineWidthAA);
1090       debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1091       debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1092    }
1093
1094    (void) mtx_init(&svgascreen->tex_mutex, mtx_plain);
1095    (void) mtx_init(&svgascreen->swc_mutex, mtx_recursive);
1096
1097    svga_screen_cache_init(svgascreen);
1098
1099    init_logging(screen);
1100
1101    return screen;
1102 error2:
1103    FREE(svgascreen);
1104 error1:
1105    return NULL;
1106 }
1107
1108
1109 struct svga_winsys_screen *
1110 svga_winsys_screen(struct pipe_screen *screen)
1111 {
1112    return svga_screen(screen)->sws;
1113 }
1114
1115
1116 #ifdef DEBUG
1117 struct svga_screen *
1118 svga_screen(struct pipe_screen *screen)
1119 {
1120    assert(screen);
1121    assert(screen->destroy == svga_destroy_screen);
1122    return (struct svga_screen *)screen;
1123 }
1124 #endif