src/gallium/drivers/svga/svga_screen.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "util/u_format.h"
  27 #include "util/u_memory.h"
  28 #include "util/u_inlines.h"
  29 #include "util/u_string.h"
  30 #include "util/u_math.h"
  31
  32 #include "svga_winsys.h"
  33 #include "svga_public.h"
  34 #include "svga_context.h"
  35 #include "svga_format.h"
  36 #include "svga_screen.h"
  37 #include "svga_tgsi.h"
  38 #include "svga_resource_texture.h"
  39 #include "svga_resource.h"
  40 #include "svga_debug.h"
  41
  42 #include "svga3d_shaderdefs.h"
  43 #include "VGPU10ShaderTokens.h"
  44
  45 /* NOTE: this constant may get moved into a svga3d*.h header file */
  46 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
  47
  48 #ifdef DEBUG
  49 int SVGA_DEBUG = 0;
  50
  51 static const struct debug_named_value svga_debug_flags[] = {
  52    { "dma",         DEBUG_DMA, NULL },
  53    { "tgsi",        DEBUG_TGSI, NULL },
  54    { "pipe",        DEBUG_PIPE, NULL },
  55    { "state",       DEBUG_STATE, NULL },
  56    { "screen",      DEBUG_SCREEN, NULL },
  57    { "tex",         DEBUG_TEX, NULL },
  58    { "swtnl",       DEBUG_SWTNL, NULL },
  59    { "const",       DEBUG_CONSTS, NULL },
  60    { "viewport",    DEBUG_VIEWPORT, NULL },
  61    { "views",       DEBUG_VIEWS, NULL },
  62    { "perf",        DEBUG_PERF, NULL },
  63    { "flush",       DEBUG_FLUSH, NULL },
  64    { "sync",        DEBUG_SYNC, NULL },
  65    { "cache",       DEBUG_CACHE, NULL },
  66    { "streamout",   DEBUG_STREAMOUT, NULL },
  67    { "query",       DEBUG_QUERY, NULL },
  68    DEBUG_NAMED_VALUE_END
  69 };
  70 #endif
  71
  72 static const char *
  73 svga_get_vendor( struct pipe_screen *pscreen )
  74 {
  75    return "VMware, Inc.";
  76 }
  77
  78
  79 static const char *
  80 svga_get_name( struct pipe_screen *pscreen )
  81 {
  82    const char *build = "", *llvm = "", *mutex = "";
  83    static char name[100];
  84 #ifdef DEBUG
  85    /* Only return internal details in the DEBUG version:
  86     */
  87    build = "build: DEBUG;";
  88    mutex = "mutex: " PIPE_ATOMIC ";";
  89 #else
  90    build = "build: RELEASE;";
  91 #endif
  92 #ifdef HAVE_LLVM
  93    llvm = "LLVM;";
  94 #endif
  95
  96    util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
  97    return name;
  98 }
  99
 100
 101 /** Helper for querying float-valued device cap */
 102 static float
 103 get_float_cap(struct svga_winsys_screen *sws, unsigned cap, float defaultVal)
 104 {
 105    SVGA3dDevCapResult result;
 106    if (sws->get_cap(sws, cap, &result))
 107       return result.f;
 108    else
 109       return defaultVal;
 110 }
 111
 112
 113 /** Helper for querying uint-valued device cap */
 114 static unsigned
 115 get_uint_cap(struct svga_winsys_screen *sws, unsigned cap, unsigned defaultVal)
 116 {
 117    SVGA3dDevCapResult result;
 118    if (sws->get_cap(sws, cap, &result))
 119       return result.u;
 120    else
 121       return defaultVal;
 122 }
 123
 124
 125 /** Helper for querying boolean-valued device cap */
 126 static boolean
 127 get_bool_cap(struct svga_winsys_screen *sws, unsigned cap, boolean defaultVal)
 128 {
 129    SVGA3dDevCapResult result;
 130    if (sws->get_cap(sws, cap, &result))
 131       return result.b;
 132    else
 133       return defaultVal;
 134 }
 135
 136
 137 static float
 138 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 139 {
 140    struct svga_screen *svgascreen = svga_screen(screen);
 141    struct svga_winsys_screen *sws = svgascreen->sws;
 142
 143    switch (param) {
 144    case PIPE_CAPF_MAX_LINE_WIDTH:
 145       return svgascreen->maxLineWidth;
 146    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 147       return svgascreen->maxLineWidthAA;
 148
 149    case PIPE_CAPF_MAX_POINT_WIDTH:
 150       /* fall-through */
 151    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 152       return svgascreen->maxPointSize;
 153
 154    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 155       return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
 156
 157    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 158       return 15.0;
 159
 160    case PIPE_CAPF_GUARD_BAND_LEFT:
 161    case PIPE_CAPF_GUARD_BAND_TOP:
 162    case PIPE_CAPF_GUARD_BAND_RIGHT:
 163    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 164       return 0.0;
 165    }
 166
 167    debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
 168    return 0;
 169 }
 170
 171
 172 static int
 173 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
 174 {
 175    struct svga_screen *svgascreen = svga_screen(screen);
 176    struct svga_winsys_screen *sws = svgascreen->sws;
 177    SVGA3dDevCapResult result;
 178
 179    switch (param) {
 180    case PIPE_CAP_NPOT_TEXTURES:
 181    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 182       return 1;
 183    case PIPE_CAP_TWO_SIDED_STENCIL:
 184       return 1;
 185    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 186       /*
 187        * "In virtually every OpenGL implementation and hardware,
 188        * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
 189        * http://www.opengl.org/wiki/Blending
 190        */
 191       return sws->have_vgpu10 ? 1 : 0;
 192    case PIPE_CAP_ANISOTROPIC_FILTER:
 193       return 1;
 194    case PIPE_CAP_POINT_SPRITE:
 195       return 1;
 196    case PIPE_CAP_TGSI_TEXCOORD:
 197       return 0;
 198    case PIPE_CAP_MAX_RENDER_TARGETS:
 199       return svgascreen->max_color_buffers;
 200    case PIPE_CAP_OCCLUSION_QUERY:
 201       return 1;
 202    case PIPE_CAP_QUERY_TIME_ELAPSED:
 203       return 0;
 204    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 205       return sws->have_vgpu10;
 206    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 207       return 1;
 208    case PIPE_CAP_TEXTURE_SWIZZLE:
 209       return 1;
 210    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 211       return 0;
 212    case PIPE_CAP_USER_VERTEX_BUFFERS:
 213    case PIPE_CAP_USER_INDEX_BUFFERS:
 214       return 0;
 215    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 216       return 1;
 217    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 218       return 256;
 219
 220    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 221       {
 222          unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
 223          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
 224             levels = MIN2(util_logbase2(result.u) + 1, levels);
 225          else
 226             levels = 12 /* 2048x2048 */;
 227          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
 228             levels = MIN2(util_logbase2(result.u) + 1, levels);
 229          else
 230             levels = 12 /* 2048x2048 */;
 231          return levels;
 232       }
 233
 234    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 235       if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
 236          return 8;  /* max 128x128x128 */
 237       return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
 238
 239    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 240       /*
 241        * No mechanism to query the host, and at least limited to 2048x2048 on
 242        * certain hardware.
 243        */
 244       return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
 245                   12 /* 2048x2048 */);
 246
 247    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 248       return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
 249
 250    case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
 251       return 1;
 252
 253    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 254       return 1;
 255    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 256       return sws->have_vgpu10;
 257    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 258       return 0;
 259    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 260       return !sws->have_vgpu10;
 261
 262    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 263       return 1; /* The color outputs of vertex shaders are not clamped */
 264    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 265       return 0; /* The driver can't clamp vertex colors */
 266    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 267       return 0; /* The driver can't clamp fragment colors */
 268
 269    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 270       return 1; /* expected for GL_ARB_framebuffer_object */
 271
 272    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 273       return sws->have_vgpu10 ? 330 : 120;
 274
 275    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 276       return 0;
 277
 278    case PIPE_CAP_SM3:
 279       return 1;
 280
 281    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 282    case PIPE_CAP_INDEP_BLEND_ENABLE:
 283    case PIPE_CAP_CONDITIONAL_RENDER:
 284    case PIPE_CAP_QUERY_TIMESTAMP:
 285    case PIPE_CAP_TGSI_INSTANCEID:
 286    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 287    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 288    case PIPE_CAP_FAKE_SW_MSAA:
 289       return sws->have_vgpu10;
 290
 291    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 292       return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
 293    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 294       return sws->have_vgpu10 ? 4 : 0;
 295    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 296       return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
 297    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 298       return 0;
 299    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 300       return svgascreen->ms_samples ? 1 : 0;
 301
 302    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 303       return SVGA3D_DX_MAX_RESOURCE_SIZE;
 304
 305    case PIPE_CAP_MIN_TEXEL_OFFSET:
 306       return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
 307    case PIPE_CAP_MAX_TEXEL_OFFSET:
 308       return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
 309
 310    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 311    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 312       return 0;
 313
 314    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 315       return sws->have_vgpu10 ? 256 : 0;
 316    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 317       return sws->have_vgpu10 ? 1024 : 0;
 318
 319    case PIPE_CAP_PRIMITIVE_RESTART:
 320       return 1; /* may be a sw fallback, depending on restart index */
 321
 322    /* Unsupported features */
 323    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 324    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 325    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 326    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 327    case PIPE_CAP_INDEP_BLEND_FUNC:
 328    case PIPE_CAP_TEXTURE_BARRIER:
 329    case PIPE_CAP_MAX_VERTEX_STREAMS:
 330    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 331    case PIPE_CAP_COMPUTE:
 332    case PIPE_CAP_START_INSTANCE:
 333    case PIPE_CAP_CUBE_MAP_ARRAY:
 334    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 335    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 336    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 337    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 338    case PIPE_CAP_TEXTURE_GATHER_SM5:
 339    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 340    case PIPE_CAP_TEXTURE_QUERY_LOD:
 341    case PIPE_CAP_SAMPLE_SHADING:
 342    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 343    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 344    case PIPE_CAP_DRAW_INDIRECT:
 345    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 346    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 347    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 348    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 349    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 350    case PIPE_CAP_CLIP_HALFZ:
 351    case PIPE_CAP_VERTEXID_NOBASE:
 352    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 353    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 354    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 355       return 0;
 356    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 357       return 64;
 358    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 359    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 360    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 361       return 1;  /* need 4-byte alignment for all offsets and strides */
 362    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 363       return 2048;
 364    case PIPE_CAP_MAX_VIEWPORTS:
 365       return 1;
 366    case PIPE_CAP_ENDIANNESS:
 367       return PIPE_ENDIAN_LITTLE;
 368
 369    case PIPE_CAP_VENDOR_ID:
 370       return 0x15ad; /* VMware Inc. */
 371    case PIPE_CAP_DEVICE_ID:
 372       return 0x0405; /* assume SVGA II */
 373    case PIPE_CAP_ACCELERATED:
 374       return 0; /* XXX: */
 375    case PIPE_CAP_VIDEO_MEMORY:
 376       /* XXX: Query the host ? */
 377       return 1;
 378    case PIPE_CAP_UMA:
 379    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 380    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 381    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 382    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 383    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 384    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 385    case PIPE_CAP_TGSI_TXQS:
 386    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 387    case PIPE_CAP_SHAREABLE_SHADERS:
 388    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 389    case PIPE_CAP_CLEAR_TEXTURE:
 390    case PIPE_CAP_DRAW_PARAMETERS:
 391    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 392    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 393       return 0;
 394    }
 395
 396    debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
 397    return 0;
 398 }
 399
 400
 401 static int
 402 vgpu9_get_shader_param(struct pipe_screen *screen, unsigned shader,
 403                        enum pipe_shader_cap param)
 404 {
 405    struct svga_screen *svgascreen = svga_screen(screen);
 406    struct svga_winsys_screen *sws = svgascreen->sws;
 407    unsigned val;
 408
 409    assert(!sws->have_vgpu10);
 410
 411    switch (shader)
 412    {
 413    case PIPE_SHADER_FRAGMENT:
 414       switch (param)
 415       {
 416       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 417       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 418       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 419       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 420          return 512;
 421       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 422          return SVGA3D_MAX_NESTING_LEVEL;
 423       case PIPE_SHADER_CAP_MAX_INPUTS:
 424          return 10;
 425       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 426          return svgascreen->max_color_buffers;
 427       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 428          return 224 * sizeof(float[4]);
 429       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 430          return 1;
 431       case PIPE_SHADER_CAP_MAX_TEMPS:
 432          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
 433          return MIN2(val, SVGA3D_TEMPREG_MAX);
 434       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 435          /*
 436           * Although PS 3.0 has some addressing abilities it can only represent
 437           * loops that can be statically determined and unrolled. Given we can
 438           * only handle a subset of the cases that the state tracker already
 439           * does it is better to defer loop unrolling to the state tracker.
 440           */
 441          return 0;
 442       case PIPE_SHADER_CAP_MAX_PREDS:
 443          return 1;
 444       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 445          return 0;
 446       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 447          return 0;
 448       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 449       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 450       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 451          return 0;
 452       case PIPE_SHADER_CAP_SUBROUTINES:
 453          return 0;
 454       case PIPE_SHADER_CAP_INTEGERS:
 455          return 0;
 456       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 457       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 458          return 16;
 459       case PIPE_SHADER_CAP_PREFERRED_IR:
 460          return PIPE_SHADER_IR_TGSI;
 461       case PIPE_SHADER_CAP_DOUBLES:
 462       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 463       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 464       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 465       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 466       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 467          return 0;
 468       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 469          return 32;
 470       }
 471       /* If we get here, we failed to handle a cap above */
 472       debug_printf("Unexpected fragment shader query %u\n", param);
 473       return 0;
 474    case PIPE_SHADER_VERTEX:
 475       switch (param)
 476       {
 477       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 478       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 479          return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
 480                              512);
 481       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 482       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 483          /* XXX: until we have vertex texture support */
 484          return 0;
 485       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 486          return SVGA3D_MAX_NESTING_LEVEL;
 487       case PIPE_SHADER_CAP_MAX_INPUTS:
 488          return 16;
 489       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 490          return 10;
 491       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 492          return 256 * sizeof(float[4]);
 493       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 494          return 1;
 495       case PIPE_SHADER_CAP_MAX_TEMPS:
 496          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
 497          return MIN2(val, SVGA3D_TEMPREG_MAX);
 498       case PIPE_SHADER_CAP_MAX_PREDS:
 499          return 1;
 500       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 501          return 0;
 502       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 503          return 0;
 504       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 505       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 506          return 1;
 507       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 508          return 0;
 509       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 510          return 1;
 511       case PIPE_SHADER_CAP_SUBROUTINES:
 512          return 0;
 513       case PIPE_SHADER_CAP_INTEGERS:
 514          return 0;
 515       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 516       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 517          return 0;
 518       case PIPE_SHADER_CAP_PREFERRED_IR:
 519          return PIPE_SHADER_IR_TGSI;
 520       case PIPE_SHADER_CAP_DOUBLES:
 521       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 522       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 523       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 524       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 525       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 526          return 0;
 527       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 528          return 32;
 529       }
 530       /* If we get here, we failed to handle a cap above */
 531       debug_printf("Unexpected vertex shader query %u\n", param);
 532       return 0;
 533    case PIPE_SHADER_GEOMETRY:
 534    case PIPE_SHADER_COMPUTE:
 535    case PIPE_SHADER_TESS_CTRL:
 536    case PIPE_SHADER_TESS_EVAL:
 537       /* no support for geometry, tess or compute shaders at this time */
 538       return 0;
 539    default:
 540       debug_printf("Unexpected shader type (%u) query\n", shader);
 541       return 0;
 542    }
 543    return 0;
 544 }
 545
 546
 547 static int
 548 vgpu10_get_shader_param(struct pipe_screen *screen, unsigned shader,
 549                         enum pipe_shader_cap param)
 550 {
 551    struct svga_screen *svgascreen = svga_screen(screen);
 552    struct svga_winsys_screen *sws = svgascreen->sws;
 553
 554    assert(sws->have_vgpu10);
 555    (void) sws;  /* silence unused var warnings in non-debug builds */
 556
 557    /* Only VS, GS, FS supported */
 558    if (shader != PIPE_SHADER_VERTEX &&
 559        shader != PIPE_SHADER_GEOMETRY &&
 560        shader != PIPE_SHADER_FRAGMENT) {
 561       return 0;
 562    }
 563
 564    /* NOTE: we do not query the device for any caps/limits at this time */
 565
 566    /* Generally the same limits for vertex, geometry and fragment shaders */
 567    switch (param) {
 568    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 569    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 570    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 571    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 572       return 64 * 1024;
 573    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 574       return 64;
 575    case PIPE_SHADER_CAP_MAX_INPUTS:
 576       if (shader == PIPE_SHADER_FRAGMENT)
 577          return VGPU10_MAX_FS_INPUTS;
 578       else if (shader == PIPE_SHADER_GEOMETRY)
 579          return VGPU10_MAX_GS_INPUTS;
 580       else
 581          return VGPU10_MAX_VS_INPUTS;
 582    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 583       if (shader == PIPE_SHADER_FRAGMENT)
 584          return VGPU10_MAX_FS_OUTPUTS;
 585       else if (shader == PIPE_SHADER_GEOMETRY)
 586          return VGPU10_MAX_GS_OUTPUTS;
 587       else
 588          return VGPU10_MAX_VS_OUTPUTS;
 589    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 590       return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
 591    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 592       return svgascreen->max_const_buffers;
 593    case PIPE_SHADER_CAP_MAX_TEMPS:
 594       return VGPU10_MAX_TEMPS;
 595    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 596    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 597    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 598    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 599       return TRUE; /* XXX verify */
 600    case PIPE_SHADER_CAP_MAX_PREDS:
 601       return 0;
 602    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 603    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 604    case PIPE_SHADER_CAP_SUBROUTINES:
 605    case PIPE_SHADER_CAP_INTEGERS:
 606       return TRUE;
 607    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 608    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 609       return SVGA3D_DX_MAX_SAMPLERS;
 610    case PIPE_SHADER_CAP_PREFERRED_IR:
 611       return PIPE_SHADER_IR_TGSI;
 612    case PIPE_SHADER_CAP_DOUBLES:
 613    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 614    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 615    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 616    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 617    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 618       return 0;
 619    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 620       return 32;
 621    default:
 622       debug_printf("Unexpected vgpu10 shader query %u\n", param);
 623       return 0;
 624    }
 625    return 0;
 626 }
 627
 628
 629 static int
 630 svga_get_shader_param(struct pipe_screen *screen, unsigned shader,
 631                       enum pipe_shader_cap param)
 632 {
 633    struct svga_screen *svgascreen = svga_screen(screen);
 634    struct svga_winsys_screen *sws = svgascreen->sws;
 635    if (sws->have_vgpu10) {
 636       return vgpu10_get_shader_param(screen, shader, param);
 637    }
 638    else {
 639       return vgpu9_get_shader_param(screen, shader, param);
 640    }
 641 }
 642
 643
 644 /**
 645  * Implement pipe_screen::is_format_supported().
 646  * \param bindings  bitmask of PIPE_BIND_x flags
 647  */
 648 static boolean
 649 svga_is_format_supported( struct pipe_screen *screen,
 650                           enum pipe_format format,
 651                           enum pipe_texture_target target,
 652                           unsigned sample_count,
 653                           unsigned bindings)
 654 {
 655    struct svga_screen *ss = svga_screen(screen);
 656    SVGA3dSurfaceFormat svga_format;
 657    SVGA3dSurfaceFormatCaps caps;
 658    SVGA3dSurfaceFormatCaps mask;
 659
 660    assert(bindings);
 661
 662    if (sample_count > 1) {
 663       /* In ms_samples, if bit N is set it means that we support
 664        * multisample with N+1 samples per pixel.
 665        */
 666       if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
 667          return FALSE;
 668       }
 669    }
 670
 671    svga_format = svga_translate_format(ss, format, bindings);
 672    if (svga_format == SVGA3D_FORMAT_INVALID) {
 673       return FALSE;
 674    }
 675
 676    /* we don't support sRGB rendering into display targets */
 677    if (util_format_is_srgb(format) && (bindings & PIPE_BIND_DISPLAY_TARGET)) {
 678       return FALSE;
 679    }
 680
 681    /*
 682     * For VGPU10 vertex formats, skip querying host capabilities
 683     */
 684
 685    if (ss->sws->have_vgpu10 && (bindings & PIPE_BIND_VERTEX_BUFFER)) {
 686       SVGA3dSurfaceFormat svga_format;
 687       unsigned flags;
 688       svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
 689       return svga_format != SVGA3D_FORMAT_INVALID;
 690    }
 691
 692    /*
 693     * Override host capabilities, so that we end up with the same
 694     * visuals for all virtual hardware implementations.
 695     */
 696
 697    if (bindings & PIPE_BIND_DISPLAY_TARGET) {
 698       switch (svga_format) {
 699       case SVGA3D_A8R8G8B8:
 700       case SVGA3D_X8R8G8B8:
 701       case SVGA3D_R5G6B5:
 702          break;
 703
 704       /* VGPU10 formats */
 705       case SVGA3D_B8G8R8A8_UNORM:
 706       case SVGA3D_B8G8R8X8_UNORM:
 707       case SVGA3D_B5G6R5_UNORM:
 708          break;
 709
 710       /* Often unsupported/problematic. This means we end up with the same
 711        * visuals for all virtual hardware implementations.
 712        */
 713       case SVGA3D_A4R4G4B4:
 714       case SVGA3D_A1R5G5B5:
 715          return FALSE;
 716
 717       default:
 718          return FALSE;
 719       }
 720    }
 721
 722    /*
 723     * Query the host capabilities.
 724     */
 725
 726    svga_get_format_cap(ss, svga_format, &caps);
 727
 728    if (bindings & PIPE_BIND_RENDER_TARGET) {
 729       /* Check that the color surface is blendable, unless it's an
 730        * integer format.
 731        */
 732       if (!svga_format_is_integer(svga_format) &&
 733           (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
 734          return FALSE;
 735       }
 736    }
 737
 738    mask.value = 0;
 739    if (bindings & PIPE_BIND_RENDER_TARGET) {
 740       mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
 741    }
 742    if (bindings & PIPE_BIND_DEPTH_STENCIL) {
 743       mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
 744    }
 745    if (bindings & PIPE_BIND_SAMPLER_VIEW) {
 746       mask.value |= SVGA3DFORMAT_OP_TEXTURE;
 747    }
 748
 749    if (target == PIPE_TEXTURE_CUBE) {
 750       mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
 751    }
 752    else if (target == PIPE_TEXTURE_3D) {
 753       mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
 754    }
 755
 756    return (caps.value & mask.value) == mask.value;
 757 }
 758
 759
 760 static void
 761 svga_fence_reference(struct pipe_screen *screen,
 762                      struct pipe_fence_handle **ptr,
 763                      struct pipe_fence_handle *fence)
 764 {
 765    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 766    sws->fence_reference(sws, ptr, fence);
 767 }
 768
 769
 770 static boolean
 771 svga_fence_finish(struct pipe_screen *screen,
 772                   struct pipe_fence_handle *fence,
 773                   uint64_t timeout)
 774 {
 775    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 776
 777    if (!timeout)
 778       return sws->fence_signalled(sws, fence, 0) == 0;
 779
 780    SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
 781             __FUNCTION__, fence);
 782
 783    return sws->fence_finish(sws, fence, 0) == 0;
 784 }
 785
 786
 787 static int
 788 svga_get_driver_query_info(struct pipe_screen *screen,
 789                            unsigned index,
 790                            struct pipe_driver_query_info *info)
 791 {
 792 #define QUERY(NAME, ENUM, UNITS) \
 793    {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
 794
 795    static const struct pipe_driver_query_info queries[] = {
 796       /* per-frame counters */
 797       QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
 798             PIPE_DRIVER_QUERY_TYPE_UINT64),
 799       QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
 800             PIPE_DRIVER_QUERY_TYPE_UINT64),
 801       QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
 802             PIPE_DRIVER_QUERY_TYPE_UINT64),
 803       QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
 804             PIPE_DRIVER_QUERY_TYPE_UINT64),
 805       QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
 806             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 807       QUERY("num-resources-mapped", SVGA_QUERY_NUM_RESOURCES_MAPPED,
 808             PIPE_DRIVER_QUERY_TYPE_UINT64),
 809       QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
 810             PIPE_DRIVER_QUERY_TYPE_BYTES),
 811
 812       /* running total counters */
 813       QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
 814             PIPE_DRIVER_QUERY_TYPE_BYTES),
 815       QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
 816             PIPE_DRIVER_QUERY_TYPE_UINT64),
 817       QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
 818             PIPE_DRIVER_QUERY_TYPE_UINT64),
 819       QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
 820             PIPE_DRIVER_QUERY_TYPE_UINT64),
 821       QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
 822             PIPE_DRIVER_QUERY_TYPE_UINT64),
 823    };
 824 #undef QUERY
 825
 826    if (!info)
 827       return Elements(queries);
 828
 829    if (index >= Elements(queries))
 830       return 0;
 831
 832    *info = queries[index];
 833    return 1;
 834 }
 835
 836
 837 static void
 838 svga_destroy_screen( struct pipe_screen *screen )
 839 {
 840    struct svga_screen *svgascreen = svga_screen(screen);
 841
 842    svga_screen_cache_cleanup(svgascreen);
 843
 844    pipe_mutex_destroy(svgascreen->swc_mutex);
 845    pipe_mutex_destroy(svgascreen->tex_mutex);
 846
 847    svgascreen->sws->destroy(svgascreen->sws);
 848
 849    FREE(svgascreen);
 850 }
 851
 852
 853 /**
 854  * Create a new svga_screen object
 855  */
 856 struct pipe_screen *
 857 svga_screen_create(struct svga_winsys_screen *sws)
 858 {
 859    struct svga_screen *svgascreen;
 860    struct pipe_screen *screen;
 861
 862 #ifdef DEBUG
 863    SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
 864 #endif
 865
 866    svgascreen = CALLOC_STRUCT(svga_screen);
 867    if (!svgascreen)
 868       goto error1;
 869
 870    svgascreen->debug.force_level_surface_view =
 871       debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
 872    svgascreen->debug.force_surface_view =
 873       debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
 874    svgascreen->debug.force_sampler_view =
 875       debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
 876    svgascreen->debug.no_surface_view =
 877       debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
 878    svgascreen->debug.no_sampler_view =
 879       debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
 880
 881    screen = &svgascreen->screen;
 882
 883    screen->destroy = svga_destroy_screen;
 884    screen->get_name = svga_get_name;
 885    screen->get_vendor = svga_get_vendor;
 886    screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
 887    screen->get_param = svga_get_param;
 888    screen->get_shader_param = svga_get_shader_param;
 889    screen->get_paramf = svga_get_paramf;
 890    screen->get_timestamp = NULL;
 891    screen->is_format_supported = svga_is_format_supported;
 892    screen->context_create = svga_context_create;
 893    screen->fence_reference = svga_fence_reference;
 894    screen->fence_finish = svga_fence_finish;
 895    screen->get_driver_query_info = svga_get_driver_query_info;
 896    svgascreen->sws = sws;
 897
 898    svga_init_screen_resource_functions(svgascreen);
 899
 900    if (sws->get_hw_version) {
 901       svgascreen->hw_version = sws->get_hw_version(sws);
 902    } else {
 903       svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
 904    }
 905
 906    /*
 907     * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
 908     * when sampled from, where as the DF16, DF24, and D24S8_INT do not.  So
 909     * we prefer the later when available.
 910     *
 911     * This mimics hardware vendors extensions for D3D depth sampling. See also
 912     * http://aras-p.info/texts/D3D9GPUHacks.html
 913     */
 914
 915    {
 916       boolean has_df16, has_df24, has_d24s8_int;
 917       SVGA3dSurfaceFormatCaps caps;
 918       SVGA3dSurfaceFormatCaps mask;
 919       mask.value = 0;
 920       mask.zStencil = 1;
 921       mask.texture = 1;
 922
 923       svgascreen->depth.z16 = SVGA3D_Z_D16;
 924       svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
 925       svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
 926
 927       svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
 928       has_df16 = (caps.value & mask.value) == mask.value;
 929
 930       svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
 931       has_df24 = (caps.value & mask.value) == mask.value;
 932
 933       svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
 934       has_d24s8_int = (caps.value & mask.value) == mask.value;
 935
 936       /* XXX: We might want some other logic here.
 937        * Like if we only have d24s8_int we should
 938        * emulate the other formats with that.
 939        */
 940       if (has_df16) {
 941          svgascreen->depth.z16 = SVGA3D_Z_DF16;
 942       }
 943       if (has_df24) {
 944          svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
 945       }
 946       if (has_d24s8_int) {
 947          svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
 948       }
 949    }
 950
 951    /* Query device caps
 952     */
 953    if (sws->have_vgpu10) {
 954       svgascreen->haveProvokingVertex
 955          = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
 956       svgascreen->haveLineSmooth = TRUE;
 957       svgascreen->maxPointSize = 80.0F;
 958       svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
 959
 960       /* Multisample samples per pixel */
 961       svgascreen->ms_samples =
 962          get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
 963
 964       /* Maximum number of constant buffers */
 965       svgascreen->max_const_buffers =
 966          get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
 967       assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
 968    }
 969    else {
 970       /* VGPU9 */
 971       unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
 972                                      SVGA3DVSVERSION_NONE);
 973       unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
 974                                      SVGA3DPSVERSION_NONE);
 975
 976       /* we require Shader model 3.0 or later */
 977       if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
 978          goto error2;
 979       }
 980
 981       svgascreen->haveProvokingVertex = FALSE;
 982
 983       svgascreen->haveLineSmooth =
 984          get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
 985
 986       svgascreen->maxPointSize =
 987          get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
 988       /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
 989       svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
 990
 991       /* The SVGA3D device always supports 4 targets at this time, regardless
 992        * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
 993        */
 994       svgascreen->max_color_buffers = 4;
 995
 996       /* Only support one constant buffer
 997        */
 998       svgascreen->max_const_buffers = 1;
 999
1000       /* No multisampling */
1001       svgascreen->ms_samples = 0;
1002    }
1003
1004    /* common VGPU9 / VGPU10 caps */
1005    svgascreen->haveLineStipple =
1006       get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1007
1008    svgascreen->maxLineWidth =
1009       get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f);
1010
1011    svgascreen->maxLineWidthAA =
1012       get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f);
1013
1014    if (0) {
1015       debug_printf("svga: haveProvokingVertex %u\n",
1016                    svgascreen->haveProvokingVertex);
1017       debug_printf("svga: haveLineStip %u  "
1018                    "haveLineSmooth %u  maxLineWidth %f\n",
1019                    svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1020                    svgascreen->maxLineWidth);
1021       debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1022    }
1023
1024    pipe_mutex_init(svgascreen->tex_mutex);
1025    pipe_mutex_init(svgascreen->swc_mutex);
1026
1027    svga_screen_cache_init(svgascreen);
1028
1029    return screen;
1030 error2:
1031    FREE(svgascreen);
1032 error1:
1033    return NULL;
1034 }
1035
1036 struct svga_winsys_screen *
1037 svga_winsys_screen(struct pipe_screen *screen)
1038 {
1039    return svga_screen(screen)->sws;
1040 }
1041
1042 #ifdef DEBUG
1043 struct svga_screen *
1044 svga_screen(struct pipe_screen *screen)
1045 {
1046    assert(screen);
1047    assert(screen->destroy == svga_destroy_screen);
1048    return (struct svga_screen *)screen;
1049 }
1050 #endif