1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
27 #include "util/u_format.h"
28 #include "util/u_memory.h"
29 #include "util/u_inlines.h"
30 #include "util/u_screen.h"
31 #include "util/u_string.h"
32 #include "util/u_math.h"
34 #include "os/os_process.h"
36 #include "svga_winsys.h"
37 #include "svga_public.h"
38 #include "svga_context.h"
39 #include "svga_format.h"
40 #include "svga_screen.h"
41 #include "svga_tgsi.h"
42 #include "svga_resource_texture.h"
43 #include "svga_resource.h"
44 #include "svga_debug.h"
46 #include "svga3d_shaderdefs.h"
47 #include "VGPU10ShaderTokens.h"
49 /* NOTE: this constant may get moved into a svga3d*.h header file */
50 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
55 static const struct debug_named_value svga_debug_flags
[] = {
56 { "dma", DEBUG_DMA
, NULL
},
57 { "tgsi", DEBUG_TGSI
, NULL
},
58 { "pipe", DEBUG_PIPE
, NULL
},
59 { "state", DEBUG_STATE
, NULL
},
60 { "screen", DEBUG_SCREEN
, NULL
},
61 { "tex", DEBUG_TEX
, NULL
},
62 { "swtnl", DEBUG_SWTNL
, NULL
},
63 { "const", DEBUG_CONSTS
, NULL
},
64 { "viewport", DEBUG_VIEWPORT
, NULL
},
65 { "views", DEBUG_VIEWS
, NULL
},
66 { "perf", DEBUG_PERF
, NULL
},
67 { "flush", DEBUG_FLUSH
, NULL
},
68 { "sync", DEBUG_SYNC
, NULL
},
69 { "cache", DEBUG_CACHE
, NULL
},
70 { "streamout", DEBUG_STREAMOUT
, NULL
},
71 { "query", DEBUG_QUERY
, NULL
},
72 { "samplers", DEBUG_SAMPLERS
, NULL
},
78 svga_get_vendor( struct pipe_screen
*pscreen
)
80 return "VMware, Inc.";
85 svga_get_name( struct pipe_screen
*pscreen
)
87 const char *build
= "", *llvm
= "", *mutex
= "";
88 static char name
[100];
90 /* Only return internal details in the DEBUG version:
92 build
= "build: DEBUG;";
93 mutex
= "mutex: " PIPE_ATOMIC
";";
95 build
= "build: RELEASE;";
101 util_snprintf(name
, sizeof(name
), "SVGA3D; %s %s %s", build
, mutex
, llvm
);
106 /** Helper for querying float-valued device cap */
108 get_float_cap(struct svga_winsys_screen
*sws
, SVGA3dDevCapIndex cap
,
111 SVGA3dDevCapResult result
;
112 if (sws
->get_cap(sws
, cap
, &result
))
119 /** Helper for querying uint-valued device cap */
121 get_uint_cap(struct svga_winsys_screen
*sws
, SVGA3dDevCapIndex cap
,
124 SVGA3dDevCapResult result
;
125 if (sws
->get_cap(sws
, cap
, &result
))
132 /** Helper for querying boolean-valued device cap */
134 get_bool_cap(struct svga_winsys_screen
*sws
, SVGA3dDevCapIndex cap
,
137 SVGA3dDevCapResult result
;
138 if (sws
->get_cap(sws
, cap
, &result
))
146 svga_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
148 struct svga_screen
*svgascreen
= svga_screen(screen
);
149 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
152 case PIPE_CAPF_MAX_LINE_WIDTH
:
153 return svgascreen
->maxLineWidth
;
154 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
155 return svgascreen
->maxLineWidthAA
;
157 case PIPE_CAPF_MAX_POINT_WIDTH
:
159 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
160 return svgascreen
->maxPointSize
;
162 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
163 return (float) get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY
, 4);
165 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
168 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
170 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
172 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
177 debug_printf("Unexpected PIPE_CAPF_ query %u\n", param
);
183 svga_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
185 struct svga_screen
*svgascreen
= svga_screen(screen
);
186 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
187 SVGA3dDevCapResult result
;
190 case PIPE_CAP_NPOT_TEXTURES
:
191 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
192 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
194 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
196 * "In virtually every OpenGL implementation and hardware,
197 * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
198 * http://www.opengl.org/wiki/Blending
200 return sws
->have_vgpu10
? 1 : 0;
201 case PIPE_CAP_ANISOTROPIC_FILTER
:
203 case PIPE_CAP_POINT_SPRITE
:
205 case PIPE_CAP_TGSI_TEXCOORD
:
207 case PIPE_CAP_MAX_RENDER_TARGETS
:
208 return svgascreen
->max_color_buffers
;
209 case PIPE_CAP_OCCLUSION_QUERY
:
211 case PIPE_CAP_QUERY_TIME_ELAPSED
:
213 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
214 return sws
->have_vgpu10
;
215 case PIPE_CAP_TEXTURE_SWIZZLE
:
217 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
219 case PIPE_CAP_USER_VERTEX_BUFFERS
:
221 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
224 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
226 unsigned size
= 1 << (SVGA_MAX_TEXTURE_LEVELS
- 1);
227 if (sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH
, &result
))
228 size
= MIN2(result
.u
, size
);
231 if (sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT
, &result
))
232 size
= MIN2(result
.u
, size
);
238 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
239 if (!sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT
, &result
))
240 return 8; /* max 128x128x128 */
241 return MIN2(util_logbase2(result
.u
) + 1, SVGA_MAX_TEXTURE_LEVELS
);
243 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
245 * No mechanism to query the host, and at least limited to 2048x2048 on
248 return MIN2(util_last_bit(screen
->get_param(screen
, PIPE_CAP_MAX_TEXTURE_2D_SIZE
)),
251 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
252 return sws
->have_vgpu10
? SVGA3D_MAX_SURFACE_ARRAYSIZE
: 0;
254 case PIPE_CAP_BLEND_EQUATION_SEPARATE
: /* req. for GL 1.5 */
257 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
259 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
260 return sws
->have_vgpu10
;
261 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
263 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
264 return !sws
->have_vgpu10
;
266 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
267 return 1; /* The color outputs of vertex shaders are not clamped */
268 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
269 return 0; /* The driver can't clamp vertex colors */
270 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
271 return 0; /* The driver can't clamp fragment colors */
273 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
274 return 1; /* expected for GL_ARB_framebuffer_object */
276 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
277 return sws
->have_vgpu10
? 330 : 120;
279 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
280 return sws
->have_vgpu10
? 330 : 120;
282 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
283 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
289 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
290 case PIPE_CAP_INDEP_BLEND_ENABLE
:
291 case PIPE_CAP_CONDITIONAL_RENDER
:
292 case PIPE_CAP_QUERY_TIMESTAMP
:
293 case PIPE_CAP_TGSI_INSTANCEID
:
294 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
295 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
296 case PIPE_CAP_FAKE_SW_MSAA
:
297 return sws
->have_vgpu10
;
299 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
300 return sws
->have_vgpu10
? SVGA3D_DX_MAX_SOTARGETS
: 0;
301 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
302 return sws
->have_vgpu10
? 4 : 0;
303 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
304 return sws
->have_vgpu10
? SVGA3D_MAX_STREAMOUT_DECLS
: 0;
305 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
306 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
308 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
309 return svgascreen
->ms_samples
? 1 : 0;
311 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
312 /* convert bytes to texels for the case of the largest texel
315 return SVGA3D_DX_MAX_RESOURCE_SIZE
/ (4 * sizeof(float));
317 case PIPE_CAP_MIN_TEXEL_OFFSET
:
318 return sws
->have_vgpu10
? VGPU10_MIN_TEXEL_FETCH_OFFSET
: 0;
319 case PIPE_CAP_MAX_TEXEL_OFFSET
:
320 return sws
->have_vgpu10
? VGPU10_MAX_TEXEL_FETCH_OFFSET
: 0;
322 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
323 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
326 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
327 return sws
->have_vgpu10
? 256 : 0;
328 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
329 return sws
->have_vgpu10
? 1024 : 0;
331 case PIPE_CAP_PRIMITIVE_RESTART
:
332 return 1; /* may be a sw fallback, depending on restart index */
334 case PIPE_CAP_GENERATE_MIPMAP
:
335 return sws
->have_generate_mipmap_cmd
;
337 case PIPE_CAP_NATIVE_FENCE_FD
:
338 return sws
->have_fence_fd
;
340 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
343 case PIPE_CAP_CUBE_MAP_ARRAY
:
344 case PIPE_CAP_INDEP_BLEND_FUNC
:
345 case PIPE_CAP_SAMPLE_SHADING
:
346 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
347 case PIPE_CAP_TEXTURE_QUERY_LOD
:
348 return sws
->have_sm4_1
;
350 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
351 return sws
->have_sm4_1
? 1 : 0; /* only single-channel textures */
352 case PIPE_CAP_MAX_VARYINGS
:
353 return sws
->have_vgpu10
? VGPU10_MAX_FS_INPUTS
: 10;
355 /* Unsupported features */
356 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
357 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
358 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
359 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
360 case PIPE_CAP_TEXTURE_BARRIER
:
361 case PIPE_CAP_MAX_VERTEX_STREAMS
:
362 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
363 case PIPE_CAP_COMPUTE
:
364 case PIPE_CAP_START_INSTANCE
:
365 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
366 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
367 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
368 case PIPE_CAP_TEXTURE_GATHER_SM5
:
369 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
370 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
371 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
372 case PIPE_CAP_DRAW_INDIRECT
:
373 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
374 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
375 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
376 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
377 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
378 case PIPE_CAP_CLIP_HALFZ
:
379 case PIPE_CAP_VERTEXID_NOBASE
:
380 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
381 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
382 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
383 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
384 case PIPE_CAP_INVALIDATE_BUFFER
:
385 case PIPE_CAP_STRING_MARKER
:
386 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
387 case PIPE_CAP_QUERY_MEMORY_INFO
:
388 case PIPE_CAP_PCI_GROUP
:
389 case PIPE_CAP_PCI_BUS
:
390 case PIPE_CAP_PCI_DEVICE
:
391 case PIPE_CAP_PCI_FUNCTION
:
392 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
393 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES
:
394 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES
:
395 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES
:
396 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES
:
397 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE
:
398 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS
:
399 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET
:
401 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
403 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
404 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
405 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
406 return 1; /* need 4-byte alignment for all offsets and strides */
407 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
409 case PIPE_CAP_MAX_VIEWPORTS
:
411 case PIPE_CAP_ENDIANNESS
:
412 return PIPE_ENDIAN_LITTLE
;
414 case PIPE_CAP_VENDOR_ID
:
415 return 0x15ad; /* VMware Inc. */
416 case PIPE_CAP_DEVICE_ID
:
417 return 0x0405; /* assume SVGA II */
418 case PIPE_CAP_ACCELERATED
:
420 case PIPE_CAP_VIDEO_MEMORY
:
421 /* XXX: Query the host ? */
423 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
424 return sws
->have_vgpu10
;
425 case PIPE_CAP_CLEAR_TEXTURE
:
426 return sws
->have_vgpu10
;
428 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
429 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
430 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
431 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
432 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
433 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
434 case PIPE_CAP_TGSI_TXQS
:
435 case PIPE_CAP_SHAREABLE_SHADERS
:
436 case PIPE_CAP_DRAW_PARAMETERS
:
437 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
438 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
439 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
440 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
441 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
442 case PIPE_CAP_CULL_DISTANCE
:
443 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
444 case PIPE_CAP_TGSI_VOTE
:
445 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
446 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
447 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
448 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
449 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
450 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
451 case PIPE_CAP_FBFETCH
:
452 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
453 case PIPE_CAP_DOUBLES
:
455 case PIPE_CAP_INT64_DIVMOD
:
456 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
457 case PIPE_CAP_TGSI_CLOCK
:
458 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
459 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
460 case PIPE_CAP_TGSI_BALLOT
:
461 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
462 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
463 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
464 case PIPE_CAP_POST_DEPTH_COVERAGE
:
465 case PIPE_CAP_BINDLESS_TEXTURE
:
466 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
467 case PIPE_CAP_QUERY_SO_OVERFLOW
:
468 case PIPE_CAP_MEMOBJ
:
469 case PIPE_CAP_LOAD_CONSTBUF
:
470 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
471 case PIPE_CAP_TILE_RASTER_ORDER
:
472 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
473 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS
:
474 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
475 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
476 case PIPE_CAP_FENCE_SIGNAL
:
477 case PIPE_CAP_CONSTBUF0_FLAGS
:
478 case PIPE_CAP_PACKED_UNIFORMS
:
479 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS
:
481 case PIPE_CAP_MAX_GS_INVOCATIONS
:
483 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
486 return u_pipe_screen_get_param_defaults(screen
, param
);
492 vgpu9_get_shader_param(struct pipe_screen
*screen
,
493 enum pipe_shader_type shader
,
494 enum pipe_shader_cap param
)
496 struct svga_screen
*svgascreen
= svga_screen(screen
);
497 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
500 assert(!sws
->have_vgpu10
);
504 case PIPE_SHADER_FRAGMENT
:
507 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
508 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
509 return get_uint_cap(sws
,
510 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS
,
512 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
513 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
515 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
516 return SVGA3D_MAX_NESTING_LEVEL
;
517 case PIPE_SHADER_CAP_MAX_INPUTS
:
519 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
520 return svgascreen
->max_color_buffers
;
521 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
522 return 224 * sizeof(float[4]);
523 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
525 case PIPE_SHADER_CAP_MAX_TEMPS
:
526 val
= get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS
, 32);
527 return MIN2(val
, SVGA3D_TEMPREG_MAX
);
528 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
530 * Although PS 3.0 has some addressing abilities it can only represent
531 * loops that can be statically determined and unrolled. Given we can
532 * only handle a subset of the cases that the state tracker already
533 * does it is better to defer loop unrolling to the state tracker.
536 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
538 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
540 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
541 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
542 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
544 case PIPE_SHADER_CAP_SUBROUTINES
:
546 case PIPE_SHADER_CAP_INT64_ATOMICS
:
547 case PIPE_SHADER_CAP_INTEGERS
:
549 case PIPE_SHADER_CAP_FP16
:
551 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
552 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
554 case PIPE_SHADER_CAP_PREFERRED_IR
:
555 return PIPE_SHADER_IR_TGSI
;
556 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
558 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
559 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
560 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
561 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
562 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
563 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
564 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
565 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
566 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
567 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
568 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
570 case PIPE_SHADER_CAP_SCALAR_ISA
:
572 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
575 /* If we get here, we failed to handle a cap above */
576 debug_printf("Unexpected fragment shader query %u\n", param
);
578 case PIPE_SHADER_VERTEX
:
581 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
582 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
583 return get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS
,
585 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
586 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
587 /* XXX: until we have vertex texture support */
589 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
590 return SVGA3D_MAX_NESTING_LEVEL
;
591 case PIPE_SHADER_CAP_MAX_INPUTS
:
593 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
595 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
596 return 256 * sizeof(float[4]);
597 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
599 case PIPE_SHADER_CAP_MAX_TEMPS
:
600 val
= get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS
, 32);
601 return MIN2(val
, SVGA3D_TEMPREG_MAX
);
602 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
604 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
606 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
607 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
609 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
611 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
613 case PIPE_SHADER_CAP_SUBROUTINES
:
615 case PIPE_SHADER_CAP_INT64_ATOMICS
:
616 case PIPE_SHADER_CAP_INTEGERS
:
618 case PIPE_SHADER_CAP_FP16
:
620 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
621 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
623 case PIPE_SHADER_CAP_PREFERRED_IR
:
624 return PIPE_SHADER_IR_TGSI
;
625 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
627 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
628 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
629 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
630 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
631 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
632 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
633 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
634 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
635 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
636 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
637 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
639 case PIPE_SHADER_CAP_SCALAR_ISA
:
641 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
644 /* If we get here, we failed to handle a cap above */
645 debug_printf("Unexpected vertex shader query %u\n", param
);
647 case PIPE_SHADER_GEOMETRY
:
648 case PIPE_SHADER_COMPUTE
:
649 case PIPE_SHADER_TESS_CTRL
:
650 case PIPE_SHADER_TESS_EVAL
:
651 /* no support for geometry, tess or compute shaders at this time */
654 debug_printf("Unexpected shader type (%u) query\n", shader
);
662 vgpu10_get_shader_param(struct pipe_screen
*screen
,
663 enum pipe_shader_type shader
,
664 enum pipe_shader_cap param
)
666 struct svga_screen
*svgascreen
= svga_screen(screen
);
667 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
669 assert(sws
->have_vgpu10
);
670 (void) sws
; /* silence unused var warnings in non-debug builds */
672 /* Only VS, GS, FS supported */
673 if (shader
!= PIPE_SHADER_VERTEX
&&
674 shader
!= PIPE_SHADER_GEOMETRY
&&
675 shader
!= PIPE_SHADER_FRAGMENT
) {
679 /* NOTE: we do not query the device for any caps/limits at this time */
681 /* Generally the same limits for vertex, geometry and fragment shaders */
683 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
684 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
685 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
686 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
688 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
690 case PIPE_SHADER_CAP_MAX_INPUTS
:
691 if (shader
== PIPE_SHADER_FRAGMENT
)
692 return VGPU10_MAX_FS_INPUTS
;
693 else if (shader
== PIPE_SHADER_GEOMETRY
)
694 return VGPU10_MAX_GS_INPUTS
;
696 return VGPU10_MAX_VS_INPUTS
;
697 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
698 if (shader
== PIPE_SHADER_FRAGMENT
)
699 return VGPU10_MAX_FS_OUTPUTS
;
700 else if (shader
== PIPE_SHADER_GEOMETRY
)
701 return VGPU10_MAX_GS_OUTPUTS
;
703 return VGPU10_MAX_VS_OUTPUTS
;
704 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
705 return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT
* sizeof(float[4]);
706 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
707 return svgascreen
->max_const_buffers
;
708 case PIPE_SHADER_CAP_MAX_TEMPS
:
709 return VGPU10_MAX_TEMPS
;
710 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
711 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
712 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
713 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
714 return TRUE
; /* XXX verify */
715 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
716 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
717 case PIPE_SHADER_CAP_SUBROUTINES
:
718 case PIPE_SHADER_CAP_INTEGERS
:
720 case PIPE_SHADER_CAP_FP16
:
722 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
723 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
724 return SVGA3D_DX_MAX_SAMPLERS
;
725 case PIPE_SHADER_CAP_PREFERRED_IR
:
726 return PIPE_SHADER_IR_TGSI
;
727 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
729 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
730 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
731 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
732 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
733 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
734 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
735 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
736 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
737 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
738 case PIPE_SHADER_CAP_INT64_ATOMICS
:
739 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
740 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
742 case PIPE_SHADER_CAP_SCALAR_ISA
:
744 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
747 debug_printf("Unexpected vgpu10 shader query %u\n", param
);
755 svga_get_shader_param(struct pipe_screen
*screen
, enum pipe_shader_type shader
,
756 enum pipe_shader_cap param
)
758 struct svga_screen
*svgascreen
= svga_screen(screen
);
759 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
760 if (sws
->have_vgpu10
) {
761 return vgpu10_get_shader_param(screen
, shader
, param
);
764 return vgpu9_get_shader_param(screen
, shader
, param
);
770 svga_fence_reference(struct pipe_screen
*screen
,
771 struct pipe_fence_handle
**ptr
,
772 struct pipe_fence_handle
*fence
)
774 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
775 sws
->fence_reference(sws
, ptr
, fence
);
780 svga_fence_finish(struct pipe_screen
*screen
,
781 struct pipe_context
*ctx
,
782 struct pipe_fence_handle
*fence
,
785 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
788 SVGA_STATS_TIME_PUSH(sws
, SVGA_STATS_TIME_FENCEFINISH
);
791 retVal
= sws
->fence_signalled(sws
, fence
, 0) == 0;
794 SVGA_DBG(DEBUG_DMA
|DEBUG_PERF
, "%s fence_ptr %p\n",
795 __FUNCTION__
, fence
);
797 retVal
= sws
->fence_finish(sws
, fence
, timeout
, 0) == 0;
800 SVGA_STATS_TIME_POP(sws
);
807 svga_fence_get_fd(struct pipe_screen
*screen
,
808 struct pipe_fence_handle
*fence
)
810 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
812 return sws
->fence_get_fd(sws
, fence
, TRUE
);
817 svga_get_driver_query_info(struct pipe_screen
*screen
,
819 struct pipe_driver_query_info
*info
)
821 #define QUERY(NAME, ENUM, UNITS) \
822 {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
824 static const struct pipe_driver_query_info queries
[] = {
825 /* per-frame counters */
826 QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS
,
827 PIPE_DRIVER_QUERY_TYPE_UINT64
),
828 QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS
,
829 PIPE_DRIVER_QUERY_TYPE_UINT64
),
830 QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES
,
831 PIPE_DRIVER_QUERY_TYPE_UINT64
),
832 QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS
,
833 PIPE_DRIVER_QUERY_TYPE_UINT64
),
834 QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME
,
835 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
),
836 QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED
,
837 PIPE_DRIVER_QUERY_TYPE_UINT64
),
838 QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED
,
839 PIPE_DRIVER_QUERY_TYPE_UINT64
),
840 QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED
,
841 PIPE_DRIVER_QUERY_TYPE_BYTES
),
842 QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE
,
843 PIPE_DRIVER_QUERY_TYPE_BYTES
),
844 QUERY("flush-time", SVGA_QUERY_FLUSH_TIME
,
845 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
),
846 QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES
,
847 PIPE_DRIVER_QUERY_TYPE_UINT64
),
848 QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS
,
849 PIPE_DRIVER_QUERY_TYPE_UINT64
),
850 QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES
,
851 PIPE_DRIVER_QUERY_TYPE_UINT64
),
852 QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS
,
853 PIPE_DRIVER_QUERY_TYPE_UINT64
),
854 QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES
,
855 PIPE_DRIVER_QUERY_TYPE_UINT64
),
856 QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES
,
857 PIPE_DRIVER_QUERY_TYPE_UINT64
),
859 /* running total counters */
860 QUERY("memory-used", SVGA_QUERY_MEMORY_USED
,
861 PIPE_DRIVER_QUERY_TYPE_BYTES
),
862 QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS
,
863 PIPE_DRIVER_QUERY_TYPE_UINT64
),
864 QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES
,
865 PIPE_DRIVER_QUERY_TYPE_UINT64
),
866 QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS
,
867 PIPE_DRIVER_QUERY_TYPE_UINT64
),
868 QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS
,
869 PIPE_DRIVER_QUERY_TYPE_UINT64
),
870 QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP
,
871 PIPE_DRIVER_QUERY_TYPE_UINT64
),
872 QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS
,
873 PIPE_DRIVER_QUERY_TYPE_UINT64
),
874 QUERY("num-commands-per-draw", SVGA_QUERY_NUM_COMMANDS_PER_DRAW
,
875 PIPE_DRIVER_QUERY_TYPE_FLOAT
),
880 return ARRAY_SIZE(queries
);
882 if (index
>= ARRAY_SIZE(queries
))
885 *info
= queries
[index
];
891 init_logging(struct pipe_screen
*screen
)
893 struct svga_screen
*svgascreen
= svga_screen(screen
);
894 static const char *log_prefix
= "Mesa: ";
897 /* Log Version to Host */
898 util_snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
899 "%s%s\n", log_prefix
, svga_get_name(screen
));
900 svgascreen
->sws
->host_log(svgascreen
->sws
, host_log
);
902 util_snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
903 "%s" PACKAGE_VERSION MESA_GIT_SHA1
, log_prefix
);
904 svgascreen
->sws
->host_log(svgascreen
->sws
, host_log
);
906 /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
907 * line (program name and arguments).
909 if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE
)) {
911 if (os_get_command_line(cmdline
, sizeof(cmdline
))) {
912 util_snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
913 "%s%s\n", log_prefix
, cmdline
);
914 svgascreen
->sws
->host_log(svgascreen
->sws
, host_log
);
921 * no-op logging function to use when SVGA_NO_LOGGING is set.
924 nop_host_log(struct svga_winsys_screen
*sws
, const char *message
)
931 svga_destroy_screen( struct pipe_screen
*screen
)
933 struct svga_screen
*svgascreen
= svga_screen(screen
);
935 svga_screen_cache_cleanup(svgascreen
);
937 mtx_destroy(&svgascreen
->swc_mutex
);
938 mtx_destroy(&svgascreen
->tex_mutex
);
940 svgascreen
->sws
->destroy(svgascreen
->sws
);
947 * Create a new svga_screen object
950 svga_screen_create(struct svga_winsys_screen
*sws
)
952 struct svga_screen
*svgascreen
;
953 struct pipe_screen
*screen
;
956 SVGA_DEBUG
= debug_get_flags_option("SVGA_DEBUG", svga_debug_flags
, 0 );
959 svgascreen
= CALLOC_STRUCT(svga_screen
);
963 svgascreen
->debug
.force_level_surface_view
=
964 debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE
);
965 svgascreen
->debug
.force_surface_view
=
966 debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE
);
967 svgascreen
->debug
.force_sampler_view
=
968 debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE
);
969 svgascreen
->debug
.no_surface_view
=
970 debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE
);
971 svgascreen
->debug
.no_sampler_view
=
972 debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE
);
973 svgascreen
->debug
.no_cache_index_buffers
=
974 debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE
);
976 screen
= &svgascreen
->screen
;
978 screen
->destroy
= svga_destroy_screen
;
979 screen
->get_name
= svga_get_name
;
980 screen
->get_vendor
= svga_get_vendor
;
981 screen
->get_device_vendor
= svga_get_vendor
; // TODO actual device vendor
982 screen
->get_param
= svga_get_param
;
983 screen
->get_shader_param
= svga_get_shader_param
;
984 screen
->get_paramf
= svga_get_paramf
;
985 screen
->get_timestamp
= NULL
;
986 screen
->is_format_supported
= svga_is_format_supported
;
987 screen
->context_create
= svga_context_create
;
988 screen
->fence_reference
= svga_fence_reference
;
989 screen
->fence_finish
= svga_fence_finish
;
990 screen
->fence_get_fd
= svga_fence_get_fd
;
992 screen
->get_driver_query_info
= svga_get_driver_query_info
;
993 svgascreen
->sws
= sws
;
995 svga_init_screen_resource_functions(svgascreen
);
997 if (sws
->get_hw_version
) {
998 svgascreen
->hw_version
= sws
->get_hw_version(sws
);
1000 svgascreen
->hw_version
= SVGA3D_HWVERSION_WS65_B1
;
1003 if (svgascreen
->hw_version
< SVGA3D_HWVERSION_WS8_B1
) {
1004 /* too old for 3D acceleration */
1005 debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
1006 svgascreen
->hw_version
);
1010 debug_printf("%s enabled = %u\n",
1011 sws
->have_sm4_1
? "SM4_1" : "VGPU10",
1012 sws
->have_sm4_1
? 1 : sws
->have_vgpu10
);
1014 debug_printf("Mesa: %s %s (%s)\n", svga_get_name(screen
),
1015 PACKAGE_VERSION
, MESA_GIT_SHA1
);
1018 * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
1019 * when sampled from, where as the DF16, DF24, and D24S8_INT do not. So
1020 * we prefer the later when available.
1022 * This mimics hardware vendors extensions for D3D depth sampling. See also
1023 * http://aras-p.info/texts/D3D9GPUHacks.html
1027 boolean has_df16
, has_df24
, has_d24s8_int
;
1028 SVGA3dSurfaceFormatCaps caps
;
1029 SVGA3dSurfaceFormatCaps mask
;
1034 svgascreen
->depth
.z16
= SVGA3D_Z_D16
;
1035 svgascreen
->depth
.x8z24
= SVGA3D_Z_D24X8
;
1036 svgascreen
->depth
.s8z24
= SVGA3D_Z_D24S8
;
1038 svga_get_format_cap(svgascreen
, SVGA3D_Z_DF16
, &caps
);
1039 has_df16
= (caps
.value
& mask
.value
) == mask
.value
;
1041 svga_get_format_cap(svgascreen
, SVGA3D_Z_DF24
, &caps
);
1042 has_df24
= (caps
.value
& mask
.value
) == mask
.value
;
1044 svga_get_format_cap(svgascreen
, SVGA3D_Z_D24S8_INT
, &caps
);
1045 has_d24s8_int
= (caps
.value
& mask
.value
) == mask
.value
;
1047 /* XXX: We might want some other logic here.
1048 * Like if we only have d24s8_int we should
1049 * emulate the other formats with that.
1052 svgascreen
->depth
.z16
= SVGA3D_Z_DF16
;
1055 svgascreen
->depth
.x8z24
= SVGA3D_Z_DF24
;
1057 if (has_d24s8_int
) {
1058 svgascreen
->depth
.s8z24
= SVGA3D_Z_D24S8_INT
;
1062 /* Query device caps
1064 if (sws
->have_vgpu10
) {
1065 svgascreen
->haveProvokingVertex
1066 = get_bool_cap(sws
, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX
, FALSE
);
1067 svgascreen
->haveLineSmooth
= TRUE
;
1068 svgascreen
->maxPointSize
= 80.0F
;
1069 svgascreen
->max_color_buffers
= SVGA3D_DX_MAX_RENDER_TARGETS
;
1071 /* Multisample samples per pixel */
1072 if (sws
->have_sm4_1
&& debug_get_bool_option("SVGA_MSAA", TRUE
)) {
1073 if (get_bool_cap(sws
, SVGA3D_DEVCAP_MULTISAMPLE_2X
, FALSE
))
1074 svgascreen
->ms_samples
|= 1 << 1;
1075 if (get_bool_cap(sws
, SVGA3D_DEVCAP_MULTISAMPLE_4X
, FALSE
))
1076 svgascreen
->ms_samples
|= 1 << 3;
1079 /* Maximum number of constant buffers */
1080 svgascreen
->max_const_buffers
=
1081 get_uint_cap(sws
, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS
, 1);
1082 svgascreen
->max_const_buffers
= MIN2(svgascreen
->max_const_buffers
,
1083 SVGA_MAX_CONST_BUFS
);
1085 screen
->is_format_supported
= svga_is_dx_format_supported
;
1089 unsigned vs_ver
= get_uint_cap(sws
, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION
,
1090 SVGA3DVSVERSION_NONE
);
1091 unsigned fs_ver
= get_uint_cap(sws
, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION
,
1092 SVGA3DPSVERSION_NONE
);
1094 /* we require Shader model 3.0 or later */
1095 if (fs_ver
< SVGA3DPSVERSION_30
|| vs_ver
< SVGA3DVSVERSION_30
) {
1099 svgascreen
->haveProvokingVertex
= FALSE
;
1101 svgascreen
->haveLineSmooth
=
1102 get_bool_cap(sws
, SVGA3D_DEVCAP_LINE_AA
, FALSE
);
1104 svgascreen
->maxPointSize
=
1105 get_float_cap(sws
, SVGA3D_DEVCAP_MAX_POINT_SIZE
, 1.0f
);
1106 /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1107 svgascreen
->maxPointSize
= MIN2(svgascreen
->maxPointSize
, 80.0f
);
1109 /* The SVGA3D device always supports 4 targets at this time, regardless
1110 * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1112 svgascreen
->max_color_buffers
= 4;
1114 /* Only support one constant buffer
1116 svgascreen
->max_const_buffers
= 1;
1118 /* No multisampling */
1119 svgascreen
->ms_samples
= 0;
1122 /* common VGPU9 / VGPU10 caps */
1123 svgascreen
->haveLineStipple
=
1124 get_bool_cap(sws
, SVGA3D_DEVCAP_LINE_STIPPLE
, FALSE
);
1126 svgascreen
->maxLineWidth
=
1127 MAX2(1.0, get_float_cap(sws
, SVGA3D_DEVCAP_MAX_LINE_WIDTH
, 1.0f
));
1129 svgascreen
->maxLineWidthAA
=
1130 MAX2(1.0, get_float_cap(sws
, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH
, 1.0f
));
1133 debug_printf("svga: haveProvokingVertex %u\n",
1134 svgascreen
->haveProvokingVertex
);
1135 debug_printf("svga: haveLineStip %u "
1136 "haveLineSmooth %u maxLineWidth %.2f maxLineWidthAA %.2f\n",
1137 svgascreen
->haveLineStipple
, svgascreen
->haveLineSmooth
,
1138 svgascreen
->maxLineWidth
, svgascreen
->maxLineWidthAA
);
1139 debug_printf("svga: maxPointSize %g\n", svgascreen
->maxPointSize
);
1140 debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen
->ms_samples
);
1143 (void) mtx_init(&svgascreen
->tex_mutex
, mtx_plain
);
1144 (void) mtx_init(&svgascreen
->swc_mutex
, mtx_recursive
);
1146 svga_screen_cache_init(svgascreen
);
1148 if (debug_get_bool_option("SVGA_NO_LOGGING", FALSE
) == TRUE
) {
1149 svgascreen
->sws
->host_log
= nop_host_log
;
1151 init_logging(screen
);
1162 struct svga_winsys_screen
*
1163 svga_winsys_screen(struct pipe_screen
*screen
)
1165 return svga_screen(screen
)->sws
;
1170 struct svga_screen
*
1171 svga_screen(struct pipe_screen
*screen
)
1174 assert(screen
->destroy
== svga_destroy_screen
);
1175 return (struct svga_screen
*)screen
;