src/gallium/drivers/svga/svga_screen.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "util/u_format.h"
  27 #include "util/u_memory.h"
  28 #include "util/u_inlines.h"
  29 #include "util/u_string.h"
  30 #include "util/u_math.h"
  31
  32 #include "svga_winsys.h"
  33 #include "svga_public.h"
  34 #include "svga_context.h"
  35 #include "svga_format.h"
  36 #include "svga_screen.h"
  37 #include "svga_tgsi.h"
  38 #include "svga_resource_texture.h"
  39 #include "svga_resource.h"
  40 #include "svga_debug.h"
  41
  42 #include "svga3d_shaderdefs.h"
  43 #include "VGPU10ShaderTokens.h"
  44
  45 /* NOTE: this constant may get moved into a svga3d*.h header file */
  46 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
  47
  48 #ifdef DEBUG
  49 int SVGA_DEBUG = 0;
  50
  51 static const struct debug_named_value svga_debug_flags[] = {
  52    { "dma",         DEBUG_DMA, NULL },
  53    { "tgsi",        DEBUG_TGSI, NULL },
  54    { "pipe",        DEBUG_PIPE, NULL },
  55    { "state",       DEBUG_STATE, NULL },
  56    { "screen",      DEBUG_SCREEN, NULL },
  57    { "tex",         DEBUG_TEX, NULL },
  58    { "swtnl",       DEBUG_SWTNL, NULL },
  59    { "const",       DEBUG_CONSTS, NULL },
  60    { "viewport",    DEBUG_VIEWPORT, NULL },
  61    { "views",       DEBUG_VIEWS, NULL },
  62    { "perf",        DEBUG_PERF, NULL },
  63    { "flush",       DEBUG_FLUSH, NULL },
  64    { "sync",        DEBUG_SYNC, NULL },
  65    { "cache",       DEBUG_CACHE, NULL },
  66    { "streamout",   DEBUG_STREAMOUT, NULL },
  67    { "query",       DEBUG_QUERY, NULL },
  68    DEBUG_NAMED_VALUE_END
  69 };
  70 #endif
  71
  72 static const char *
  73 svga_get_vendor( struct pipe_screen *pscreen )
  74 {
  75    return "VMware, Inc.";
  76 }
  77
  78
  79 static const char *
  80 svga_get_name( struct pipe_screen *pscreen )
  81 {
  82    const char *build = "", *llvm = "", *mutex = "";
  83    static char name[100];
  84 #ifdef DEBUG
  85    /* Only return internal details in the DEBUG version:
  86     */
  87    build = "build: DEBUG;";
  88    mutex = "mutex: " PIPE_ATOMIC ";";
  89 #elif defined(VMX86_STATS)
  90    build = "build: OPT;";
  91 #else
  92    build = "build: RELEASE;";
  93 #endif
  94 #ifdef HAVE_LLVM
  95    llvm = "LLVM;";
  96 #endif
  97
  98    util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
  99    return name;
 100 }
 101
 102
 103 /** Helper for querying float-valued device cap */
 104 static float
 105 get_float_cap(struct svga_winsys_screen *sws, unsigned cap, float defaultVal)
 106 {
 107    SVGA3dDevCapResult result;
 108    if (sws->get_cap(sws, cap, &result))
 109       return result.f;
 110    else
 111       return defaultVal;
 112 }
 113
 114
 115 /** Helper for querying uint-valued device cap */
 116 static unsigned
 117 get_uint_cap(struct svga_winsys_screen *sws, unsigned cap, unsigned defaultVal)
 118 {
 119    SVGA3dDevCapResult result;
 120    if (sws->get_cap(sws, cap, &result))
 121       return result.u;
 122    else
 123       return defaultVal;
 124 }
 125
 126
 127 /** Helper for querying boolean-valued device cap */
 128 static boolean
 129 get_bool_cap(struct svga_winsys_screen *sws, unsigned cap, boolean defaultVal)
 130 {
 131    SVGA3dDevCapResult result;
 132    if (sws->get_cap(sws, cap, &result))
 133       return result.b;
 134    else
 135       return defaultVal;
 136 }
 137
 138
 139 static float
 140 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 141 {
 142    struct svga_screen *svgascreen = svga_screen(screen);
 143    struct svga_winsys_screen *sws = svgascreen->sws;
 144
 145    switch (param) {
 146    case PIPE_CAPF_MAX_LINE_WIDTH:
 147       return svgascreen->maxLineWidth;
 148    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 149       return svgascreen->maxLineWidthAA;
 150
 151    case PIPE_CAPF_MAX_POINT_WIDTH:
 152       /* fall-through */
 153    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 154       return svgascreen->maxPointSize;
 155
 156    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 157       return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
 158
 159    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 160       return 15.0;
 161
 162    case PIPE_CAPF_GUARD_BAND_LEFT:
 163    case PIPE_CAPF_GUARD_BAND_TOP:
 164    case PIPE_CAPF_GUARD_BAND_RIGHT:
 165    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 166       return 0.0;
 167    }
 168
 169    debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
 170    return 0;
 171 }
 172
 173
 174 static int
 175 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
 176 {
 177    struct svga_screen *svgascreen = svga_screen(screen);
 178    struct svga_winsys_screen *sws = svgascreen->sws;
 179    SVGA3dDevCapResult result;
 180
 181    switch (param) {
 182    case PIPE_CAP_NPOT_TEXTURES:
 183    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 184    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 185       return 1;
 186    case PIPE_CAP_TWO_SIDED_STENCIL:
 187       return 1;
 188    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 189       /*
 190        * "In virtually every OpenGL implementation and hardware,
 191        * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
 192        * http://www.opengl.org/wiki/Blending
 193        */
 194       return sws->have_vgpu10 ? 1 : 0;
 195    case PIPE_CAP_ANISOTROPIC_FILTER:
 196       return 1;
 197    case PIPE_CAP_POINT_SPRITE:
 198       return 1;
 199    case PIPE_CAP_TGSI_TEXCOORD:
 200       return 0;
 201    case PIPE_CAP_MAX_RENDER_TARGETS:
 202       return svgascreen->max_color_buffers;
 203    case PIPE_CAP_OCCLUSION_QUERY:
 204       return 1;
 205    case PIPE_CAP_QUERY_TIME_ELAPSED:
 206       return 0;
 207    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 208       return sws->have_vgpu10;
 209    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 210       return 1;
 211    case PIPE_CAP_TEXTURE_SWIZZLE:
 212       return 1;
 213    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 214       return 0;
 215    case PIPE_CAP_USER_VERTEX_BUFFERS:
 216    case PIPE_CAP_USER_INDEX_BUFFERS:
 217       return 0;
 218    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 219       return 1;
 220    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 221       return 256;
 222
 223    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 224       {
 225          unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
 226          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
 227             levels = MIN2(util_logbase2(result.u) + 1, levels);
 228          else
 229             levels = 12 /* 2048x2048 */;
 230          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
 231             levels = MIN2(util_logbase2(result.u) + 1, levels);
 232          else
 233             levels = 12 /* 2048x2048 */;
 234          return levels;
 235       }
 236
 237    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 238       if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
 239          return 8;  /* max 128x128x128 */
 240       return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
 241
 242    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 243       /*
 244        * No mechanism to query the host, and at least limited to 2048x2048 on
 245        * certain hardware.
 246        */
 247       return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
 248                   12 /* 2048x2048 */);
 249
 250    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 251       return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
 252
 253    case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
 254       return 1;
 255
 256    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 257       return 1;
 258    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 259       return sws->have_vgpu10;
 260    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 261       return 0;
 262    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 263       return !sws->have_vgpu10;
 264
 265    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 266       return 1; /* The color outputs of vertex shaders are not clamped */
 267    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 268       return 0; /* The driver can't clamp vertex colors */
 269    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 270       return 0; /* The driver can't clamp fragment colors */
 271
 272    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 273       return 1; /* expected for GL_ARB_framebuffer_object */
 274
 275    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 276       return sws->have_vgpu10 ? 330 : 120;
 277
 278    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 279       return 0;
 280
 281    case PIPE_CAP_SM3:
 282       return 1;
 283
 284    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 285    case PIPE_CAP_INDEP_BLEND_ENABLE:
 286    case PIPE_CAP_CONDITIONAL_RENDER:
 287    case PIPE_CAP_QUERY_TIMESTAMP:
 288    case PIPE_CAP_TGSI_INSTANCEID:
 289    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 290    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 291    case PIPE_CAP_FAKE_SW_MSAA:
 292       return sws->have_vgpu10;
 293
 294    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 295       return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
 296    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 297       return sws->have_vgpu10 ? 4 : 0;
 298    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 299       return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
 300    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 301    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 302       return 0;
 303    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 304       return svgascreen->ms_samples ? 1 : 0;
 305
 306    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 307       return SVGA3D_DX_MAX_RESOURCE_SIZE;
 308
 309    case PIPE_CAP_MIN_TEXEL_OFFSET:
 310       return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
 311    case PIPE_CAP_MAX_TEXEL_OFFSET:
 312       return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
 313
 314    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 315    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 316       return 0;
 317
 318    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 319       return sws->have_vgpu10 ? 256 : 0;
 320    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 321       return sws->have_vgpu10 ? 1024 : 0;
 322
 323    case PIPE_CAP_PRIMITIVE_RESTART:
 324       return 1; /* may be a sw fallback, depending on restart index */
 325
 326    case PIPE_CAP_GENERATE_MIPMAP:
 327       return sws->have_generate_mipmap_cmd;
 328
 329    /* Unsupported features */
 330    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 331    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 332    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 333    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 334    case PIPE_CAP_INDEP_BLEND_FUNC:
 335    case PIPE_CAP_TEXTURE_BARRIER:
 336    case PIPE_CAP_MAX_VERTEX_STREAMS:
 337    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 338    case PIPE_CAP_COMPUTE:
 339    case PIPE_CAP_START_INSTANCE:
 340    case PIPE_CAP_CUBE_MAP_ARRAY:
 341    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 342    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 343    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 344    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 345    case PIPE_CAP_TEXTURE_GATHER_SM5:
 346    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 347    case PIPE_CAP_TEXTURE_QUERY_LOD:
 348    case PIPE_CAP_SAMPLE_SHADING:
 349    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 350    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 351    case PIPE_CAP_DRAW_INDIRECT:
 352    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 353    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 354    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 355    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 356    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 357    case PIPE_CAP_CLIP_HALFZ:
 358    case PIPE_CAP_VERTEXID_NOBASE:
 359    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 360    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 361    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 362    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 363    case PIPE_CAP_INVALIDATE_BUFFER:
 364    case PIPE_CAP_STRING_MARKER:
 365    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 366    case PIPE_CAP_QUERY_MEMORY_INFO:
 367    case PIPE_CAP_PCI_GROUP:
 368    case PIPE_CAP_PCI_BUS:
 369    case PIPE_CAP_PCI_DEVICE:
 370    case PIPE_CAP_PCI_FUNCTION:
 371    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 372       return 0;
 373    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 374       return 64;
 375    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 376    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 377    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 378       return 1;  /* need 4-byte alignment for all offsets and strides */
 379    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 380       return 2048;
 381    case PIPE_CAP_MAX_VIEWPORTS:
 382       return 1;
 383    case PIPE_CAP_ENDIANNESS:
 384       return PIPE_ENDIAN_LITTLE;
 385
 386    case PIPE_CAP_VENDOR_ID:
 387       return 0x15ad; /* VMware Inc. */
 388    case PIPE_CAP_DEVICE_ID:
 389       return 0x0405; /* assume SVGA II */
 390    case PIPE_CAP_ACCELERATED:
 391       return 0; /* XXX: */
 392    case PIPE_CAP_VIDEO_MEMORY:
 393       /* XXX: Query the host ? */
 394       return 1;
 395    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 396       return sws->have_vgpu10;
 397    case PIPE_CAP_CLEAR_TEXTURE:
 398       return sws->have_vgpu10;
 399    case PIPE_CAP_UMA:
 400    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 401    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 402    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 403    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 404    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 405    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 406    case PIPE_CAP_TGSI_TXQS:
 407    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 408    case PIPE_CAP_SHAREABLE_SHADERS:
 409    case PIPE_CAP_DRAW_PARAMETERS:
 410    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 411    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 412    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 413    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 414    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 415    case PIPE_CAP_CULL_DISTANCE:
 416    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 417    case PIPE_CAP_TGSI_VOTE:
 418    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 419    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 420    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 421    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 422       return 0;
 423    }
 424
 425    debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
 426    return 0;
 427 }
 428
 429
 430 static int
 431 vgpu9_get_shader_param(struct pipe_screen *screen, unsigned shader,
 432                        enum pipe_shader_cap param)
 433 {
 434    struct svga_screen *svgascreen = svga_screen(screen);
 435    struct svga_winsys_screen *sws = svgascreen->sws;
 436    unsigned val;
 437
 438    assert(!sws->have_vgpu10);
 439
 440    switch (shader)
 441    {
 442    case PIPE_SHADER_FRAGMENT:
 443       switch (param)
 444       {
 445       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 446       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 447          return get_uint_cap(sws,
 448                              SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
 449                              512);
 450       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 451       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 452          return 512;
 453       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 454          return SVGA3D_MAX_NESTING_LEVEL;
 455       case PIPE_SHADER_CAP_MAX_INPUTS:
 456          return 10;
 457       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 458          return svgascreen->max_color_buffers;
 459       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 460          return 224 * sizeof(float[4]);
 461       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 462          return 1;
 463       case PIPE_SHADER_CAP_MAX_TEMPS:
 464          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
 465          return MIN2(val, SVGA3D_TEMPREG_MAX);
 466       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 467          /*
 468           * Although PS 3.0 has some addressing abilities it can only represent
 469           * loops that can be statically determined and unrolled. Given we can
 470           * only handle a subset of the cases that the state tracker already
 471           * does it is better to defer loop unrolling to the state tracker.
 472           */
 473          return 0;
 474       case PIPE_SHADER_CAP_MAX_PREDS:
 475          return 1;
 476       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 477          return 0;
 478       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 479          return 0;
 480       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 481       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 482       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 483          return 0;
 484       case PIPE_SHADER_CAP_SUBROUTINES:
 485          return 0;
 486       case PIPE_SHADER_CAP_INTEGERS:
 487          return 0;
 488       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 489       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 490          return 16;
 491       case PIPE_SHADER_CAP_PREFERRED_IR:
 492          return PIPE_SHADER_IR_TGSI;
 493       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 494          return 0;
 495       case PIPE_SHADER_CAP_DOUBLES:
 496       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 497       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 498       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 499       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 500       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 501       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 502          return 0;
 503       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 504          return 32;
 505       }
 506       /* If we get here, we failed to handle a cap above */
 507       debug_printf("Unexpected fragment shader query %u\n", param);
 508       return 0;
 509    case PIPE_SHADER_VERTEX:
 510       switch (param)
 511       {
 512       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 513       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 514          return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
 515                              512);
 516       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 517       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 518          /* XXX: until we have vertex texture support */
 519          return 0;
 520       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 521          return SVGA3D_MAX_NESTING_LEVEL;
 522       case PIPE_SHADER_CAP_MAX_INPUTS:
 523          return 16;
 524       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 525          return 10;
 526       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 527          return 256 * sizeof(float[4]);
 528       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 529          return 1;
 530       case PIPE_SHADER_CAP_MAX_TEMPS:
 531          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
 532          return MIN2(val, SVGA3D_TEMPREG_MAX);
 533       case PIPE_SHADER_CAP_MAX_PREDS:
 534          return 1;
 535       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 536          return 0;
 537       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 538          return 0;
 539       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 540       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 541          return 1;
 542       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 543          return 0;
 544       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 545          return 1;
 546       case PIPE_SHADER_CAP_SUBROUTINES:
 547          return 0;
 548       case PIPE_SHADER_CAP_INTEGERS:
 549          return 0;
 550       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 551       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 552          return 0;
 553       case PIPE_SHADER_CAP_PREFERRED_IR:
 554          return PIPE_SHADER_IR_TGSI;
 555       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 556          return 0;
 557       case PIPE_SHADER_CAP_DOUBLES:
 558       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 559       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 560       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 561       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 562       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 563       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 564          return 0;
 565       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 566          return 32;
 567       }
 568       /* If we get here, we failed to handle a cap above */
 569       debug_printf("Unexpected vertex shader query %u\n", param);
 570       return 0;
 571    case PIPE_SHADER_GEOMETRY:
 572    case PIPE_SHADER_COMPUTE:
 573    case PIPE_SHADER_TESS_CTRL:
 574    case PIPE_SHADER_TESS_EVAL:
 575       /* no support for geometry, tess or compute shaders at this time */
 576       return 0;
 577    default:
 578       debug_printf("Unexpected shader type (%u) query\n", shader);
 579       return 0;
 580    }
 581    return 0;
 582 }
 583
 584
 585 static int
 586 vgpu10_get_shader_param(struct pipe_screen *screen, unsigned shader,
 587                         enum pipe_shader_cap param)
 588 {
 589    struct svga_screen *svgascreen = svga_screen(screen);
 590    struct svga_winsys_screen *sws = svgascreen->sws;
 591
 592    assert(sws->have_vgpu10);
 593    (void) sws;  /* silence unused var warnings in non-debug builds */
 594
 595    /* Only VS, GS, FS supported */
 596    if (shader != PIPE_SHADER_VERTEX &&
 597        shader != PIPE_SHADER_GEOMETRY &&
 598        shader != PIPE_SHADER_FRAGMENT) {
 599       return 0;
 600    }
 601
 602    /* NOTE: we do not query the device for any caps/limits at this time */
 603
 604    /* Generally the same limits for vertex, geometry and fragment shaders */
 605    switch (param) {
 606    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 607    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 608    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 609    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 610       return 64 * 1024;
 611    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 612       return 64;
 613    case PIPE_SHADER_CAP_MAX_INPUTS:
 614       if (shader == PIPE_SHADER_FRAGMENT)
 615          return VGPU10_MAX_FS_INPUTS;
 616       else if (shader == PIPE_SHADER_GEOMETRY)
 617          return VGPU10_MAX_GS_INPUTS;
 618       else
 619          return VGPU10_MAX_VS_INPUTS;
 620    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 621       if (shader == PIPE_SHADER_FRAGMENT)
 622          return VGPU10_MAX_FS_OUTPUTS;
 623       else if (shader == PIPE_SHADER_GEOMETRY)
 624          return VGPU10_MAX_GS_OUTPUTS;
 625       else
 626          return VGPU10_MAX_VS_OUTPUTS;
 627    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 628       return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
 629    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 630       return svgascreen->max_const_buffers;
 631    case PIPE_SHADER_CAP_MAX_TEMPS:
 632       return VGPU10_MAX_TEMPS;
 633    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 634    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 635    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 636    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 637       return TRUE; /* XXX verify */
 638    case PIPE_SHADER_CAP_MAX_PREDS:
 639       return 0;
 640    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 641    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 642    case PIPE_SHADER_CAP_SUBROUTINES:
 643    case PIPE_SHADER_CAP_INTEGERS:
 644       return TRUE;
 645    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 646    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 647       return SVGA3D_DX_MAX_SAMPLERS;
 648    case PIPE_SHADER_CAP_PREFERRED_IR:
 649       return PIPE_SHADER_IR_TGSI;
 650    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 651          return 0;
 652    case PIPE_SHADER_CAP_DOUBLES:
 653    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 654    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 655    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 656    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 657    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 658    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 659       return 0;
 660    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 661       return 32;
 662    default:
 663       debug_printf("Unexpected vgpu10 shader query %u\n", param);
 664       return 0;
 665    }
 666    return 0;
 667 }
 668
 669
 670 static int
 671 svga_get_shader_param(struct pipe_screen *screen, unsigned shader,
 672                       enum pipe_shader_cap param)
 673 {
 674    struct svga_screen *svgascreen = svga_screen(screen);
 675    struct svga_winsys_screen *sws = svgascreen->sws;
 676    if (sws->have_vgpu10) {
 677       return vgpu10_get_shader_param(screen, shader, param);
 678    }
 679    else {
 680       return vgpu9_get_shader_param(screen, shader, param);
 681    }
 682 }
 683
 684
 685 /**
 686  * Implement pipe_screen::is_format_supported().
 687  * \param bindings  bitmask of PIPE_BIND_x flags
 688  */
 689 static boolean
 690 svga_is_format_supported( struct pipe_screen *screen,
 691                           enum pipe_format format,
 692                           enum pipe_texture_target target,
 693                           unsigned sample_count,
 694                           unsigned bindings)
 695 {
 696    struct svga_screen *ss = svga_screen(screen);
 697    SVGA3dSurfaceFormat svga_format;
 698    SVGA3dSurfaceFormatCaps caps;
 699    SVGA3dSurfaceFormatCaps mask;
 700
 701    assert(bindings);
 702
 703    if (sample_count > 1) {
 704       /* In ms_samples, if bit N is set it means that we support
 705        * multisample with N+1 samples per pixel.
 706        */
 707       if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
 708          return FALSE;
 709       }
 710    }
 711
 712    svga_format = svga_translate_format(ss, format, bindings);
 713    if (svga_format == SVGA3D_FORMAT_INVALID) {
 714       return FALSE;
 715    }
 716
 717    /* we don't support sRGB rendering into display targets */
 718    if (util_format_is_srgb(format) && (bindings & PIPE_BIND_DISPLAY_TARGET)) {
 719       return FALSE;
 720    }
 721
 722    /*
 723     * For VGPU10 vertex formats, skip querying host capabilities
 724     */
 725
 726    if (ss->sws->have_vgpu10 && (bindings & PIPE_BIND_VERTEX_BUFFER)) {
 727       SVGA3dSurfaceFormat svga_format;
 728       unsigned flags;
 729       svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
 730       return svga_format != SVGA3D_FORMAT_INVALID;
 731    }
 732
 733    /*
 734     * Override host capabilities, so that we end up with the same
 735     * visuals for all virtual hardware implementations.
 736     */
 737
 738    if (bindings & PIPE_BIND_DISPLAY_TARGET) {
 739       switch (svga_format) {
 740       case SVGA3D_A8R8G8B8:
 741       case SVGA3D_X8R8G8B8:
 742       case SVGA3D_R5G6B5:
 743          break;
 744
 745       /* VGPU10 formats */
 746       case SVGA3D_B8G8R8A8_UNORM:
 747       case SVGA3D_B8G8R8X8_UNORM:
 748       case SVGA3D_B5G6R5_UNORM:
 749          break;
 750
 751       /* Often unsupported/problematic. This means we end up with the same
 752        * visuals for all virtual hardware implementations.
 753        */
 754       case SVGA3D_A4R4G4B4:
 755       case SVGA3D_A1R5G5B5:
 756          return FALSE;
 757
 758       default:
 759          return FALSE;
 760       }
 761    }
 762
 763    /*
 764     * Query the host capabilities.
 765     */
 766
 767    svga_get_format_cap(ss, svga_format, &caps);
 768
 769    if (bindings & PIPE_BIND_RENDER_TARGET) {
 770       /* Check that the color surface is blendable, unless it's an
 771        * integer format.
 772        */
 773       if (!svga_format_is_integer(svga_format) &&
 774           (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
 775          return FALSE;
 776       }
 777    }
 778
 779    mask.value = 0;
 780    if (bindings & PIPE_BIND_RENDER_TARGET) {
 781       mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
 782    }
 783    if (bindings & PIPE_BIND_DEPTH_STENCIL) {
 784       mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
 785    }
 786    if (bindings & PIPE_BIND_SAMPLER_VIEW) {
 787       mask.value |= SVGA3DFORMAT_OP_TEXTURE;
 788    }
 789
 790    if (target == PIPE_TEXTURE_CUBE) {
 791       mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
 792    }
 793    else if (target == PIPE_TEXTURE_3D) {
 794       mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
 795    }
 796
 797    return (caps.value & mask.value) == mask.value;
 798 }
 799
 800
 801 static void
 802 svga_fence_reference(struct pipe_screen *screen,
 803                      struct pipe_fence_handle **ptr,
 804                      struct pipe_fence_handle *fence)
 805 {
 806    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 807    sws->fence_reference(sws, ptr, fence);
 808 }
 809
 810
 811 static boolean
 812 svga_fence_finish(struct pipe_screen *screen,
 813                   struct pipe_context *ctx,
 814                   struct pipe_fence_handle *fence,
 815                   uint64_t timeout)
 816 {
 817    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 818    boolean retVal;
 819
 820    SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
 821
 822    if (!timeout) {
 823       retVal = sws->fence_signalled(sws, fence, 0) == 0;
 824    }
 825    else {
 826       SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
 827                __FUNCTION__, fence);
 828
 829       retVal = sws->fence_finish(sws, fence, 0) == 0;
 830    }
 831
 832    SVGA_STATS_TIME_POP(sws);
 833
 834    return retVal;
 835 }
 836
 837
 838 static int
 839 svga_get_driver_query_info(struct pipe_screen *screen,
 840                            unsigned index,
 841                            struct pipe_driver_query_info *info)
 842 {
 843 #define QUERY(NAME, ENUM, UNITS) \
 844    {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
 845
 846    static const struct pipe_driver_query_info queries[] = {
 847       /* per-frame counters */
 848       QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
 849             PIPE_DRIVER_QUERY_TYPE_UINT64),
 850       QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
 851             PIPE_DRIVER_QUERY_TYPE_UINT64),
 852       QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
 853             PIPE_DRIVER_QUERY_TYPE_UINT64),
 854       QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
 855             PIPE_DRIVER_QUERY_TYPE_UINT64),
 856       QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
 857             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 858       QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
 859             PIPE_DRIVER_QUERY_TYPE_UINT64),
 860       QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
 861             PIPE_DRIVER_QUERY_TYPE_UINT64),
 862       QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
 863             PIPE_DRIVER_QUERY_TYPE_BYTES),
 864       QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
 865             PIPE_DRIVER_QUERY_TYPE_BYTES),
 866       QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
 867             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 868       QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
 869             PIPE_DRIVER_QUERY_TYPE_UINT64),
 870       QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
 871             PIPE_DRIVER_QUERY_TYPE_UINT64),
 872       QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
 873             PIPE_DRIVER_QUERY_TYPE_UINT64),
 874       QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
 875             PIPE_DRIVER_QUERY_TYPE_UINT64),
 876       QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
 877             PIPE_DRIVER_QUERY_TYPE_UINT64),
 878       QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
 879             PIPE_DRIVER_QUERY_TYPE_UINT64),
 880
 881       /* running total counters */
 882       QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
 883             PIPE_DRIVER_QUERY_TYPE_BYTES),
 884       QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
 885             PIPE_DRIVER_QUERY_TYPE_UINT64),
 886       QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
 887             PIPE_DRIVER_QUERY_TYPE_UINT64),
 888       QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
 889             PIPE_DRIVER_QUERY_TYPE_UINT64),
 890       QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
 891             PIPE_DRIVER_QUERY_TYPE_UINT64),
 892       QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
 893             PIPE_DRIVER_QUERY_TYPE_UINT64),
 894    };
 895 #undef QUERY
 896
 897    if (!info)
 898       return ARRAY_SIZE(queries);
 899
 900    if (index >= ARRAY_SIZE(queries))
 901       return 0;
 902
 903    *info = queries[index];
 904    return 1;
 905 }
 906
 907
 908 static void
 909 svga_destroy_screen( struct pipe_screen *screen )
 910 {
 911    struct svga_screen *svgascreen = svga_screen(screen);
 912
 913    svga_screen_cache_cleanup(svgascreen);
 914
 915    pipe_mutex_destroy(svgascreen->swc_mutex);
 916    pipe_mutex_destroy(svgascreen->tex_mutex);
 917
 918    svgascreen->sws->destroy(svgascreen->sws);
 919
 920    FREE(svgascreen);
 921 }
 922
 923
 924 /**
 925  * Create a new svga_screen object
 926  */
 927 struct pipe_screen *
 928 svga_screen_create(struct svga_winsys_screen *sws)
 929 {
 930    struct svga_screen *svgascreen;
 931    struct pipe_screen *screen;
 932
 933 #ifdef DEBUG
 934    SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
 935 #endif
 936
 937    svgascreen = CALLOC_STRUCT(svga_screen);
 938    if (!svgascreen)
 939       goto error1;
 940
 941    svgascreen->debug.force_level_surface_view =
 942       debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
 943    svgascreen->debug.force_surface_view =
 944       debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
 945    svgascreen->debug.force_sampler_view =
 946       debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
 947    svgascreen->debug.no_surface_view =
 948       debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
 949    svgascreen->debug.no_sampler_view =
 950       debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
 951    svgascreen->debug.no_cache_index_buffers =
 952       debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
 953
 954    screen = &svgascreen->screen;
 955
 956    screen->destroy = svga_destroy_screen;
 957    screen->get_name = svga_get_name;
 958    screen->get_vendor = svga_get_vendor;
 959    screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
 960    screen->get_param = svga_get_param;
 961    screen->get_shader_param = svga_get_shader_param;
 962    screen->get_paramf = svga_get_paramf;
 963    screen->get_timestamp = NULL;
 964    screen->is_format_supported = svga_is_format_supported;
 965    screen->context_create = svga_context_create;
 966    screen->fence_reference = svga_fence_reference;
 967    screen->fence_finish = svga_fence_finish;
 968    screen->get_driver_query_info = svga_get_driver_query_info;
 969    svgascreen->sws = sws;
 970
 971    svga_init_screen_resource_functions(svgascreen);
 972
 973    if (sws->get_hw_version) {
 974       svgascreen->hw_version = sws->get_hw_version(sws);
 975    } else {
 976       svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
 977    }
 978
 979    /*
 980     * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
 981     * when sampled from, where as the DF16, DF24, and D24S8_INT do not.  So
 982     * we prefer the later when available.
 983     *
 984     * This mimics hardware vendors extensions for D3D depth sampling. See also
 985     * http://aras-p.info/texts/D3D9GPUHacks.html
 986     */
 987
 988    {
 989       boolean has_df16, has_df24, has_d24s8_int;
 990       SVGA3dSurfaceFormatCaps caps;
 991       SVGA3dSurfaceFormatCaps mask;
 992       mask.value = 0;
 993       mask.zStencil = 1;
 994       mask.texture = 1;
 995
 996       svgascreen->depth.z16 = SVGA3D_Z_D16;
 997       svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
 998       svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
 999
1000       svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
1001       has_df16 = (caps.value & mask.value) == mask.value;
1002
1003       svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
1004       has_df24 = (caps.value & mask.value) == mask.value;
1005
1006       svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
1007       has_d24s8_int = (caps.value & mask.value) == mask.value;
1008
1009       /* XXX: We might want some other logic here.
1010        * Like if we only have d24s8_int we should
1011        * emulate the other formats with that.
1012        */
1013       if (has_df16) {
1014          svgascreen->depth.z16 = SVGA3D_Z_DF16;
1015       }
1016       if (has_df24) {
1017          svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1018       }
1019       if (has_d24s8_int) {
1020          svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1021       }
1022    }
1023
1024    /* Query device caps
1025     */
1026    if (sws->have_vgpu10) {
1027       svgascreen->haveProvokingVertex
1028          = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1029       svgascreen->haveLineSmooth = TRUE;
1030       svgascreen->maxPointSize = 80.0F;
1031       svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1032
1033       /* Multisample samples per pixel */
1034       if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
1035          svgascreen->ms_samples =
1036             get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
1037       }
1038
1039       /* Maximum number of constant buffers */
1040       svgascreen->max_const_buffers =
1041          get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1042       assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1043    }
1044    else {
1045       /* VGPU9 */
1046       unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1047                                      SVGA3DVSVERSION_NONE);
1048       unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1049                                      SVGA3DPSVERSION_NONE);
1050
1051       /* we require Shader model 3.0 or later */
1052       if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1053          goto error2;
1054       }
1055
1056       svgascreen->haveProvokingVertex = FALSE;
1057
1058       svgascreen->haveLineSmooth =
1059          get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1060
1061       svgascreen->maxPointSize =
1062          get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1063       /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1064       svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1065
1066       /* The SVGA3D device always supports 4 targets at this time, regardless
1067        * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1068        */
1069       svgascreen->max_color_buffers = 4;
1070
1071       /* Only support one constant buffer
1072        */
1073       svgascreen->max_const_buffers = 1;
1074
1075       /* No multisampling */
1076       svgascreen->ms_samples = 0;
1077    }
1078
1079    /* common VGPU9 / VGPU10 caps */
1080    svgascreen->haveLineStipple =
1081       get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1082
1083    svgascreen->maxLineWidth =
1084       get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f);
1085
1086    svgascreen->maxLineWidthAA =
1087       get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f);
1088
1089    if (0) {
1090       debug_printf("svga: haveProvokingVertex %u\n",
1091                    svgascreen->haveProvokingVertex);
1092       debug_printf("svga: haveLineStip %u  "
1093                    "haveLineSmooth %u  maxLineWidth %f\n",
1094                    svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1095                    svgascreen->maxLineWidth);
1096       debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1097       debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1098    }
1099
1100    pipe_mutex_init(svgascreen->tex_mutex);
1101    pipe_mutex_init(svgascreen->swc_mutex);
1102
1103    svga_screen_cache_init(svgascreen);
1104
1105    return screen;
1106 error2:
1107    FREE(svgascreen);
1108 error1:
1109    return NULL;
1110 }
1111
1112 struct svga_winsys_screen *
1113 svga_winsys_screen(struct pipe_screen *screen)
1114 {
1115    return svga_screen(screen)->sws;
1116 }
1117
1118 #ifdef DEBUG
1119 struct svga_screen *
1120 svga_screen(struct pipe_screen *screen)
1121 {
1122    assert(screen);
1123    assert(screen->destroy == svga_destroy_screen);
1124    return (struct svga_screen *)screen;
1125 }
1126 #endif