src/gallium/drivers/svga/svga_screen.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "util/u_format.h"
  27 #include "util/u_memory.h"
  28 #include "util/u_inlines.h"
  29 #include "util/u_string.h"
  30 #include "util/u_math.h"
  31
  32 #include "svga_winsys.h"
  33 #include "svga_public.h"
  34 #include "svga_context.h"
  35 #include "svga_format.h"
  36 #include "svga_screen.h"
  37 #include "svga_tgsi.h"
  38 #include "svga_resource_texture.h"
  39 #include "svga_resource.h"
  40 #include "svga_debug.h"
  41
  42 #include "svga3d_shaderdefs.h"
  43 #include "VGPU10ShaderTokens.h"
  44
  45 /* NOTE: this constant may get moved into a svga3d*.h header file */
  46 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
  47
  48 #ifdef DEBUG
  49 int SVGA_DEBUG = 0;
  50
  51 static const struct debug_named_value svga_debug_flags[] = {
  52    { "dma",         DEBUG_DMA, NULL },
  53    { "tgsi",        DEBUG_TGSI, NULL },
  54    { "pipe",        DEBUG_PIPE, NULL },
  55    { "state",       DEBUG_STATE, NULL },
  56    { "screen",      DEBUG_SCREEN, NULL },
  57    { "tex",         DEBUG_TEX, NULL },
  58    { "swtnl",       DEBUG_SWTNL, NULL },
  59    { "const",       DEBUG_CONSTS, NULL },
  60    { "viewport",    DEBUG_VIEWPORT, NULL },
  61    { "views",       DEBUG_VIEWS, NULL },
  62    { "perf",        DEBUG_PERF, NULL },
  63    { "flush",       DEBUG_FLUSH, NULL },
  64    { "sync",        DEBUG_SYNC, NULL },
  65    { "cache",       DEBUG_CACHE, NULL },
  66    { "streamout",   DEBUG_STREAMOUT, NULL },
  67    { "query",       DEBUG_QUERY, NULL },
  68    DEBUG_NAMED_VALUE_END
  69 };
  70 #endif
  71
  72 static const char *
  73 svga_get_vendor( struct pipe_screen *pscreen )
  74 {
  75    return "VMware, Inc.";
  76 }
  77
  78
  79 static const char *
  80 svga_get_name( struct pipe_screen *pscreen )
  81 {
  82    const char *build = "", *llvm = "", *mutex = "";
  83    static char name[100];
  84 #ifdef DEBUG
  85    /* Only return internal details in the DEBUG version:
  86     */
  87    build = "build: DEBUG;";
  88    mutex = "mutex: " PIPE_ATOMIC ";";
  89 #elif defined(VMX86_STATS)
  90    build = "build: OPT;";
  91 #else
  92    build = "build: RELEASE;";
  93 #endif
  94 #ifdef HAVE_LLVM
  95    llvm = "LLVM;";
  96 #endif
  97
  98    util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
  99    return name;
 100 }
 101
 102
 103 /** Helper for querying float-valued device cap */
 104 static float
 105 get_float_cap(struct svga_winsys_screen *sws, unsigned cap, float defaultVal)
 106 {
 107    SVGA3dDevCapResult result;
 108    if (sws->get_cap(sws, cap, &result))
 109       return result.f;
 110    else
 111       return defaultVal;
 112 }
 113
 114
 115 /** Helper for querying uint-valued device cap */
 116 static unsigned
 117 get_uint_cap(struct svga_winsys_screen *sws, unsigned cap, unsigned defaultVal)
 118 {
 119    SVGA3dDevCapResult result;
 120    if (sws->get_cap(sws, cap, &result))
 121       return result.u;
 122    else
 123       return defaultVal;
 124 }
 125
 126
 127 /** Helper for querying boolean-valued device cap */
 128 static boolean
 129 get_bool_cap(struct svga_winsys_screen *sws, unsigned cap, boolean defaultVal)
 130 {
 131    SVGA3dDevCapResult result;
 132    if (sws->get_cap(sws, cap, &result))
 133       return result.b;
 134    else
 135       return defaultVal;
 136 }
 137
 138
 139 static float
 140 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 141 {
 142    struct svga_screen *svgascreen = svga_screen(screen);
 143    struct svga_winsys_screen *sws = svgascreen->sws;
 144
 145    switch (param) {
 146    case PIPE_CAPF_MAX_LINE_WIDTH:
 147       return svgascreen->maxLineWidth;
 148    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 149       return svgascreen->maxLineWidthAA;
 150
 151    case PIPE_CAPF_MAX_POINT_WIDTH:
 152       /* fall-through */
 153    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 154       return svgascreen->maxPointSize;
 155
 156    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 157       return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
 158
 159    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 160       return 15.0;
 161
 162    case PIPE_CAPF_GUARD_BAND_LEFT:
 163    case PIPE_CAPF_GUARD_BAND_TOP:
 164    case PIPE_CAPF_GUARD_BAND_RIGHT:
 165    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 166       return 0.0;
 167    }
 168
 169    debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
 170    return 0;
 171 }
 172
 173
 174 static int
 175 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
 176 {
 177    struct svga_screen *svgascreen = svga_screen(screen);
 178    struct svga_winsys_screen *sws = svgascreen->sws;
 179    SVGA3dDevCapResult result;
 180
 181    switch (param) {
 182    case PIPE_CAP_NPOT_TEXTURES:
 183    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 184    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 185       return 1;
 186    case PIPE_CAP_TWO_SIDED_STENCIL:
 187       return 1;
 188    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 189       /*
 190        * "In virtually every OpenGL implementation and hardware,
 191        * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
 192        * http://www.opengl.org/wiki/Blending
 193        */
 194       return sws->have_vgpu10 ? 1 : 0;
 195    case PIPE_CAP_ANISOTROPIC_FILTER:
 196       return 1;
 197    case PIPE_CAP_POINT_SPRITE:
 198       return 1;
 199    case PIPE_CAP_TGSI_TEXCOORD:
 200       return 0;
 201    case PIPE_CAP_MAX_RENDER_TARGETS:
 202       return svgascreen->max_color_buffers;
 203    case PIPE_CAP_OCCLUSION_QUERY:
 204       return 1;
 205    case PIPE_CAP_QUERY_TIME_ELAPSED:
 206       return 0;
 207    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 208       return sws->have_vgpu10;
 209    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 210       return 1;
 211    case PIPE_CAP_TEXTURE_SWIZZLE:
 212       return 1;
 213    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 214       return 0;
 215    case PIPE_CAP_USER_VERTEX_BUFFERS:
 216    case PIPE_CAP_USER_INDEX_BUFFERS:
 217       return 0;
 218    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 219       return 1;
 220    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 221       return 256;
 222
 223    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 224       {
 225          unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
 226          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
 227             levels = MIN2(util_logbase2(result.u) + 1, levels);
 228          else
 229             levels = 12 /* 2048x2048 */;
 230          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
 231             levels = MIN2(util_logbase2(result.u) + 1, levels);
 232          else
 233             levels = 12 /* 2048x2048 */;
 234          return levels;
 235       }
 236
 237    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 238       if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
 239          return 8;  /* max 128x128x128 */
 240       return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
 241
 242    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 243       /*
 244        * No mechanism to query the host, and at least limited to 2048x2048 on
 245        * certain hardware.
 246        */
 247       return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
 248                   12 /* 2048x2048 */);
 249
 250    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 251       return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
 252
 253    case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
 254       return 1;
 255
 256    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 257       return 1;
 258    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 259       return sws->have_vgpu10;
 260    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 261       return 0;
 262    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 263       return !sws->have_vgpu10;
 264
 265    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 266       return 1; /* The color outputs of vertex shaders are not clamped */
 267    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 268       return 0; /* The driver can't clamp vertex colors */
 269    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 270       return 0; /* The driver can't clamp fragment colors */
 271
 272    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 273       return 1; /* expected for GL_ARB_framebuffer_object */
 274
 275    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 276       return sws->have_vgpu10 ? 330 : 120;
 277
 278    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 279       return 0;
 280
 281    case PIPE_CAP_SM3:
 282       return 1;
 283
 284    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 285    case PIPE_CAP_INDEP_BLEND_ENABLE:
 286    case PIPE_CAP_CONDITIONAL_RENDER:
 287    case PIPE_CAP_QUERY_TIMESTAMP:
 288    case PIPE_CAP_TGSI_INSTANCEID:
 289    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 290    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 291    case PIPE_CAP_FAKE_SW_MSAA:
 292       return sws->have_vgpu10;
 293
 294    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 295       return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
 296    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 297       return sws->have_vgpu10 ? 4 : 0;
 298    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 299       return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
 300    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 301       return 0;
 302    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 303       return svgascreen->ms_samples ? 1 : 0;
 304
 305    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 306       return SVGA3D_DX_MAX_RESOURCE_SIZE;
 307
 308    case PIPE_CAP_MIN_TEXEL_OFFSET:
 309       return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
 310    case PIPE_CAP_MAX_TEXEL_OFFSET:
 311       return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
 312
 313    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 314    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 315       return 0;
 316
 317    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 318       return sws->have_vgpu10 ? 256 : 0;
 319    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 320       return sws->have_vgpu10 ? 1024 : 0;
 321
 322    case PIPE_CAP_PRIMITIVE_RESTART:
 323       return 1; /* may be a sw fallback, depending on restart index */
 324
 325    case PIPE_CAP_GENERATE_MIPMAP:
 326       return sws->have_generate_mipmap_cmd;
 327
 328    /* Unsupported features */
 329    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 330    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 331    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 332    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 333    case PIPE_CAP_INDEP_BLEND_FUNC:
 334    case PIPE_CAP_TEXTURE_BARRIER:
 335    case PIPE_CAP_MAX_VERTEX_STREAMS:
 336    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 337    case PIPE_CAP_COMPUTE:
 338    case PIPE_CAP_START_INSTANCE:
 339    case PIPE_CAP_CUBE_MAP_ARRAY:
 340    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 341    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 342    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 343    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 344    case PIPE_CAP_TEXTURE_GATHER_SM5:
 345    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 346    case PIPE_CAP_TEXTURE_QUERY_LOD:
 347    case PIPE_CAP_SAMPLE_SHADING:
 348    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 349    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 350    case PIPE_CAP_DRAW_INDIRECT:
 351    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 352    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 353    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 354    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 355    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 356    case PIPE_CAP_CLIP_HALFZ:
 357    case PIPE_CAP_VERTEXID_NOBASE:
 358    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 359    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 360    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 361    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 362    case PIPE_CAP_INVALIDATE_BUFFER:
 363    case PIPE_CAP_STRING_MARKER:
 364    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 365    case PIPE_CAP_QUERY_MEMORY_INFO:
 366    case PIPE_CAP_PCI_GROUP:
 367    case PIPE_CAP_PCI_BUS:
 368    case PIPE_CAP_PCI_DEVICE:
 369    case PIPE_CAP_PCI_FUNCTION:
 370    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 371       return 0;
 372    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 373       return 64;
 374    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 375    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 376    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 377       return 1;  /* need 4-byte alignment for all offsets and strides */
 378    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 379       return 2048;
 380    case PIPE_CAP_MAX_VIEWPORTS:
 381       return 1;
 382    case PIPE_CAP_ENDIANNESS:
 383       return PIPE_ENDIAN_LITTLE;
 384
 385    case PIPE_CAP_VENDOR_ID:
 386       return 0x15ad; /* VMware Inc. */
 387    case PIPE_CAP_DEVICE_ID:
 388       return 0x0405; /* assume SVGA II */
 389    case PIPE_CAP_ACCELERATED:
 390       return 0; /* XXX: */
 391    case PIPE_CAP_VIDEO_MEMORY:
 392       /* XXX: Query the host ? */
 393       return 1;
 394    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 395       return sws->have_vgpu10;
 396    case PIPE_CAP_CLEAR_TEXTURE:
 397       return sws->have_vgpu10;
 398    case PIPE_CAP_UMA:
 399    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 400    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 401    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 402    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 403    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 404    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 405    case PIPE_CAP_TGSI_TXQS:
 406    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 407    case PIPE_CAP_SHAREABLE_SHADERS:
 408    case PIPE_CAP_DRAW_PARAMETERS:
 409    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 410    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 411    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 412    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 413    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 414    case PIPE_CAP_CULL_DISTANCE:
 415    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 416    case PIPE_CAP_TGSI_VOTE:
 417    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 418    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 419    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 420       return 0;
 421    }
 422
 423    debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
 424    return 0;
 425 }
 426
 427
 428 static int
 429 vgpu9_get_shader_param(struct pipe_screen *screen, unsigned shader,
 430                        enum pipe_shader_cap param)
 431 {
 432    struct svga_screen *svgascreen = svga_screen(screen);
 433    struct svga_winsys_screen *sws = svgascreen->sws;
 434    unsigned val;
 435
 436    assert(!sws->have_vgpu10);
 437
 438    switch (shader)
 439    {
 440    case PIPE_SHADER_FRAGMENT:
 441       switch (param)
 442       {
 443       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 444       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 445          return get_uint_cap(sws,
 446                              SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
 447                              512);
 448       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 449       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 450          return 512;
 451       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 452          return SVGA3D_MAX_NESTING_LEVEL;
 453       case PIPE_SHADER_CAP_MAX_INPUTS:
 454          return 10;
 455       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 456          return svgascreen->max_color_buffers;
 457       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 458          return 224 * sizeof(float[4]);
 459       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 460          return 1;
 461       case PIPE_SHADER_CAP_MAX_TEMPS:
 462          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
 463          return MIN2(val, SVGA3D_TEMPREG_MAX);
 464       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 465          /*
 466           * Although PS 3.0 has some addressing abilities it can only represent
 467           * loops that can be statically determined and unrolled. Given we can
 468           * only handle a subset of the cases that the state tracker already
 469           * does it is better to defer loop unrolling to the state tracker.
 470           */
 471          return 0;
 472       case PIPE_SHADER_CAP_MAX_PREDS:
 473          return 1;
 474       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 475          return 0;
 476       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 477          return 0;
 478       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 479       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 480       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 481          return 0;
 482       case PIPE_SHADER_CAP_SUBROUTINES:
 483          return 0;
 484       case PIPE_SHADER_CAP_INTEGERS:
 485          return 0;
 486       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 487       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 488          return 16;
 489       case PIPE_SHADER_CAP_PREFERRED_IR:
 490          return PIPE_SHADER_IR_TGSI;
 491       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 492          return 0;
 493       case PIPE_SHADER_CAP_DOUBLES:
 494       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 495       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 496       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 497       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 498       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 499       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 500          return 0;
 501       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 502          return 32;
 503       }
 504       /* If we get here, we failed to handle a cap above */
 505       debug_printf("Unexpected fragment shader query %u\n", param);
 506       return 0;
 507    case PIPE_SHADER_VERTEX:
 508       switch (param)
 509       {
 510       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 511       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 512          return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
 513                              512);
 514       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 515       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 516          /* XXX: until we have vertex texture support */
 517          return 0;
 518       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 519          return SVGA3D_MAX_NESTING_LEVEL;
 520       case PIPE_SHADER_CAP_MAX_INPUTS:
 521          return 16;
 522       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 523          return 10;
 524       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 525          return 256 * sizeof(float[4]);
 526       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 527          return 1;
 528       case PIPE_SHADER_CAP_MAX_TEMPS:
 529          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
 530          return MIN2(val, SVGA3D_TEMPREG_MAX);
 531       case PIPE_SHADER_CAP_MAX_PREDS:
 532          return 1;
 533       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 534          return 0;
 535       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 536          return 0;
 537       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 538       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 539          return 1;
 540       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 541          return 0;
 542       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 543          return 1;
 544       case PIPE_SHADER_CAP_SUBROUTINES:
 545          return 0;
 546       case PIPE_SHADER_CAP_INTEGERS:
 547          return 0;
 548       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 549       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 550          return 0;
 551       case PIPE_SHADER_CAP_PREFERRED_IR:
 552          return PIPE_SHADER_IR_TGSI;
 553       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 554          return 0;
 555       case PIPE_SHADER_CAP_DOUBLES:
 556       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 557       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 558       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 559       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 560       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 561       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 562          return 0;
 563       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 564          return 32;
 565       }
 566       /* If we get here, we failed to handle a cap above */
 567       debug_printf("Unexpected vertex shader query %u\n", param);
 568       return 0;
 569    case PIPE_SHADER_GEOMETRY:
 570    case PIPE_SHADER_COMPUTE:
 571    case PIPE_SHADER_TESS_CTRL:
 572    case PIPE_SHADER_TESS_EVAL:
 573       /* no support for geometry, tess or compute shaders at this time */
 574       return 0;
 575    default:
 576       debug_printf("Unexpected shader type (%u) query\n", shader);
 577       return 0;
 578    }
 579    return 0;
 580 }
 581
 582
 583 static int
 584 vgpu10_get_shader_param(struct pipe_screen *screen, unsigned shader,
 585                         enum pipe_shader_cap param)
 586 {
 587    struct svga_screen *svgascreen = svga_screen(screen);
 588    struct svga_winsys_screen *sws = svgascreen->sws;
 589
 590    assert(sws->have_vgpu10);
 591    (void) sws;  /* silence unused var warnings in non-debug builds */
 592
 593    /* Only VS, GS, FS supported */
 594    if (shader != PIPE_SHADER_VERTEX &&
 595        shader != PIPE_SHADER_GEOMETRY &&
 596        shader != PIPE_SHADER_FRAGMENT) {
 597       return 0;
 598    }
 599
 600    /* NOTE: we do not query the device for any caps/limits at this time */
 601
 602    /* Generally the same limits for vertex, geometry and fragment shaders */
 603    switch (param) {
 604    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 605    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 606    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 607    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 608       return 64 * 1024;
 609    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 610       return 64;
 611    case PIPE_SHADER_CAP_MAX_INPUTS:
 612       if (shader == PIPE_SHADER_FRAGMENT)
 613          return VGPU10_MAX_FS_INPUTS;
 614       else if (shader == PIPE_SHADER_GEOMETRY)
 615          return VGPU10_MAX_GS_INPUTS;
 616       else
 617          return VGPU10_MAX_VS_INPUTS;
 618    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 619       if (shader == PIPE_SHADER_FRAGMENT)
 620          return VGPU10_MAX_FS_OUTPUTS;
 621       else if (shader == PIPE_SHADER_GEOMETRY)
 622          return VGPU10_MAX_GS_OUTPUTS;
 623       else
 624          return VGPU10_MAX_VS_OUTPUTS;
 625    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 626       return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
 627    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 628       return svgascreen->max_const_buffers;
 629    case PIPE_SHADER_CAP_MAX_TEMPS:
 630       return VGPU10_MAX_TEMPS;
 631    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 632    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 633    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 634    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 635       return TRUE; /* XXX verify */
 636    case PIPE_SHADER_CAP_MAX_PREDS:
 637       return 0;
 638    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 639    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 640    case PIPE_SHADER_CAP_SUBROUTINES:
 641    case PIPE_SHADER_CAP_INTEGERS:
 642       return TRUE;
 643    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 644    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 645       return SVGA3D_DX_MAX_SAMPLERS;
 646    case PIPE_SHADER_CAP_PREFERRED_IR:
 647       return PIPE_SHADER_IR_TGSI;
 648    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 649          return 0;
 650    case PIPE_SHADER_CAP_DOUBLES:
 651    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 652    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 653    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 654    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 655    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 656    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 657       return 0;
 658    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 659       return 32;
 660    default:
 661       debug_printf("Unexpected vgpu10 shader query %u\n", param);
 662       return 0;
 663    }
 664    return 0;
 665 }
 666
 667
 668 static int
 669 svga_get_shader_param(struct pipe_screen *screen, unsigned shader,
 670                       enum pipe_shader_cap param)
 671 {
 672    struct svga_screen *svgascreen = svga_screen(screen);
 673    struct svga_winsys_screen *sws = svgascreen->sws;
 674    if (sws->have_vgpu10) {
 675       return vgpu10_get_shader_param(screen, shader, param);
 676    }
 677    else {
 678       return vgpu9_get_shader_param(screen, shader, param);
 679    }
 680 }
 681
 682
 683 /**
 684  * Implement pipe_screen::is_format_supported().
 685  * \param bindings  bitmask of PIPE_BIND_x flags
 686  */
 687 static boolean
 688 svga_is_format_supported( struct pipe_screen *screen,
 689                           enum pipe_format format,
 690                           enum pipe_texture_target target,
 691                           unsigned sample_count,
 692                           unsigned bindings)
 693 {
 694    struct svga_screen *ss = svga_screen(screen);
 695    SVGA3dSurfaceFormat svga_format;
 696    SVGA3dSurfaceFormatCaps caps;
 697    SVGA3dSurfaceFormatCaps mask;
 698
 699    assert(bindings);
 700
 701    if (sample_count > 1) {
 702       /* In ms_samples, if bit N is set it means that we support
 703        * multisample with N+1 samples per pixel.
 704        */
 705       if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
 706          return FALSE;
 707       }
 708    }
 709
 710    svga_format = svga_translate_format(ss, format, bindings);
 711    if (svga_format == SVGA3D_FORMAT_INVALID) {
 712       return FALSE;
 713    }
 714
 715    /* we don't support sRGB rendering into display targets */
 716    if (util_format_is_srgb(format) && (bindings & PIPE_BIND_DISPLAY_TARGET)) {
 717       return FALSE;
 718    }
 719
 720    /*
 721     * For VGPU10 vertex formats, skip querying host capabilities
 722     */
 723
 724    if (ss->sws->have_vgpu10 && (bindings & PIPE_BIND_VERTEX_BUFFER)) {
 725       SVGA3dSurfaceFormat svga_format;
 726       unsigned flags;
 727       svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
 728       return svga_format != SVGA3D_FORMAT_INVALID;
 729    }
 730
 731    /*
 732     * Override host capabilities, so that we end up with the same
 733     * visuals for all virtual hardware implementations.
 734     */
 735
 736    if (bindings & PIPE_BIND_DISPLAY_TARGET) {
 737       switch (svga_format) {
 738       case SVGA3D_A8R8G8B8:
 739       case SVGA3D_X8R8G8B8:
 740       case SVGA3D_R5G6B5:
 741          break;
 742
 743       /* VGPU10 formats */
 744       case SVGA3D_B8G8R8A8_UNORM:
 745       case SVGA3D_B8G8R8X8_UNORM:
 746       case SVGA3D_B5G6R5_UNORM:
 747          break;
 748
 749       /* Often unsupported/problematic. This means we end up with the same
 750        * visuals for all virtual hardware implementations.
 751        */
 752       case SVGA3D_A4R4G4B4:
 753       case SVGA3D_A1R5G5B5:
 754          return FALSE;
 755
 756       default:
 757          return FALSE;
 758       }
 759    }
 760
 761    /*
 762     * Query the host capabilities.
 763     */
 764
 765    svga_get_format_cap(ss, svga_format, &caps);
 766
 767    if (bindings & PIPE_BIND_RENDER_TARGET) {
 768       /* Check that the color surface is blendable, unless it's an
 769        * integer format.
 770        */
 771       if (!svga_format_is_integer(svga_format) &&
 772           (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
 773          return FALSE;
 774       }
 775    }
 776
 777    mask.value = 0;
 778    if (bindings & PIPE_BIND_RENDER_TARGET) {
 779       mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
 780    }
 781    if (bindings & PIPE_BIND_DEPTH_STENCIL) {
 782       mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
 783    }
 784    if (bindings & PIPE_BIND_SAMPLER_VIEW) {
 785       mask.value |= SVGA3DFORMAT_OP_TEXTURE;
 786    }
 787
 788    if (target == PIPE_TEXTURE_CUBE) {
 789       mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
 790    }
 791    else if (target == PIPE_TEXTURE_3D) {
 792       mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
 793    }
 794
 795    return (caps.value & mask.value) == mask.value;
 796 }
 797
 798
 799 static void
 800 svga_fence_reference(struct pipe_screen *screen,
 801                      struct pipe_fence_handle **ptr,
 802                      struct pipe_fence_handle *fence)
 803 {
 804    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 805    sws->fence_reference(sws, ptr, fence);
 806 }
 807
 808
 809 static boolean
 810 svga_fence_finish(struct pipe_screen *screen,
 811                   struct pipe_context *ctx,
 812                   struct pipe_fence_handle *fence,
 813                   uint64_t timeout)
 814 {
 815    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 816    boolean retVal;
 817
 818    SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
 819
 820    if (!timeout) {
 821       retVal = sws->fence_signalled(sws, fence, 0) == 0;
 822    }
 823    else {
 824       SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
 825                __FUNCTION__, fence);
 826
 827       retVal = sws->fence_finish(sws, fence, 0) == 0;
 828    }
 829
 830    SVGA_STATS_TIME_POP(sws);
 831
 832    return retVal;
 833 }
 834
 835
 836 static int
 837 svga_get_driver_query_info(struct pipe_screen *screen,
 838                            unsigned index,
 839                            struct pipe_driver_query_info *info)
 840 {
 841 #define QUERY(NAME, ENUM, UNITS) \
 842    {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
 843
 844    static const struct pipe_driver_query_info queries[] = {
 845       /* per-frame counters */
 846       QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
 847             PIPE_DRIVER_QUERY_TYPE_UINT64),
 848       QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
 849             PIPE_DRIVER_QUERY_TYPE_UINT64),
 850       QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
 851             PIPE_DRIVER_QUERY_TYPE_UINT64),
 852       QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
 853             PIPE_DRIVER_QUERY_TYPE_UINT64),
 854       QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
 855             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 856       QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
 857             PIPE_DRIVER_QUERY_TYPE_UINT64),
 858       QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
 859             PIPE_DRIVER_QUERY_TYPE_UINT64),
 860       QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
 861             PIPE_DRIVER_QUERY_TYPE_BYTES),
 862       QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
 863             PIPE_DRIVER_QUERY_TYPE_BYTES),
 864       QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
 865             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 866       QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
 867             PIPE_DRIVER_QUERY_TYPE_UINT64),
 868       QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
 869             PIPE_DRIVER_QUERY_TYPE_UINT64),
 870       QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
 871             PIPE_DRIVER_QUERY_TYPE_UINT64),
 872       QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
 873             PIPE_DRIVER_QUERY_TYPE_UINT64),
 874       QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
 875             PIPE_DRIVER_QUERY_TYPE_UINT64),
 876       QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
 877             PIPE_DRIVER_QUERY_TYPE_UINT64),
 878
 879       /* running total counters */
 880       QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
 881             PIPE_DRIVER_QUERY_TYPE_BYTES),
 882       QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
 883             PIPE_DRIVER_QUERY_TYPE_UINT64),
 884       QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
 885             PIPE_DRIVER_QUERY_TYPE_UINT64),
 886       QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
 887             PIPE_DRIVER_QUERY_TYPE_UINT64),
 888       QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
 889             PIPE_DRIVER_QUERY_TYPE_UINT64),
 890       QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
 891             PIPE_DRIVER_QUERY_TYPE_UINT64),
 892    };
 893 #undef QUERY
 894
 895    if (!info)
 896       return ARRAY_SIZE(queries);
 897
 898    if (index >= ARRAY_SIZE(queries))
 899       return 0;
 900
 901    *info = queries[index];
 902    return 1;
 903 }
 904
 905
 906 static void
 907 svga_destroy_screen( struct pipe_screen *screen )
 908 {
 909    struct svga_screen *svgascreen = svga_screen(screen);
 910
 911    svga_screen_cache_cleanup(svgascreen);
 912
 913    pipe_mutex_destroy(svgascreen->swc_mutex);
 914    pipe_mutex_destroy(svgascreen->tex_mutex);
 915
 916    svgascreen->sws->destroy(svgascreen->sws);
 917
 918    FREE(svgascreen);
 919 }
 920
 921
 922 /**
 923  * Create a new svga_screen object
 924  */
 925 struct pipe_screen *
 926 svga_screen_create(struct svga_winsys_screen *sws)
 927 {
 928    struct svga_screen *svgascreen;
 929    struct pipe_screen *screen;
 930
 931 #ifdef DEBUG
 932    SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
 933 #endif
 934
 935    svgascreen = CALLOC_STRUCT(svga_screen);
 936    if (!svgascreen)
 937       goto error1;
 938
 939    svgascreen->debug.force_level_surface_view =
 940       debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
 941    svgascreen->debug.force_surface_view =
 942       debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
 943    svgascreen->debug.force_sampler_view =
 944       debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
 945    svgascreen->debug.no_surface_view =
 946       debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
 947    svgascreen->debug.no_sampler_view =
 948       debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
 949    svgascreen->debug.no_cache_index_buffers =
 950       debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
 951
 952    screen = &svgascreen->screen;
 953
 954    screen->destroy = svga_destroy_screen;
 955    screen->get_name = svga_get_name;
 956    screen->get_vendor = svga_get_vendor;
 957    screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
 958    screen->get_param = svga_get_param;
 959    screen->get_shader_param = svga_get_shader_param;
 960    screen->get_paramf = svga_get_paramf;
 961    screen->get_timestamp = NULL;
 962    screen->is_format_supported = svga_is_format_supported;
 963    screen->context_create = svga_context_create;
 964    screen->fence_reference = svga_fence_reference;
 965    screen->fence_finish = svga_fence_finish;
 966    screen->get_driver_query_info = svga_get_driver_query_info;
 967    svgascreen->sws = sws;
 968
 969    svga_init_screen_resource_functions(svgascreen);
 970
 971    if (sws->get_hw_version) {
 972       svgascreen->hw_version = sws->get_hw_version(sws);
 973    } else {
 974       svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
 975    }
 976
 977    /*
 978     * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
 979     * when sampled from, where as the DF16, DF24, and D24S8_INT do not.  So
 980     * we prefer the later when available.
 981     *
 982     * This mimics hardware vendors extensions for D3D depth sampling. See also
 983     * http://aras-p.info/texts/D3D9GPUHacks.html
 984     */
 985
 986    {
 987       boolean has_df16, has_df24, has_d24s8_int;
 988       SVGA3dSurfaceFormatCaps caps;
 989       SVGA3dSurfaceFormatCaps mask;
 990       mask.value = 0;
 991       mask.zStencil = 1;
 992       mask.texture = 1;
 993
 994       svgascreen->depth.z16 = SVGA3D_Z_D16;
 995       svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
 996       svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
 997
 998       svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
 999       has_df16 = (caps.value & mask.value) == mask.value;
1000
1001       svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
1002       has_df24 = (caps.value & mask.value) == mask.value;
1003
1004       svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
1005       has_d24s8_int = (caps.value & mask.value) == mask.value;
1006
1007       /* XXX: We might want some other logic here.
1008        * Like if we only have d24s8_int we should
1009        * emulate the other formats with that.
1010        */
1011       if (has_df16) {
1012          svgascreen->depth.z16 = SVGA3D_Z_DF16;
1013       }
1014       if (has_df24) {
1015          svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1016       }
1017       if (has_d24s8_int) {
1018          svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1019       }
1020    }
1021
1022    /* Query device caps
1023     */
1024    if (sws->have_vgpu10) {
1025       svgascreen->haveProvokingVertex
1026          = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1027       svgascreen->haveLineSmooth = TRUE;
1028       svgascreen->maxPointSize = 80.0F;
1029       svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1030
1031       /* Multisample samples per pixel */
1032       if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
1033          svgascreen->ms_samples =
1034             get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
1035       }
1036
1037       /* Maximum number of constant buffers */
1038       svgascreen->max_const_buffers =
1039          get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1040       assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1041    }
1042    else {
1043       /* VGPU9 */
1044       unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1045                                      SVGA3DVSVERSION_NONE);
1046       unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1047                                      SVGA3DPSVERSION_NONE);
1048
1049       /* we require Shader model 3.0 or later */
1050       if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1051          goto error2;
1052       }
1053
1054       svgascreen->haveProvokingVertex = FALSE;
1055
1056       svgascreen->haveLineSmooth =
1057          get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1058
1059       svgascreen->maxPointSize =
1060          get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1061       /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1062       svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1063
1064       /* The SVGA3D device always supports 4 targets at this time, regardless
1065        * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1066        */
1067       svgascreen->max_color_buffers = 4;
1068
1069       /* Only support one constant buffer
1070        */
1071       svgascreen->max_const_buffers = 1;
1072
1073       /* No multisampling */
1074       svgascreen->ms_samples = 0;
1075    }
1076
1077    /* common VGPU9 / VGPU10 caps */
1078    svgascreen->haveLineStipple =
1079       get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1080
1081    svgascreen->maxLineWidth =
1082       get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f);
1083
1084    svgascreen->maxLineWidthAA =
1085       get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f);
1086
1087    if (0) {
1088       debug_printf("svga: haveProvokingVertex %u\n",
1089                    svgascreen->haveProvokingVertex);
1090       debug_printf("svga: haveLineStip %u  "
1091                    "haveLineSmooth %u  maxLineWidth %f\n",
1092                    svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1093                    svgascreen->maxLineWidth);
1094       debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1095       debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1096    }
1097
1098    pipe_mutex_init(svgascreen->tex_mutex);
1099    pipe_mutex_init(svgascreen->swc_mutex);
1100
1101    svga_screen_cache_init(svgascreen);
1102
1103    return screen;
1104 error2:
1105    FREE(svgascreen);
1106 error1:
1107    return NULL;
1108 }
1109
1110 struct svga_winsys_screen *
1111 svga_winsys_screen(struct pipe_screen *screen)
1112 {
1113    return svga_screen(screen)->sws;
1114 }
1115
1116 #ifdef DEBUG
1117 struct svga_screen *
1118 svga_screen(struct pipe_screen *screen)
1119 {
1120    assert(screen);
1121    assert(screen->destroy == svga_destroy_screen);
1122    return (struct svga_screen *)screen;
1123 }
1124 #endif