src/gallium/drivers/svga/svga_screen.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
  27 #include "util/u_format.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_inlines.h"
  30 #include "util/u_string.h"
  31 #include "util/u_math.h"
  32
  33 #include "os/os_process.h"
  34
  35 #include "svga_winsys.h"
  36 #include "svga_public.h"
  37 #include "svga_context.h"
  38 #include "svga_format.h"
  39 #include "svga_msg.h"
  40 #include "svga_screen.h"
  41 #include "svga_tgsi.h"
  42 #include "svga_resource_texture.h"
  43 #include "svga_resource.h"
  44 #include "svga_debug.h"
  45
  46 #include "svga3d_shaderdefs.h"
  47 #include "VGPU10ShaderTokens.h"
  48
  49 /* NOTE: this constant may get moved into a svga3d*.h header file */
  50 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
  51
  52 #ifndef MESA_GIT_SHA1
  53 #define MESA_GIT_SHA1 "(unknown git revision)"
  54 #endif
  55
  56 #ifdef DEBUG
  57 int SVGA_DEBUG = 0;
  58
  59 static const struct debug_named_value svga_debug_flags[] = {
  60    { "dma",         DEBUG_DMA, NULL },
  61    { "tgsi",        DEBUG_TGSI, NULL },
  62    { "pipe",        DEBUG_PIPE, NULL },
  63    { "state",       DEBUG_STATE, NULL },
  64    { "screen",      DEBUG_SCREEN, NULL },
  65    { "tex",         DEBUG_TEX, NULL },
  66    { "swtnl",       DEBUG_SWTNL, NULL },
  67    { "const",       DEBUG_CONSTS, NULL },
  68    { "viewport",    DEBUG_VIEWPORT, NULL },
  69    { "views",       DEBUG_VIEWS, NULL },
  70    { "perf",        DEBUG_PERF, NULL },
  71    { "flush",       DEBUG_FLUSH, NULL },
  72    { "sync",        DEBUG_SYNC, NULL },
  73    { "cache",       DEBUG_CACHE, NULL },
  74    { "streamout",   DEBUG_STREAMOUT, NULL },
  75    { "query",       DEBUG_QUERY, NULL },
  76    { "samplers",    DEBUG_SAMPLERS, NULL },
  77    DEBUG_NAMED_VALUE_END
  78 };
  79 #endif
  80
  81 static const char *
  82 svga_get_vendor( struct pipe_screen *pscreen )
  83 {
  84    return "VMware, Inc.";
  85 }
  86
  87
  88 static const char *
  89 svga_get_name( struct pipe_screen *pscreen )
  90 {
  91    const char *build = "", *llvm = "", *mutex = "";
  92    static char name[100];
  93 #ifdef DEBUG
  94    /* Only return internal details in the DEBUG version:
  95     */
  96    build = "build: DEBUG;";
  97    mutex = "mutex: " PIPE_ATOMIC ";";
  98 #elif defined(VMX86_STATS)
  99    build = "build: OPT;";
 100 #else
 101    build = "build: RELEASE;";
 102 #endif
 103 #ifdef HAVE_LLVM
 104    llvm = "LLVM;";
 105 #endif
 106
 107    util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
 108    return name;
 109 }
 110
 111
 112 /** Helper for querying float-valued device cap */
 113 static float
 114 get_float_cap(struct svga_winsys_screen *sws, unsigned cap, float defaultVal)
 115 {
 116    SVGA3dDevCapResult result;
 117    if (sws->get_cap(sws, cap, &result))
 118       return result.f;
 119    else
 120       return defaultVal;
 121 }
 122
 123
 124 /** Helper for querying uint-valued device cap */
 125 static unsigned
 126 get_uint_cap(struct svga_winsys_screen *sws, unsigned cap, unsigned defaultVal)
 127 {
 128    SVGA3dDevCapResult result;
 129    if (sws->get_cap(sws, cap, &result))
 130       return result.u;
 131    else
 132       return defaultVal;
 133 }
 134
 135
 136 /** Helper for querying boolean-valued device cap */
 137 static boolean
 138 get_bool_cap(struct svga_winsys_screen *sws, unsigned cap, boolean defaultVal)
 139 {
 140    SVGA3dDevCapResult result;
 141    if (sws->get_cap(sws, cap, &result))
 142       return result.b;
 143    else
 144       return defaultVal;
 145 }
 146
 147
 148 static float
 149 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 150 {
 151    struct svga_screen *svgascreen = svga_screen(screen);
 152    struct svga_winsys_screen *sws = svgascreen->sws;
 153
 154    switch (param) {
 155    case PIPE_CAPF_MAX_LINE_WIDTH:
 156       return svgascreen->maxLineWidth;
 157    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 158       return svgascreen->maxLineWidthAA;
 159
 160    case PIPE_CAPF_MAX_POINT_WIDTH:
 161       /* fall-through */
 162    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 163       return svgascreen->maxPointSize;
 164
 165    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 166       return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
 167
 168    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 169       return 15.0;
 170
 171    case PIPE_CAPF_GUARD_BAND_LEFT:
 172    case PIPE_CAPF_GUARD_BAND_TOP:
 173    case PIPE_CAPF_GUARD_BAND_RIGHT:
 174    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 175       return 0.0;
 176    }
 177
 178    debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
 179    return 0;
 180 }
 181
 182
 183 static int
 184 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
 185 {
 186    struct svga_screen *svgascreen = svga_screen(screen);
 187    struct svga_winsys_screen *sws = svgascreen->sws;
 188    SVGA3dDevCapResult result;
 189
 190    switch (param) {
 191    case PIPE_CAP_NPOT_TEXTURES:
 192    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 193    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 194       return 1;
 195    case PIPE_CAP_TWO_SIDED_STENCIL:
 196       return 1;
 197    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 198       /*
 199        * "In virtually every OpenGL implementation and hardware,
 200        * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
 201        * http://www.opengl.org/wiki/Blending
 202        */
 203       return sws->have_vgpu10 ? 1 : 0;
 204    case PIPE_CAP_ANISOTROPIC_FILTER:
 205       return 1;
 206    case PIPE_CAP_POINT_SPRITE:
 207       return 1;
 208    case PIPE_CAP_TGSI_TEXCOORD:
 209       return 0;
 210    case PIPE_CAP_MAX_RENDER_TARGETS:
 211       return svgascreen->max_color_buffers;
 212    case PIPE_CAP_OCCLUSION_QUERY:
 213       return 1;
 214    case PIPE_CAP_QUERY_TIME_ELAPSED:
 215       return 0;
 216    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 217       return sws->have_vgpu10;
 218    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 219       return 1;
 220    case PIPE_CAP_TEXTURE_SWIZZLE:
 221       return 1;
 222    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 223       return 0;
 224    case PIPE_CAP_USER_VERTEX_BUFFERS:
 225       return 0;
 226    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 227       return 1;
 228    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 229       return 256;
 230
 231    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 232       {
 233          unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
 234          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
 235             levels = MIN2(util_logbase2(result.u) + 1, levels);
 236          else
 237             levels = 12 /* 2048x2048 */;
 238          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
 239             levels = MIN2(util_logbase2(result.u) + 1, levels);
 240          else
 241             levels = 12 /* 2048x2048 */;
 242          return levels;
 243       }
 244
 245    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 246       if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
 247          return 8;  /* max 128x128x128 */
 248       return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
 249
 250    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 251       /*
 252        * No mechanism to query the host, and at least limited to 2048x2048 on
 253        * certain hardware.
 254        */
 255       return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
 256                   12 /* 2048x2048 */);
 257
 258    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 259       return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
 260
 261    case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
 262       return 1;
 263
 264    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 265       return 1;
 266    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 267       return sws->have_vgpu10;
 268    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 269       return 0;
 270    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 271       return !sws->have_vgpu10;
 272
 273    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 274       return 1; /* The color outputs of vertex shaders are not clamped */
 275    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 276       return 0; /* The driver can't clamp vertex colors */
 277    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 278       return 0; /* The driver can't clamp fragment colors */
 279
 280    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 281       return 1; /* expected for GL_ARB_framebuffer_object */
 282
 283    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 284       return sws->have_vgpu10 ? 330 : 120;
 285
 286    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 287       return 0;
 288
 289    case PIPE_CAP_SM3:
 290       return 1;
 291
 292    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 293    case PIPE_CAP_INDEP_BLEND_ENABLE:
 294    case PIPE_CAP_CONDITIONAL_RENDER:
 295    case PIPE_CAP_QUERY_TIMESTAMP:
 296    case PIPE_CAP_TGSI_INSTANCEID:
 297    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 298    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 299    case PIPE_CAP_FAKE_SW_MSAA:
 300       return sws->have_vgpu10;
 301
 302    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 303       return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
 304    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 305       return sws->have_vgpu10 ? 4 : 0;
 306    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 307       return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
 308    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 309    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 310       return 0;
 311    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 312       return svgascreen->ms_samples ? 1 : 0;
 313
 314    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 315       /* convert bytes to texels for the case of the largest texel
 316        * size: float[4].
 317        */
 318       return SVGA3D_DX_MAX_RESOURCE_SIZE / (4 * sizeof(float));
 319
 320    case PIPE_CAP_MIN_TEXEL_OFFSET:
 321       return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
 322    case PIPE_CAP_MAX_TEXEL_OFFSET:
 323       return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
 324
 325    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 326    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 327       return 0;
 328
 329    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 330       return sws->have_vgpu10 ? 256 : 0;
 331    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 332       return sws->have_vgpu10 ? 1024 : 0;
 333
 334    case PIPE_CAP_PRIMITIVE_RESTART:
 335       return 1; /* may be a sw fallback, depending on restart index */
 336
 337    case PIPE_CAP_GENERATE_MIPMAP:
 338       return sws->have_generate_mipmap_cmd;
 339
 340    case PIPE_CAP_NATIVE_FENCE_FD:
 341       return sws->have_fence_fd;
 342
 343    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 344       return 1;
 345
 346    /* Unsupported features */
 347    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 348    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 349    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 350    case PIPE_CAP_INDEP_BLEND_FUNC:
 351    case PIPE_CAP_TEXTURE_BARRIER:
 352    case PIPE_CAP_MAX_VERTEX_STREAMS:
 353    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 354    case PIPE_CAP_COMPUTE:
 355    case PIPE_CAP_START_INSTANCE:
 356    case PIPE_CAP_CUBE_MAP_ARRAY:
 357    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 358    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 359    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 360    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 361    case PIPE_CAP_TEXTURE_GATHER_SM5:
 362    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 363    case PIPE_CAP_TEXTURE_QUERY_LOD:
 364    case PIPE_CAP_SAMPLE_SHADING:
 365    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 366    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 367    case PIPE_CAP_DRAW_INDIRECT:
 368    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 369    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 370    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 371    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 372    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 373    case PIPE_CAP_CLIP_HALFZ:
 374    case PIPE_CAP_VERTEXID_NOBASE:
 375    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 376    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 377    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 378    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 379    case PIPE_CAP_INVALIDATE_BUFFER:
 380    case PIPE_CAP_STRING_MARKER:
 381    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 382    case PIPE_CAP_QUERY_MEMORY_INFO:
 383    case PIPE_CAP_PCI_GROUP:
 384    case PIPE_CAP_PCI_BUS:
 385    case PIPE_CAP_PCI_DEVICE:
 386    case PIPE_CAP_PCI_FUNCTION:
 387    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 388       return 0;
 389    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 390       return 64;
 391    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 392    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 393    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 394       return 1;  /* need 4-byte alignment for all offsets and strides */
 395    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 396       return 2048;
 397    case PIPE_CAP_MAX_VIEWPORTS:
 398       return 1;
 399    case PIPE_CAP_ENDIANNESS:
 400       return PIPE_ENDIAN_LITTLE;
 401
 402    case PIPE_CAP_VENDOR_ID:
 403       return 0x15ad; /* VMware Inc. */
 404    case PIPE_CAP_DEVICE_ID:
 405       return 0x0405; /* assume SVGA II */
 406    case PIPE_CAP_ACCELERATED:
 407       return 0; /* XXX: */
 408    case PIPE_CAP_VIDEO_MEMORY:
 409       /* XXX: Query the host ? */
 410       return 1;
 411    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 412       return sws->have_vgpu10;
 413    case PIPE_CAP_CLEAR_TEXTURE:
 414       return sws->have_vgpu10;
 415    case PIPE_CAP_UMA:
 416    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 417    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 418    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 419    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 420    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 421    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 422    case PIPE_CAP_TGSI_TXQS:
 423    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 424    case PIPE_CAP_SHAREABLE_SHADERS:
 425    case PIPE_CAP_DRAW_PARAMETERS:
 426    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 427    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 428    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 429    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 430    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 431    case PIPE_CAP_CULL_DISTANCE:
 432    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 433    case PIPE_CAP_TGSI_VOTE:
 434    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 435    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 436    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 437    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 438    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 439    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 440    case PIPE_CAP_TGSI_FS_FBFETCH:
 441    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 442    case PIPE_CAP_DOUBLES:
 443    case PIPE_CAP_INT64:
 444    case PIPE_CAP_INT64_DIVMOD:
 445    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 446    case PIPE_CAP_TGSI_CLOCK:
 447    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 448    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 449    case PIPE_CAP_TGSI_BALLOT:
 450    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 451    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 452    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 453    case PIPE_CAP_POST_DEPTH_COVERAGE:
 454    case PIPE_CAP_BINDLESS_TEXTURE:
 455    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 456    case PIPE_CAP_QUERY_SO_OVERFLOW:
 457    case PIPE_CAP_MEMOBJ:
 458    case PIPE_CAP_LOAD_CONSTBUF:
 459       return 0;
 460    }
 461
 462    debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
 463    return 0;
 464 }
 465
 466
 467 static int
 468 vgpu9_get_shader_param(struct pipe_screen *screen,
 469                        enum pipe_shader_type shader,
 470                        enum pipe_shader_cap param)
 471 {
 472    struct svga_screen *svgascreen = svga_screen(screen);
 473    struct svga_winsys_screen *sws = svgascreen->sws;
 474    unsigned val;
 475
 476    assert(!sws->have_vgpu10);
 477
 478    switch (shader)
 479    {
 480    case PIPE_SHADER_FRAGMENT:
 481       switch (param)
 482       {
 483       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 484       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 485          return get_uint_cap(sws,
 486                              SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
 487                              512);
 488       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 489       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 490          return 512;
 491       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 492          return SVGA3D_MAX_NESTING_LEVEL;
 493       case PIPE_SHADER_CAP_MAX_INPUTS:
 494          return 10;
 495       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 496          return svgascreen->max_color_buffers;
 497       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 498          return 224 * sizeof(float[4]);
 499       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 500          return 1;
 501       case PIPE_SHADER_CAP_MAX_TEMPS:
 502          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
 503          return MIN2(val, SVGA3D_TEMPREG_MAX);
 504       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 505          /*
 506           * Although PS 3.0 has some addressing abilities it can only represent
 507           * loops that can be statically determined and unrolled. Given we can
 508           * only handle a subset of the cases that the state tracker already
 509           * does it is better to defer loop unrolling to the state tracker.
 510           */
 511          return 0;
 512       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 513          return 0;
 514       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 515          return 0;
 516       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 517       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 518       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 519          return 0;
 520       case PIPE_SHADER_CAP_SUBROUTINES:
 521          return 0;
 522       case PIPE_SHADER_CAP_INT64_ATOMICS:
 523       case PIPE_SHADER_CAP_INTEGERS:
 524          return 0;
 525       case PIPE_SHADER_CAP_FP16:
 526          return 0;
 527       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 528       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 529          return 16;
 530       case PIPE_SHADER_CAP_PREFERRED_IR:
 531          return PIPE_SHADER_IR_TGSI;
 532       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 533          return 0;
 534       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 535       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 536       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 537       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 538       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 539       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 540       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 541       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 542       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 543          return 0;
 544       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 545          return 32;
 546       }
 547       /* If we get here, we failed to handle a cap above */
 548       debug_printf("Unexpected fragment shader query %u\n", param);
 549       return 0;
 550    case PIPE_SHADER_VERTEX:
 551       switch (param)
 552       {
 553       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 554       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 555          return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
 556                              512);
 557       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 558       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 559          /* XXX: until we have vertex texture support */
 560          return 0;
 561       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 562          return SVGA3D_MAX_NESTING_LEVEL;
 563       case PIPE_SHADER_CAP_MAX_INPUTS:
 564          return 16;
 565       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 566          return 10;
 567       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 568          return 256 * sizeof(float[4]);
 569       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 570          return 1;
 571       case PIPE_SHADER_CAP_MAX_TEMPS:
 572          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
 573          return MIN2(val, SVGA3D_TEMPREG_MAX);
 574       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 575          return 0;
 576       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 577          return 0;
 578       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 579       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 580          return 1;
 581       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 582          return 0;
 583       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 584          return 1;
 585       case PIPE_SHADER_CAP_SUBROUTINES:
 586          return 0;
 587       case PIPE_SHADER_CAP_INT64_ATOMICS:
 588       case PIPE_SHADER_CAP_INTEGERS:
 589          return 0;
 590       case PIPE_SHADER_CAP_FP16:
 591          return 0;
 592       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 593       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 594          return 0;
 595       case PIPE_SHADER_CAP_PREFERRED_IR:
 596          return PIPE_SHADER_IR_TGSI;
 597       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 598          return 0;
 599       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 600       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 601       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 602       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 603       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 604       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 605       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 606       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 607       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 608          return 0;
 609       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 610          return 32;
 611       }
 612       /* If we get here, we failed to handle a cap above */
 613       debug_printf("Unexpected vertex shader query %u\n", param);
 614       return 0;
 615    case PIPE_SHADER_GEOMETRY:
 616    case PIPE_SHADER_COMPUTE:
 617    case PIPE_SHADER_TESS_CTRL:
 618    case PIPE_SHADER_TESS_EVAL:
 619       /* no support for geometry, tess or compute shaders at this time */
 620       return 0;
 621    default:
 622       debug_printf("Unexpected shader type (%u) query\n", shader);
 623       return 0;
 624    }
 625    return 0;
 626 }
 627
 628
 629 static int
 630 vgpu10_get_shader_param(struct pipe_screen *screen,
 631                         enum pipe_shader_type shader,
 632                         enum pipe_shader_cap param)
 633 {
 634    struct svga_screen *svgascreen = svga_screen(screen);
 635    struct svga_winsys_screen *sws = svgascreen->sws;
 636
 637    assert(sws->have_vgpu10);
 638    (void) sws;  /* silence unused var warnings in non-debug builds */
 639
 640    /* Only VS, GS, FS supported */
 641    if (shader != PIPE_SHADER_VERTEX &&
 642        shader != PIPE_SHADER_GEOMETRY &&
 643        shader != PIPE_SHADER_FRAGMENT) {
 644       return 0;
 645    }
 646
 647    /* NOTE: we do not query the device for any caps/limits at this time */
 648
 649    /* Generally the same limits for vertex, geometry and fragment shaders */
 650    switch (param) {
 651    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 652    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 653    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 654    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 655       return 64 * 1024;
 656    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 657       return 64;
 658    case PIPE_SHADER_CAP_MAX_INPUTS:
 659       if (shader == PIPE_SHADER_FRAGMENT)
 660          return VGPU10_MAX_FS_INPUTS;
 661       else if (shader == PIPE_SHADER_GEOMETRY)
 662          return VGPU10_MAX_GS_INPUTS;
 663       else
 664          return VGPU10_MAX_VS_INPUTS;
 665    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 666       if (shader == PIPE_SHADER_FRAGMENT)
 667          return VGPU10_MAX_FS_OUTPUTS;
 668       else if (shader == PIPE_SHADER_GEOMETRY)
 669          return VGPU10_MAX_GS_OUTPUTS;
 670       else
 671          return VGPU10_MAX_VS_OUTPUTS;
 672    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 673       return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
 674    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 675       return svgascreen->max_const_buffers;
 676    case PIPE_SHADER_CAP_MAX_TEMPS:
 677       return VGPU10_MAX_TEMPS;
 678    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 679    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 680    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 681    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 682       return TRUE; /* XXX verify */
 683    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 684    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 685    case PIPE_SHADER_CAP_SUBROUTINES:
 686    case PIPE_SHADER_CAP_INTEGERS:
 687       return TRUE;
 688    case PIPE_SHADER_CAP_FP16:
 689       return FALSE;
 690    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 691    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 692       return SVGA3D_DX_MAX_SAMPLERS;
 693    case PIPE_SHADER_CAP_PREFERRED_IR:
 694       return PIPE_SHADER_IR_TGSI;
 695    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 696       return 0;
 697    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 698    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 699    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 700    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 701    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 702    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 703    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 704    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 705    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 706    case PIPE_SHADER_CAP_INT64_ATOMICS:
 707       return 0;
 708    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 709       return 32;
 710    default:
 711       debug_printf("Unexpected vgpu10 shader query %u\n", param);
 712       return 0;
 713    }
 714    return 0;
 715 }
 716
 717
 718 static int
 719 svga_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
 720                       enum pipe_shader_cap param)
 721 {
 722    struct svga_screen *svgascreen = svga_screen(screen);
 723    struct svga_winsys_screen *sws = svgascreen->sws;
 724    if (sws->have_vgpu10) {
 725       return vgpu10_get_shader_param(screen, shader, param);
 726    }
 727    else {
 728       return vgpu9_get_shader_param(screen, shader, param);
 729    }
 730 }
 731
 732
 733 /**
 734  * Implement pipe_screen::is_format_supported().
 735  * \param bindings  bitmask of PIPE_BIND_x flags
 736  */
 737 static boolean
 738 svga_is_format_supported( struct pipe_screen *screen,
 739                           enum pipe_format format,
 740                           enum pipe_texture_target target,
 741                           unsigned sample_count,
 742                           unsigned bindings)
 743 {
 744    struct svga_screen *ss = svga_screen(screen);
 745    SVGA3dSurfaceFormat svga_format;
 746    SVGA3dSurfaceFormatCaps caps;
 747    SVGA3dSurfaceFormatCaps mask;
 748
 749    assert(bindings);
 750
 751    if (sample_count > 1) {
 752       /* In ms_samples, if bit N is set it means that we support
 753        * multisample with N+1 samples per pixel.
 754        */
 755       if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
 756          return FALSE;
 757       }
 758    }
 759
 760    svga_format = svga_translate_format(ss, format, bindings);
 761    if (svga_format == SVGA3D_FORMAT_INVALID) {
 762       return FALSE;
 763    }
 764
 765    if (!ss->sws->have_vgpu10 &&
 766        util_format_is_srgb(format) &&
 767        (bindings & PIPE_BIND_DISPLAY_TARGET)) {
 768        /* We only support sRGB rendering with vgpu10 */
 769       return FALSE;
 770    }
 771
 772    /*
 773     * For VGPU10 vertex formats, skip querying host capabilities
 774     */
 775
 776    if (ss->sws->have_vgpu10 && (bindings & PIPE_BIND_VERTEX_BUFFER)) {
 777       SVGA3dSurfaceFormat svga_format;
 778       unsigned flags;
 779       svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
 780       return svga_format != SVGA3D_FORMAT_INVALID;
 781    }
 782
 783    /*
 784     * Override host capabilities, so that we end up with the same
 785     * visuals for all virtual hardware implementations.
 786     */
 787
 788    if (bindings & PIPE_BIND_DISPLAY_TARGET) {
 789       switch (svga_format) {
 790       case SVGA3D_A8R8G8B8:
 791       case SVGA3D_X8R8G8B8:
 792       case SVGA3D_R5G6B5:
 793          break;
 794
 795       /* VGPU10 formats */
 796       case SVGA3D_B8G8R8A8_UNORM:
 797       case SVGA3D_B8G8R8X8_UNORM:
 798       case SVGA3D_B5G6R5_UNORM:
 799       case SVGA3D_B8G8R8X8_UNORM_SRGB:
 800       case SVGA3D_B8G8R8A8_UNORM_SRGB:
 801       case SVGA3D_R8G8B8A8_UNORM_SRGB:
 802          break;
 803
 804       /* Often unsupported/problematic. This means we end up with the same
 805        * visuals for all virtual hardware implementations.
 806        */
 807       case SVGA3D_A4R4G4B4:
 808       case SVGA3D_A1R5G5B5:
 809          return FALSE;
 810
 811       default:
 812          return FALSE;
 813       }
 814    }
 815
 816    /*
 817     * Query the host capabilities.
 818     */
 819
 820    svga_get_format_cap(ss, svga_format, &caps);
 821
 822    if (bindings & PIPE_BIND_RENDER_TARGET) {
 823       /* Check that the color surface is blendable, unless it's an
 824        * integer format.
 825        */
 826       if (!svga_format_is_integer(svga_format) &&
 827           (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
 828          return FALSE;
 829       }
 830    }
 831
 832    mask.value = 0;
 833    if (bindings & PIPE_BIND_RENDER_TARGET) {
 834       mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
 835    }
 836    if (bindings & PIPE_BIND_DEPTH_STENCIL) {
 837       mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
 838    }
 839    if (bindings & PIPE_BIND_SAMPLER_VIEW) {
 840       mask.value |= SVGA3DFORMAT_OP_TEXTURE;
 841    }
 842
 843    if (target == PIPE_TEXTURE_CUBE) {
 844       mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
 845    }
 846    else if (target == PIPE_TEXTURE_3D) {
 847       mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
 848    }
 849
 850    return (caps.value & mask.value) == mask.value;
 851 }
 852
 853
 854 static void
 855 svga_fence_reference(struct pipe_screen *screen,
 856                      struct pipe_fence_handle **ptr,
 857                      struct pipe_fence_handle *fence)
 858 {
 859    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 860    sws->fence_reference(sws, ptr, fence);
 861 }
 862
 863
 864 static boolean
 865 svga_fence_finish(struct pipe_screen *screen,
 866                   struct pipe_context *ctx,
 867                   struct pipe_fence_handle *fence,
 868                   uint64_t timeout)
 869 {
 870    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 871    boolean retVal;
 872
 873    SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
 874
 875    if (!timeout) {
 876       retVal = sws->fence_signalled(sws, fence, 0) == 0;
 877    }
 878    else {
 879       SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
 880                __FUNCTION__, fence);
 881
 882       retVal = sws->fence_finish(sws, fence, timeout, 0) == 0;
 883    }
 884
 885    SVGA_STATS_TIME_POP(sws);
 886
 887    return retVal;
 888 }
 889
 890
 891 static int
 892 svga_fence_get_fd(struct pipe_screen *screen,
 893                   struct pipe_fence_handle *fence)
 894 {
 895    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 896
 897    return sws->fence_get_fd(sws, fence, TRUE);
 898 }
 899
 900
 901 static int
 902 svga_get_driver_query_info(struct pipe_screen *screen,
 903                            unsigned index,
 904                            struct pipe_driver_query_info *info)
 905 {
 906 #define QUERY(NAME, ENUM, UNITS) \
 907    {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
 908
 909    static const struct pipe_driver_query_info queries[] = {
 910       /* per-frame counters */
 911       QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
 912             PIPE_DRIVER_QUERY_TYPE_UINT64),
 913       QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
 914             PIPE_DRIVER_QUERY_TYPE_UINT64),
 915       QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
 916             PIPE_DRIVER_QUERY_TYPE_UINT64),
 917       QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
 918             PIPE_DRIVER_QUERY_TYPE_UINT64),
 919       QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
 920             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 921       QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
 922             PIPE_DRIVER_QUERY_TYPE_UINT64),
 923       QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
 924             PIPE_DRIVER_QUERY_TYPE_UINT64),
 925       QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
 926             PIPE_DRIVER_QUERY_TYPE_BYTES),
 927       QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
 928             PIPE_DRIVER_QUERY_TYPE_BYTES),
 929       QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
 930             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 931       QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
 932             PIPE_DRIVER_QUERY_TYPE_UINT64),
 933       QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
 934             PIPE_DRIVER_QUERY_TYPE_UINT64),
 935       QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
 936             PIPE_DRIVER_QUERY_TYPE_UINT64),
 937       QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
 938             PIPE_DRIVER_QUERY_TYPE_UINT64),
 939       QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
 940             PIPE_DRIVER_QUERY_TYPE_UINT64),
 941       QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
 942             PIPE_DRIVER_QUERY_TYPE_UINT64),
 943
 944       /* running total counters */
 945       QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
 946             PIPE_DRIVER_QUERY_TYPE_BYTES),
 947       QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
 948             PIPE_DRIVER_QUERY_TYPE_UINT64),
 949       QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
 950             PIPE_DRIVER_QUERY_TYPE_UINT64),
 951       QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
 952             PIPE_DRIVER_QUERY_TYPE_UINT64),
 953       QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
 954             PIPE_DRIVER_QUERY_TYPE_UINT64),
 955       QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
 956             PIPE_DRIVER_QUERY_TYPE_UINT64),
 957       QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS,
 958             PIPE_DRIVER_QUERY_TYPE_UINT64),
 959    };
 960 #undef QUERY
 961
 962    if (!info)
 963       return ARRAY_SIZE(queries);
 964
 965    if (index >= ARRAY_SIZE(queries))
 966       return 0;
 967
 968    *info = queries[index];
 969    return 1;
 970 }
 971
 972
 973 static void
 974 init_logging(struct pipe_screen *screen)
 975 {
 976    static const char *log_prefix = "Mesa: ";
 977    char host_log[1000];
 978
 979    /* Log Version to Host */
 980    util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 981                  "%s%s", log_prefix, svga_get_name(screen));
 982    svga_host_log(host_log);
 983
 984    util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 985                  "%s%s (%s)", log_prefix, PACKAGE_VERSION, MESA_GIT_SHA1);
 986    svga_host_log(host_log);
 987
 988    /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
 989     * line (program name and arguments).
 990     */
 991    if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE)) {
 992       char cmdline[1000];
 993       if (os_get_command_line(cmdline, sizeof(cmdline))) {
 994          util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 995                        "%s%s", log_prefix, cmdline);
 996          svga_host_log(host_log);
 997       }
 998    }
 999 }
1000
1001
1002 static void
1003 svga_destroy_screen( struct pipe_screen *screen )
1004 {
1005    struct svga_screen *svgascreen = svga_screen(screen);
1006
1007    svga_screen_cache_cleanup(svgascreen);
1008
1009    mtx_destroy(&svgascreen->swc_mutex);
1010    mtx_destroy(&svgascreen->tex_mutex);
1011
1012    svgascreen->sws->destroy(svgascreen->sws);
1013
1014    FREE(svgascreen);
1015 }
1016
1017
1018 /**
1019  * Create a new svga_screen object
1020  */
1021 struct pipe_screen *
1022 svga_screen_create(struct svga_winsys_screen *sws)
1023 {
1024    struct svga_screen *svgascreen;
1025    struct pipe_screen *screen;
1026
1027 #ifdef DEBUG
1028    SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
1029 #endif
1030
1031    svgascreen = CALLOC_STRUCT(svga_screen);
1032    if (!svgascreen)
1033       goto error1;
1034
1035    svgascreen->debug.force_level_surface_view =
1036       debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
1037    svgascreen->debug.force_surface_view =
1038       debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
1039    svgascreen->debug.force_sampler_view =
1040       debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
1041    svgascreen->debug.no_surface_view =
1042       debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
1043    svgascreen->debug.no_sampler_view =
1044       debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
1045    svgascreen->debug.no_cache_index_buffers =
1046       debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
1047
1048    screen = &svgascreen->screen;
1049
1050    screen->destroy = svga_destroy_screen;
1051    screen->get_name = svga_get_name;
1052    screen->get_vendor = svga_get_vendor;
1053    screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
1054    screen->get_param = svga_get_param;
1055    screen->get_shader_param = svga_get_shader_param;
1056    screen->get_paramf = svga_get_paramf;
1057    screen->get_timestamp = NULL;
1058    screen->is_format_supported = svga_is_format_supported;
1059    screen->context_create = svga_context_create;
1060    screen->fence_reference = svga_fence_reference;
1061    screen->fence_finish = svga_fence_finish;
1062    screen->fence_get_fd = svga_fence_get_fd;
1063
1064    screen->get_driver_query_info = svga_get_driver_query_info;
1065    svgascreen->sws = sws;
1066
1067    svga_init_screen_resource_functions(svgascreen);
1068
1069    if (sws->get_hw_version) {
1070       svgascreen->hw_version = sws->get_hw_version(sws);
1071    } else {
1072       svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
1073    }
1074
1075    if (svgascreen->hw_version < SVGA3D_HWVERSION_WS8_B1) {
1076       /* too old for 3D acceleration */
1077       debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
1078                    svgascreen->hw_version);
1079       goto error2;
1080    }
1081
1082    /*
1083     * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
1084     * when sampled from, where as the DF16, DF24, and D24S8_INT do not.  So
1085     * we prefer the later when available.
1086     *
1087     * This mimics hardware vendors extensions for D3D depth sampling. See also
1088     * http://aras-p.info/texts/D3D9GPUHacks.html
1089     */
1090
1091    {
1092       boolean has_df16, has_df24, has_d24s8_int;
1093       SVGA3dSurfaceFormatCaps caps;
1094       SVGA3dSurfaceFormatCaps mask;
1095       mask.value = 0;
1096       mask.zStencil = 1;
1097       mask.texture = 1;
1098
1099       svgascreen->depth.z16 = SVGA3D_Z_D16;
1100       svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
1101       svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
1102
1103       svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
1104       has_df16 = (caps.value & mask.value) == mask.value;
1105
1106       svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
1107       has_df24 = (caps.value & mask.value) == mask.value;
1108
1109       svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
1110       has_d24s8_int = (caps.value & mask.value) == mask.value;
1111
1112       /* XXX: We might want some other logic here.
1113        * Like if we only have d24s8_int we should
1114        * emulate the other formats with that.
1115        */
1116       if (has_df16) {
1117          svgascreen->depth.z16 = SVGA3D_Z_DF16;
1118       }
1119       if (has_df24) {
1120          svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1121       }
1122       if (has_d24s8_int) {
1123          svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1124       }
1125    }
1126
1127    /* Query device caps
1128     */
1129    if (sws->have_vgpu10) {
1130       svgascreen->haveProvokingVertex
1131          = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1132       svgascreen->haveLineSmooth = TRUE;
1133       svgascreen->maxPointSize = 80.0F;
1134       svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1135
1136       /* Multisample samples per pixel */
1137       if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
1138          svgascreen->ms_samples =
1139             get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
1140       }
1141
1142       /* We only support 4x, 8x, 16x MSAA */
1143       svgascreen->ms_samples &= ((1 << (4-1)) |
1144                                  (1 << (8-1)) |
1145                                  (1 << (16-1)));
1146
1147       /* Maximum number of constant buffers */
1148       svgascreen->max_const_buffers =
1149          get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1150       assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1151    }
1152    else {
1153       /* VGPU9 */
1154       unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1155                                      SVGA3DVSVERSION_NONE);
1156       unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1157                                      SVGA3DPSVERSION_NONE);
1158
1159       /* we require Shader model 3.0 or later */
1160       if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1161          goto error2;
1162       }
1163
1164       svgascreen->haveProvokingVertex = FALSE;
1165
1166       svgascreen->haveLineSmooth =
1167          get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1168
1169       svgascreen->maxPointSize =
1170          get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1171       /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1172       svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1173
1174       /* The SVGA3D device always supports 4 targets at this time, regardless
1175        * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1176        */
1177       svgascreen->max_color_buffers = 4;
1178
1179       /* Only support one constant buffer
1180        */
1181       svgascreen->max_const_buffers = 1;
1182
1183       /* No multisampling */
1184       svgascreen->ms_samples = 0;
1185    }
1186
1187    /* common VGPU9 / VGPU10 caps */
1188    svgascreen->haveLineStipple =
1189       get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1190
1191    svgascreen->maxLineWidth =
1192       MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f));
1193
1194    svgascreen->maxLineWidthAA =
1195       MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f));
1196
1197    if (0) {
1198       debug_printf("svga: haveProvokingVertex %u\n",
1199                    svgascreen->haveProvokingVertex);
1200       debug_printf("svga: haveLineStip %u  "
1201                    "haveLineSmooth %u  maxLineWidth %.2f  maxLineWidthAA %.2f\n",
1202                    svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1203                    svgascreen->maxLineWidth, svgascreen->maxLineWidthAA);
1204       debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1205       debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1206    }
1207
1208    (void) mtx_init(&svgascreen->tex_mutex, mtx_plain);
1209    (void) mtx_init(&svgascreen->swc_mutex, mtx_recursive);
1210
1211    svga_screen_cache_init(svgascreen);
1212
1213    init_logging(screen);
1214
1215    return screen;
1216 error2:
1217    FREE(svgascreen);
1218 error1:
1219    return NULL;
1220 }
1221
1222
1223 struct svga_winsys_screen *
1224 svga_winsys_screen(struct pipe_screen *screen)
1225 {
1226    return svga_screen(screen)->sws;
1227 }
1228
1229
1230 #ifdef DEBUG
1231 struct svga_screen *
1232 svga_screen(struct pipe_screen *screen)
1233 {
1234    assert(screen);
1235    assert(screen->destroy == svga_destroy_screen);
1236    return (struct svga_screen *)screen;
1237 }
1238 #endif