src/gallium/drivers/svga/svga_screen.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
  27 #include "util/u_format.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_inlines.h"
  30 #include "util/u_string.h"
  31 #include "util/u_math.h"
  32
  33 #include "os/os_process.h"
  34
  35 #include "svga_winsys.h"
  36 #include "svga_public.h"
  37 #include "svga_context.h"
  38 #include "svga_format.h"
  39 #include "svga_msg.h"
  40 #include "svga_screen.h"
  41 #include "svga_tgsi.h"
  42 #include "svga_resource_texture.h"
  43 #include "svga_resource.h"
  44 #include "svga_debug.h"
  45
  46 #include "svga3d_shaderdefs.h"
  47 #include "VGPU10ShaderTokens.h"
  48
  49 /* NOTE: this constant may get moved into a svga3d*.h header file */
  50 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
  51
  52 #ifdef DEBUG
  53 int SVGA_DEBUG = 0;
  54
  55 static const struct debug_named_value svga_debug_flags[] = {
  56    { "dma",         DEBUG_DMA, NULL },
  57    { "tgsi",        DEBUG_TGSI, NULL },
  58    { "pipe",        DEBUG_PIPE, NULL },
  59    { "state",       DEBUG_STATE, NULL },
  60    { "screen",      DEBUG_SCREEN, NULL },
  61    { "tex",         DEBUG_TEX, NULL },
  62    { "swtnl",       DEBUG_SWTNL, NULL },
  63    { "const",       DEBUG_CONSTS, NULL },
  64    { "viewport",    DEBUG_VIEWPORT, NULL },
  65    { "views",       DEBUG_VIEWS, NULL },
  66    { "perf",        DEBUG_PERF, NULL },
  67    { "flush",       DEBUG_FLUSH, NULL },
  68    { "sync",        DEBUG_SYNC, NULL },
  69    { "cache",       DEBUG_CACHE, NULL },
  70    { "streamout",   DEBUG_STREAMOUT, NULL },
  71    { "query",       DEBUG_QUERY, NULL },
  72    { "samplers",    DEBUG_SAMPLERS, NULL },
  73    DEBUG_NAMED_VALUE_END
  74 };
  75 #endif
  76
  77 static const char *
  78 svga_get_vendor( struct pipe_screen *pscreen )
  79 {
  80    return "VMware, Inc.";
  81 }
  82
  83
  84 static const char *
  85 svga_get_name( struct pipe_screen *pscreen )
  86 {
  87    const char *build = "", *llvm = "", *mutex = "";
  88    static char name[100];
  89 #ifdef DEBUG
  90    /* Only return internal details in the DEBUG version:
  91     */
  92    build = "build: DEBUG;";
  93    mutex = "mutex: " PIPE_ATOMIC ";";
  94 #elif defined(VMX86_STATS)
  95    build = "build: OPT;";
  96 #else
  97    build = "build: RELEASE;";
  98 #endif
  99 #ifdef HAVE_LLVM
 100    llvm = "LLVM;";
 101 #endif
 102
 103    util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
 104    return name;
 105 }
 106
 107
 108 /** Helper for querying float-valued device cap */
 109 static float
 110 get_float_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
 111               float defaultVal)
 112 {
 113    SVGA3dDevCapResult result;
 114    if (sws->get_cap(sws, cap, &result))
 115       return result.f;
 116    else
 117       return defaultVal;
 118 }
 119
 120
 121 /** Helper for querying uint-valued device cap */
 122 static unsigned
 123 get_uint_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
 124              unsigned defaultVal)
 125 {
 126    SVGA3dDevCapResult result;
 127    if (sws->get_cap(sws, cap, &result))
 128       return result.u;
 129    else
 130       return defaultVal;
 131 }
 132
 133
 134 /** Helper for querying boolean-valued device cap */
 135 static boolean
 136 get_bool_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
 137              boolean defaultVal)
 138 {
 139    SVGA3dDevCapResult result;
 140    if (sws->get_cap(sws, cap, &result))
 141       return result.b;
 142    else
 143       return defaultVal;
 144 }
 145
 146
 147 static float
 148 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 149 {
 150    struct svga_screen *svgascreen = svga_screen(screen);
 151    struct svga_winsys_screen *sws = svgascreen->sws;
 152
 153    switch (param) {
 154    case PIPE_CAPF_MAX_LINE_WIDTH:
 155       return svgascreen->maxLineWidth;
 156    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 157       return svgascreen->maxLineWidthAA;
 158
 159    case PIPE_CAPF_MAX_POINT_WIDTH:
 160       /* fall-through */
 161    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 162       return svgascreen->maxPointSize;
 163
 164    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 165       return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
 166
 167    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 168       return 15.0;
 169
 170    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 171       /* fall-through */
 172    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 173       /* fall-through */
 174    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 175       return 0.0f;
 176
 177    }
 178
 179    debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
 180    return 0;
 181 }
 182
 183
 184 static int
 185 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
 186 {
 187    struct svga_screen *svgascreen = svga_screen(screen);
 188    struct svga_winsys_screen *sws = svgascreen->sws;
 189    SVGA3dDevCapResult result;
 190
 191    switch (param) {
 192    case PIPE_CAP_NPOT_TEXTURES:
 193    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 194    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 195       return 1;
 196    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 197       /*
 198        * "In virtually every OpenGL implementation and hardware,
 199        * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
 200        * http://www.opengl.org/wiki/Blending
 201        */
 202       return sws->have_vgpu10 ? 1 : 0;
 203    case PIPE_CAP_ANISOTROPIC_FILTER:
 204       return 1;
 205    case PIPE_CAP_POINT_SPRITE:
 206       return 1;
 207    case PIPE_CAP_TGSI_TEXCOORD:
 208       return 0;
 209    case PIPE_CAP_MAX_RENDER_TARGETS:
 210       return svgascreen->max_color_buffers;
 211    case PIPE_CAP_OCCLUSION_QUERY:
 212       return 1;
 213    case PIPE_CAP_QUERY_TIME_ELAPSED:
 214       return 0;
 215    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 216       return sws->have_vgpu10;
 217    case PIPE_CAP_TEXTURE_SWIZZLE:
 218       return 1;
 219    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 220       return 0;
 221    case PIPE_CAP_USER_VERTEX_BUFFERS:
 222       return 0;
 223    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 224       return 256;
 225
 226    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 227       {
 228          unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
 229          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
 230             levels = MIN2(util_logbase2(result.u) + 1, levels);
 231          else
 232             levels = 12 /* 2048x2048 */;
 233          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
 234             levels = MIN2(util_logbase2(result.u) + 1, levels);
 235          else
 236             levels = 12 /* 2048x2048 */;
 237          return levels;
 238       }
 239
 240    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 241       if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
 242          return 8;  /* max 128x128x128 */
 243       return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
 244
 245    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 246       /*
 247        * No mechanism to query the host, and at least limited to 2048x2048 on
 248        * certain hardware.
 249        */
 250       return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
 251                   12 /* 2048x2048 */);
 252
 253    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 254       return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
 255
 256    case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
 257       return 1;
 258
 259    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 260       return 1;
 261    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 262       return sws->have_vgpu10;
 263    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 264       return 0;
 265    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 266       return !sws->have_vgpu10;
 267
 268    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 269       return 1; /* The color outputs of vertex shaders are not clamped */
 270    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 271       return 0; /* The driver can't clamp vertex colors */
 272    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 273       return 0; /* The driver can't clamp fragment colors */
 274
 275    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 276       return 1; /* expected for GL_ARB_framebuffer_object */
 277
 278    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 279       return sws->have_vgpu10 ? 330 : 120;
 280
 281    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 282       return 0;
 283
 284    case PIPE_CAP_SM3:
 285       return 1;
 286
 287    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 288    case PIPE_CAP_INDEP_BLEND_ENABLE:
 289    case PIPE_CAP_CONDITIONAL_RENDER:
 290    case PIPE_CAP_QUERY_TIMESTAMP:
 291    case PIPE_CAP_TGSI_INSTANCEID:
 292    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 293    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 294    case PIPE_CAP_FAKE_SW_MSAA:
 295       return sws->have_vgpu10;
 296
 297    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 298       return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
 299    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 300       return sws->have_vgpu10 ? 4 : 0;
 301    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 302       return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
 303    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 304    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 305       return 0;
 306    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 307       return svgascreen->ms_samples ? 1 : 0;
 308
 309    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 310       /* convert bytes to texels for the case of the largest texel
 311        * size: float[4].
 312        */
 313       return SVGA3D_DX_MAX_RESOURCE_SIZE / (4 * sizeof(float));
 314
 315    case PIPE_CAP_MIN_TEXEL_OFFSET:
 316       return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
 317    case PIPE_CAP_MAX_TEXEL_OFFSET:
 318       return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
 319
 320    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 321    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 322       return 0;
 323
 324    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 325       return sws->have_vgpu10 ? 256 : 0;
 326    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 327       return sws->have_vgpu10 ? 1024 : 0;
 328
 329    case PIPE_CAP_PRIMITIVE_RESTART:
 330       return 1; /* may be a sw fallback, depending on restart index */
 331
 332    case PIPE_CAP_GENERATE_MIPMAP:
 333       return sws->have_generate_mipmap_cmd;
 334
 335    case PIPE_CAP_NATIVE_FENCE_FD:
 336       return sws->have_fence_fd;
 337
 338    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 339       return 1;
 340
 341    /* Unsupported features */
 342    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 343    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 344    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 345    case PIPE_CAP_INDEP_BLEND_FUNC:
 346    case PIPE_CAP_TEXTURE_BARRIER:
 347    case PIPE_CAP_MAX_VERTEX_STREAMS:
 348    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 349    case PIPE_CAP_COMPUTE:
 350    case PIPE_CAP_START_INSTANCE:
 351    case PIPE_CAP_CUBE_MAP_ARRAY:
 352    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 353    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 354    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 355    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 356    case PIPE_CAP_TEXTURE_GATHER_SM5:
 357    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 358    case PIPE_CAP_TEXTURE_QUERY_LOD:
 359    case PIPE_CAP_SAMPLE_SHADING:
 360    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 361    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 362    case PIPE_CAP_DRAW_INDIRECT:
 363    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 364    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 365    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 366    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 367    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 368    case PIPE_CAP_CLIP_HALFZ:
 369    case PIPE_CAP_VERTEXID_NOBASE:
 370    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 371    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 372    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 373    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 374    case PIPE_CAP_INVALIDATE_BUFFER:
 375    case PIPE_CAP_STRING_MARKER:
 376    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 377    case PIPE_CAP_QUERY_MEMORY_INFO:
 378    case PIPE_CAP_PCI_GROUP:
 379    case PIPE_CAP_PCI_BUS:
 380    case PIPE_CAP_PCI_DEVICE:
 381    case PIPE_CAP_PCI_FUNCTION:
 382    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 383    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 384    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 385    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 386    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 387    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 388    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 389       return 0;
 390    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 391       return 64;
 392    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 393    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 394    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 395       return 1;  /* need 4-byte alignment for all offsets and strides */
 396    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 397       return 2048;
 398    case PIPE_CAP_MAX_VIEWPORTS:
 399       return 1;
 400    case PIPE_CAP_ENDIANNESS:
 401       return PIPE_ENDIAN_LITTLE;
 402
 403    case PIPE_CAP_VENDOR_ID:
 404       return 0x15ad; /* VMware Inc. */
 405    case PIPE_CAP_DEVICE_ID:
 406       return 0x0405; /* assume SVGA II */
 407    case PIPE_CAP_ACCELERATED:
 408       return 0; /* XXX: */
 409    case PIPE_CAP_VIDEO_MEMORY:
 410       /* XXX: Query the host ? */
 411       return 1;
 412    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 413       return sws->have_vgpu10;
 414    case PIPE_CAP_CLEAR_TEXTURE:
 415       return sws->have_vgpu10;
 416    case PIPE_CAP_UMA:
 417    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 418    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 419    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 420    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 421    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 422    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 423    case PIPE_CAP_TGSI_TXQS:
 424    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 425    case PIPE_CAP_SHAREABLE_SHADERS:
 426    case PIPE_CAP_DRAW_PARAMETERS:
 427    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 428    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 429    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 430    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 431    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 432    case PIPE_CAP_CULL_DISTANCE:
 433    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 434    case PIPE_CAP_TGSI_VOTE:
 435    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 436    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 437    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 438    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 439    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 440    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 441    case PIPE_CAP_TGSI_FS_FBFETCH:
 442    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 443    case PIPE_CAP_DOUBLES:
 444    case PIPE_CAP_INT64:
 445    case PIPE_CAP_INT64_DIVMOD:
 446    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 447    case PIPE_CAP_TGSI_CLOCK:
 448    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 449    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 450    case PIPE_CAP_TGSI_BALLOT:
 451    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 452    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 453    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 454    case PIPE_CAP_POST_DEPTH_COVERAGE:
 455    case PIPE_CAP_BINDLESS_TEXTURE:
 456    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 457    case PIPE_CAP_QUERY_SO_OVERFLOW:
 458    case PIPE_CAP_MEMOBJ:
 459    case PIPE_CAP_LOAD_CONSTBUF:
 460    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 461    case PIPE_CAP_TILE_RASTER_ORDER:
 462    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 463    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 464    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 465    case PIPE_CAP_FENCE_SIGNAL:
 466    case PIPE_CAP_CONSTBUF0_FLAGS:
 467    case PIPE_CAP_PACKED_UNIFORMS:
 468       return 0;
 469    }
 470
 471    debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
 472    return 0;
 473 }
 474
 475
 476 static int
 477 vgpu9_get_shader_param(struct pipe_screen *screen,
 478                        enum pipe_shader_type shader,
 479                        enum pipe_shader_cap param)
 480 {
 481    struct svga_screen *svgascreen = svga_screen(screen);
 482    struct svga_winsys_screen *sws = svgascreen->sws;
 483    unsigned val;
 484
 485    assert(!sws->have_vgpu10);
 486
 487    switch (shader)
 488    {
 489    case PIPE_SHADER_FRAGMENT:
 490       switch (param)
 491       {
 492       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 493       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 494          return get_uint_cap(sws,
 495                              SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
 496                              512);
 497       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 498       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 499          return 512;
 500       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 501          return SVGA3D_MAX_NESTING_LEVEL;
 502       case PIPE_SHADER_CAP_MAX_INPUTS:
 503          return 10;
 504       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 505          return svgascreen->max_color_buffers;
 506       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 507          return 224 * sizeof(float[4]);
 508       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 509          return 1;
 510       case PIPE_SHADER_CAP_MAX_TEMPS:
 511          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
 512          return MIN2(val, SVGA3D_TEMPREG_MAX);
 513       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 514          /*
 515           * Although PS 3.0 has some addressing abilities it can only represent
 516           * loops that can be statically determined and unrolled. Given we can
 517           * only handle a subset of the cases that the state tracker already
 518           * does it is better to defer loop unrolling to the state tracker.
 519           */
 520          return 0;
 521       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 522          return 0;
 523       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 524          return 0;
 525       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 526       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 527       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 528          return 0;
 529       case PIPE_SHADER_CAP_SUBROUTINES:
 530          return 0;
 531       case PIPE_SHADER_CAP_INT64_ATOMICS:
 532       case PIPE_SHADER_CAP_INTEGERS:
 533          return 0;
 534       case PIPE_SHADER_CAP_FP16:
 535          return 0;
 536       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 537       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 538          return 16;
 539       case PIPE_SHADER_CAP_PREFERRED_IR:
 540          return PIPE_SHADER_IR_TGSI;
 541       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 542          return 0;
 543       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 544       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 545       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 546       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 547       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 548       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 549       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 550       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 551       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 552       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 553       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 554          return 0;
 555       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 556          return 32;
 557       }
 558       /* If we get here, we failed to handle a cap above */
 559       debug_printf("Unexpected fragment shader query %u\n", param);
 560       return 0;
 561    case PIPE_SHADER_VERTEX:
 562       switch (param)
 563       {
 564       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 565       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 566          return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
 567                              512);
 568       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 569       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 570          /* XXX: until we have vertex texture support */
 571          return 0;
 572       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 573          return SVGA3D_MAX_NESTING_LEVEL;
 574       case PIPE_SHADER_CAP_MAX_INPUTS:
 575          return 16;
 576       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 577          return 10;
 578       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 579          return 256 * sizeof(float[4]);
 580       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 581          return 1;
 582       case PIPE_SHADER_CAP_MAX_TEMPS:
 583          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
 584          return MIN2(val, SVGA3D_TEMPREG_MAX);
 585       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 586          return 0;
 587       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 588          return 0;
 589       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 590       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 591          return 1;
 592       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 593          return 0;
 594       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 595          return 1;
 596       case PIPE_SHADER_CAP_SUBROUTINES:
 597          return 0;
 598       case PIPE_SHADER_CAP_INT64_ATOMICS:
 599       case PIPE_SHADER_CAP_INTEGERS:
 600          return 0;
 601       case PIPE_SHADER_CAP_FP16:
 602          return 0;
 603       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 604       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 605          return 0;
 606       case PIPE_SHADER_CAP_PREFERRED_IR:
 607          return PIPE_SHADER_IR_TGSI;
 608       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 609          return 0;
 610       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 611       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 612       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 613       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 614       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 615       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 616       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 617       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 618       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 619       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 620       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 621          return 0;
 622       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 623          return 32;
 624       }
 625       /* If we get here, we failed to handle a cap above */
 626       debug_printf("Unexpected vertex shader query %u\n", param);
 627       return 0;
 628    case PIPE_SHADER_GEOMETRY:
 629    case PIPE_SHADER_COMPUTE:
 630    case PIPE_SHADER_TESS_CTRL:
 631    case PIPE_SHADER_TESS_EVAL:
 632       /* no support for geometry, tess or compute shaders at this time */
 633       return 0;
 634    default:
 635       debug_printf("Unexpected shader type (%u) query\n", shader);
 636       return 0;
 637    }
 638    return 0;
 639 }
 640
 641
 642 static int
 643 vgpu10_get_shader_param(struct pipe_screen *screen,
 644                         enum pipe_shader_type shader,
 645                         enum pipe_shader_cap param)
 646 {
 647    struct svga_screen *svgascreen = svga_screen(screen);
 648    struct svga_winsys_screen *sws = svgascreen->sws;
 649
 650    assert(sws->have_vgpu10);
 651    (void) sws;  /* silence unused var warnings in non-debug builds */
 652
 653    /* Only VS, GS, FS supported */
 654    if (shader != PIPE_SHADER_VERTEX &&
 655        shader != PIPE_SHADER_GEOMETRY &&
 656        shader != PIPE_SHADER_FRAGMENT) {
 657       return 0;
 658    }
 659
 660    /* NOTE: we do not query the device for any caps/limits at this time */
 661
 662    /* Generally the same limits for vertex, geometry and fragment shaders */
 663    switch (param) {
 664    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 665    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 666    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 667    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 668       return 64 * 1024;
 669    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 670       return 64;
 671    case PIPE_SHADER_CAP_MAX_INPUTS:
 672       if (shader == PIPE_SHADER_FRAGMENT)
 673          return VGPU10_MAX_FS_INPUTS;
 674       else if (shader == PIPE_SHADER_GEOMETRY)
 675          return VGPU10_MAX_GS_INPUTS;
 676       else
 677          return VGPU10_MAX_VS_INPUTS;
 678    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 679       if (shader == PIPE_SHADER_FRAGMENT)
 680          return VGPU10_MAX_FS_OUTPUTS;
 681       else if (shader == PIPE_SHADER_GEOMETRY)
 682          return VGPU10_MAX_GS_OUTPUTS;
 683       else
 684          return VGPU10_MAX_VS_OUTPUTS;
 685    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 686       return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
 687    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 688       return svgascreen->max_const_buffers;
 689    case PIPE_SHADER_CAP_MAX_TEMPS:
 690       return VGPU10_MAX_TEMPS;
 691    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 692    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 693    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 694    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 695       return TRUE; /* XXX verify */
 696    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 697    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 698    case PIPE_SHADER_CAP_SUBROUTINES:
 699    case PIPE_SHADER_CAP_INTEGERS:
 700       return TRUE;
 701    case PIPE_SHADER_CAP_FP16:
 702       return FALSE;
 703    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 704    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 705       return SVGA3D_DX_MAX_SAMPLERS;
 706    case PIPE_SHADER_CAP_PREFERRED_IR:
 707       return PIPE_SHADER_IR_TGSI;
 708    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 709       return 0;
 710    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 711    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 712    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 713    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 714    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 715    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 716    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 717    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 718    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 719    case PIPE_SHADER_CAP_INT64_ATOMICS:
 720    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 721    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 722       return 0;
 723    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 724       return 32;
 725    default:
 726       debug_printf("Unexpected vgpu10 shader query %u\n", param);
 727       return 0;
 728    }
 729    return 0;
 730 }
 731
 732
 733 static int
 734 svga_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
 735                       enum pipe_shader_cap param)
 736 {
 737    struct svga_screen *svgascreen = svga_screen(screen);
 738    struct svga_winsys_screen *sws = svgascreen->sws;
 739    if (sws->have_vgpu10) {
 740       return vgpu10_get_shader_param(screen, shader, param);
 741    }
 742    else {
 743       return vgpu9_get_shader_param(screen, shader, param);
 744    }
 745 }
 746
 747
 748 static void
 749 svga_fence_reference(struct pipe_screen *screen,
 750                      struct pipe_fence_handle **ptr,
 751                      struct pipe_fence_handle *fence)
 752 {
 753    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 754    sws->fence_reference(sws, ptr, fence);
 755 }
 756
 757
 758 static boolean
 759 svga_fence_finish(struct pipe_screen *screen,
 760                   struct pipe_context *ctx,
 761                   struct pipe_fence_handle *fence,
 762                   uint64_t timeout)
 763 {
 764    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 765    boolean retVal;
 766
 767    SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
 768
 769    if (!timeout) {
 770       retVal = sws->fence_signalled(sws, fence, 0) == 0;
 771    }
 772    else {
 773       SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
 774                __FUNCTION__, fence);
 775
 776       retVal = sws->fence_finish(sws, fence, timeout, 0) == 0;
 777    }
 778
 779    SVGA_STATS_TIME_POP(sws);
 780
 781    return retVal;
 782 }
 783
 784
 785 static int
 786 svga_fence_get_fd(struct pipe_screen *screen,
 787                   struct pipe_fence_handle *fence)
 788 {
 789    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 790
 791    return sws->fence_get_fd(sws, fence, TRUE);
 792 }
 793
 794
 795 static int
 796 svga_get_driver_query_info(struct pipe_screen *screen,
 797                            unsigned index,
 798                            struct pipe_driver_query_info *info)
 799 {
 800 #define QUERY(NAME, ENUM, UNITS) \
 801    {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
 802
 803    static const struct pipe_driver_query_info queries[] = {
 804       /* per-frame counters */
 805       QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
 806             PIPE_DRIVER_QUERY_TYPE_UINT64),
 807       QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
 808             PIPE_DRIVER_QUERY_TYPE_UINT64),
 809       QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
 810             PIPE_DRIVER_QUERY_TYPE_UINT64),
 811       QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
 812             PIPE_DRIVER_QUERY_TYPE_UINT64),
 813       QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
 814             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 815       QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
 816             PIPE_DRIVER_QUERY_TYPE_UINT64),
 817       QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
 818             PIPE_DRIVER_QUERY_TYPE_UINT64),
 819       QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
 820             PIPE_DRIVER_QUERY_TYPE_BYTES),
 821       QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
 822             PIPE_DRIVER_QUERY_TYPE_BYTES),
 823       QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
 824             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 825       QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
 826             PIPE_DRIVER_QUERY_TYPE_UINT64),
 827       QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
 828             PIPE_DRIVER_QUERY_TYPE_UINT64),
 829       QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
 830             PIPE_DRIVER_QUERY_TYPE_UINT64),
 831       QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
 832             PIPE_DRIVER_QUERY_TYPE_UINT64),
 833       QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
 834             PIPE_DRIVER_QUERY_TYPE_UINT64),
 835       QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
 836             PIPE_DRIVER_QUERY_TYPE_UINT64),
 837
 838       /* running total counters */
 839       QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
 840             PIPE_DRIVER_QUERY_TYPE_BYTES),
 841       QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
 842             PIPE_DRIVER_QUERY_TYPE_UINT64),
 843       QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
 844             PIPE_DRIVER_QUERY_TYPE_UINT64),
 845       QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
 846             PIPE_DRIVER_QUERY_TYPE_UINT64),
 847       QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
 848             PIPE_DRIVER_QUERY_TYPE_UINT64),
 849       QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
 850             PIPE_DRIVER_QUERY_TYPE_UINT64),
 851       QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS,
 852             PIPE_DRIVER_QUERY_TYPE_UINT64),
 853       QUERY("num-commands-per-draw", SVGA_QUERY_NUM_COMMANDS_PER_DRAW,
 854             PIPE_DRIVER_QUERY_TYPE_FLOAT),
 855    };
 856 #undef QUERY
 857
 858    if (!info)
 859       return ARRAY_SIZE(queries);
 860
 861    if (index >= ARRAY_SIZE(queries))
 862       return 0;
 863
 864    *info = queries[index];
 865    return 1;
 866 }
 867
 868
 869 static void
 870 init_logging(struct pipe_screen *screen)
 871 {
 872    static const char *log_prefix = "Mesa: ";
 873    char host_log[1000];
 874
 875    /* Log Version to Host */
 876    util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 877                  "%s%s", log_prefix, svga_get_name(screen));
 878    svga_host_log(host_log);
 879
 880    util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 881                  "%s%s"
 882 #ifdef MESA_GIT_SHA1
 883                  " (" MESA_GIT_SHA1 ")"
 884 #endif
 885                  , log_prefix, PACKAGE_VERSION);
 886    svga_host_log(host_log);
 887
 888    /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
 889     * line (program name and arguments).
 890     */
 891    if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE)) {
 892       char cmdline[1000];
 893       if (os_get_command_line(cmdline, sizeof(cmdline))) {
 894          util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 895                        "%s%s", log_prefix, cmdline);
 896          svga_host_log(host_log);
 897       }
 898    }
 899 }
 900
 901
 902 static void
 903 svga_destroy_screen( struct pipe_screen *screen )
 904 {
 905    struct svga_screen *svgascreen = svga_screen(screen);
 906
 907    svga_screen_cache_cleanup(svgascreen);
 908
 909    mtx_destroy(&svgascreen->swc_mutex);
 910    mtx_destroy(&svgascreen->tex_mutex);
 911
 912    svgascreen->sws->destroy(svgascreen->sws);
 913
 914    FREE(svgascreen);
 915 }
 916
 917
 918 /**
 919  * Create a new svga_screen object
 920  */
 921 struct pipe_screen *
 922 svga_screen_create(struct svga_winsys_screen *sws)
 923 {
 924    struct svga_screen *svgascreen;
 925    struct pipe_screen *screen;
 926
 927 #ifdef DEBUG
 928    SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
 929 #endif
 930
 931    svgascreen = CALLOC_STRUCT(svga_screen);
 932    if (!svgascreen)
 933       goto error1;
 934
 935    svgascreen->debug.force_level_surface_view =
 936       debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
 937    svgascreen->debug.force_surface_view =
 938       debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
 939    svgascreen->debug.force_sampler_view =
 940       debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
 941    svgascreen->debug.no_surface_view =
 942       debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
 943    svgascreen->debug.no_sampler_view =
 944       debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
 945    svgascreen->debug.no_cache_index_buffers =
 946       debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
 947
 948    screen = &svgascreen->screen;
 949
 950    screen->destroy = svga_destroy_screen;
 951    screen->get_name = svga_get_name;
 952    screen->get_vendor = svga_get_vendor;
 953    screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
 954    screen->get_param = svga_get_param;
 955    screen->get_shader_param = svga_get_shader_param;
 956    screen->get_paramf = svga_get_paramf;
 957    screen->get_timestamp = NULL;
 958    screen->is_format_supported = svga_is_format_supported;
 959    screen->context_create = svga_context_create;
 960    screen->fence_reference = svga_fence_reference;
 961    screen->fence_finish = svga_fence_finish;
 962    screen->fence_get_fd = svga_fence_get_fd;
 963
 964    screen->get_driver_query_info = svga_get_driver_query_info;
 965    svgascreen->sws = sws;
 966
 967    svga_init_screen_resource_functions(svgascreen);
 968
 969    if (sws->get_hw_version) {
 970       svgascreen->hw_version = sws->get_hw_version(sws);
 971    } else {
 972       svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
 973    }
 974
 975    if (svgascreen->hw_version < SVGA3D_HWVERSION_WS8_B1) {
 976       /* too old for 3D acceleration */
 977       debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
 978                    svgascreen->hw_version);
 979       goto error2;
 980    }
 981
 982    /*
 983     * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
 984     * when sampled from, where as the DF16, DF24, and D24S8_INT do not.  So
 985     * we prefer the later when available.
 986     *
 987     * This mimics hardware vendors extensions for D3D depth sampling. See also
 988     * http://aras-p.info/texts/D3D9GPUHacks.html
 989     */
 990
 991    {
 992       boolean has_df16, has_df24, has_d24s8_int;
 993       SVGA3dSurfaceFormatCaps caps;
 994       SVGA3dSurfaceFormatCaps mask;
 995       mask.value = 0;
 996       mask.zStencil = 1;
 997       mask.texture = 1;
 998
 999       svgascreen->depth.z16 = SVGA3D_Z_D16;
1000       svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
1001       svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
1002
1003       svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
1004       has_df16 = (caps.value & mask.value) == mask.value;
1005
1006       svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
1007       has_df24 = (caps.value & mask.value) == mask.value;
1008
1009       svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
1010       has_d24s8_int = (caps.value & mask.value) == mask.value;
1011
1012       /* XXX: We might want some other logic here.
1013        * Like if we only have d24s8_int we should
1014        * emulate the other formats with that.
1015        */
1016       if (has_df16) {
1017          svgascreen->depth.z16 = SVGA3D_Z_DF16;
1018       }
1019       if (has_df24) {
1020          svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1021       }
1022       if (has_d24s8_int) {
1023          svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1024       }
1025    }
1026
1027    /* Query device caps
1028     */
1029    if (sws->have_vgpu10) {
1030       svgascreen->haveProvokingVertex
1031          = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1032       svgascreen->haveLineSmooth = TRUE;
1033       svgascreen->maxPointSize = 80.0F;
1034       svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1035
1036       /* Multisample samples per pixel */
1037       if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
1038          svgascreen->ms_samples =
1039             get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
1040       }
1041
1042       /* We only support 4x, 8x, 16x MSAA */
1043       svgascreen->ms_samples &= ((1 << (4-1)) |
1044                                  (1 << (8-1)) |
1045                                  (1 << (16-1)));
1046
1047       /* Maximum number of constant buffers */
1048       svgascreen->max_const_buffers =
1049          get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1050       assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1051    }
1052    else {
1053       /* VGPU9 */
1054       unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1055                                      SVGA3DVSVERSION_NONE);
1056       unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1057                                      SVGA3DPSVERSION_NONE);
1058
1059       /* we require Shader model 3.0 or later */
1060       if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1061          goto error2;
1062       }
1063
1064       svgascreen->haveProvokingVertex = FALSE;
1065
1066       svgascreen->haveLineSmooth =
1067          get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1068
1069       svgascreen->maxPointSize =
1070          get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1071       /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1072       svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1073
1074       /* The SVGA3D device always supports 4 targets at this time, regardless
1075        * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1076        */
1077       svgascreen->max_color_buffers = 4;
1078
1079       /* Only support one constant buffer
1080        */
1081       svgascreen->max_const_buffers = 1;
1082
1083       /* No multisampling */
1084       svgascreen->ms_samples = 0;
1085    }
1086
1087    /* common VGPU9 / VGPU10 caps */
1088    svgascreen->haveLineStipple =
1089       get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1090
1091    svgascreen->maxLineWidth =
1092       MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f));
1093
1094    svgascreen->maxLineWidthAA =
1095       MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f));
1096
1097    if (0) {
1098       debug_printf("svga: haveProvokingVertex %u\n",
1099                    svgascreen->haveProvokingVertex);
1100       debug_printf("svga: haveLineStip %u  "
1101                    "haveLineSmooth %u  maxLineWidth %.2f  maxLineWidthAA %.2f\n",
1102                    svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1103                    svgascreen->maxLineWidth, svgascreen->maxLineWidthAA);
1104       debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1105       debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1106    }
1107
1108    (void) mtx_init(&svgascreen->tex_mutex, mtx_plain);
1109    (void) mtx_init(&svgascreen->swc_mutex, mtx_recursive);
1110
1111    svga_screen_cache_init(svgascreen);
1112
1113    init_logging(screen);
1114
1115    return screen;
1116 error2:
1117    FREE(svgascreen);
1118 error1:
1119    return NULL;
1120 }
1121
1122
1123 struct svga_winsys_screen *
1124 svga_winsys_screen(struct pipe_screen *screen)
1125 {
1126    return svga_screen(screen)->sws;
1127 }
1128
1129
1130 #ifdef DEBUG
1131 struct svga_screen *
1132 svga_screen(struct pipe_screen *screen)
1133 {
1134    assert(screen);
1135    assert(screen->destroy == svga_destroy_screen);
1136    return (struct svga_screen *)screen;
1137 }
1138 #endif