src/gallium/drivers/svga/svga_screen.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
  27 #include "util/u_format.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_inlines.h"
  30 #include "util/u_screen.h"
  31 #include "util/u_string.h"
  32 #include "util/u_math.h"
  33
  34 #include "os/os_process.h"
  35
  36 #include "svga_winsys.h"
  37 #include "svga_public.h"
  38 #include "svga_context.h"
  39 #include "svga_format.h"
  40 #include "svga_msg.h"
  41 #include "svga_screen.h"
  42 #include "svga_tgsi.h"
  43 #include "svga_resource_texture.h"
  44 #include "svga_resource.h"
  45 #include "svga_debug.h"
  46
  47 #include "svga3d_shaderdefs.h"
  48 #include "VGPU10ShaderTokens.h"
  49
  50 /* NOTE: this constant may get moved into a svga3d*.h header file */
  51 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
  52
  53 #ifdef DEBUG
  54 int SVGA_DEBUG = 0;
  55
  56 static const struct debug_named_value svga_debug_flags[] = {
  57    { "dma",         DEBUG_DMA, NULL },
  58    { "tgsi",        DEBUG_TGSI, NULL },
  59    { "pipe",        DEBUG_PIPE, NULL },
  60    { "state",       DEBUG_STATE, NULL },
  61    { "screen",      DEBUG_SCREEN, NULL },
  62    { "tex",         DEBUG_TEX, NULL },
  63    { "swtnl",       DEBUG_SWTNL, NULL },
  64    { "const",       DEBUG_CONSTS, NULL },
  65    { "viewport",    DEBUG_VIEWPORT, NULL },
  66    { "views",       DEBUG_VIEWS, NULL },
  67    { "perf",        DEBUG_PERF, NULL },
  68    { "flush",       DEBUG_FLUSH, NULL },
  69    { "sync",        DEBUG_SYNC, NULL },
  70    { "cache",       DEBUG_CACHE, NULL },
  71    { "streamout",   DEBUG_STREAMOUT, NULL },
  72    { "query",       DEBUG_QUERY, NULL },
  73    { "samplers",    DEBUG_SAMPLERS, NULL },
  74    DEBUG_NAMED_VALUE_END
  75 };
  76 #endif
  77
  78 static const char *
  79 svga_get_vendor( struct pipe_screen *pscreen )
  80 {
  81    return "VMware, Inc.";
  82 }
  83
  84
  85 static const char *
  86 svga_get_name( struct pipe_screen *pscreen )
  87 {
  88    const char *build = "", *llvm = "", *mutex = "";
  89    static char name[100];
  90 #ifdef DEBUG
  91    /* Only return internal details in the DEBUG version:
  92     */
  93    build = "build: DEBUG;";
  94    mutex = "mutex: " PIPE_ATOMIC ";";
  95 #else
  96    build = "build: RELEASE;";
  97 #endif
  98 #ifdef HAVE_LLVM
  99    llvm = "LLVM;";
 100 #endif
 101
 102    util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
 103    return name;
 104 }
 105
 106
 107 /** Helper for querying float-valued device cap */
 108 static float
 109 get_float_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
 110               float defaultVal)
 111 {
 112    SVGA3dDevCapResult result;
 113    if (sws->get_cap(sws, cap, &result))
 114       return result.f;
 115    else
 116       return defaultVal;
 117 }
 118
 119
 120 /** Helper for querying uint-valued device cap */
 121 static unsigned
 122 get_uint_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
 123              unsigned defaultVal)
 124 {
 125    SVGA3dDevCapResult result;
 126    if (sws->get_cap(sws, cap, &result))
 127       return result.u;
 128    else
 129       return defaultVal;
 130 }
 131
 132
 133 /** Helper for querying boolean-valued device cap */
 134 static boolean
 135 get_bool_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
 136              boolean defaultVal)
 137 {
 138    SVGA3dDevCapResult result;
 139    if (sws->get_cap(sws, cap, &result))
 140       return result.b;
 141    else
 142       return defaultVal;
 143 }
 144
 145
 146 static float
 147 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 148 {
 149    struct svga_screen *svgascreen = svga_screen(screen);
 150    struct svga_winsys_screen *sws = svgascreen->sws;
 151
 152    switch (param) {
 153    case PIPE_CAPF_MAX_LINE_WIDTH:
 154       return svgascreen->maxLineWidth;
 155    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 156       return svgascreen->maxLineWidthAA;
 157
 158    case PIPE_CAPF_MAX_POINT_WIDTH:
 159       /* fall-through */
 160    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 161       return svgascreen->maxPointSize;
 162
 163    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 164       return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
 165
 166    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 167       return 15.0;
 168
 169    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 170       /* fall-through */
 171    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 172       /* fall-through */
 173    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 174       return 0.0f;
 175
 176    }
 177
 178    debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
 179    return 0;
 180 }
 181
 182
 183 static int
 184 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
 185 {
 186    struct svga_screen *svgascreen = svga_screen(screen);
 187    struct svga_winsys_screen *sws = svgascreen->sws;
 188    SVGA3dDevCapResult result;
 189
 190    switch (param) {
 191    case PIPE_CAP_NPOT_TEXTURES:
 192    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 193    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 194       return 1;
 195    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 196       /*
 197        * "In virtually every OpenGL implementation and hardware,
 198        * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
 199        * http://www.opengl.org/wiki/Blending
 200        */
 201       return sws->have_vgpu10 ? 1 : 0;
 202    case PIPE_CAP_ANISOTROPIC_FILTER:
 203       return 1;
 204    case PIPE_CAP_POINT_SPRITE:
 205       return 1;
 206    case PIPE_CAP_TGSI_TEXCOORD:
 207       return 0;
 208    case PIPE_CAP_MAX_RENDER_TARGETS:
 209       return svgascreen->max_color_buffers;
 210    case PIPE_CAP_OCCLUSION_QUERY:
 211       return 1;
 212    case PIPE_CAP_QUERY_TIME_ELAPSED:
 213       return 0;
 214    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 215       return sws->have_vgpu10;
 216    case PIPE_CAP_TEXTURE_SWIZZLE:
 217       return 1;
 218    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 219       return 0;
 220    case PIPE_CAP_USER_VERTEX_BUFFERS:
 221       return 0;
 222    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 223       return 256;
 224
 225    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 226       {
 227          unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
 228          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
 229             levels = MIN2(util_logbase2(result.u) + 1, levels);
 230          else
 231             levels = 12 /* 2048x2048 */;
 232          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
 233             levels = MIN2(util_logbase2(result.u) + 1, levels);
 234          else
 235             levels = 12 /* 2048x2048 */;
 236          return levels;
 237       }
 238
 239    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 240       if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
 241          return 8;  /* max 128x128x128 */
 242       return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
 243
 244    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 245       /*
 246        * No mechanism to query the host, and at least limited to 2048x2048 on
 247        * certain hardware.
 248        */
 249       return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
 250                   12 /* 2048x2048 */);
 251
 252    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 253       return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
 254
 255    case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
 256       return 1;
 257
 258    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 259       return 1;
 260    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 261       return sws->have_vgpu10;
 262    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 263       return 0;
 264    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 265       return !sws->have_vgpu10;
 266
 267    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 268       return 1; /* The color outputs of vertex shaders are not clamped */
 269    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 270       return 0; /* The driver can't clamp vertex colors */
 271    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 272       return 0; /* The driver can't clamp fragment colors */
 273
 274    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 275       return 1; /* expected for GL_ARB_framebuffer_object */
 276
 277    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 278       return sws->have_vgpu10 ? 330 : 120;
 279
 280    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 281       return sws->have_vgpu10 ? 330 : 120;
 282
 283    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 284    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 285       return 0;
 286
 287    case PIPE_CAP_SM3:
 288       return 1;
 289
 290    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 291    case PIPE_CAP_INDEP_BLEND_ENABLE:
 292    case PIPE_CAP_CONDITIONAL_RENDER:
 293    case PIPE_CAP_QUERY_TIMESTAMP:
 294    case PIPE_CAP_TGSI_INSTANCEID:
 295    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 296    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 297    case PIPE_CAP_FAKE_SW_MSAA:
 298       return sws->have_vgpu10;
 299
 300    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 301       return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
 302    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 303       return sws->have_vgpu10 ? 4 : 0;
 304    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 305       return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
 306    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 307    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 308       return 0;
 309    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 310       return svgascreen->ms_samples ? 1 : 0;
 311
 312    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 313       /* convert bytes to texels for the case of the largest texel
 314        * size: float[4].
 315        */
 316       return SVGA3D_DX_MAX_RESOURCE_SIZE / (4 * sizeof(float));
 317
 318    case PIPE_CAP_MIN_TEXEL_OFFSET:
 319       return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
 320    case PIPE_CAP_MAX_TEXEL_OFFSET:
 321       return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
 322
 323    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 324    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 325       return 0;
 326
 327    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 328       return sws->have_vgpu10 ? 256 : 0;
 329    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 330       return sws->have_vgpu10 ? 1024 : 0;
 331
 332    case PIPE_CAP_PRIMITIVE_RESTART:
 333       return 1; /* may be a sw fallback, depending on restart index */
 334
 335    case PIPE_CAP_GENERATE_MIPMAP:
 336       return sws->have_generate_mipmap_cmd;
 337
 338    case PIPE_CAP_NATIVE_FENCE_FD:
 339       return sws->have_fence_fd;
 340
 341    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 342       return 1;
 343
 344    case PIPE_CAP_CUBE_MAP_ARRAY:
 345    case PIPE_CAP_INDEP_BLEND_FUNC:
 346    case PIPE_CAP_SAMPLE_SHADING:
 347    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 348    case PIPE_CAP_TEXTURE_QUERY_LOD:
 349       return sws->have_sm4_1;
 350
 351    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 352       return sws->have_sm4_1 ? 1 : 0; /* only single-channel textures */
 353
 354    /* Unsupported features */
 355    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 356    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 357    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 358    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 359    case PIPE_CAP_TEXTURE_BARRIER:
 360    case PIPE_CAP_MAX_VERTEX_STREAMS:
 361    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 362    case PIPE_CAP_COMPUTE:
 363    case PIPE_CAP_START_INSTANCE:
 364    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 365    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 366    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 367    case PIPE_CAP_TEXTURE_GATHER_SM5:
 368    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 369    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 370    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 371    case PIPE_CAP_DRAW_INDIRECT:
 372    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 373    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 374    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 375    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 376    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 377    case PIPE_CAP_CLIP_HALFZ:
 378    case PIPE_CAP_VERTEXID_NOBASE:
 379    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 380    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 381    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 382    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 383    case PIPE_CAP_INVALIDATE_BUFFER:
 384    case PIPE_CAP_STRING_MARKER:
 385    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 386    case PIPE_CAP_QUERY_MEMORY_INFO:
 387    case PIPE_CAP_PCI_GROUP:
 388    case PIPE_CAP_PCI_BUS:
 389    case PIPE_CAP_PCI_DEVICE:
 390    case PIPE_CAP_PCI_FUNCTION:
 391    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 392    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 393    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 394    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 395    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 396    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 397    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 398    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 399       return 0;
 400    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 401       return 64;
 402    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 403    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 404    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 405       return 1;  /* need 4-byte alignment for all offsets and strides */
 406    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 407       return 2048;
 408    case PIPE_CAP_MAX_VIEWPORTS:
 409       return 1;
 410    case PIPE_CAP_ENDIANNESS:
 411       return PIPE_ENDIAN_LITTLE;
 412
 413    case PIPE_CAP_VENDOR_ID:
 414       return 0x15ad; /* VMware Inc. */
 415    case PIPE_CAP_DEVICE_ID:
 416       return 0x0405; /* assume SVGA II */
 417    case PIPE_CAP_ACCELERATED:
 418       return 0; /* XXX: */
 419    case PIPE_CAP_VIDEO_MEMORY:
 420       /* XXX: Query the host ? */
 421       return 1;
 422    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 423       return sws->have_vgpu10;
 424    case PIPE_CAP_CLEAR_TEXTURE:
 425       return sws->have_vgpu10;
 426    case PIPE_CAP_UMA:
 427    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 428    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 429    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 430    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 431    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 432    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 433    case PIPE_CAP_TGSI_TXQS:
 434    case PIPE_CAP_SHAREABLE_SHADERS:
 435    case PIPE_CAP_DRAW_PARAMETERS:
 436    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 437    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 438    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 439    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 440    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 441    case PIPE_CAP_CULL_DISTANCE:
 442    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 443    case PIPE_CAP_TGSI_VOTE:
 444    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 445    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 446    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 447    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 448    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 449    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 450    case PIPE_CAP_TGSI_FS_FBFETCH:
 451    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 452    case PIPE_CAP_DOUBLES:
 453    case PIPE_CAP_INT64:
 454    case PIPE_CAP_INT64_DIVMOD:
 455    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 456    case PIPE_CAP_TGSI_CLOCK:
 457    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 458    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 459    case PIPE_CAP_TGSI_BALLOT:
 460    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 461    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 462    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 463    case PIPE_CAP_POST_DEPTH_COVERAGE:
 464    case PIPE_CAP_BINDLESS_TEXTURE:
 465    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 466    case PIPE_CAP_QUERY_SO_OVERFLOW:
 467    case PIPE_CAP_MEMOBJ:
 468    case PIPE_CAP_LOAD_CONSTBUF:
 469    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 470    case PIPE_CAP_TILE_RASTER_ORDER:
 471    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 472    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 473    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 474    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 475    case PIPE_CAP_FENCE_SIGNAL:
 476    case PIPE_CAP_CONSTBUF0_FLAGS:
 477    case PIPE_CAP_PACKED_UNIFORMS:
 478    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 479       return 0;
 480    case PIPE_CAP_MAX_GS_INVOCATIONS:
 481       return 32;
 482    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 483       return 1 << 27;
 484    default:
 485       return u_pipe_screen_get_param_defaults(screen, param);
 486    }
 487 }
 488
 489
 490 static int
 491 vgpu9_get_shader_param(struct pipe_screen *screen,
 492                        enum pipe_shader_type shader,
 493                        enum pipe_shader_cap param)
 494 {
 495    struct svga_screen *svgascreen = svga_screen(screen);
 496    struct svga_winsys_screen *sws = svgascreen->sws;
 497    unsigned val;
 498
 499    assert(!sws->have_vgpu10);
 500
 501    switch (shader)
 502    {
 503    case PIPE_SHADER_FRAGMENT:
 504       switch (param)
 505       {
 506       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 507       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 508          return get_uint_cap(sws,
 509                              SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
 510                              512);
 511       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 512       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 513          return 512;
 514       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 515          return SVGA3D_MAX_NESTING_LEVEL;
 516       case PIPE_SHADER_CAP_MAX_INPUTS:
 517          return 10;
 518       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 519          return svgascreen->max_color_buffers;
 520       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 521          return 224 * sizeof(float[4]);
 522       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 523          return 1;
 524       case PIPE_SHADER_CAP_MAX_TEMPS:
 525          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
 526          return MIN2(val, SVGA3D_TEMPREG_MAX);
 527       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 528          /*
 529           * Although PS 3.0 has some addressing abilities it can only represent
 530           * loops that can be statically determined and unrolled. Given we can
 531           * only handle a subset of the cases that the state tracker already
 532           * does it is better to defer loop unrolling to the state tracker.
 533           */
 534          return 0;
 535       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 536          return 0;
 537       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 538          return 0;
 539       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 540       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 541       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 542          return 0;
 543       case PIPE_SHADER_CAP_SUBROUTINES:
 544          return 0;
 545       case PIPE_SHADER_CAP_INT64_ATOMICS:
 546       case PIPE_SHADER_CAP_INTEGERS:
 547          return 0;
 548       case PIPE_SHADER_CAP_FP16:
 549          return 0;
 550       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 551       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 552          return 16;
 553       case PIPE_SHADER_CAP_PREFERRED_IR:
 554          return PIPE_SHADER_IR_TGSI;
 555       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 556          return 0;
 557       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 558       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 559       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 560       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 561       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 562       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 563       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 564       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 565       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 566       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 567       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 568          return 0;
 569       case PIPE_SHADER_CAP_SCALAR_ISA:
 570          return 1;
 571       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 572          return 32;
 573       }
 574       /* If we get here, we failed to handle a cap above */
 575       debug_printf("Unexpected fragment shader query %u\n", param);
 576       return 0;
 577    case PIPE_SHADER_VERTEX:
 578       switch (param)
 579       {
 580       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 581       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 582          return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
 583                              512);
 584       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 585       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 586          /* XXX: until we have vertex texture support */
 587          return 0;
 588       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 589          return SVGA3D_MAX_NESTING_LEVEL;
 590       case PIPE_SHADER_CAP_MAX_INPUTS:
 591          return 16;
 592       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 593          return 10;
 594       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 595          return 256 * sizeof(float[4]);
 596       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 597          return 1;
 598       case PIPE_SHADER_CAP_MAX_TEMPS:
 599          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
 600          return MIN2(val, SVGA3D_TEMPREG_MAX);
 601       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 602          return 0;
 603       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 604          return 0;
 605       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 606       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 607          return 1;
 608       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 609          return 0;
 610       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 611          return 1;
 612       case PIPE_SHADER_CAP_SUBROUTINES:
 613          return 0;
 614       case PIPE_SHADER_CAP_INT64_ATOMICS:
 615       case PIPE_SHADER_CAP_INTEGERS:
 616          return 0;
 617       case PIPE_SHADER_CAP_FP16:
 618          return 0;
 619       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 620       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 621          return 0;
 622       case PIPE_SHADER_CAP_PREFERRED_IR:
 623          return PIPE_SHADER_IR_TGSI;
 624       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 625          return 0;
 626       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 627       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 628       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 629       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 630       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 631       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 632       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 633       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 634       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 635       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 636       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 637          return 0;
 638       case PIPE_SHADER_CAP_SCALAR_ISA:
 639          return 1;
 640       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 641          return 32;
 642       }
 643       /* If we get here, we failed to handle a cap above */
 644       debug_printf("Unexpected vertex shader query %u\n", param);
 645       return 0;
 646    case PIPE_SHADER_GEOMETRY:
 647    case PIPE_SHADER_COMPUTE:
 648    case PIPE_SHADER_TESS_CTRL:
 649    case PIPE_SHADER_TESS_EVAL:
 650       /* no support for geometry, tess or compute shaders at this time */
 651       return 0;
 652    default:
 653       debug_printf("Unexpected shader type (%u) query\n", shader);
 654       return 0;
 655    }
 656    return 0;
 657 }
 658
 659
 660 static int
 661 vgpu10_get_shader_param(struct pipe_screen *screen,
 662                         enum pipe_shader_type shader,
 663                         enum pipe_shader_cap param)
 664 {
 665    struct svga_screen *svgascreen = svga_screen(screen);
 666    struct svga_winsys_screen *sws = svgascreen->sws;
 667
 668    assert(sws->have_vgpu10);
 669    (void) sws;  /* silence unused var warnings in non-debug builds */
 670
 671    /* Only VS, GS, FS supported */
 672    if (shader != PIPE_SHADER_VERTEX &&
 673        shader != PIPE_SHADER_GEOMETRY &&
 674        shader != PIPE_SHADER_FRAGMENT) {
 675       return 0;
 676    }
 677
 678    /* NOTE: we do not query the device for any caps/limits at this time */
 679
 680    /* Generally the same limits for vertex, geometry and fragment shaders */
 681    switch (param) {
 682    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 683    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 684    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 685    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 686       return 64 * 1024;
 687    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 688       return 64;
 689    case PIPE_SHADER_CAP_MAX_INPUTS:
 690       if (shader == PIPE_SHADER_FRAGMENT)
 691          return VGPU10_MAX_FS_INPUTS;
 692       else if (shader == PIPE_SHADER_GEOMETRY)
 693          return VGPU10_MAX_GS_INPUTS;
 694       else
 695          return VGPU10_MAX_VS_INPUTS;
 696    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 697       if (shader == PIPE_SHADER_FRAGMENT)
 698          return VGPU10_MAX_FS_OUTPUTS;
 699       else if (shader == PIPE_SHADER_GEOMETRY)
 700          return VGPU10_MAX_GS_OUTPUTS;
 701       else
 702          return VGPU10_MAX_VS_OUTPUTS;
 703    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 704       return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
 705    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 706       return svgascreen->max_const_buffers;
 707    case PIPE_SHADER_CAP_MAX_TEMPS:
 708       return VGPU10_MAX_TEMPS;
 709    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 710    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 711    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 712    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 713       return TRUE; /* XXX verify */
 714    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 715    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 716    case PIPE_SHADER_CAP_SUBROUTINES:
 717    case PIPE_SHADER_CAP_INTEGERS:
 718       return TRUE;
 719    case PIPE_SHADER_CAP_FP16:
 720       return FALSE;
 721    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 722    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 723       return SVGA3D_DX_MAX_SAMPLERS;
 724    case PIPE_SHADER_CAP_PREFERRED_IR:
 725       return PIPE_SHADER_IR_TGSI;
 726    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 727       return 0;
 728    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 729    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 730    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 731    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 732    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 733    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 734    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 735    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 736    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 737    case PIPE_SHADER_CAP_INT64_ATOMICS:
 738    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 739    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 740       return 0;
 741    case PIPE_SHADER_CAP_SCALAR_ISA:
 742       return 1;
 743    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 744       return 32;
 745    default:
 746       debug_printf("Unexpected vgpu10 shader query %u\n", param);
 747       return 0;
 748    }
 749    return 0;
 750 }
 751
 752
 753 static int
 754 svga_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
 755                       enum pipe_shader_cap param)
 756 {
 757    struct svga_screen *svgascreen = svga_screen(screen);
 758    struct svga_winsys_screen *sws = svgascreen->sws;
 759    if (sws->have_vgpu10) {
 760       return vgpu10_get_shader_param(screen, shader, param);
 761    }
 762    else {
 763       return vgpu9_get_shader_param(screen, shader, param);
 764    }
 765 }
 766
 767
 768 static void
 769 svga_fence_reference(struct pipe_screen *screen,
 770                      struct pipe_fence_handle **ptr,
 771                      struct pipe_fence_handle *fence)
 772 {
 773    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 774    sws->fence_reference(sws, ptr, fence);
 775 }
 776
 777
 778 static boolean
 779 svga_fence_finish(struct pipe_screen *screen,
 780                   struct pipe_context *ctx,
 781                   struct pipe_fence_handle *fence,
 782                   uint64_t timeout)
 783 {
 784    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 785    boolean retVal;
 786
 787    SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
 788
 789    if (!timeout) {
 790       retVal = sws->fence_signalled(sws, fence, 0) == 0;
 791    }
 792    else {
 793       SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
 794                __FUNCTION__, fence);
 795
 796       retVal = sws->fence_finish(sws, fence, timeout, 0) == 0;
 797    }
 798
 799    SVGA_STATS_TIME_POP(sws);
 800
 801    return retVal;
 802 }
 803
 804
 805 static int
 806 svga_fence_get_fd(struct pipe_screen *screen,
 807                   struct pipe_fence_handle *fence)
 808 {
 809    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 810
 811    return sws->fence_get_fd(sws, fence, TRUE);
 812 }
 813
 814
 815 static int
 816 svga_get_driver_query_info(struct pipe_screen *screen,
 817                            unsigned index,
 818                            struct pipe_driver_query_info *info)
 819 {
 820 #define QUERY(NAME, ENUM, UNITS) \
 821    {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
 822
 823    static const struct pipe_driver_query_info queries[] = {
 824       /* per-frame counters */
 825       QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
 826             PIPE_DRIVER_QUERY_TYPE_UINT64),
 827       QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
 828             PIPE_DRIVER_QUERY_TYPE_UINT64),
 829       QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
 830             PIPE_DRIVER_QUERY_TYPE_UINT64),
 831       QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
 832             PIPE_DRIVER_QUERY_TYPE_UINT64),
 833       QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
 834             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 835       QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
 836             PIPE_DRIVER_QUERY_TYPE_UINT64),
 837       QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
 838             PIPE_DRIVER_QUERY_TYPE_UINT64),
 839       QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
 840             PIPE_DRIVER_QUERY_TYPE_BYTES),
 841       QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
 842             PIPE_DRIVER_QUERY_TYPE_BYTES),
 843       QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
 844             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 845       QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
 846             PIPE_DRIVER_QUERY_TYPE_UINT64),
 847       QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
 848             PIPE_DRIVER_QUERY_TYPE_UINT64),
 849       QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
 850             PIPE_DRIVER_QUERY_TYPE_UINT64),
 851       QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
 852             PIPE_DRIVER_QUERY_TYPE_UINT64),
 853       QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
 854             PIPE_DRIVER_QUERY_TYPE_UINT64),
 855       QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
 856             PIPE_DRIVER_QUERY_TYPE_UINT64),
 857
 858       /* running total counters */
 859       QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
 860             PIPE_DRIVER_QUERY_TYPE_BYTES),
 861       QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
 862             PIPE_DRIVER_QUERY_TYPE_UINT64),
 863       QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
 864             PIPE_DRIVER_QUERY_TYPE_UINT64),
 865       QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
 866             PIPE_DRIVER_QUERY_TYPE_UINT64),
 867       QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
 868             PIPE_DRIVER_QUERY_TYPE_UINT64),
 869       QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
 870             PIPE_DRIVER_QUERY_TYPE_UINT64),
 871       QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS,
 872             PIPE_DRIVER_QUERY_TYPE_UINT64),
 873       QUERY("num-commands-per-draw", SVGA_QUERY_NUM_COMMANDS_PER_DRAW,
 874             PIPE_DRIVER_QUERY_TYPE_FLOAT),
 875    };
 876 #undef QUERY
 877
 878    if (!info)
 879       return ARRAY_SIZE(queries);
 880
 881    if (index >= ARRAY_SIZE(queries))
 882       return 0;
 883
 884    *info = queries[index];
 885    return 1;
 886 }
 887
 888
 889 static void
 890 init_logging(struct pipe_screen *screen)
 891 {
 892    static const char *log_prefix = "Mesa: ";
 893    char host_log[1000];
 894
 895    /* Log Version to Host */
 896    util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 897                  "%s%s", log_prefix, svga_get_name(screen));
 898    svga_host_log(host_log);
 899
 900    util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 901                  "%s" PACKAGE_VERSION MESA_GIT_SHA1, log_prefix);
 902    svga_host_log(host_log);
 903
 904    /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
 905     * line (program name and arguments).
 906     */
 907    if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE)) {
 908       char cmdline[1000];
 909       if (os_get_command_line(cmdline, sizeof(cmdline))) {
 910          util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 911                        "%s%s", log_prefix, cmdline);
 912          svga_host_log(host_log);
 913       }
 914    }
 915 }
 916
 917
 918 static void
 919 svga_destroy_screen( struct pipe_screen *screen )
 920 {
 921    struct svga_screen *svgascreen = svga_screen(screen);
 922
 923    svga_screen_cache_cleanup(svgascreen);
 924
 925    mtx_destroy(&svgascreen->swc_mutex);
 926    mtx_destroy(&svgascreen->tex_mutex);
 927
 928    svgascreen->sws->destroy(svgascreen->sws);
 929
 930    FREE(svgascreen);
 931 }
 932
 933
 934 /**
 935  * Create a new svga_screen object
 936  */
 937 struct pipe_screen *
 938 svga_screen_create(struct svga_winsys_screen *sws)
 939 {
 940    struct svga_screen *svgascreen;
 941    struct pipe_screen *screen;
 942
 943 #ifdef DEBUG
 944    SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
 945 #endif
 946
 947    svgascreen = CALLOC_STRUCT(svga_screen);
 948    if (!svgascreen)
 949       goto error1;
 950
 951    svgascreen->debug.force_level_surface_view =
 952       debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
 953    svgascreen->debug.force_surface_view =
 954       debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
 955    svgascreen->debug.force_sampler_view =
 956       debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
 957    svgascreen->debug.no_surface_view =
 958       debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
 959    svgascreen->debug.no_sampler_view =
 960       debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
 961    svgascreen->debug.no_cache_index_buffers =
 962       debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
 963
 964    screen = &svgascreen->screen;
 965
 966    screen->destroy = svga_destroy_screen;
 967    screen->get_name = svga_get_name;
 968    screen->get_vendor = svga_get_vendor;
 969    screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
 970    screen->get_param = svga_get_param;
 971    screen->get_shader_param = svga_get_shader_param;
 972    screen->get_paramf = svga_get_paramf;
 973    screen->get_timestamp = NULL;
 974    screen->is_format_supported = svga_is_format_supported;
 975    screen->context_create = svga_context_create;
 976    screen->fence_reference = svga_fence_reference;
 977    screen->fence_finish = svga_fence_finish;
 978    screen->fence_get_fd = svga_fence_get_fd;
 979
 980    screen->get_driver_query_info = svga_get_driver_query_info;
 981    svgascreen->sws = sws;
 982
 983    svga_init_screen_resource_functions(svgascreen);
 984
 985    if (sws->get_hw_version) {
 986       svgascreen->hw_version = sws->get_hw_version(sws);
 987    } else {
 988       svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
 989    }
 990
 991    if (svgascreen->hw_version < SVGA3D_HWVERSION_WS8_B1) {
 992       /* too old for 3D acceleration */
 993       debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
 994                    svgascreen->hw_version);
 995       goto error2;
 996    }
 997
 998    debug_printf("%s enabled = %u\n",
 999                 sws->have_sm4_1 ? "SM4_1" : "VGPU10",
1000                 sws->have_sm4_1 ? 1 : sws->have_vgpu10);
1001
1002    debug_printf("Mesa: %s %s (%s)\n", svga_get_name(screen),
1003                 PACKAGE_VERSION, MESA_GIT_SHA1);
1004
1005    /*
1006     * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
1007     * when sampled from, where as the DF16, DF24, and D24S8_INT do not.  So
1008     * we prefer the later when available.
1009     *
1010     * This mimics hardware vendors extensions for D3D depth sampling. See also
1011     * http://aras-p.info/texts/D3D9GPUHacks.html
1012     */
1013
1014    {
1015       boolean has_df16, has_df24, has_d24s8_int;
1016       SVGA3dSurfaceFormatCaps caps;
1017       SVGA3dSurfaceFormatCaps mask;
1018       mask.value = 0;
1019       mask.zStencil = 1;
1020       mask.texture = 1;
1021
1022       svgascreen->depth.z16 = SVGA3D_Z_D16;
1023       svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
1024       svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
1025
1026       svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
1027       has_df16 = (caps.value & mask.value) == mask.value;
1028
1029       svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
1030       has_df24 = (caps.value & mask.value) == mask.value;
1031
1032       svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
1033       has_d24s8_int = (caps.value & mask.value) == mask.value;
1034
1035       /* XXX: We might want some other logic here.
1036        * Like if we only have d24s8_int we should
1037        * emulate the other formats with that.
1038        */
1039       if (has_df16) {
1040          svgascreen->depth.z16 = SVGA3D_Z_DF16;
1041       }
1042       if (has_df24) {
1043          svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1044       }
1045       if (has_d24s8_int) {
1046          svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1047       }
1048    }
1049
1050    /* Query device caps
1051     */
1052    if (sws->have_vgpu10) {
1053       svgascreen->haveProvokingVertex
1054          = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1055       svgascreen->haveLineSmooth = TRUE;
1056       svgascreen->maxPointSize = 80.0F;
1057       svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1058
1059       /* Multisample samples per pixel */
1060       if (sws->have_sm4_1 && debug_get_bool_option("SVGA_MSAA", TRUE)) {
1061          if (get_bool_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_2X, FALSE))
1062             svgascreen->ms_samples |= 1 << 1;
1063          if (get_bool_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_4X, FALSE))
1064             svgascreen->ms_samples |= 1 << 3;
1065       }
1066
1067       /* Maximum number of constant buffers */
1068       svgascreen->max_const_buffers =
1069          get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1070       assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1071
1072       screen->is_format_supported = svga_is_dx_format_supported;
1073    }
1074    else {
1075       /* VGPU9 */
1076       unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1077                                      SVGA3DVSVERSION_NONE);
1078       unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1079                                      SVGA3DPSVERSION_NONE);
1080
1081       /* we require Shader model 3.0 or later */
1082       if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1083          goto error2;
1084       }
1085
1086       svgascreen->haveProvokingVertex = FALSE;
1087
1088       svgascreen->haveLineSmooth =
1089          get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1090
1091       svgascreen->maxPointSize =
1092          get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1093       /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1094       svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1095
1096       /* The SVGA3D device always supports 4 targets at this time, regardless
1097        * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1098        */
1099       svgascreen->max_color_buffers = 4;
1100
1101       /* Only support one constant buffer
1102        */
1103       svgascreen->max_const_buffers = 1;
1104
1105       /* No multisampling */
1106       svgascreen->ms_samples = 0;
1107    }
1108
1109    /* common VGPU9 / VGPU10 caps */
1110    svgascreen->haveLineStipple =
1111       get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1112
1113    svgascreen->maxLineWidth =
1114       MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f));
1115
1116    svgascreen->maxLineWidthAA =
1117       MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f));
1118
1119    if (0) {
1120       debug_printf("svga: haveProvokingVertex %u\n",
1121                    svgascreen->haveProvokingVertex);
1122       debug_printf("svga: haveLineStip %u  "
1123                    "haveLineSmooth %u  maxLineWidth %.2f  maxLineWidthAA %.2f\n",
1124                    svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1125                    svgascreen->maxLineWidth, svgascreen->maxLineWidthAA);
1126       debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1127       debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1128    }
1129
1130    (void) mtx_init(&svgascreen->tex_mutex, mtx_plain);
1131    (void) mtx_init(&svgascreen->swc_mutex, mtx_recursive);
1132
1133    svga_screen_cache_init(svgascreen);
1134
1135    init_logging(screen);
1136
1137    return screen;
1138 error2:
1139    FREE(svgascreen);
1140 error1:
1141    return NULL;
1142 }
1143
1144
1145 struct svga_winsys_screen *
1146 svga_winsys_screen(struct pipe_screen *screen)
1147 {
1148    return svga_screen(screen)->sws;
1149 }
1150
1151
1152 #ifdef DEBUG
1153 struct svga_screen *
1154 svga_screen(struct pipe_screen *screen)
1155 {
1156    assert(screen);
1157    assert(screen->destroy == svga_destroy_screen);
1158    return (struct svga_screen *)screen;
1159 }
1160 #endif