src/gallium/drivers/svga/svga_screen.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "util/u_format.h"
  27 #include "util/u_memory.h"
  28 #include "util/u_inlines.h"
  29 #include "util/u_string.h"
  30 #include "util/u_math.h"
  31
  32 #include "svga_winsys.h"
  33 #include "svga_public.h"
  34 #include "svga_context.h"
  35 #include "svga_format.h"
  36 #include "svga_screen.h"
  37 #include "svga_tgsi.h"
  38 #include "svga_resource_texture.h"
  39 #include "svga_resource.h"
  40 #include "svga_debug.h"
  41
  42 #include "svga3d_shaderdefs.h"
  43 #include "VGPU10ShaderTokens.h"
  44
  45 /* NOTE: this constant may get moved into a svga3d*.h header file */
  46 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
  47
  48 #ifdef DEBUG
  49 int SVGA_DEBUG = 0;
  50
  51 static const struct debug_named_value svga_debug_flags[] = {
  52    { "dma",         DEBUG_DMA, NULL },
  53    { "tgsi",        DEBUG_TGSI, NULL },
  54    { "pipe",        DEBUG_PIPE, NULL },
  55    { "state",       DEBUG_STATE, NULL },
  56    { "screen",      DEBUG_SCREEN, NULL },
  57    { "tex",         DEBUG_TEX, NULL },
  58    { "swtnl",       DEBUG_SWTNL, NULL },
  59    { "const",       DEBUG_CONSTS, NULL },
  60    { "viewport",    DEBUG_VIEWPORT, NULL },
  61    { "views",       DEBUG_VIEWS, NULL },
  62    { "perf",        DEBUG_PERF, NULL },
  63    { "flush",       DEBUG_FLUSH, NULL },
  64    { "sync",        DEBUG_SYNC, NULL },
  65    { "cache",       DEBUG_CACHE, NULL },
  66    { "streamout",   DEBUG_STREAMOUT, NULL },
  67    { "query",       DEBUG_QUERY, NULL },
  68    DEBUG_NAMED_VALUE_END
  69 };
  70 #endif
  71
  72 static const char *
  73 svga_get_vendor( struct pipe_screen *pscreen )
  74 {
  75    return "VMware, Inc.";
  76 }
  77
  78
  79 static const char *
  80 svga_get_name( struct pipe_screen *pscreen )
  81 {
  82    const char *build = "", *llvm = "", *mutex = "";
  83    static char name[100];
  84 #ifdef DEBUG
  85    /* Only return internal details in the DEBUG version:
  86     */
  87    build = "build: DEBUG;";
  88    mutex = "mutex: " PIPE_ATOMIC ";";
  89 #else
  90    build = "build: RELEASE;";
  91 #endif
  92 #ifdef HAVE_LLVM
  93    llvm = "LLVM;";
  94 #endif
  95
  96    util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
  97    return name;
  98 }
  99
 100
 101 /** Helper for querying float-valued device cap */
 102 static float
 103 get_float_cap(struct svga_winsys_screen *sws, unsigned cap, float defaultVal)
 104 {
 105    SVGA3dDevCapResult result;
 106    if (sws->get_cap(sws, cap, &result))
 107       return result.f;
 108    else
 109       return defaultVal;
 110 }
 111
 112
 113 /** Helper for querying uint-valued device cap */
 114 static unsigned
 115 get_uint_cap(struct svga_winsys_screen *sws, unsigned cap, unsigned defaultVal)
 116 {
 117    SVGA3dDevCapResult result;
 118    if (sws->get_cap(sws, cap, &result))
 119       return result.u;
 120    else
 121       return defaultVal;
 122 }
 123
 124
 125 /** Helper for querying boolean-valued device cap */
 126 static boolean
 127 get_bool_cap(struct svga_winsys_screen *sws, unsigned cap, boolean defaultVal)
 128 {
 129    SVGA3dDevCapResult result;
 130    if (sws->get_cap(sws, cap, &result))
 131       return result.b;
 132    else
 133       return defaultVal;
 134 }
 135
 136
 137 static float
 138 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 139 {
 140    struct svga_screen *svgascreen = svga_screen(screen);
 141    struct svga_winsys_screen *sws = svgascreen->sws;
 142
 143    switch (param) {
 144    case PIPE_CAPF_MAX_LINE_WIDTH:
 145       return svgascreen->maxLineWidth;
 146    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 147       return svgascreen->maxLineWidthAA;
 148
 149    case PIPE_CAPF_MAX_POINT_WIDTH:
 150       /* fall-through */
 151    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 152       return svgascreen->maxPointSize;
 153
 154    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 155       return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
 156
 157    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 158       return 15.0;
 159
 160    case PIPE_CAPF_GUARD_BAND_LEFT:
 161    case PIPE_CAPF_GUARD_BAND_TOP:
 162    case PIPE_CAPF_GUARD_BAND_RIGHT:
 163    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 164       return 0.0;
 165    }
 166
 167    debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
 168    return 0;
 169 }
 170
 171
 172 static int
 173 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
 174 {
 175    struct svga_screen *svgascreen = svga_screen(screen);
 176    struct svga_winsys_screen *sws = svgascreen->sws;
 177    SVGA3dDevCapResult result;
 178
 179    switch (param) {
 180    case PIPE_CAP_NPOT_TEXTURES:
 181    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 182    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 183       return 1;
 184    case PIPE_CAP_TWO_SIDED_STENCIL:
 185       return 1;
 186    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 187       /*
 188        * "In virtually every OpenGL implementation and hardware,
 189        * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
 190        * http://www.opengl.org/wiki/Blending
 191        */
 192       return sws->have_vgpu10 ? 1 : 0;
 193    case PIPE_CAP_ANISOTROPIC_FILTER:
 194       return 1;
 195    case PIPE_CAP_POINT_SPRITE:
 196       return 1;
 197    case PIPE_CAP_TGSI_TEXCOORD:
 198       return 0;
 199    case PIPE_CAP_MAX_RENDER_TARGETS:
 200       return svgascreen->max_color_buffers;
 201    case PIPE_CAP_OCCLUSION_QUERY:
 202       return 1;
 203    case PIPE_CAP_QUERY_TIME_ELAPSED:
 204       return 0;
 205    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 206       return sws->have_vgpu10;
 207    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 208       return 1;
 209    case PIPE_CAP_TEXTURE_SWIZZLE:
 210       return 1;
 211    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 212       return 0;
 213    case PIPE_CAP_USER_VERTEX_BUFFERS:
 214    case PIPE_CAP_USER_INDEX_BUFFERS:
 215       return 0;
 216    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 217       return 1;
 218    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 219       return 256;
 220
 221    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 222       {
 223          unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
 224          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
 225             levels = MIN2(util_logbase2(result.u) + 1, levels);
 226          else
 227             levels = 12 /* 2048x2048 */;
 228          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
 229             levels = MIN2(util_logbase2(result.u) + 1, levels);
 230          else
 231             levels = 12 /* 2048x2048 */;
 232          return levels;
 233       }
 234
 235    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 236       if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
 237          return 8;  /* max 128x128x128 */
 238       return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
 239
 240    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 241       /*
 242        * No mechanism to query the host, and at least limited to 2048x2048 on
 243        * certain hardware.
 244        */
 245       return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
 246                   12 /* 2048x2048 */);
 247
 248    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 249       return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
 250
 251    case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
 252       return 1;
 253
 254    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 255       return 1;
 256    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 257       return sws->have_vgpu10;
 258    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 259       return 0;
 260    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 261       return !sws->have_vgpu10;
 262
 263    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 264       return 1; /* The color outputs of vertex shaders are not clamped */
 265    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 266       return 0; /* The driver can't clamp vertex colors */
 267    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 268       return 0; /* The driver can't clamp fragment colors */
 269
 270    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 271       return 1; /* expected for GL_ARB_framebuffer_object */
 272
 273    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 274       return sws->have_vgpu10 ? 330 : 120;
 275
 276    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 277       return 0;
 278
 279    case PIPE_CAP_SM3:
 280       return 1;
 281
 282    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 283    case PIPE_CAP_INDEP_BLEND_ENABLE:
 284    case PIPE_CAP_CONDITIONAL_RENDER:
 285    case PIPE_CAP_QUERY_TIMESTAMP:
 286    case PIPE_CAP_TGSI_INSTANCEID:
 287    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 288    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 289    case PIPE_CAP_FAKE_SW_MSAA:
 290       return sws->have_vgpu10;
 291
 292    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 293       return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
 294    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 295       return sws->have_vgpu10 ? 4 : 0;
 296    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 297       return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
 298    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 299       return 0;
 300    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 301       return svgascreen->ms_samples ? 1 : 0;
 302
 303    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 304       return SVGA3D_DX_MAX_RESOURCE_SIZE;
 305
 306    case PIPE_CAP_MIN_TEXEL_OFFSET:
 307       return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
 308    case PIPE_CAP_MAX_TEXEL_OFFSET:
 309       return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
 310
 311    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 312    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 313       return 0;
 314
 315    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 316       return sws->have_vgpu10 ? 256 : 0;
 317    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 318       return sws->have_vgpu10 ? 1024 : 0;
 319
 320    case PIPE_CAP_PRIMITIVE_RESTART:
 321       return 1; /* may be a sw fallback, depending on restart index */
 322
 323    case PIPE_CAP_GENERATE_MIPMAP:
 324       return sws->have_generate_mipmap_cmd;
 325
 326    /* Unsupported features */
 327    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 328    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 329    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 330    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 331    case PIPE_CAP_INDEP_BLEND_FUNC:
 332    case PIPE_CAP_TEXTURE_BARRIER:
 333    case PIPE_CAP_MAX_VERTEX_STREAMS:
 334    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 335    case PIPE_CAP_COMPUTE:
 336    case PIPE_CAP_START_INSTANCE:
 337    case PIPE_CAP_CUBE_MAP_ARRAY:
 338    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 339    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 340    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 341    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 342    case PIPE_CAP_TEXTURE_GATHER_SM5:
 343    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 344    case PIPE_CAP_TEXTURE_QUERY_LOD:
 345    case PIPE_CAP_SAMPLE_SHADING:
 346    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 347    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 348    case PIPE_CAP_DRAW_INDIRECT:
 349    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 350    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 351    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 352    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 353    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 354    case PIPE_CAP_CLIP_HALFZ:
 355    case PIPE_CAP_VERTEXID_NOBASE:
 356    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 357    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 358    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 359    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 360    case PIPE_CAP_INVALIDATE_BUFFER:
 361    case PIPE_CAP_STRING_MARKER:
 362    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 363    case PIPE_CAP_QUERY_MEMORY_INFO:
 364    case PIPE_CAP_PCI_GROUP:
 365    case PIPE_CAP_PCI_BUS:
 366    case PIPE_CAP_PCI_DEVICE:
 367    case PIPE_CAP_PCI_FUNCTION:
 368    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 369       return 0;
 370    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 371       return 64;
 372    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 373    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 374    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 375       return 1;  /* need 4-byte alignment for all offsets and strides */
 376    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 377       return 2048;
 378    case PIPE_CAP_MAX_VIEWPORTS:
 379       return 1;
 380    case PIPE_CAP_ENDIANNESS:
 381       return PIPE_ENDIAN_LITTLE;
 382
 383    case PIPE_CAP_VENDOR_ID:
 384       return 0x15ad; /* VMware Inc. */
 385    case PIPE_CAP_DEVICE_ID:
 386       return 0x0405; /* assume SVGA II */
 387    case PIPE_CAP_ACCELERATED:
 388       return 0; /* XXX: */
 389    case PIPE_CAP_VIDEO_MEMORY:
 390       /* XXX: Query the host ? */
 391       return 1;
 392    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 393       return sws->have_vgpu10;
 394    case PIPE_CAP_UMA:
 395    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 396    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 397    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 398    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 399    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 400    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 401    case PIPE_CAP_TGSI_TXQS:
 402    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 403    case PIPE_CAP_SHAREABLE_SHADERS:
 404    case PIPE_CAP_CLEAR_TEXTURE:
 405    case PIPE_CAP_DRAW_PARAMETERS:
 406    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 407    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 408    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 409    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 410    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 411    case PIPE_CAP_CULL_DISTANCE:
 412    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 413    case PIPE_CAP_TGSI_VOTE:
 414    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 415    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 416    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 417       return 0;
 418    }
 419
 420    debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
 421    return 0;
 422 }
 423
 424
 425 static int
 426 vgpu9_get_shader_param(struct pipe_screen *screen, unsigned shader,
 427                        enum pipe_shader_cap param)
 428 {
 429    struct svga_screen *svgascreen = svga_screen(screen);
 430    struct svga_winsys_screen *sws = svgascreen->sws;
 431    unsigned val;
 432
 433    assert(!sws->have_vgpu10);
 434
 435    switch (shader)
 436    {
 437    case PIPE_SHADER_FRAGMENT:
 438       switch (param)
 439       {
 440       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 441       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 442          return get_uint_cap(sws,
 443                              SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
 444                              512);
 445       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 446       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 447          return 512;
 448       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 449          return SVGA3D_MAX_NESTING_LEVEL;
 450       case PIPE_SHADER_CAP_MAX_INPUTS:
 451          return 10;
 452       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 453          return svgascreen->max_color_buffers;
 454       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 455          return 224 * sizeof(float[4]);
 456       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 457          return 1;
 458       case PIPE_SHADER_CAP_MAX_TEMPS:
 459          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
 460          return MIN2(val, SVGA3D_TEMPREG_MAX);
 461       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 462          /*
 463           * Although PS 3.0 has some addressing abilities it can only represent
 464           * loops that can be statically determined and unrolled. Given we can
 465           * only handle a subset of the cases that the state tracker already
 466           * does it is better to defer loop unrolling to the state tracker.
 467           */
 468          return 0;
 469       case PIPE_SHADER_CAP_MAX_PREDS:
 470          return 1;
 471       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 472          return 0;
 473       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 474          return 0;
 475       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 476       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 477       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 478          return 0;
 479       case PIPE_SHADER_CAP_SUBROUTINES:
 480          return 0;
 481       case PIPE_SHADER_CAP_INTEGERS:
 482          return 0;
 483       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 484       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 485          return 16;
 486       case PIPE_SHADER_CAP_PREFERRED_IR:
 487          return PIPE_SHADER_IR_TGSI;
 488       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 489          return 0;
 490       case PIPE_SHADER_CAP_DOUBLES:
 491       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 492       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 493       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 494       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 495       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 496       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 497          return 0;
 498       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 499          return 32;
 500       }
 501       /* If we get here, we failed to handle a cap above */
 502       debug_printf("Unexpected fragment shader query %u\n", param);
 503       return 0;
 504    case PIPE_SHADER_VERTEX:
 505       switch (param)
 506       {
 507       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 508       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 509          return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
 510                              512);
 511       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 512       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 513          /* XXX: until we have vertex texture support */
 514          return 0;
 515       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 516          return SVGA3D_MAX_NESTING_LEVEL;
 517       case PIPE_SHADER_CAP_MAX_INPUTS:
 518          return 16;
 519       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 520          return 10;
 521       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 522          return 256 * sizeof(float[4]);
 523       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 524          return 1;
 525       case PIPE_SHADER_CAP_MAX_TEMPS:
 526          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
 527          return MIN2(val, SVGA3D_TEMPREG_MAX);
 528       case PIPE_SHADER_CAP_MAX_PREDS:
 529          return 1;
 530       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 531          return 0;
 532       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 533          return 0;
 534       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 535       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 536          return 1;
 537       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 538          return 0;
 539       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 540          return 1;
 541       case PIPE_SHADER_CAP_SUBROUTINES:
 542          return 0;
 543       case PIPE_SHADER_CAP_INTEGERS:
 544          return 0;
 545       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 546       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 547          return 0;
 548       case PIPE_SHADER_CAP_PREFERRED_IR:
 549          return PIPE_SHADER_IR_TGSI;
 550       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 551          return 0;
 552       case PIPE_SHADER_CAP_DOUBLES:
 553       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 554       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 555       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 556       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 557       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 558       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 559          return 0;
 560       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 561          return 32;
 562       }
 563       /* If we get here, we failed to handle a cap above */
 564       debug_printf("Unexpected vertex shader query %u\n", param);
 565       return 0;
 566    case PIPE_SHADER_GEOMETRY:
 567    case PIPE_SHADER_COMPUTE:
 568    case PIPE_SHADER_TESS_CTRL:
 569    case PIPE_SHADER_TESS_EVAL:
 570       /* no support for geometry, tess or compute shaders at this time */
 571       return 0;
 572    default:
 573       debug_printf("Unexpected shader type (%u) query\n", shader);
 574       return 0;
 575    }
 576    return 0;
 577 }
 578
 579
 580 static int
 581 vgpu10_get_shader_param(struct pipe_screen *screen, unsigned shader,
 582                         enum pipe_shader_cap param)
 583 {
 584    struct svga_screen *svgascreen = svga_screen(screen);
 585    struct svga_winsys_screen *sws = svgascreen->sws;
 586
 587    assert(sws->have_vgpu10);
 588    (void) sws;  /* silence unused var warnings in non-debug builds */
 589
 590    /* Only VS, GS, FS supported */
 591    if (shader != PIPE_SHADER_VERTEX &&
 592        shader != PIPE_SHADER_GEOMETRY &&
 593        shader != PIPE_SHADER_FRAGMENT) {
 594       return 0;
 595    }
 596
 597    /* NOTE: we do not query the device for any caps/limits at this time */
 598
 599    /* Generally the same limits for vertex, geometry and fragment shaders */
 600    switch (param) {
 601    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 602    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 603    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 604    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 605       return 64 * 1024;
 606    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 607       return 64;
 608    case PIPE_SHADER_CAP_MAX_INPUTS:
 609       if (shader == PIPE_SHADER_FRAGMENT)
 610          return VGPU10_MAX_FS_INPUTS;
 611       else if (shader == PIPE_SHADER_GEOMETRY)
 612          return VGPU10_MAX_GS_INPUTS;
 613       else
 614          return VGPU10_MAX_VS_INPUTS;
 615    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 616       if (shader == PIPE_SHADER_FRAGMENT)
 617          return VGPU10_MAX_FS_OUTPUTS;
 618       else if (shader == PIPE_SHADER_GEOMETRY)
 619          return VGPU10_MAX_GS_OUTPUTS;
 620       else
 621          return VGPU10_MAX_VS_OUTPUTS;
 622    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 623       return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
 624    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 625       return svgascreen->max_const_buffers;
 626    case PIPE_SHADER_CAP_MAX_TEMPS:
 627       return VGPU10_MAX_TEMPS;
 628    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 629    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 630    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 631    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 632       return TRUE; /* XXX verify */
 633    case PIPE_SHADER_CAP_MAX_PREDS:
 634       return 0;
 635    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 636    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 637    case PIPE_SHADER_CAP_SUBROUTINES:
 638    case PIPE_SHADER_CAP_INTEGERS:
 639       return TRUE;
 640    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 641    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 642       return SVGA3D_DX_MAX_SAMPLERS;
 643    case PIPE_SHADER_CAP_PREFERRED_IR:
 644       return PIPE_SHADER_IR_TGSI;
 645    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 646          return 0;
 647    case PIPE_SHADER_CAP_DOUBLES:
 648    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 649    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 650    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 651    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 652    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 653    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 654       return 0;
 655    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 656       return 32;
 657    default:
 658       debug_printf("Unexpected vgpu10 shader query %u\n", param);
 659       return 0;
 660    }
 661    return 0;
 662 }
 663
 664
 665 static int
 666 svga_get_shader_param(struct pipe_screen *screen, unsigned shader,
 667                       enum pipe_shader_cap param)
 668 {
 669    struct svga_screen *svgascreen = svga_screen(screen);
 670    struct svga_winsys_screen *sws = svgascreen->sws;
 671    if (sws->have_vgpu10) {
 672       return vgpu10_get_shader_param(screen, shader, param);
 673    }
 674    else {
 675       return vgpu9_get_shader_param(screen, shader, param);
 676    }
 677 }
 678
 679
 680 /**
 681  * Implement pipe_screen::is_format_supported().
 682  * \param bindings  bitmask of PIPE_BIND_x flags
 683  */
 684 static boolean
 685 svga_is_format_supported( struct pipe_screen *screen,
 686                           enum pipe_format format,
 687                           enum pipe_texture_target target,
 688                           unsigned sample_count,
 689                           unsigned bindings)
 690 {
 691    struct svga_screen *ss = svga_screen(screen);
 692    SVGA3dSurfaceFormat svga_format;
 693    SVGA3dSurfaceFormatCaps caps;
 694    SVGA3dSurfaceFormatCaps mask;
 695
 696    assert(bindings);
 697
 698    if (sample_count > 1) {
 699       /* In ms_samples, if bit N is set it means that we support
 700        * multisample with N+1 samples per pixel.
 701        */
 702       if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
 703          return FALSE;
 704       }
 705    }
 706
 707    svga_format = svga_translate_format(ss, format, bindings);
 708    if (svga_format == SVGA3D_FORMAT_INVALID) {
 709       return FALSE;
 710    }
 711
 712    /* we don't support sRGB rendering into display targets */
 713    if (util_format_is_srgb(format) && (bindings & PIPE_BIND_DISPLAY_TARGET)) {
 714       return FALSE;
 715    }
 716
 717    /*
 718     * For VGPU10 vertex formats, skip querying host capabilities
 719     */
 720
 721    if (ss->sws->have_vgpu10 && (bindings & PIPE_BIND_VERTEX_BUFFER)) {
 722       SVGA3dSurfaceFormat svga_format;
 723       unsigned flags;
 724       svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
 725       return svga_format != SVGA3D_FORMAT_INVALID;
 726    }
 727
 728    /*
 729     * Override host capabilities, so that we end up with the same
 730     * visuals for all virtual hardware implementations.
 731     */
 732
 733    if (bindings & PIPE_BIND_DISPLAY_TARGET) {
 734       switch (svga_format) {
 735       case SVGA3D_A8R8G8B8:
 736       case SVGA3D_X8R8G8B8:
 737       case SVGA3D_R5G6B5:
 738          break;
 739
 740       /* VGPU10 formats */
 741       case SVGA3D_B8G8R8A8_UNORM:
 742       case SVGA3D_B8G8R8X8_UNORM:
 743       case SVGA3D_B5G6R5_UNORM:
 744          break;
 745
 746       /* Often unsupported/problematic. This means we end up with the same
 747        * visuals for all virtual hardware implementations.
 748        */
 749       case SVGA3D_A4R4G4B4:
 750       case SVGA3D_A1R5G5B5:
 751          return FALSE;
 752
 753       default:
 754          return FALSE;
 755       }
 756    }
 757
 758    /*
 759     * Query the host capabilities.
 760     */
 761
 762    svga_get_format_cap(ss, svga_format, &caps);
 763
 764    if (bindings & PIPE_BIND_RENDER_TARGET) {
 765       /* Check that the color surface is blendable, unless it's an
 766        * integer format.
 767        */
 768       if (!svga_format_is_integer(svga_format) &&
 769           (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
 770          return FALSE;
 771       }
 772    }
 773
 774    mask.value = 0;
 775    if (bindings & PIPE_BIND_RENDER_TARGET) {
 776       mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
 777    }
 778    if (bindings & PIPE_BIND_DEPTH_STENCIL) {
 779       mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
 780    }
 781    if (bindings & PIPE_BIND_SAMPLER_VIEW) {
 782       mask.value |= SVGA3DFORMAT_OP_TEXTURE;
 783    }
 784
 785    if (target == PIPE_TEXTURE_CUBE) {
 786       mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
 787    }
 788    else if (target == PIPE_TEXTURE_3D) {
 789       mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
 790    }
 791
 792    return (caps.value & mask.value) == mask.value;
 793 }
 794
 795
 796 static void
 797 svga_fence_reference(struct pipe_screen *screen,
 798                      struct pipe_fence_handle **ptr,
 799                      struct pipe_fence_handle *fence)
 800 {
 801    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 802    sws->fence_reference(sws, ptr, fence);
 803 }
 804
 805
 806 static boolean
 807 svga_fence_finish(struct pipe_screen *screen,
 808                   struct pipe_context *ctx,
 809                   struct pipe_fence_handle *fence,
 810                   uint64_t timeout)
 811 {
 812    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 813
 814    if (!timeout)
 815       return sws->fence_signalled(sws, fence, 0) == 0;
 816
 817    SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
 818             __FUNCTION__, fence);
 819
 820    return sws->fence_finish(sws, fence, 0) == 0;
 821 }
 822
 823
 824 static int
 825 svga_get_driver_query_info(struct pipe_screen *screen,
 826                            unsigned index,
 827                            struct pipe_driver_query_info *info)
 828 {
 829 #define QUERY(NAME, ENUM, UNITS) \
 830    {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
 831
 832    static const struct pipe_driver_query_info queries[] = {
 833       /* per-frame counters */
 834       QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
 835             PIPE_DRIVER_QUERY_TYPE_UINT64),
 836       QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
 837             PIPE_DRIVER_QUERY_TYPE_UINT64),
 838       QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
 839             PIPE_DRIVER_QUERY_TYPE_UINT64),
 840       QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
 841             PIPE_DRIVER_QUERY_TYPE_UINT64),
 842       QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
 843             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 844       QUERY("num-resources-mapped", SVGA_QUERY_NUM_RESOURCES_MAPPED,
 845             PIPE_DRIVER_QUERY_TYPE_UINT64),
 846       QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
 847             PIPE_DRIVER_QUERY_TYPE_BYTES),
 848       QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
 849             PIPE_DRIVER_QUERY_TYPE_BYTES),
 850       QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
 851             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 852       QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
 853             PIPE_DRIVER_QUERY_TYPE_UINT64),
 854       QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
 855             PIPE_DRIVER_QUERY_TYPE_UINT64),
 856       QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
 857             PIPE_DRIVER_QUERY_TYPE_UINT64),
 858       QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
 859             PIPE_DRIVER_QUERY_TYPE_UINT64),
 860       QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
 861             PIPE_DRIVER_QUERY_TYPE_UINT64),
 862       QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
 863             PIPE_DRIVER_QUERY_TYPE_UINT64),
 864
 865       /* running total counters */
 866       QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
 867             PIPE_DRIVER_QUERY_TYPE_BYTES),
 868       QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
 869             PIPE_DRIVER_QUERY_TYPE_UINT64),
 870       QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
 871             PIPE_DRIVER_QUERY_TYPE_UINT64),
 872       QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
 873             PIPE_DRIVER_QUERY_TYPE_UINT64),
 874       QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
 875             PIPE_DRIVER_QUERY_TYPE_UINT64),
 876       QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
 877             PIPE_DRIVER_QUERY_TYPE_UINT64),
 878    };
 879 #undef QUERY
 880
 881    if (!info)
 882       return ARRAY_SIZE(queries);
 883
 884    if (index >= ARRAY_SIZE(queries))
 885       return 0;
 886
 887    *info = queries[index];
 888    return 1;
 889 }
 890
 891
 892 static void
 893 svga_destroy_screen( struct pipe_screen *screen )
 894 {
 895    struct svga_screen *svgascreen = svga_screen(screen);
 896
 897    svga_screen_cache_cleanup(svgascreen);
 898
 899    pipe_mutex_destroy(svgascreen->swc_mutex);
 900    pipe_mutex_destroy(svgascreen->tex_mutex);
 901
 902    svgascreen->sws->destroy(svgascreen->sws);
 903
 904    FREE(svgascreen);
 905 }
 906
 907
 908 /**
 909  * Create a new svga_screen object
 910  */
 911 struct pipe_screen *
 912 svga_screen_create(struct svga_winsys_screen *sws)
 913 {
 914    struct svga_screen *svgascreen;
 915    struct pipe_screen *screen;
 916
 917 #ifdef DEBUG
 918    SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
 919 #endif
 920
 921    svgascreen = CALLOC_STRUCT(svga_screen);
 922    if (!svgascreen)
 923       goto error1;
 924
 925    svgascreen->debug.force_level_surface_view =
 926       debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
 927    svgascreen->debug.force_surface_view =
 928       debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
 929    svgascreen->debug.force_sampler_view =
 930       debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
 931    svgascreen->debug.no_surface_view =
 932       debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
 933    svgascreen->debug.no_sampler_view =
 934       debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
 935
 936    screen = &svgascreen->screen;
 937
 938    screen->destroy = svga_destroy_screen;
 939    screen->get_name = svga_get_name;
 940    screen->get_vendor = svga_get_vendor;
 941    screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
 942    screen->get_param = svga_get_param;
 943    screen->get_shader_param = svga_get_shader_param;
 944    screen->get_paramf = svga_get_paramf;
 945    screen->get_timestamp = NULL;
 946    screen->is_format_supported = svga_is_format_supported;
 947    screen->context_create = svga_context_create;
 948    screen->fence_reference = svga_fence_reference;
 949    screen->fence_finish = svga_fence_finish;
 950    screen->get_driver_query_info = svga_get_driver_query_info;
 951    svgascreen->sws = sws;
 952
 953    svga_init_screen_resource_functions(svgascreen);
 954
 955    if (sws->get_hw_version) {
 956       svgascreen->hw_version = sws->get_hw_version(sws);
 957    } else {
 958       svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
 959    }
 960
 961    /*
 962     * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
 963     * when sampled from, where as the DF16, DF24, and D24S8_INT do not.  So
 964     * we prefer the later when available.
 965     *
 966     * This mimics hardware vendors extensions for D3D depth sampling. See also
 967     * http://aras-p.info/texts/D3D9GPUHacks.html
 968     */
 969
 970    {
 971       boolean has_df16, has_df24, has_d24s8_int;
 972       SVGA3dSurfaceFormatCaps caps;
 973       SVGA3dSurfaceFormatCaps mask;
 974       mask.value = 0;
 975       mask.zStencil = 1;
 976       mask.texture = 1;
 977
 978       svgascreen->depth.z16 = SVGA3D_Z_D16;
 979       svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
 980       svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
 981
 982       svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
 983       has_df16 = (caps.value & mask.value) == mask.value;
 984
 985       svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
 986       has_df24 = (caps.value & mask.value) == mask.value;
 987
 988       svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
 989       has_d24s8_int = (caps.value & mask.value) == mask.value;
 990
 991       /* XXX: We might want some other logic here.
 992        * Like if we only have d24s8_int we should
 993        * emulate the other formats with that.
 994        */
 995       if (has_df16) {
 996          svgascreen->depth.z16 = SVGA3D_Z_DF16;
 997       }
 998       if (has_df24) {
 999          svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1000       }
1001       if (has_d24s8_int) {
1002          svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1003       }
1004    }
1005
1006    /* Query device caps
1007     */
1008    if (sws->have_vgpu10) {
1009       svgascreen->haveProvokingVertex
1010          = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1011       svgascreen->haveLineSmooth = TRUE;
1012       svgascreen->maxPointSize = 80.0F;
1013       svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1014
1015       /* Multisample samples per pixel */
1016       if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
1017          svgascreen->ms_samples =
1018             get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
1019       }
1020
1021       /* Maximum number of constant buffers */
1022       svgascreen->max_const_buffers =
1023          get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1024       assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1025    }
1026    else {
1027       /* VGPU9 */
1028       unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1029                                      SVGA3DVSVERSION_NONE);
1030       unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1031                                      SVGA3DPSVERSION_NONE);
1032
1033       /* we require Shader model 3.0 or later */
1034       if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1035          goto error2;
1036       }
1037
1038       svgascreen->haveProvokingVertex = FALSE;
1039
1040       svgascreen->haveLineSmooth =
1041          get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1042
1043       svgascreen->maxPointSize =
1044          get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1045       /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1046       svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1047
1048       /* The SVGA3D device always supports 4 targets at this time, regardless
1049        * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1050        */
1051       svgascreen->max_color_buffers = 4;
1052
1053       /* Only support one constant buffer
1054        */
1055       svgascreen->max_const_buffers = 1;
1056
1057       /* No multisampling */
1058       svgascreen->ms_samples = 0;
1059    }
1060
1061    /* common VGPU9 / VGPU10 caps */
1062    svgascreen->haveLineStipple =
1063       get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1064
1065    svgascreen->maxLineWidth =
1066       get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f);
1067
1068    svgascreen->maxLineWidthAA =
1069       get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f);
1070
1071    if (0) {
1072       debug_printf("svga: haveProvokingVertex %u\n",
1073                    svgascreen->haveProvokingVertex);
1074       debug_printf("svga: haveLineStip %u  "
1075                    "haveLineSmooth %u  maxLineWidth %f\n",
1076                    svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1077                    svgascreen->maxLineWidth);
1078       debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1079       debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1080    }
1081
1082    pipe_mutex_init(svgascreen->tex_mutex);
1083    pipe_mutex_init(svgascreen->swc_mutex);
1084
1085    svga_screen_cache_init(svgascreen);
1086
1087    return screen;
1088 error2:
1089    FREE(svgascreen);
1090 error1:
1091    return NULL;
1092 }
1093
1094 struct svga_winsys_screen *
1095 svga_winsys_screen(struct pipe_screen *screen)
1096 {
1097    return svga_screen(screen)->sws;
1098 }
1099
1100 #ifdef DEBUG
1101 struct svga_screen *
1102 svga_screen(struct pipe_screen *screen)
1103 {
1104    assert(screen);
1105    assert(screen->destroy == svga_destroy_screen);
1106    return (struct svga_screen *)screen;
1107 }
1108 #endif