src/gallium/drivers/svga/svga_screen.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
  27 #include "util/u_format.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_inlines.h"
  30 #include "util/u_string.h"
  31 #include "util/u_math.h"
  32
  33 #include "os/os_process.h"
  34
  35 #include "svga_winsys.h"
  36 #include "svga_public.h"
  37 #include "svga_context.h"
  38 #include "svga_format.h"
  39 #include "svga_msg.h"
  40 #include "svga_screen.h"
  41 #include "svga_tgsi.h"
  42 #include "svga_resource_texture.h"
  43 #include "svga_resource.h"
  44 #include "svga_debug.h"
  45
  46 #include "svga3d_shaderdefs.h"
  47 #include "VGPU10ShaderTokens.h"
  48
  49 /* NOTE: this constant may get moved into a svga3d*.h header file */
  50 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
  51
  52 #ifndef MESA_GIT_SHA1
  53 #define MESA_GIT_SHA1 "(unknown git revision)"
  54 #endif
  55
  56 #ifdef DEBUG
  57 int SVGA_DEBUG = 0;
  58
  59 static const struct debug_named_value svga_debug_flags[] = {
  60    { "dma",         DEBUG_DMA, NULL },
  61    { "tgsi",        DEBUG_TGSI, NULL },
  62    { "pipe",        DEBUG_PIPE, NULL },
  63    { "state",       DEBUG_STATE, NULL },
  64    { "screen",      DEBUG_SCREEN, NULL },
  65    { "tex",         DEBUG_TEX, NULL },
  66    { "swtnl",       DEBUG_SWTNL, NULL },
  67    { "const",       DEBUG_CONSTS, NULL },
  68    { "viewport",    DEBUG_VIEWPORT, NULL },
  69    { "views",       DEBUG_VIEWS, NULL },
  70    { "perf",        DEBUG_PERF, NULL },
  71    { "flush",       DEBUG_FLUSH, NULL },
  72    { "sync",        DEBUG_SYNC, NULL },
  73    { "cache",       DEBUG_CACHE, NULL },
  74    { "streamout",   DEBUG_STREAMOUT, NULL },
  75    { "query",       DEBUG_QUERY, NULL },
  76    { "samplers",    DEBUG_SAMPLERS, NULL },
  77    DEBUG_NAMED_VALUE_END
  78 };
  79 #endif
  80
  81 static const char *
  82 svga_get_vendor( struct pipe_screen *pscreen )
  83 {
  84    return "VMware, Inc.";
  85 }
  86
  87
  88 static const char *
  89 svga_get_name( struct pipe_screen *pscreen )
  90 {
  91    const char *build = "", *llvm = "", *mutex = "";
  92    static char name[100];
  93 #ifdef DEBUG
  94    /* Only return internal details in the DEBUG version:
  95     */
  96    build = "build: DEBUG;";
  97    mutex = "mutex: " PIPE_ATOMIC ";";
  98 #elif defined(VMX86_STATS)
  99    build = "build: OPT;";
 100 #else
 101    build = "build: RELEASE;";
 102 #endif
 103 #ifdef HAVE_LLVM
 104    llvm = "LLVM;";
 105 #endif
 106
 107    util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
 108    return name;
 109 }
 110
 111
 112 /** Helper for querying float-valued device cap */
 113 static float
 114 get_float_cap(struct svga_winsys_screen *sws, unsigned cap, float defaultVal)
 115 {
 116    SVGA3dDevCapResult result;
 117    if (sws->get_cap(sws, cap, &result))
 118       return result.f;
 119    else
 120       return defaultVal;
 121 }
 122
 123
 124 /** Helper for querying uint-valued device cap */
 125 static unsigned
 126 get_uint_cap(struct svga_winsys_screen *sws, unsigned cap, unsigned defaultVal)
 127 {
 128    SVGA3dDevCapResult result;
 129    if (sws->get_cap(sws, cap, &result))
 130       return result.u;
 131    else
 132       return defaultVal;
 133 }
 134
 135
 136 /** Helper for querying boolean-valued device cap */
 137 static boolean
 138 get_bool_cap(struct svga_winsys_screen *sws, unsigned cap, boolean defaultVal)
 139 {
 140    SVGA3dDevCapResult result;
 141    if (sws->get_cap(sws, cap, &result))
 142       return result.b;
 143    else
 144       return defaultVal;
 145 }
 146
 147
 148 static float
 149 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 150 {
 151    struct svga_screen *svgascreen = svga_screen(screen);
 152    struct svga_winsys_screen *sws = svgascreen->sws;
 153
 154    switch (param) {
 155    case PIPE_CAPF_MAX_LINE_WIDTH:
 156       return svgascreen->maxLineWidth;
 157    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 158       return svgascreen->maxLineWidthAA;
 159
 160    case PIPE_CAPF_MAX_POINT_WIDTH:
 161       /* fall-through */
 162    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 163       return svgascreen->maxPointSize;
 164
 165    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 166       return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
 167
 168    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 169       return 15.0;
 170
 171    case PIPE_CAPF_GUARD_BAND_LEFT:
 172    case PIPE_CAPF_GUARD_BAND_TOP:
 173    case PIPE_CAPF_GUARD_BAND_RIGHT:
 174    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 175       return 0.0;
 176    }
 177
 178    debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
 179    return 0;
 180 }
 181
 182
 183 static int
 184 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
 185 {
 186    struct svga_screen *svgascreen = svga_screen(screen);
 187    struct svga_winsys_screen *sws = svgascreen->sws;
 188    SVGA3dDevCapResult result;
 189
 190    switch (param) {
 191    case PIPE_CAP_NPOT_TEXTURES:
 192    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 193    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 194       return 1;
 195    case PIPE_CAP_TWO_SIDED_STENCIL:
 196       return 1;
 197    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 198       /*
 199        * "In virtually every OpenGL implementation and hardware,
 200        * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
 201        * http://www.opengl.org/wiki/Blending
 202        */
 203       return sws->have_vgpu10 ? 1 : 0;
 204    case PIPE_CAP_ANISOTROPIC_FILTER:
 205       return 1;
 206    case PIPE_CAP_POINT_SPRITE:
 207       return 1;
 208    case PIPE_CAP_TGSI_TEXCOORD:
 209       return 0;
 210    case PIPE_CAP_MAX_RENDER_TARGETS:
 211       return svgascreen->max_color_buffers;
 212    case PIPE_CAP_OCCLUSION_QUERY:
 213       return 1;
 214    case PIPE_CAP_QUERY_TIME_ELAPSED:
 215       return 0;
 216    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 217       return sws->have_vgpu10;
 218    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 219       return 1;
 220    case PIPE_CAP_TEXTURE_SWIZZLE:
 221       return 1;
 222    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 223       return 0;
 224    case PIPE_CAP_USER_VERTEX_BUFFERS:
 225       return 0;
 226    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 227       return 1;
 228    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 229       return 256;
 230
 231    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 232       {
 233          unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
 234          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
 235             levels = MIN2(util_logbase2(result.u) + 1, levels);
 236          else
 237             levels = 12 /* 2048x2048 */;
 238          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
 239             levels = MIN2(util_logbase2(result.u) + 1, levels);
 240          else
 241             levels = 12 /* 2048x2048 */;
 242          return levels;
 243       }
 244
 245    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 246       if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
 247          return 8;  /* max 128x128x128 */
 248       return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
 249
 250    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 251       /*
 252        * No mechanism to query the host, and at least limited to 2048x2048 on
 253        * certain hardware.
 254        */
 255       return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
 256                   12 /* 2048x2048 */);
 257
 258    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 259       return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
 260
 261    case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
 262       return 1;
 263
 264    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 265       return 1;
 266    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 267       return sws->have_vgpu10;
 268    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 269       return 0;
 270    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 271       return !sws->have_vgpu10;
 272
 273    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 274       return 1; /* The color outputs of vertex shaders are not clamped */
 275    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 276       return 0; /* The driver can't clamp vertex colors */
 277    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 278       return 0; /* The driver can't clamp fragment colors */
 279
 280    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 281       return 1; /* expected for GL_ARB_framebuffer_object */
 282
 283    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 284       return sws->have_vgpu10 ? 330 : 120;
 285
 286    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 287       return 0;
 288
 289    case PIPE_CAP_SM3:
 290       return 1;
 291
 292    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 293    case PIPE_CAP_INDEP_BLEND_ENABLE:
 294    case PIPE_CAP_CONDITIONAL_RENDER:
 295    case PIPE_CAP_QUERY_TIMESTAMP:
 296    case PIPE_CAP_TGSI_INSTANCEID:
 297    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 298    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 299    case PIPE_CAP_FAKE_SW_MSAA:
 300       return sws->have_vgpu10;
 301
 302    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 303       return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
 304    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 305       return sws->have_vgpu10 ? 4 : 0;
 306    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 307       return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
 308    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 309    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 310       return 0;
 311    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 312       return svgascreen->ms_samples ? 1 : 0;
 313
 314    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 315       /* convert bytes to texels for the case of the largest texel
 316        * size: float[4].
 317        */
 318       return SVGA3D_DX_MAX_RESOURCE_SIZE / (4 * sizeof(float));
 319
 320    case PIPE_CAP_MIN_TEXEL_OFFSET:
 321       return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
 322    case PIPE_CAP_MAX_TEXEL_OFFSET:
 323       return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
 324
 325    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 326    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 327       return 0;
 328
 329    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 330       return sws->have_vgpu10 ? 256 : 0;
 331    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 332       return sws->have_vgpu10 ? 1024 : 0;
 333
 334    case PIPE_CAP_PRIMITIVE_RESTART:
 335       return 1; /* may be a sw fallback, depending on restart index */
 336
 337    case PIPE_CAP_GENERATE_MIPMAP:
 338       return sws->have_generate_mipmap_cmd;
 339
 340    /* Unsupported features */
 341    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 342    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 343    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 344    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 345    case PIPE_CAP_INDEP_BLEND_FUNC:
 346    case PIPE_CAP_TEXTURE_BARRIER:
 347    case PIPE_CAP_MAX_VERTEX_STREAMS:
 348    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 349    case PIPE_CAP_COMPUTE:
 350    case PIPE_CAP_START_INSTANCE:
 351    case PIPE_CAP_CUBE_MAP_ARRAY:
 352    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 353    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 354    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 355    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 356    case PIPE_CAP_TEXTURE_GATHER_SM5:
 357    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 358    case PIPE_CAP_TEXTURE_QUERY_LOD:
 359    case PIPE_CAP_SAMPLE_SHADING:
 360    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 361    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 362    case PIPE_CAP_DRAW_INDIRECT:
 363    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 364    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 365    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 366    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 367    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 368    case PIPE_CAP_CLIP_HALFZ:
 369    case PIPE_CAP_VERTEXID_NOBASE:
 370    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 371    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 372    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 373    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 374    case PIPE_CAP_INVALIDATE_BUFFER:
 375    case PIPE_CAP_STRING_MARKER:
 376    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 377    case PIPE_CAP_QUERY_MEMORY_INFO:
 378    case PIPE_CAP_PCI_GROUP:
 379    case PIPE_CAP_PCI_BUS:
 380    case PIPE_CAP_PCI_DEVICE:
 381    case PIPE_CAP_PCI_FUNCTION:
 382    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 383    case PIPE_CAP_NATIVE_FENCE_FD:
 384       return 0;
 385    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 386       return 64;
 387    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 388    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 389    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 390       return 1;  /* need 4-byte alignment for all offsets and strides */
 391    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 392       return 2048;
 393    case PIPE_CAP_MAX_VIEWPORTS:
 394       return 1;
 395    case PIPE_CAP_ENDIANNESS:
 396       return PIPE_ENDIAN_LITTLE;
 397
 398    case PIPE_CAP_VENDOR_ID:
 399       return 0x15ad; /* VMware Inc. */
 400    case PIPE_CAP_DEVICE_ID:
 401       return 0x0405; /* assume SVGA II */
 402    case PIPE_CAP_ACCELERATED:
 403       return 0; /* XXX: */
 404    case PIPE_CAP_VIDEO_MEMORY:
 405       /* XXX: Query the host ? */
 406       return 1;
 407    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 408       return sws->have_vgpu10;
 409    case PIPE_CAP_CLEAR_TEXTURE:
 410       return sws->have_vgpu10;
 411    case PIPE_CAP_UMA:
 412    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 413    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 414    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 415    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 416    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 417    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 418    case PIPE_CAP_TGSI_TXQS:
 419    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 420    case PIPE_CAP_SHAREABLE_SHADERS:
 421    case PIPE_CAP_DRAW_PARAMETERS:
 422    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 423    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 424    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 425    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 426    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 427    case PIPE_CAP_CULL_DISTANCE:
 428    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 429    case PIPE_CAP_TGSI_VOTE:
 430    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 431    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 432    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 433    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 434    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 435    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 436    case PIPE_CAP_TGSI_FS_FBFETCH:
 437    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 438    case PIPE_CAP_DOUBLES:
 439    case PIPE_CAP_INT64:
 440    case PIPE_CAP_INT64_DIVMOD:
 441    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 442    case PIPE_CAP_TGSI_CLOCK:
 443    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 444    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 445    case PIPE_CAP_TGSI_BALLOT:
 446    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 447    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 448    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 449    case PIPE_CAP_POST_DEPTH_COVERAGE:
 450    case PIPE_CAP_BINDLESS_TEXTURE:
 451       return 0;
 452    }
 453
 454    debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
 455    return 0;
 456 }
 457
 458
 459 static int
 460 vgpu9_get_shader_param(struct pipe_screen *screen,
 461                        enum pipe_shader_type shader,
 462                        enum pipe_shader_cap param)
 463 {
 464    struct svga_screen *svgascreen = svga_screen(screen);
 465    struct svga_winsys_screen *sws = svgascreen->sws;
 466    unsigned val;
 467
 468    assert(!sws->have_vgpu10);
 469
 470    switch (shader)
 471    {
 472    case PIPE_SHADER_FRAGMENT:
 473       switch (param)
 474       {
 475       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 476       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 477          return get_uint_cap(sws,
 478                              SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
 479                              512);
 480       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 481       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 482          return 512;
 483       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 484          return SVGA3D_MAX_NESTING_LEVEL;
 485       case PIPE_SHADER_CAP_MAX_INPUTS:
 486          return 10;
 487       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 488          return svgascreen->max_color_buffers;
 489       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 490          return 224 * sizeof(float[4]);
 491       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 492          return 1;
 493       case PIPE_SHADER_CAP_MAX_TEMPS:
 494          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
 495          return MIN2(val, SVGA3D_TEMPREG_MAX);
 496       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 497          /*
 498           * Although PS 3.0 has some addressing abilities it can only represent
 499           * loops that can be statically determined and unrolled. Given we can
 500           * only handle a subset of the cases that the state tracker already
 501           * does it is better to defer loop unrolling to the state tracker.
 502           */
 503          return 0;
 504       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 505          return 0;
 506       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 507          return 0;
 508       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 509       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 510       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 511          return 0;
 512       case PIPE_SHADER_CAP_SUBROUTINES:
 513          return 0;
 514       case PIPE_SHADER_CAP_INTEGERS:
 515          return 0;
 516       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 517       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 518          return 16;
 519       case PIPE_SHADER_CAP_PREFERRED_IR:
 520          return PIPE_SHADER_IR_TGSI;
 521       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 522          return 0;
 523       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 524       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 525       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 526       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 527       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 528       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 529       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 530       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 531          return 0;
 532       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 533          return 32;
 534       }
 535       /* If we get here, we failed to handle a cap above */
 536       debug_printf("Unexpected fragment shader query %u\n", param);
 537       return 0;
 538    case PIPE_SHADER_VERTEX:
 539       switch (param)
 540       {
 541       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 542       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 543          return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
 544                              512);
 545       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 546       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 547          /* XXX: until we have vertex texture support */
 548          return 0;
 549       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 550          return SVGA3D_MAX_NESTING_LEVEL;
 551       case PIPE_SHADER_CAP_MAX_INPUTS:
 552          return 16;
 553       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 554          return 10;
 555       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 556          return 256 * sizeof(float[4]);
 557       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 558          return 1;
 559       case PIPE_SHADER_CAP_MAX_TEMPS:
 560          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
 561          return MIN2(val, SVGA3D_TEMPREG_MAX);
 562       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 563          return 0;
 564       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 565          return 0;
 566       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 567       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 568          return 1;
 569       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 570          return 0;
 571       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 572          return 1;
 573       case PIPE_SHADER_CAP_SUBROUTINES:
 574          return 0;
 575       case PIPE_SHADER_CAP_INTEGERS:
 576          return 0;
 577       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 578       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 579          return 0;
 580       case PIPE_SHADER_CAP_PREFERRED_IR:
 581          return PIPE_SHADER_IR_TGSI;
 582       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 583          return 0;
 584       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 585       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 586       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 587       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 588       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 589       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 590       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 591       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 592          return 0;
 593       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 594          return 32;
 595       }
 596       /* If we get here, we failed to handle a cap above */
 597       debug_printf("Unexpected vertex shader query %u\n", param);
 598       return 0;
 599    case PIPE_SHADER_GEOMETRY:
 600    case PIPE_SHADER_COMPUTE:
 601    case PIPE_SHADER_TESS_CTRL:
 602    case PIPE_SHADER_TESS_EVAL:
 603       /* no support for geometry, tess or compute shaders at this time */
 604       return 0;
 605    default:
 606       debug_printf("Unexpected shader type (%u) query\n", shader);
 607       return 0;
 608    }
 609    return 0;
 610 }
 611
 612
 613 static int
 614 vgpu10_get_shader_param(struct pipe_screen *screen,
 615                         enum pipe_shader_type shader,
 616                         enum pipe_shader_cap param)
 617 {
 618    struct svga_screen *svgascreen = svga_screen(screen);
 619    struct svga_winsys_screen *sws = svgascreen->sws;
 620
 621    assert(sws->have_vgpu10);
 622    (void) sws;  /* silence unused var warnings in non-debug builds */
 623
 624    /* Only VS, GS, FS supported */
 625    if (shader != PIPE_SHADER_VERTEX &&
 626        shader != PIPE_SHADER_GEOMETRY &&
 627        shader != PIPE_SHADER_FRAGMENT) {
 628       return 0;
 629    }
 630
 631    /* NOTE: we do not query the device for any caps/limits at this time */
 632
 633    /* Generally the same limits for vertex, geometry and fragment shaders */
 634    switch (param) {
 635    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 636    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 637    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 638    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 639       return 64 * 1024;
 640    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 641       return 64;
 642    case PIPE_SHADER_CAP_MAX_INPUTS:
 643       if (shader == PIPE_SHADER_FRAGMENT)
 644          return VGPU10_MAX_FS_INPUTS;
 645       else if (shader == PIPE_SHADER_GEOMETRY)
 646          return VGPU10_MAX_GS_INPUTS;
 647       else
 648          return VGPU10_MAX_VS_INPUTS;
 649    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 650       if (shader == PIPE_SHADER_FRAGMENT)
 651          return VGPU10_MAX_FS_OUTPUTS;
 652       else if (shader == PIPE_SHADER_GEOMETRY)
 653          return VGPU10_MAX_GS_OUTPUTS;
 654       else
 655          return VGPU10_MAX_VS_OUTPUTS;
 656    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 657       return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
 658    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 659       return svgascreen->max_const_buffers;
 660    case PIPE_SHADER_CAP_MAX_TEMPS:
 661       return VGPU10_MAX_TEMPS;
 662    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 663    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 664    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 665    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 666       return TRUE; /* XXX verify */
 667    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 668    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 669    case PIPE_SHADER_CAP_SUBROUTINES:
 670    case PIPE_SHADER_CAP_INTEGERS:
 671       return TRUE;
 672    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 673    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 674       return SVGA3D_DX_MAX_SAMPLERS;
 675    case PIPE_SHADER_CAP_PREFERRED_IR:
 676       return PIPE_SHADER_IR_TGSI;
 677    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 678          return 0;
 679    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 680    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 681    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 682    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 683    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 684    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 685    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 686    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 687       return 0;
 688    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 689       return 32;
 690    default:
 691       debug_printf("Unexpected vgpu10 shader query %u\n", param);
 692       return 0;
 693    }
 694    return 0;
 695 }
 696
 697
 698 static int
 699 svga_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
 700                       enum pipe_shader_cap param)
 701 {
 702    struct svga_screen *svgascreen = svga_screen(screen);
 703    struct svga_winsys_screen *sws = svgascreen->sws;
 704    if (sws->have_vgpu10) {
 705       return vgpu10_get_shader_param(screen, shader, param);
 706    }
 707    else {
 708       return vgpu9_get_shader_param(screen, shader, param);
 709    }
 710 }
 711
 712
 713 /**
 714  * Implement pipe_screen::is_format_supported().
 715  * \param bindings  bitmask of PIPE_BIND_x flags
 716  */
 717 static boolean
 718 svga_is_format_supported( struct pipe_screen *screen,
 719                           enum pipe_format format,
 720                           enum pipe_texture_target target,
 721                           unsigned sample_count,
 722                           unsigned bindings)
 723 {
 724    struct svga_screen *ss = svga_screen(screen);
 725    SVGA3dSurfaceFormat svga_format;
 726    SVGA3dSurfaceFormatCaps caps;
 727    SVGA3dSurfaceFormatCaps mask;
 728
 729    assert(bindings);
 730
 731    if (sample_count > 1) {
 732       /* In ms_samples, if bit N is set it means that we support
 733        * multisample with N+1 samples per pixel.
 734        */
 735       if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
 736          return FALSE;
 737       }
 738    }
 739
 740    svga_format = svga_translate_format(ss, format, bindings);
 741    if (svga_format == SVGA3D_FORMAT_INVALID) {
 742       return FALSE;
 743    }
 744
 745    /* we don't support sRGB rendering into display targets */
 746    if (util_format_is_srgb(format) && (bindings & PIPE_BIND_DISPLAY_TARGET)) {
 747       return FALSE;
 748    }
 749
 750    /*
 751     * For VGPU10 vertex formats, skip querying host capabilities
 752     */
 753
 754    if (ss->sws->have_vgpu10 && (bindings & PIPE_BIND_VERTEX_BUFFER)) {
 755       SVGA3dSurfaceFormat svga_format;
 756       unsigned flags;
 757       svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
 758       return svga_format != SVGA3D_FORMAT_INVALID;
 759    }
 760
 761    /*
 762     * Override host capabilities, so that we end up with the same
 763     * visuals for all virtual hardware implementations.
 764     */
 765
 766    if (bindings & PIPE_BIND_DISPLAY_TARGET) {
 767       switch (svga_format) {
 768       case SVGA3D_A8R8G8B8:
 769       case SVGA3D_X8R8G8B8:
 770       case SVGA3D_R5G6B5:
 771          break;
 772
 773       /* VGPU10 formats */
 774       case SVGA3D_B8G8R8A8_UNORM:
 775       case SVGA3D_B8G8R8X8_UNORM:
 776       case SVGA3D_B5G6R5_UNORM:
 777          break;
 778
 779       /* Often unsupported/problematic. This means we end up with the same
 780        * visuals for all virtual hardware implementations.
 781        */
 782       case SVGA3D_A4R4G4B4:
 783       case SVGA3D_A1R5G5B5:
 784          return FALSE;
 785
 786       default:
 787          return FALSE;
 788       }
 789    }
 790
 791    /*
 792     * Query the host capabilities.
 793     */
 794
 795    svga_get_format_cap(ss, svga_format, &caps);
 796
 797    if (bindings & PIPE_BIND_RENDER_TARGET) {
 798       /* Check that the color surface is blendable, unless it's an
 799        * integer format.
 800        */
 801       if (!svga_format_is_integer(svga_format) &&
 802           (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
 803          return FALSE;
 804       }
 805    }
 806
 807    mask.value = 0;
 808    if (bindings & PIPE_BIND_RENDER_TARGET) {
 809       mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
 810    }
 811    if (bindings & PIPE_BIND_DEPTH_STENCIL) {
 812       mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
 813    }
 814    if (bindings & PIPE_BIND_SAMPLER_VIEW) {
 815       mask.value |= SVGA3DFORMAT_OP_TEXTURE;
 816    }
 817
 818    if (target == PIPE_TEXTURE_CUBE) {
 819       mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
 820    }
 821    else if (target == PIPE_TEXTURE_3D) {
 822       mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
 823    }
 824
 825    return (caps.value & mask.value) == mask.value;
 826 }
 827
 828
 829 static void
 830 svga_fence_reference(struct pipe_screen *screen,
 831                      struct pipe_fence_handle **ptr,
 832                      struct pipe_fence_handle *fence)
 833 {
 834    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 835    sws->fence_reference(sws, ptr, fence);
 836 }
 837
 838
 839 static boolean
 840 svga_fence_finish(struct pipe_screen *screen,
 841                   struct pipe_context *ctx,
 842                   struct pipe_fence_handle *fence,
 843                   uint64_t timeout)
 844 {
 845    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 846    boolean retVal;
 847
 848    SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
 849
 850    if (!timeout) {
 851       retVal = sws->fence_signalled(sws, fence, 0) == 0;
 852    }
 853    else {
 854       SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
 855                __FUNCTION__, fence);
 856
 857       retVal = sws->fence_finish(sws, fence, 0) == 0;
 858    }
 859
 860    SVGA_STATS_TIME_POP(sws);
 861
 862    return retVal;
 863 }
 864
 865
 866 static int
 867 svga_get_driver_query_info(struct pipe_screen *screen,
 868                            unsigned index,
 869                            struct pipe_driver_query_info *info)
 870 {
 871 #define QUERY(NAME, ENUM, UNITS) \
 872    {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
 873
 874    static const struct pipe_driver_query_info queries[] = {
 875       /* per-frame counters */
 876       QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
 877             PIPE_DRIVER_QUERY_TYPE_UINT64),
 878       QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
 879             PIPE_DRIVER_QUERY_TYPE_UINT64),
 880       QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
 881             PIPE_DRIVER_QUERY_TYPE_UINT64),
 882       QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
 883             PIPE_DRIVER_QUERY_TYPE_UINT64),
 884       QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
 885             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 886       QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
 887             PIPE_DRIVER_QUERY_TYPE_UINT64),
 888       QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
 889             PIPE_DRIVER_QUERY_TYPE_UINT64),
 890       QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
 891             PIPE_DRIVER_QUERY_TYPE_BYTES),
 892       QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
 893             PIPE_DRIVER_QUERY_TYPE_BYTES),
 894       QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
 895             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 896       QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
 897             PIPE_DRIVER_QUERY_TYPE_UINT64),
 898       QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
 899             PIPE_DRIVER_QUERY_TYPE_UINT64),
 900       QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
 901             PIPE_DRIVER_QUERY_TYPE_UINT64),
 902       QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
 903             PIPE_DRIVER_QUERY_TYPE_UINT64),
 904       QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
 905             PIPE_DRIVER_QUERY_TYPE_UINT64),
 906       QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
 907             PIPE_DRIVER_QUERY_TYPE_UINT64),
 908
 909       /* running total counters */
 910       QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
 911             PIPE_DRIVER_QUERY_TYPE_BYTES),
 912       QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
 913             PIPE_DRIVER_QUERY_TYPE_UINT64),
 914       QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
 915             PIPE_DRIVER_QUERY_TYPE_UINT64),
 916       QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
 917             PIPE_DRIVER_QUERY_TYPE_UINT64),
 918       QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
 919             PIPE_DRIVER_QUERY_TYPE_UINT64),
 920       QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
 921             PIPE_DRIVER_QUERY_TYPE_UINT64),
 922       QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS,
 923             PIPE_DRIVER_QUERY_TYPE_UINT64),
 924    };
 925 #undef QUERY
 926
 927    if (!info)
 928       return ARRAY_SIZE(queries);
 929
 930    if (index >= ARRAY_SIZE(queries))
 931       return 0;
 932
 933    *info = queries[index];
 934    return 1;
 935 }
 936
 937
 938 static void
 939 init_logging(struct pipe_screen *screen)
 940 {
 941    static const char *log_prefix = "Mesa: ";
 942    char host_log[1000];
 943
 944    /* Log Version to Host */
 945    util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 946                  "%s%s", log_prefix, svga_get_name(screen));
 947    svga_host_log(host_log);
 948
 949    util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 950                  "%s%s (%s)", log_prefix, PACKAGE_VERSION, MESA_GIT_SHA1);
 951    svga_host_log(host_log);
 952
 953    /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
 954     * line (program name and arguments).
 955     */
 956    if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE)) {
 957       char cmdline[1000];
 958       if (os_get_command_line(cmdline, sizeof(cmdline))) {
 959          util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 960                        "%s%s", log_prefix, cmdline);
 961          svga_host_log(host_log);
 962       }
 963    }
 964 }
 965
 966
 967 static void
 968 svga_destroy_screen( struct pipe_screen *screen )
 969 {
 970    struct svga_screen *svgascreen = svga_screen(screen);
 971
 972    svga_screen_cache_cleanup(svgascreen);
 973
 974    mtx_destroy(&svgascreen->swc_mutex);
 975    mtx_destroy(&svgascreen->tex_mutex);
 976
 977    svgascreen->sws->destroy(svgascreen->sws);
 978
 979    FREE(svgascreen);
 980 }
 981
 982
 983 /**
 984  * Create a new svga_screen object
 985  */
 986 struct pipe_screen *
 987 svga_screen_create(struct svga_winsys_screen *sws)
 988 {
 989    struct svga_screen *svgascreen;
 990    struct pipe_screen *screen;
 991
 992 #ifdef DEBUG
 993    SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
 994 #endif
 995
 996    svgascreen = CALLOC_STRUCT(svga_screen);
 997    if (!svgascreen)
 998       goto error1;
 999
1000    svgascreen->debug.force_level_surface_view =
1001       debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
1002    svgascreen->debug.force_surface_view =
1003       debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
1004    svgascreen->debug.force_sampler_view =
1005       debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
1006    svgascreen->debug.no_surface_view =
1007       debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
1008    svgascreen->debug.no_sampler_view =
1009       debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
1010    svgascreen->debug.no_cache_index_buffers =
1011       debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
1012
1013    screen = &svgascreen->screen;
1014
1015    screen->destroy = svga_destroy_screen;
1016    screen->get_name = svga_get_name;
1017    screen->get_vendor = svga_get_vendor;
1018    screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
1019    screen->get_param = svga_get_param;
1020    screen->get_shader_param = svga_get_shader_param;
1021    screen->get_paramf = svga_get_paramf;
1022    screen->get_timestamp = NULL;
1023    screen->is_format_supported = svga_is_format_supported;
1024    screen->context_create = svga_context_create;
1025    screen->fence_reference = svga_fence_reference;
1026    screen->fence_finish = svga_fence_finish;
1027    screen->get_driver_query_info = svga_get_driver_query_info;
1028    svgascreen->sws = sws;
1029
1030    svga_init_screen_resource_functions(svgascreen);
1031
1032    if (sws->get_hw_version) {
1033       svgascreen->hw_version = sws->get_hw_version(sws);
1034    } else {
1035       svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
1036    }
1037
1038    if (svgascreen->hw_version < SVGA3D_HWVERSION_WS8_B1) {
1039       /* too old for 3D acceleration */
1040       debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
1041                    svgascreen->hw_version);
1042       goto error2;
1043    }
1044
1045    /*
1046     * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
1047     * when sampled from, where as the DF16, DF24, and D24S8_INT do not.  So
1048     * we prefer the later when available.
1049     *
1050     * This mimics hardware vendors extensions for D3D depth sampling. See also
1051     * http://aras-p.info/texts/D3D9GPUHacks.html
1052     */
1053
1054    {
1055       boolean has_df16, has_df24, has_d24s8_int;
1056       SVGA3dSurfaceFormatCaps caps;
1057       SVGA3dSurfaceFormatCaps mask;
1058       mask.value = 0;
1059       mask.zStencil = 1;
1060       mask.texture = 1;
1061
1062       svgascreen->depth.z16 = SVGA3D_Z_D16;
1063       svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
1064       svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
1065
1066       svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
1067       has_df16 = (caps.value & mask.value) == mask.value;
1068
1069       svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
1070       has_df24 = (caps.value & mask.value) == mask.value;
1071
1072       svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
1073       has_d24s8_int = (caps.value & mask.value) == mask.value;
1074
1075       /* XXX: We might want some other logic here.
1076        * Like if we only have d24s8_int we should
1077        * emulate the other formats with that.
1078        */
1079       if (has_df16) {
1080          svgascreen->depth.z16 = SVGA3D_Z_DF16;
1081       }
1082       if (has_df24) {
1083          svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1084       }
1085       if (has_d24s8_int) {
1086          svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1087       }
1088    }
1089
1090    /* Query device caps
1091     */
1092    if (sws->have_vgpu10) {
1093       svgascreen->haveProvokingVertex
1094          = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1095       svgascreen->haveLineSmooth = TRUE;
1096       svgascreen->maxPointSize = 80.0F;
1097       svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1098
1099       /* Multisample samples per pixel */
1100       if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
1101          svgascreen->ms_samples =
1102             get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
1103       }
1104
1105       /* Maximum number of constant buffers */
1106       svgascreen->max_const_buffers =
1107          get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1108       assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1109    }
1110    else {
1111       /* VGPU9 */
1112       unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1113                                      SVGA3DVSVERSION_NONE);
1114       unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1115                                      SVGA3DPSVERSION_NONE);
1116
1117       /* we require Shader model 3.0 or later */
1118       if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1119          goto error2;
1120       }
1121
1122       svgascreen->haveProvokingVertex = FALSE;
1123
1124       svgascreen->haveLineSmooth =
1125          get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1126
1127       svgascreen->maxPointSize =
1128          get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1129       /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1130       svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1131
1132       /* The SVGA3D device always supports 4 targets at this time, regardless
1133        * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1134        */
1135       svgascreen->max_color_buffers = 4;
1136
1137       /* Only support one constant buffer
1138        */
1139       svgascreen->max_const_buffers = 1;
1140
1141       /* No multisampling */
1142       svgascreen->ms_samples = 0;
1143    }
1144
1145    /* common VGPU9 / VGPU10 caps */
1146    svgascreen->haveLineStipple =
1147       get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1148
1149    svgascreen->maxLineWidth =
1150       MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f));
1151
1152    svgascreen->maxLineWidthAA =
1153       MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f));
1154
1155    if (0) {
1156       debug_printf("svga: haveProvokingVertex %u\n",
1157                    svgascreen->haveProvokingVertex);
1158       debug_printf("svga: haveLineStip %u  "
1159                    "haveLineSmooth %u  maxLineWidth %.2f  maxLineWidthAA %.2f\n",
1160                    svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1161                    svgascreen->maxLineWidth, svgascreen->maxLineWidthAA);
1162       debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1163       debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1164    }
1165
1166    (void) mtx_init(&svgascreen->tex_mutex, mtx_plain);
1167    (void) mtx_init(&svgascreen->swc_mutex, mtx_recursive);
1168
1169    svga_screen_cache_init(svgascreen);
1170
1171    init_logging(screen);
1172
1173    return screen;
1174 error2:
1175    FREE(svgascreen);
1176 error1:
1177    return NULL;
1178 }
1179
1180 struct svga_winsys_screen *
1181 svga_winsys_screen(struct pipe_screen *screen)
1182 {
1183    return svga_screen(screen)->sws;
1184 }
1185
1186 #ifdef DEBUG
1187 struct svga_screen *
1188 svga_screen(struct pipe_screen *screen)
1189 {
1190    assert(screen);
1191    assert(screen->destroy == svga_destroy_screen);
1192    return (struct svga_screen *)screen;
1193 }
1194 #endif