1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
27 #include "util/u_format.h"
28 #include "util/u_memory.h"
29 #include "util/u_inlines.h"
30 #include "util/u_string.h"
31 #include "util/u_math.h"
33 #include "os/os_process.h"
35 #include "svga_winsys.h"
36 #include "svga_public.h"
37 #include "svga_context.h"
38 #include "svga_format.h"
40 #include "svga_screen.h"
41 #include "svga_tgsi.h"
42 #include "svga_resource_texture.h"
43 #include "svga_resource.h"
44 #include "svga_debug.h"
46 #include "svga3d_shaderdefs.h"
47 #include "VGPU10ShaderTokens.h"
49 /* NOTE: this constant may get moved into a svga3d*.h header file */
50 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
53 #define MESA_GIT_SHA1 "(unknown git revision)"
59 static const struct debug_named_value svga_debug_flags
[] = {
60 { "dma", DEBUG_DMA
, NULL
},
61 { "tgsi", DEBUG_TGSI
, NULL
},
62 { "pipe", DEBUG_PIPE
, NULL
},
63 { "state", DEBUG_STATE
, NULL
},
64 { "screen", DEBUG_SCREEN
, NULL
},
65 { "tex", DEBUG_TEX
, NULL
},
66 { "swtnl", DEBUG_SWTNL
, NULL
},
67 { "const", DEBUG_CONSTS
, NULL
},
68 { "viewport", DEBUG_VIEWPORT
, NULL
},
69 { "views", DEBUG_VIEWS
, NULL
},
70 { "perf", DEBUG_PERF
, NULL
},
71 { "flush", DEBUG_FLUSH
, NULL
},
72 { "sync", DEBUG_SYNC
, NULL
},
73 { "cache", DEBUG_CACHE
, NULL
},
74 { "streamout", DEBUG_STREAMOUT
, NULL
},
75 { "query", DEBUG_QUERY
, NULL
},
76 { "samplers", DEBUG_SAMPLERS
, NULL
},
82 svga_get_vendor( struct pipe_screen
*pscreen
)
84 return "VMware, Inc.";
89 svga_get_name( struct pipe_screen
*pscreen
)
91 const char *build
= "", *llvm
= "", *mutex
= "";
92 static char name
[100];
94 /* Only return internal details in the DEBUG version:
96 build
= "build: DEBUG;";
97 mutex
= "mutex: " PIPE_ATOMIC
";";
98 #elif defined(VMX86_STATS)
99 build
= "build: OPT;";
101 build
= "build: RELEASE;";
107 util_snprintf(name
, sizeof(name
), "SVGA3D; %s %s %s", build
, mutex
, llvm
);
112 /** Helper for querying float-valued device cap */
114 get_float_cap(struct svga_winsys_screen
*sws
, unsigned cap
, float defaultVal
)
116 SVGA3dDevCapResult result
;
117 if (sws
->get_cap(sws
, cap
, &result
))
124 /** Helper for querying uint-valued device cap */
126 get_uint_cap(struct svga_winsys_screen
*sws
, unsigned cap
, unsigned defaultVal
)
128 SVGA3dDevCapResult result
;
129 if (sws
->get_cap(sws
, cap
, &result
))
136 /** Helper for querying boolean-valued device cap */
138 get_bool_cap(struct svga_winsys_screen
*sws
, unsigned cap
, boolean defaultVal
)
140 SVGA3dDevCapResult result
;
141 if (sws
->get_cap(sws
, cap
, &result
))
149 svga_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
151 struct svga_screen
*svgascreen
= svga_screen(screen
);
152 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
155 case PIPE_CAPF_MAX_LINE_WIDTH
:
156 return svgascreen
->maxLineWidth
;
157 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
158 return svgascreen
->maxLineWidthAA
;
160 case PIPE_CAPF_MAX_POINT_WIDTH
:
162 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
163 return svgascreen
->maxPointSize
;
165 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
166 return (float) get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY
, 4);
168 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
171 case PIPE_CAPF_GUARD_BAND_LEFT
:
172 case PIPE_CAPF_GUARD_BAND_TOP
:
173 case PIPE_CAPF_GUARD_BAND_RIGHT
:
174 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
178 debug_printf("Unexpected PIPE_CAPF_ query %u\n", param
);
184 svga_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
186 struct svga_screen
*svgascreen
= svga_screen(screen
);
187 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
188 SVGA3dDevCapResult result
;
191 case PIPE_CAP_NPOT_TEXTURES
:
192 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
193 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
195 case PIPE_CAP_TWO_SIDED_STENCIL
:
197 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
199 * "In virtually every OpenGL implementation and hardware,
200 * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
201 * http://www.opengl.org/wiki/Blending
203 return sws
->have_vgpu10
? 1 : 0;
204 case PIPE_CAP_ANISOTROPIC_FILTER
:
206 case PIPE_CAP_POINT_SPRITE
:
208 case PIPE_CAP_TGSI_TEXCOORD
:
210 case PIPE_CAP_MAX_RENDER_TARGETS
:
211 return svgascreen
->max_color_buffers
;
212 case PIPE_CAP_OCCLUSION_QUERY
:
214 case PIPE_CAP_QUERY_TIME_ELAPSED
:
216 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
217 return sws
->have_vgpu10
;
218 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
220 case PIPE_CAP_TEXTURE_SWIZZLE
:
222 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
224 case PIPE_CAP_USER_VERTEX_BUFFERS
:
226 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
228 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
231 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
233 unsigned levels
= SVGA_MAX_TEXTURE_LEVELS
;
234 if (sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH
, &result
))
235 levels
= MIN2(util_logbase2(result
.u
) + 1, levels
);
237 levels
= 12 /* 2048x2048 */;
238 if (sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT
, &result
))
239 levels
= MIN2(util_logbase2(result
.u
) + 1, levels
);
241 levels
= 12 /* 2048x2048 */;
245 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
246 if (!sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT
, &result
))
247 return 8; /* max 128x128x128 */
248 return MIN2(util_logbase2(result
.u
) + 1, SVGA_MAX_TEXTURE_LEVELS
);
250 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
252 * No mechanism to query the host, and at least limited to 2048x2048 on
255 return MIN2(screen
->get_param(screen
, PIPE_CAP_MAX_TEXTURE_2D_LEVELS
),
258 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
259 return sws
->have_vgpu10
? SVGA3D_MAX_SURFACE_ARRAYSIZE
: 0;
261 case PIPE_CAP_BLEND_EQUATION_SEPARATE
: /* req. for GL 1.5 */
264 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
266 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
267 return sws
->have_vgpu10
;
268 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
270 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
271 return !sws
->have_vgpu10
;
273 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
274 return 1; /* The color outputs of vertex shaders are not clamped */
275 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
276 return 0; /* The driver can't clamp vertex colors */
277 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
278 return 0; /* The driver can't clamp fragment colors */
280 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
281 return 1; /* expected for GL_ARB_framebuffer_object */
283 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
284 return sws
->have_vgpu10
? 330 : 120;
286 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
292 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
293 case PIPE_CAP_INDEP_BLEND_ENABLE
:
294 case PIPE_CAP_CONDITIONAL_RENDER
:
295 case PIPE_CAP_QUERY_TIMESTAMP
:
296 case PIPE_CAP_TGSI_INSTANCEID
:
297 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
298 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
299 case PIPE_CAP_FAKE_SW_MSAA
:
300 return sws
->have_vgpu10
;
302 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
303 return sws
->have_vgpu10
? SVGA3D_DX_MAX_SOTARGETS
: 0;
304 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
305 return sws
->have_vgpu10
? 4 : 0;
306 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
307 return sws
->have_vgpu10
? SVGA3D_MAX_STREAMOUT_DECLS
: 0;
308 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
309 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
311 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
312 return svgascreen
->ms_samples
? 1 : 0;
314 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
315 /* convert bytes to texels for the case of the largest texel
318 return SVGA3D_DX_MAX_RESOURCE_SIZE
/ (4 * sizeof(float));
320 case PIPE_CAP_MIN_TEXEL_OFFSET
:
321 return sws
->have_vgpu10
? VGPU10_MIN_TEXEL_FETCH_OFFSET
: 0;
322 case PIPE_CAP_MAX_TEXEL_OFFSET
:
323 return sws
->have_vgpu10
? VGPU10_MAX_TEXEL_FETCH_OFFSET
: 0;
325 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
326 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
329 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
330 return sws
->have_vgpu10
? 256 : 0;
331 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
332 return sws
->have_vgpu10
? 1024 : 0;
334 case PIPE_CAP_PRIMITIVE_RESTART
:
335 return 1; /* may be a sw fallback, depending on restart index */
337 case PIPE_CAP_GENERATE_MIPMAP
:
338 return sws
->have_generate_mipmap_cmd
;
340 case PIPE_CAP_NATIVE_FENCE_FD
:
341 return sws
->have_fence_fd
;
343 /* Unsupported features */
344 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
345 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
346 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
347 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
348 case PIPE_CAP_INDEP_BLEND_FUNC
:
349 case PIPE_CAP_TEXTURE_BARRIER
:
350 case PIPE_CAP_MAX_VERTEX_STREAMS
:
351 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
352 case PIPE_CAP_COMPUTE
:
353 case PIPE_CAP_START_INSTANCE
:
354 case PIPE_CAP_CUBE_MAP_ARRAY
:
355 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
356 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
357 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
358 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
359 case PIPE_CAP_TEXTURE_GATHER_SM5
:
360 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
361 case PIPE_CAP_TEXTURE_QUERY_LOD
:
362 case PIPE_CAP_SAMPLE_SHADING
:
363 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
364 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
365 case PIPE_CAP_DRAW_INDIRECT
:
366 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
367 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
368 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
369 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
370 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
371 case PIPE_CAP_CLIP_HALFZ
:
372 case PIPE_CAP_VERTEXID_NOBASE
:
373 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
374 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
375 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
376 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
377 case PIPE_CAP_INVALIDATE_BUFFER
:
378 case PIPE_CAP_STRING_MARKER
:
379 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
380 case PIPE_CAP_QUERY_MEMORY_INFO
:
381 case PIPE_CAP_PCI_GROUP
:
382 case PIPE_CAP_PCI_BUS
:
383 case PIPE_CAP_PCI_DEVICE
:
384 case PIPE_CAP_PCI_FUNCTION
:
385 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
387 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
389 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
390 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
391 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
392 return 1; /* need 4-byte alignment for all offsets and strides */
393 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
395 case PIPE_CAP_MAX_VIEWPORTS
:
397 case PIPE_CAP_ENDIANNESS
:
398 return PIPE_ENDIAN_LITTLE
;
400 case PIPE_CAP_VENDOR_ID
:
401 return 0x15ad; /* VMware Inc. */
402 case PIPE_CAP_DEVICE_ID
:
403 return 0x0405; /* assume SVGA II */
404 case PIPE_CAP_ACCELERATED
:
406 case PIPE_CAP_VIDEO_MEMORY
:
407 /* XXX: Query the host ? */
409 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
410 return sws
->have_vgpu10
;
411 case PIPE_CAP_CLEAR_TEXTURE
:
412 return sws
->have_vgpu10
;
414 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
415 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
416 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
417 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
418 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
419 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
420 case PIPE_CAP_TGSI_TXQS
:
421 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
422 case PIPE_CAP_SHAREABLE_SHADERS
:
423 case PIPE_CAP_DRAW_PARAMETERS
:
424 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
425 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
426 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
427 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
428 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
429 case PIPE_CAP_CULL_DISTANCE
:
430 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
431 case PIPE_CAP_TGSI_VOTE
:
432 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
433 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
434 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
435 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
436 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
437 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
438 case PIPE_CAP_TGSI_FS_FBFETCH
:
439 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
440 case PIPE_CAP_DOUBLES
:
442 case PIPE_CAP_INT64_DIVMOD
:
443 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
444 case PIPE_CAP_TGSI_CLOCK
:
445 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
446 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
447 case PIPE_CAP_TGSI_BALLOT
:
448 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
449 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
450 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
451 case PIPE_CAP_POST_DEPTH_COVERAGE
:
452 case PIPE_CAP_BINDLESS_TEXTURE
:
453 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
454 case PIPE_CAP_QUERY_SO_OVERFLOW
:
455 case PIPE_CAP_MEMOBJ
:
459 debug_printf("Unexpected PIPE_CAP_ query %u\n", param
);
465 vgpu9_get_shader_param(struct pipe_screen
*screen
,
466 enum pipe_shader_type shader
,
467 enum pipe_shader_cap param
)
469 struct svga_screen
*svgascreen
= svga_screen(screen
);
470 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
473 assert(!sws
->have_vgpu10
);
477 case PIPE_SHADER_FRAGMENT
:
480 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
481 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
482 return get_uint_cap(sws
,
483 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS
,
485 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
486 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
488 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
489 return SVGA3D_MAX_NESTING_LEVEL
;
490 case PIPE_SHADER_CAP_MAX_INPUTS
:
492 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
493 return svgascreen
->max_color_buffers
;
494 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
495 return 224 * sizeof(float[4]);
496 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
498 case PIPE_SHADER_CAP_MAX_TEMPS
:
499 val
= get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS
, 32);
500 return MIN2(val
, SVGA3D_TEMPREG_MAX
);
501 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
503 * Although PS 3.0 has some addressing abilities it can only represent
504 * loops that can be statically determined and unrolled. Given we can
505 * only handle a subset of the cases that the state tracker already
506 * does it is better to defer loop unrolling to the state tracker.
509 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
511 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
513 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
514 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
515 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
517 case PIPE_SHADER_CAP_SUBROUTINES
:
519 case PIPE_SHADER_CAP_INTEGERS
:
521 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
522 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
524 case PIPE_SHADER_CAP_PREFERRED_IR
:
525 return PIPE_SHADER_IR_TGSI
;
526 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
528 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
529 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
530 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
531 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
532 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
533 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
534 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
535 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
537 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
540 /* If we get here, we failed to handle a cap above */
541 debug_printf("Unexpected fragment shader query %u\n", param
);
543 case PIPE_SHADER_VERTEX
:
546 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
547 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
548 return get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS
,
550 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
551 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
552 /* XXX: until we have vertex texture support */
554 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
555 return SVGA3D_MAX_NESTING_LEVEL
;
556 case PIPE_SHADER_CAP_MAX_INPUTS
:
558 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
560 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
561 return 256 * sizeof(float[4]);
562 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
564 case PIPE_SHADER_CAP_MAX_TEMPS
:
565 val
= get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS
, 32);
566 return MIN2(val
, SVGA3D_TEMPREG_MAX
);
567 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
569 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
571 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
572 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
574 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
576 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
578 case PIPE_SHADER_CAP_SUBROUTINES
:
580 case PIPE_SHADER_CAP_INTEGERS
:
582 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
583 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
585 case PIPE_SHADER_CAP_PREFERRED_IR
:
586 return PIPE_SHADER_IR_TGSI
;
587 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
589 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
590 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
591 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
592 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
593 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
594 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
595 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
596 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
598 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
601 /* If we get here, we failed to handle a cap above */
602 debug_printf("Unexpected vertex shader query %u\n", param
);
604 case PIPE_SHADER_GEOMETRY
:
605 case PIPE_SHADER_COMPUTE
:
606 case PIPE_SHADER_TESS_CTRL
:
607 case PIPE_SHADER_TESS_EVAL
:
608 /* no support for geometry, tess or compute shaders at this time */
611 debug_printf("Unexpected shader type (%u) query\n", shader
);
619 vgpu10_get_shader_param(struct pipe_screen
*screen
,
620 enum pipe_shader_type shader
,
621 enum pipe_shader_cap param
)
623 struct svga_screen
*svgascreen
= svga_screen(screen
);
624 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
626 assert(sws
->have_vgpu10
);
627 (void) sws
; /* silence unused var warnings in non-debug builds */
629 /* Only VS, GS, FS supported */
630 if (shader
!= PIPE_SHADER_VERTEX
&&
631 shader
!= PIPE_SHADER_GEOMETRY
&&
632 shader
!= PIPE_SHADER_FRAGMENT
) {
636 /* NOTE: we do not query the device for any caps/limits at this time */
638 /* Generally the same limits for vertex, geometry and fragment shaders */
640 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
641 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
642 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
643 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
645 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
647 case PIPE_SHADER_CAP_MAX_INPUTS
:
648 if (shader
== PIPE_SHADER_FRAGMENT
)
649 return VGPU10_MAX_FS_INPUTS
;
650 else if (shader
== PIPE_SHADER_GEOMETRY
)
651 return VGPU10_MAX_GS_INPUTS
;
653 return VGPU10_MAX_VS_INPUTS
;
654 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
655 if (shader
== PIPE_SHADER_FRAGMENT
)
656 return VGPU10_MAX_FS_OUTPUTS
;
657 else if (shader
== PIPE_SHADER_GEOMETRY
)
658 return VGPU10_MAX_GS_OUTPUTS
;
660 return VGPU10_MAX_VS_OUTPUTS
;
661 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
662 return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT
* sizeof(float[4]);
663 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
664 return svgascreen
->max_const_buffers
;
665 case PIPE_SHADER_CAP_MAX_TEMPS
:
666 return VGPU10_MAX_TEMPS
;
667 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
668 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
669 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
670 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
671 return TRUE
; /* XXX verify */
672 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
673 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
674 case PIPE_SHADER_CAP_SUBROUTINES
:
675 case PIPE_SHADER_CAP_INTEGERS
:
677 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
678 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
679 return SVGA3D_DX_MAX_SAMPLERS
;
680 case PIPE_SHADER_CAP_PREFERRED_IR
:
681 return PIPE_SHADER_IR_TGSI
;
682 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
684 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
685 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
686 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
687 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
688 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
689 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
690 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
691 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
693 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
696 debug_printf("Unexpected vgpu10 shader query %u\n", param
);
704 svga_get_shader_param(struct pipe_screen
*screen
, enum pipe_shader_type shader
,
705 enum pipe_shader_cap param
)
707 struct svga_screen
*svgascreen
= svga_screen(screen
);
708 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
709 if (sws
->have_vgpu10
) {
710 return vgpu10_get_shader_param(screen
, shader
, param
);
713 return vgpu9_get_shader_param(screen
, shader
, param
);
719 * Implement pipe_screen::is_format_supported().
720 * \param bindings bitmask of PIPE_BIND_x flags
723 svga_is_format_supported( struct pipe_screen
*screen
,
724 enum pipe_format format
,
725 enum pipe_texture_target target
,
726 unsigned sample_count
,
729 struct svga_screen
*ss
= svga_screen(screen
);
730 SVGA3dSurfaceFormat svga_format
;
731 SVGA3dSurfaceFormatCaps caps
;
732 SVGA3dSurfaceFormatCaps mask
;
736 if (sample_count
> 1) {
737 /* In ms_samples, if bit N is set it means that we support
738 * multisample with N+1 samples per pixel.
740 if ((ss
->ms_samples
& (1 << (sample_count
- 1))) == 0) {
745 svga_format
= svga_translate_format(ss
, format
, bindings
);
746 if (svga_format
== SVGA3D_FORMAT_INVALID
) {
750 /* we don't support sRGB rendering into display targets */
751 if (util_format_is_srgb(format
) && (bindings
& PIPE_BIND_DISPLAY_TARGET
)) {
756 * For VGPU10 vertex formats, skip querying host capabilities
759 if (ss
->sws
->have_vgpu10
&& (bindings
& PIPE_BIND_VERTEX_BUFFER
)) {
760 SVGA3dSurfaceFormat svga_format
;
762 svga_translate_vertex_format_vgpu10(format
, &svga_format
, &flags
);
763 return svga_format
!= SVGA3D_FORMAT_INVALID
;
767 * Override host capabilities, so that we end up with the same
768 * visuals for all virtual hardware implementations.
771 if (bindings
& PIPE_BIND_DISPLAY_TARGET
) {
772 switch (svga_format
) {
773 case SVGA3D_A8R8G8B8
:
774 case SVGA3D_X8R8G8B8
:
779 case SVGA3D_B8G8R8A8_UNORM
:
780 case SVGA3D_B8G8R8X8_UNORM
:
781 case SVGA3D_B5G6R5_UNORM
:
784 /* Often unsupported/problematic. This means we end up with the same
785 * visuals for all virtual hardware implementations.
787 case SVGA3D_A4R4G4B4
:
788 case SVGA3D_A1R5G5B5
:
797 * Query the host capabilities.
800 svga_get_format_cap(ss
, svga_format
, &caps
);
802 if (bindings
& PIPE_BIND_RENDER_TARGET
) {
803 /* Check that the color surface is blendable, unless it's an
806 if (!svga_format_is_integer(svga_format
) &&
807 (caps
.value
& SVGA3DFORMAT_OP_NOALPHABLEND
)) {
813 if (bindings
& PIPE_BIND_RENDER_TARGET
) {
814 mask
.value
|= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
;
816 if (bindings
& PIPE_BIND_DEPTH_STENCIL
) {
817 mask
.value
|= SVGA3DFORMAT_OP_ZSTENCIL
;
819 if (bindings
& PIPE_BIND_SAMPLER_VIEW
) {
820 mask
.value
|= SVGA3DFORMAT_OP_TEXTURE
;
823 if (target
== PIPE_TEXTURE_CUBE
) {
824 mask
.value
|= SVGA3DFORMAT_OP_CUBETEXTURE
;
826 else if (target
== PIPE_TEXTURE_3D
) {
827 mask
.value
|= SVGA3DFORMAT_OP_VOLUMETEXTURE
;
830 return (caps
.value
& mask
.value
) == mask
.value
;
835 svga_fence_reference(struct pipe_screen
*screen
,
836 struct pipe_fence_handle
**ptr
,
837 struct pipe_fence_handle
*fence
)
839 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
840 sws
->fence_reference(sws
, ptr
, fence
);
845 svga_fence_finish(struct pipe_screen
*screen
,
846 struct pipe_context
*ctx
,
847 struct pipe_fence_handle
*fence
,
850 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
853 SVGA_STATS_TIME_PUSH(sws
, SVGA_STATS_TIME_FENCEFINISH
);
856 retVal
= sws
->fence_signalled(sws
, fence
, 0) == 0;
859 SVGA_DBG(DEBUG_DMA
|DEBUG_PERF
, "%s fence_ptr %p\n",
860 __FUNCTION__
, fence
);
862 retVal
= sws
->fence_finish(sws
, fence
, timeout
, 0) == 0;
865 SVGA_STATS_TIME_POP(sws
);
872 svga_fence_get_fd(struct pipe_screen
*screen
,
873 struct pipe_fence_handle
*fence
)
875 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
877 return sws
->fence_get_fd(sws
, fence
, TRUE
);
882 svga_get_driver_query_info(struct pipe_screen
*screen
,
884 struct pipe_driver_query_info
*info
)
886 #define QUERY(NAME, ENUM, UNITS) \
887 {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
889 static const struct pipe_driver_query_info queries
[] = {
890 /* per-frame counters */
891 QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS
,
892 PIPE_DRIVER_QUERY_TYPE_UINT64
),
893 QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS
,
894 PIPE_DRIVER_QUERY_TYPE_UINT64
),
895 QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES
,
896 PIPE_DRIVER_QUERY_TYPE_UINT64
),
897 QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS
,
898 PIPE_DRIVER_QUERY_TYPE_UINT64
),
899 QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME
,
900 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
),
901 QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED
,
902 PIPE_DRIVER_QUERY_TYPE_UINT64
),
903 QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED
,
904 PIPE_DRIVER_QUERY_TYPE_UINT64
),
905 QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED
,
906 PIPE_DRIVER_QUERY_TYPE_BYTES
),
907 QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE
,
908 PIPE_DRIVER_QUERY_TYPE_BYTES
),
909 QUERY("flush-time", SVGA_QUERY_FLUSH_TIME
,
910 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
),
911 QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES
,
912 PIPE_DRIVER_QUERY_TYPE_UINT64
),
913 QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS
,
914 PIPE_DRIVER_QUERY_TYPE_UINT64
),
915 QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES
,
916 PIPE_DRIVER_QUERY_TYPE_UINT64
),
917 QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS
,
918 PIPE_DRIVER_QUERY_TYPE_UINT64
),
919 QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES
,
920 PIPE_DRIVER_QUERY_TYPE_UINT64
),
921 QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES
,
922 PIPE_DRIVER_QUERY_TYPE_UINT64
),
924 /* running total counters */
925 QUERY("memory-used", SVGA_QUERY_MEMORY_USED
,
926 PIPE_DRIVER_QUERY_TYPE_BYTES
),
927 QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS
,
928 PIPE_DRIVER_QUERY_TYPE_UINT64
),
929 QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES
,
930 PIPE_DRIVER_QUERY_TYPE_UINT64
),
931 QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS
,
932 PIPE_DRIVER_QUERY_TYPE_UINT64
),
933 QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS
,
934 PIPE_DRIVER_QUERY_TYPE_UINT64
),
935 QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP
,
936 PIPE_DRIVER_QUERY_TYPE_UINT64
),
937 QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS
,
938 PIPE_DRIVER_QUERY_TYPE_UINT64
),
943 return ARRAY_SIZE(queries
);
945 if (index
>= ARRAY_SIZE(queries
))
948 *info
= queries
[index
];
954 init_logging(struct pipe_screen
*screen
)
956 static const char *log_prefix
= "Mesa: ";
959 /* Log Version to Host */
960 util_snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
961 "%s%s", log_prefix
, svga_get_name(screen
));
962 svga_host_log(host_log
);
964 util_snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
965 "%s%s (%s)", log_prefix
, PACKAGE_VERSION
, MESA_GIT_SHA1
);
966 svga_host_log(host_log
);
968 /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
969 * line (program name and arguments).
971 if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE
)) {
973 if (os_get_command_line(cmdline
, sizeof(cmdline
))) {
974 util_snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
975 "%s%s", log_prefix
, cmdline
);
976 svga_host_log(host_log
);
983 svga_destroy_screen( struct pipe_screen
*screen
)
985 struct svga_screen
*svgascreen
= svga_screen(screen
);
987 svga_screen_cache_cleanup(svgascreen
);
989 mtx_destroy(&svgascreen
->swc_mutex
);
990 mtx_destroy(&svgascreen
->tex_mutex
);
992 svgascreen
->sws
->destroy(svgascreen
->sws
);
999 * Create a new svga_screen object
1001 struct pipe_screen
*
1002 svga_screen_create(struct svga_winsys_screen
*sws
)
1004 struct svga_screen
*svgascreen
;
1005 struct pipe_screen
*screen
;
1008 SVGA_DEBUG
= debug_get_flags_option("SVGA_DEBUG", svga_debug_flags
, 0 );
1011 svgascreen
= CALLOC_STRUCT(svga_screen
);
1015 svgascreen
->debug
.force_level_surface_view
=
1016 debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE
);
1017 svgascreen
->debug
.force_surface_view
=
1018 debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE
);
1019 svgascreen
->debug
.force_sampler_view
=
1020 debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE
);
1021 svgascreen
->debug
.no_surface_view
=
1022 debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE
);
1023 svgascreen
->debug
.no_sampler_view
=
1024 debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE
);
1025 svgascreen
->debug
.no_cache_index_buffers
=
1026 debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE
);
1028 screen
= &svgascreen
->screen
;
1030 screen
->destroy
= svga_destroy_screen
;
1031 screen
->get_name
= svga_get_name
;
1032 screen
->get_vendor
= svga_get_vendor
;
1033 screen
->get_device_vendor
= svga_get_vendor
; // TODO actual device vendor
1034 screen
->get_param
= svga_get_param
;
1035 screen
->get_shader_param
= svga_get_shader_param
;
1036 screen
->get_paramf
= svga_get_paramf
;
1037 screen
->get_timestamp
= NULL
;
1038 screen
->is_format_supported
= svga_is_format_supported
;
1039 screen
->context_create
= svga_context_create
;
1040 screen
->fence_reference
= svga_fence_reference
;
1041 screen
->fence_finish
= svga_fence_finish
;
1042 screen
->fence_get_fd
= svga_fence_get_fd
;
1044 screen
->get_driver_query_info
= svga_get_driver_query_info
;
1045 svgascreen
->sws
= sws
;
1047 svga_init_screen_resource_functions(svgascreen
);
1049 if (sws
->get_hw_version
) {
1050 svgascreen
->hw_version
= sws
->get_hw_version(sws
);
1052 svgascreen
->hw_version
= SVGA3D_HWVERSION_WS65_B1
;
1055 if (svgascreen
->hw_version
< SVGA3D_HWVERSION_WS8_B1
) {
1056 /* too old for 3D acceleration */
1057 debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
1058 svgascreen
->hw_version
);
1063 * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
1064 * when sampled from, where as the DF16, DF24, and D24S8_INT do not. So
1065 * we prefer the later when available.
1067 * This mimics hardware vendors extensions for D3D depth sampling. See also
1068 * http://aras-p.info/texts/D3D9GPUHacks.html
1072 boolean has_df16
, has_df24
, has_d24s8_int
;
1073 SVGA3dSurfaceFormatCaps caps
;
1074 SVGA3dSurfaceFormatCaps mask
;
1079 svgascreen
->depth
.z16
= SVGA3D_Z_D16
;
1080 svgascreen
->depth
.x8z24
= SVGA3D_Z_D24X8
;
1081 svgascreen
->depth
.s8z24
= SVGA3D_Z_D24S8
;
1083 svga_get_format_cap(svgascreen
, SVGA3D_Z_DF16
, &caps
);
1084 has_df16
= (caps
.value
& mask
.value
) == mask
.value
;
1086 svga_get_format_cap(svgascreen
, SVGA3D_Z_DF24
, &caps
);
1087 has_df24
= (caps
.value
& mask
.value
) == mask
.value
;
1089 svga_get_format_cap(svgascreen
, SVGA3D_Z_D24S8_INT
, &caps
);
1090 has_d24s8_int
= (caps
.value
& mask
.value
) == mask
.value
;
1092 /* XXX: We might want some other logic here.
1093 * Like if we only have d24s8_int we should
1094 * emulate the other formats with that.
1097 svgascreen
->depth
.z16
= SVGA3D_Z_DF16
;
1100 svgascreen
->depth
.x8z24
= SVGA3D_Z_DF24
;
1102 if (has_d24s8_int
) {
1103 svgascreen
->depth
.s8z24
= SVGA3D_Z_D24S8_INT
;
1107 /* Query device caps
1109 if (sws
->have_vgpu10
) {
1110 svgascreen
->haveProvokingVertex
1111 = get_bool_cap(sws
, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX
, FALSE
);
1112 svgascreen
->haveLineSmooth
= TRUE
;
1113 svgascreen
->maxPointSize
= 80.0F
;
1114 svgascreen
->max_color_buffers
= SVGA3D_DX_MAX_RENDER_TARGETS
;
1116 /* Multisample samples per pixel */
1117 if (debug_get_bool_option("SVGA_MSAA", TRUE
)) {
1118 svgascreen
->ms_samples
=
1119 get_uint_cap(sws
, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES
, 0);
1122 /* We only support 4x, 8x, 16x MSAA */
1123 svgascreen
->ms_samples
&= ((1 << (4-1)) |
1127 /* Maximum number of constant buffers */
1128 svgascreen
->max_const_buffers
=
1129 get_uint_cap(sws
, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS
, 1);
1130 assert(svgascreen
->max_const_buffers
<= SVGA_MAX_CONST_BUFS
);
1134 unsigned vs_ver
= get_uint_cap(sws
, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION
,
1135 SVGA3DVSVERSION_NONE
);
1136 unsigned fs_ver
= get_uint_cap(sws
, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION
,
1137 SVGA3DPSVERSION_NONE
);
1139 /* we require Shader model 3.0 or later */
1140 if (fs_ver
< SVGA3DPSVERSION_30
|| vs_ver
< SVGA3DVSVERSION_30
) {
1144 svgascreen
->haveProvokingVertex
= FALSE
;
1146 svgascreen
->haveLineSmooth
=
1147 get_bool_cap(sws
, SVGA3D_DEVCAP_LINE_AA
, FALSE
);
1149 svgascreen
->maxPointSize
=
1150 get_float_cap(sws
, SVGA3D_DEVCAP_MAX_POINT_SIZE
, 1.0f
);
1151 /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1152 svgascreen
->maxPointSize
= MIN2(svgascreen
->maxPointSize
, 80.0f
);
1154 /* The SVGA3D device always supports 4 targets at this time, regardless
1155 * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1157 svgascreen
->max_color_buffers
= 4;
1159 /* Only support one constant buffer
1161 svgascreen
->max_const_buffers
= 1;
1163 /* No multisampling */
1164 svgascreen
->ms_samples
= 0;
1167 /* common VGPU9 / VGPU10 caps */
1168 svgascreen
->haveLineStipple
=
1169 get_bool_cap(sws
, SVGA3D_DEVCAP_LINE_STIPPLE
, FALSE
);
1171 svgascreen
->maxLineWidth
=
1172 MAX2(1.0, get_float_cap(sws
, SVGA3D_DEVCAP_MAX_LINE_WIDTH
, 1.0f
));
1174 svgascreen
->maxLineWidthAA
=
1175 MAX2(1.0, get_float_cap(sws
, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH
, 1.0f
));
1178 debug_printf("svga: haveProvokingVertex %u\n",
1179 svgascreen
->haveProvokingVertex
);
1180 debug_printf("svga: haveLineStip %u "
1181 "haveLineSmooth %u maxLineWidth %.2f maxLineWidthAA %.2f\n",
1182 svgascreen
->haveLineStipple
, svgascreen
->haveLineSmooth
,
1183 svgascreen
->maxLineWidth
, svgascreen
->maxLineWidthAA
);
1184 debug_printf("svga: maxPointSize %g\n", svgascreen
->maxPointSize
);
1185 debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen
->ms_samples
);
1188 (void) mtx_init(&svgascreen
->tex_mutex
, mtx_plain
);
1189 (void) mtx_init(&svgascreen
->swc_mutex
, mtx_recursive
);
1191 svga_screen_cache_init(svgascreen
);
1193 init_logging(screen
);
1202 struct svga_winsys_screen
*
1203 svga_winsys_screen(struct pipe_screen
*screen
)
1205 return svga_screen(screen
)->sws
;
1209 struct svga_screen
*
1210 svga_screen(struct pipe_screen
*screen
)
1213 assert(screen
->destroy
== svga_destroy_screen
);
1214 return (struct svga_screen
*)screen
;