src/gallium/drivers/svga/svga_screen.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "util/u_format.h"
  27 #include "util/u_memory.h"
  28 #include "util/u_inlines.h"
  29 #include "util/u_string.h"
  30 #include "util/u_math.h"
  31
  32 #include "svga_winsys.h"
  33 #include "svga_public.h"
  34 #include "svga_context.h"
  35 #include "svga_format.h"
  36 #include "svga_screen.h"
  37 #include "svga_tgsi.h"
  38 #include "svga_resource_texture.h"
  39 #include "svga_resource.h"
  40 #include "svga_debug.h"
  41
  42 #include "svga3d_shaderdefs.h"
  43 #include "VGPU10ShaderTokens.h"
  44
  45 /* NOTE: this constant may get moved into a svga3d*.h header file */
  46 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
  47
  48 #ifdef DEBUG
  49 int SVGA_DEBUG = 0;
  50
  51 static const struct debug_named_value svga_debug_flags[] = {
  52    { "dma",         DEBUG_DMA, NULL },
  53    { "tgsi",        DEBUG_TGSI, NULL },
  54    { "pipe",        DEBUG_PIPE, NULL },
  55    { "state",       DEBUG_STATE, NULL },
  56    { "screen",      DEBUG_SCREEN, NULL },
  57    { "tex",         DEBUG_TEX, NULL },
  58    { "swtnl",       DEBUG_SWTNL, NULL },
  59    { "const",       DEBUG_CONSTS, NULL },
  60    { "viewport",    DEBUG_VIEWPORT, NULL },
  61    { "views",       DEBUG_VIEWS, NULL },
  62    { "perf",        DEBUG_PERF, NULL },
  63    { "flush",       DEBUG_FLUSH, NULL },
  64    { "sync",        DEBUG_SYNC, NULL },
  65    { "cache",       DEBUG_CACHE, NULL },
  66    { "streamout",   DEBUG_STREAMOUT, NULL },
  67    { "query",       DEBUG_QUERY, NULL },
  68    { "samplers",    DEBUG_SAMPLERS, NULL },
  69    DEBUG_NAMED_VALUE_END
  70 };
  71 #endif
  72
  73 static const char *
  74 svga_get_vendor( struct pipe_screen *pscreen )
  75 {
  76    return "VMware, Inc.";
  77 }
  78
  79
  80 static const char *
  81 svga_get_name( struct pipe_screen *pscreen )
  82 {
  83    const char *build = "", *llvm = "", *mutex = "";
  84    static char name[100];
  85 #ifdef DEBUG
  86    /* Only return internal details in the DEBUG version:
  87     */
  88    build = "build: DEBUG;";
  89    mutex = "mutex: " PIPE_ATOMIC ";";
  90 #elif defined(VMX86_STATS)
  91    build = "build: OPT;";
  92 #else
  93    build = "build: RELEASE;";
  94 #endif
  95 #ifdef HAVE_LLVM
  96    llvm = "LLVM;";
  97 #endif
  98
  99    util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
 100    return name;
 101 }
 102
 103
 104 /** Helper for querying float-valued device cap */
 105 static float
 106 get_float_cap(struct svga_winsys_screen *sws, unsigned cap, float defaultVal)
 107 {
 108    SVGA3dDevCapResult result;
 109    if (sws->get_cap(sws, cap, &result))
 110       return result.f;
 111    else
 112       return defaultVal;
 113 }
 114
 115
 116 /** Helper for querying uint-valued device cap */
 117 static unsigned
 118 get_uint_cap(struct svga_winsys_screen *sws, unsigned cap, unsigned defaultVal)
 119 {
 120    SVGA3dDevCapResult result;
 121    if (sws->get_cap(sws, cap, &result))
 122       return result.u;
 123    else
 124       return defaultVal;
 125 }
 126
 127
 128 /** Helper for querying boolean-valued device cap */
 129 static boolean
 130 get_bool_cap(struct svga_winsys_screen *sws, unsigned cap, boolean defaultVal)
 131 {
 132    SVGA3dDevCapResult result;
 133    if (sws->get_cap(sws, cap, &result))
 134       return result.b;
 135    else
 136       return defaultVal;
 137 }
 138
 139
 140 static float
 141 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 142 {
 143    struct svga_screen *svgascreen = svga_screen(screen);
 144    struct svga_winsys_screen *sws = svgascreen->sws;
 145
 146    switch (param) {
 147    case PIPE_CAPF_MAX_LINE_WIDTH:
 148       return svgascreen->maxLineWidth;
 149    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 150       return svgascreen->maxLineWidthAA;
 151
 152    case PIPE_CAPF_MAX_POINT_WIDTH:
 153       /* fall-through */
 154    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 155       return svgascreen->maxPointSize;
 156
 157    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 158       return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
 159
 160    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 161       return 15.0;
 162
 163    case PIPE_CAPF_GUARD_BAND_LEFT:
 164    case PIPE_CAPF_GUARD_BAND_TOP:
 165    case PIPE_CAPF_GUARD_BAND_RIGHT:
 166    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 167       return 0.0;
 168    }
 169
 170    debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
 171    return 0;
 172 }
 173
 174
 175 static int
 176 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
 177 {
 178    struct svga_screen *svgascreen = svga_screen(screen);
 179    struct svga_winsys_screen *sws = svgascreen->sws;
 180    SVGA3dDevCapResult result;
 181
 182    switch (param) {
 183    case PIPE_CAP_NPOT_TEXTURES:
 184    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 185    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 186       return 1;
 187    case PIPE_CAP_TWO_SIDED_STENCIL:
 188       return 1;
 189    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 190       /*
 191        * "In virtually every OpenGL implementation and hardware,
 192        * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
 193        * http://www.opengl.org/wiki/Blending
 194        */
 195       return sws->have_vgpu10 ? 1 : 0;
 196    case PIPE_CAP_ANISOTROPIC_FILTER:
 197       return 1;
 198    case PIPE_CAP_POINT_SPRITE:
 199       return 1;
 200    case PIPE_CAP_TGSI_TEXCOORD:
 201       return 0;
 202    case PIPE_CAP_MAX_RENDER_TARGETS:
 203       return svgascreen->max_color_buffers;
 204    case PIPE_CAP_OCCLUSION_QUERY:
 205       return 1;
 206    case PIPE_CAP_QUERY_TIME_ELAPSED:
 207       return 0;
 208    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 209       return sws->have_vgpu10;
 210    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 211       return 1;
 212    case PIPE_CAP_TEXTURE_SWIZZLE:
 213       return 1;
 214    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 215       return 0;
 216    case PIPE_CAP_USER_VERTEX_BUFFERS:
 217       return 0;
 218    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 219       return 1;
 220    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 221       return 256;
 222
 223    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 224       {
 225          unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
 226          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
 227             levels = MIN2(util_logbase2(result.u) + 1, levels);
 228          else
 229             levels = 12 /* 2048x2048 */;
 230          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
 231             levels = MIN2(util_logbase2(result.u) + 1, levels);
 232          else
 233             levels = 12 /* 2048x2048 */;
 234          return levels;
 235       }
 236
 237    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 238       if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
 239          return 8;  /* max 128x128x128 */
 240       return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
 241
 242    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 243       /*
 244        * No mechanism to query the host, and at least limited to 2048x2048 on
 245        * certain hardware.
 246        */
 247       return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
 248                   12 /* 2048x2048 */);
 249
 250    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 251       return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
 252
 253    case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
 254       return 1;
 255
 256    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 257       return 1;
 258    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 259       return sws->have_vgpu10;
 260    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 261       return 0;
 262    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 263       return !sws->have_vgpu10;
 264
 265    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 266       return 1; /* The color outputs of vertex shaders are not clamped */
 267    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 268       return 0; /* The driver can't clamp vertex colors */
 269    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 270       return 0; /* The driver can't clamp fragment colors */
 271
 272    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 273       return 1; /* expected for GL_ARB_framebuffer_object */
 274
 275    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 276       return sws->have_vgpu10 ? 330 : 120;
 277
 278    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 279       return 0;
 280
 281    case PIPE_CAP_SM3:
 282       return 1;
 283
 284    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 285    case PIPE_CAP_INDEP_BLEND_ENABLE:
 286    case PIPE_CAP_CONDITIONAL_RENDER:
 287    case PIPE_CAP_QUERY_TIMESTAMP:
 288    case PIPE_CAP_TGSI_INSTANCEID:
 289    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 290    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 291    case PIPE_CAP_FAKE_SW_MSAA:
 292       return sws->have_vgpu10;
 293
 294    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 295       return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
 296    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 297       return sws->have_vgpu10 ? 4 : 0;
 298    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 299       return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
 300    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 301    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 302       return 0;
 303    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 304       return svgascreen->ms_samples ? 1 : 0;
 305
 306    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 307       return SVGA3D_DX_MAX_RESOURCE_SIZE;
 308
 309    case PIPE_CAP_MIN_TEXEL_OFFSET:
 310       return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
 311    case PIPE_CAP_MAX_TEXEL_OFFSET:
 312       return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
 313
 314    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 315    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 316       return 0;
 317
 318    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 319       return sws->have_vgpu10 ? 256 : 0;
 320    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 321       return sws->have_vgpu10 ? 1024 : 0;
 322
 323    case PIPE_CAP_PRIMITIVE_RESTART:
 324       return 1; /* may be a sw fallback, depending on restart index */
 325
 326    case PIPE_CAP_GENERATE_MIPMAP:
 327       return sws->have_generate_mipmap_cmd;
 328
 329    /* Unsupported features */
 330    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 331    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 332    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 333    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 334    case PIPE_CAP_INDEP_BLEND_FUNC:
 335    case PIPE_CAP_TEXTURE_BARRIER:
 336    case PIPE_CAP_MAX_VERTEX_STREAMS:
 337    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 338    case PIPE_CAP_COMPUTE:
 339    case PIPE_CAP_START_INSTANCE:
 340    case PIPE_CAP_CUBE_MAP_ARRAY:
 341    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 342    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 343    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 344    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 345    case PIPE_CAP_TEXTURE_GATHER_SM5:
 346    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 347    case PIPE_CAP_TEXTURE_QUERY_LOD:
 348    case PIPE_CAP_SAMPLE_SHADING:
 349    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 350    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 351    case PIPE_CAP_DRAW_INDIRECT:
 352    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 353    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 354    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 355    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 356    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 357    case PIPE_CAP_CLIP_HALFZ:
 358    case PIPE_CAP_VERTEXID_NOBASE:
 359    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 360    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 361    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 362    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 363    case PIPE_CAP_INVALIDATE_BUFFER:
 364    case PIPE_CAP_STRING_MARKER:
 365    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 366    case PIPE_CAP_QUERY_MEMORY_INFO:
 367    case PIPE_CAP_PCI_GROUP:
 368    case PIPE_CAP_PCI_BUS:
 369    case PIPE_CAP_PCI_DEVICE:
 370    case PIPE_CAP_PCI_FUNCTION:
 371    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 372    case PIPE_CAP_NATIVE_FENCE_FD:
 373       return 0;
 374    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 375       return 64;
 376    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 377    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 378    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 379       return 1;  /* need 4-byte alignment for all offsets and strides */
 380    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 381       return 2048;
 382    case PIPE_CAP_MAX_VIEWPORTS:
 383       return 1;
 384    case PIPE_CAP_ENDIANNESS:
 385       return PIPE_ENDIAN_LITTLE;
 386
 387    case PIPE_CAP_VENDOR_ID:
 388       return 0x15ad; /* VMware Inc. */
 389    case PIPE_CAP_DEVICE_ID:
 390       return 0x0405; /* assume SVGA II */
 391    case PIPE_CAP_ACCELERATED:
 392       return 0; /* XXX: */
 393    case PIPE_CAP_VIDEO_MEMORY:
 394       /* XXX: Query the host ? */
 395       return 1;
 396    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 397       return sws->have_vgpu10;
 398    case PIPE_CAP_CLEAR_TEXTURE:
 399       return sws->have_vgpu10;
 400    case PIPE_CAP_UMA:
 401    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 402    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 403    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 404    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 405    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 406    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 407    case PIPE_CAP_TGSI_TXQS:
 408    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 409    case PIPE_CAP_SHAREABLE_SHADERS:
 410    case PIPE_CAP_DRAW_PARAMETERS:
 411    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 412    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 413    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 414    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 415    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 416    case PIPE_CAP_CULL_DISTANCE:
 417    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 418    case PIPE_CAP_TGSI_VOTE:
 419    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 420    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 421    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 422    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 423    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 424    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 425    case PIPE_CAP_TGSI_FS_FBFETCH:
 426    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 427    case PIPE_CAP_DOUBLES:
 428    case PIPE_CAP_INT64:
 429    case PIPE_CAP_INT64_DIVMOD:
 430    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 431    case PIPE_CAP_TGSI_CLOCK:
 432    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 433    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 434    case PIPE_CAP_TGSI_BALLOT:
 435    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 436    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 437    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 438       return 0;
 439    }
 440
 441    debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
 442    return 0;
 443 }
 444
 445
 446 static int
 447 vgpu9_get_shader_param(struct pipe_screen *screen,
 448                        enum pipe_shader_type shader,
 449                        enum pipe_shader_cap param)
 450 {
 451    struct svga_screen *svgascreen = svga_screen(screen);
 452    struct svga_winsys_screen *sws = svgascreen->sws;
 453    unsigned val;
 454
 455    assert(!sws->have_vgpu10);
 456
 457    switch (shader)
 458    {
 459    case PIPE_SHADER_FRAGMENT:
 460       switch (param)
 461       {
 462       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 463       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 464          return get_uint_cap(sws,
 465                              SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
 466                              512);
 467       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 468       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 469          return 512;
 470       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 471          return SVGA3D_MAX_NESTING_LEVEL;
 472       case PIPE_SHADER_CAP_MAX_INPUTS:
 473          return 10;
 474       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 475          return svgascreen->max_color_buffers;
 476       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 477          return 224 * sizeof(float[4]);
 478       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 479          return 1;
 480       case PIPE_SHADER_CAP_MAX_TEMPS:
 481          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
 482          return MIN2(val, SVGA3D_TEMPREG_MAX);
 483       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 484          /*
 485           * Although PS 3.0 has some addressing abilities it can only represent
 486           * loops that can be statically determined and unrolled. Given we can
 487           * only handle a subset of the cases that the state tracker already
 488           * does it is better to defer loop unrolling to the state tracker.
 489           */
 490          return 0;
 491       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 492          return 0;
 493       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 494          return 0;
 495       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 496       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 497       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 498          return 0;
 499       case PIPE_SHADER_CAP_SUBROUTINES:
 500          return 0;
 501       case PIPE_SHADER_CAP_INTEGERS:
 502          return 0;
 503       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 504       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 505          return 16;
 506       case PIPE_SHADER_CAP_PREFERRED_IR:
 507          return PIPE_SHADER_IR_TGSI;
 508       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 509          return 0;
 510       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 511       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 512       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 513       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 514       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 515       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 516       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 517       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 518          return 0;
 519       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 520          return 32;
 521       }
 522       /* If we get here, we failed to handle a cap above */
 523       debug_printf("Unexpected fragment shader query %u\n", param);
 524       return 0;
 525    case PIPE_SHADER_VERTEX:
 526       switch (param)
 527       {
 528       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 529       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 530          return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
 531                              512);
 532       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 533       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 534          /* XXX: until we have vertex texture support */
 535          return 0;
 536       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 537          return SVGA3D_MAX_NESTING_LEVEL;
 538       case PIPE_SHADER_CAP_MAX_INPUTS:
 539          return 16;
 540       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 541          return 10;
 542       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 543          return 256 * sizeof(float[4]);
 544       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 545          return 1;
 546       case PIPE_SHADER_CAP_MAX_TEMPS:
 547          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
 548          return MIN2(val, SVGA3D_TEMPREG_MAX);
 549       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 550          return 0;
 551       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 552          return 0;
 553       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 554       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 555          return 1;
 556       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 557          return 0;
 558       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 559          return 1;
 560       case PIPE_SHADER_CAP_SUBROUTINES:
 561          return 0;
 562       case PIPE_SHADER_CAP_INTEGERS:
 563          return 0;
 564       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 565       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 566          return 0;
 567       case PIPE_SHADER_CAP_PREFERRED_IR:
 568          return PIPE_SHADER_IR_TGSI;
 569       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 570          return 0;
 571       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 572       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 573       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 574       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 575       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 576       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 577       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 578       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 579          return 0;
 580       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 581          return 32;
 582       }
 583       /* If we get here, we failed to handle a cap above */
 584       debug_printf("Unexpected vertex shader query %u\n", param);
 585       return 0;
 586    case PIPE_SHADER_GEOMETRY:
 587    case PIPE_SHADER_COMPUTE:
 588    case PIPE_SHADER_TESS_CTRL:
 589    case PIPE_SHADER_TESS_EVAL:
 590       /* no support for geometry, tess or compute shaders at this time */
 591       return 0;
 592    default:
 593       debug_printf("Unexpected shader type (%u) query\n", shader);
 594       return 0;
 595    }
 596    return 0;
 597 }
 598
 599
 600 static int
 601 vgpu10_get_shader_param(struct pipe_screen *screen,
 602                         enum pipe_shader_type shader,
 603                         enum pipe_shader_cap param)
 604 {
 605    struct svga_screen *svgascreen = svga_screen(screen);
 606    struct svga_winsys_screen *sws = svgascreen->sws;
 607
 608    assert(sws->have_vgpu10);
 609    (void) sws;  /* silence unused var warnings in non-debug builds */
 610
 611    /* Only VS, GS, FS supported */
 612    if (shader != PIPE_SHADER_VERTEX &&
 613        shader != PIPE_SHADER_GEOMETRY &&
 614        shader != PIPE_SHADER_FRAGMENT) {
 615       return 0;
 616    }
 617
 618    /* NOTE: we do not query the device for any caps/limits at this time */
 619
 620    /* Generally the same limits for vertex, geometry and fragment shaders */
 621    switch (param) {
 622    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 623    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 624    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 625    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 626       return 64 * 1024;
 627    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 628       return 64;
 629    case PIPE_SHADER_CAP_MAX_INPUTS:
 630       if (shader == PIPE_SHADER_FRAGMENT)
 631          return VGPU10_MAX_FS_INPUTS;
 632       else if (shader == PIPE_SHADER_GEOMETRY)
 633          return VGPU10_MAX_GS_INPUTS;
 634       else
 635          return VGPU10_MAX_VS_INPUTS;
 636    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 637       if (shader == PIPE_SHADER_FRAGMENT)
 638          return VGPU10_MAX_FS_OUTPUTS;
 639       else if (shader == PIPE_SHADER_GEOMETRY)
 640          return VGPU10_MAX_GS_OUTPUTS;
 641       else
 642          return VGPU10_MAX_VS_OUTPUTS;
 643    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 644       return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
 645    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 646       return svgascreen->max_const_buffers;
 647    case PIPE_SHADER_CAP_MAX_TEMPS:
 648       return VGPU10_MAX_TEMPS;
 649    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 650    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 651    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 652    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 653       return TRUE; /* XXX verify */
 654    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 655    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 656    case PIPE_SHADER_CAP_SUBROUTINES:
 657    case PIPE_SHADER_CAP_INTEGERS:
 658       return TRUE;
 659    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 660    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 661       return SVGA3D_DX_MAX_SAMPLERS;
 662    case PIPE_SHADER_CAP_PREFERRED_IR:
 663       return PIPE_SHADER_IR_TGSI;
 664    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 665          return 0;
 666    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 667    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 668    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 669    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 670    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 671    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 672    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 673    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 674       return 0;
 675    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 676       return 32;
 677    default:
 678       debug_printf("Unexpected vgpu10 shader query %u\n", param);
 679       return 0;
 680    }
 681    return 0;
 682 }
 683
 684
 685 static int
 686 svga_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
 687                       enum pipe_shader_cap param)
 688 {
 689    struct svga_screen *svgascreen = svga_screen(screen);
 690    struct svga_winsys_screen *sws = svgascreen->sws;
 691    if (sws->have_vgpu10) {
 692       return vgpu10_get_shader_param(screen, shader, param);
 693    }
 694    else {
 695       return vgpu9_get_shader_param(screen, shader, param);
 696    }
 697 }
 698
 699
 700 /**
 701  * Implement pipe_screen::is_format_supported().
 702  * \param bindings  bitmask of PIPE_BIND_x flags
 703  */
 704 static boolean
 705 svga_is_format_supported( struct pipe_screen *screen,
 706                           enum pipe_format format,
 707                           enum pipe_texture_target target,
 708                           unsigned sample_count,
 709                           unsigned bindings)
 710 {
 711    struct svga_screen *ss = svga_screen(screen);
 712    SVGA3dSurfaceFormat svga_format;
 713    SVGA3dSurfaceFormatCaps caps;
 714    SVGA3dSurfaceFormatCaps mask;
 715
 716    assert(bindings);
 717
 718    if (sample_count > 1) {
 719       /* In ms_samples, if bit N is set it means that we support
 720        * multisample with N+1 samples per pixel.
 721        */
 722       if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
 723          return FALSE;
 724       }
 725    }
 726
 727    svga_format = svga_translate_format(ss, format, bindings);
 728    if (svga_format == SVGA3D_FORMAT_INVALID) {
 729       return FALSE;
 730    }
 731
 732    /* we don't support sRGB rendering into display targets */
 733    if (util_format_is_srgb(format) && (bindings & PIPE_BIND_DISPLAY_TARGET)) {
 734       return FALSE;
 735    }
 736
 737    /*
 738     * For VGPU10 vertex formats, skip querying host capabilities
 739     */
 740
 741    if (ss->sws->have_vgpu10 && (bindings & PIPE_BIND_VERTEX_BUFFER)) {
 742       SVGA3dSurfaceFormat svga_format;
 743       unsigned flags;
 744       svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
 745       return svga_format != SVGA3D_FORMAT_INVALID;
 746    }
 747
 748    /*
 749     * Override host capabilities, so that we end up with the same
 750     * visuals for all virtual hardware implementations.
 751     */
 752
 753    if (bindings & PIPE_BIND_DISPLAY_TARGET) {
 754       switch (svga_format) {
 755       case SVGA3D_A8R8G8B8:
 756       case SVGA3D_X8R8G8B8:
 757       case SVGA3D_R5G6B5:
 758          break;
 759
 760       /* VGPU10 formats */
 761       case SVGA3D_B8G8R8A8_UNORM:
 762       case SVGA3D_B8G8R8X8_UNORM:
 763       case SVGA3D_B5G6R5_UNORM:
 764          break;
 765
 766       /* Often unsupported/problematic. This means we end up with the same
 767        * visuals for all virtual hardware implementations.
 768        */
 769       case SVGA3D_A4R4G4B4:
 770       case SVGA3D_A1R5G5B5:
 771          return FALSE;
 772
 773       default:
 774          return FALSE;
 775       }
 776    }
 777
 778    /*
 779     * Query the host capabilities.
 780     */
 781
 782    svga_get_format_cap(ss, svga_format, &caps);
 783
 784    if (bindings & PIPE_BIND_RENDER_TARGET) {
 785       /* Check that the color surface is blendable, unless it's an
 786        * integer format.
 787        */
 788       if (!svga_format_is_integer(svga_format) &&
 789           (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
 790          return FALSE;
 791       }
 792    }
 793
 794    mask.value = 0;
 795    if (bindings & PIPE_BIND_RENDER_TARGET) {
 796       mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
 797    }
 798    if (bindings & PIPE_BIND_DEPTH_STENCIL) {
 799       mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
 800    }
 801    if (bindings & PIPE_BIND_SAMPLER_VIEW) {
 802       mask.value |= SVGA3DFORMAT_OP_TEXTURE;
 803    }
 804
 805    if (target == PIPE_TEXTURE_CUBE) {
 806       mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
 807    }
 808    else if (target == PIPE_TEXTURE_3D) {
 809       mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
 810    }
 811
 812    return (caps.value & mask.value) == mask.value;
 813 }
 814
 815
 816 static void
 817 svga_fence_reference(struct pipe_screen *screen,
 818                      struct pipe_fence_handle **ptr,
 819                      struct pipe_fence_handle *fence)
 820 {
 821    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 822    sws->fence_reference(sws, ptr, fence);
 823 }
 824
 825
 826 static boolean
 827 svga_fence_finish(struct pipe_screen *screen,
 828                   struct pipe_context *ctx,
 829                   struct pipe_fence_handle *fence,
 830                   uint64_t timeout)
 831 {
 832    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 833    boolean retVal;
 834
 835    SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
 836
 837    if (!timeout) {
 838       retVal = sws->fence_signalled(sws, fence, 0) == 0;
 839    }
 840    else {
 841       SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
 842                __FUNCTION__, fence);
 843
 844       retVal = sws->fence_finish(sws, fence, 0) == 0;
 845    }
 846
 847    SVGA_STATS_TIME_POP(sws);
 848
 849    return retVal;
 850 }
 851
 852
 853 static int
 854 svga_get_driver_query_info(struct pipe_screen *screen,
 855                            unsigned index,
 856                            struct pipe_driver_query_info *info)
 857 {
 858 #define QUERY(NAME, ENUM, UNITS) \
 859    {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
 860
 861    static const struct pipe_driver_query_info queries[] = {
 862       /* per-frame counters */
 863       QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
 864             PIPE_DRIVER_QUERY_TYPE_UINT64),
 865       QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
 866             PIPE_DRIVER_QUERY_TYPE_UINT64),
 867       QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
 868             PIPE_DRIVER_QUERY_TYPE_UINT64),
 869       QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
 870             PIPE_DRIVER_QUERY_TYPE_UINT64),
 871       QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
 872             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 873       QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
 874             PIPE_DRIVER_QUERY_TYPE_UINT64),
 875       QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
 876             PIPE_DRIVER_QUERY_TYPE_UINT64),
 877       QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
 878             PIPE_DRIVER_QUERY_TYPE_BYTES),
 879       QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
 880             PIPE_DRIVER_QUERY_TYPE_BYTES),
 881       QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
 882             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 883       QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
 884             PIPE_DRIVER_QUERY_TYPE_UINT64),
 885       QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
 886             PIPE_DRIVER_QUERY_TYPE_UINT64),
 887       QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
 888             PIPE_DRIVER_QUERY_TYPE_UINT64),
 889       QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
 890             PIPE_DRIVER_QUERY_TYPE_UINT64),
 891       QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
 892             PIPE_DRIVER_QUERY_TYPE_UINT64),
 893       QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
 894             PIPE_DRIVER_QUERY_TYPE_UINT64),
 895
 896       /* running total counters */
 897       QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
 898             PIPE_DRIVER_QUERY_TYPE_BYTES),
 899       QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
 900             PIPE_DRIVER_QUERY_TYPE_UINT64),
 901       QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
 902             PIPE_DRIVER_QUERY_TYPE_UINT64),
 903       QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
 904             PIPE_DRIVER_QUERY_TYPE_UINT64),
 905       QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
 906             PIPE_DRIVER_QUERY_TYPE_UINT64),
 907       QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
 908             PIPE_DRIVER_QUERY_TYPE_UINT64),
 909    };
 910 #undef QUERY
 911
 912    if (!info)
 913       return ARRAY_SIZE(queries);
 914
 915    if (index >= ARRAY_SIZE(queries))
 916       return 0;
 917
 918    *info = queries[index];
 919    return 1;
 920 }
 921
 922
 923 static void
 924 svga_destroy_screen( struct pipe_screen *screen )
 925 {
 926    struct svga_screen *svgascreen = svga_screen(screen);
 927
 928    svga_screen_cache_cleanup(svgascreen);
 929
 930    mtx_destroy(&svgascreen->swc_mutex);
 931    mtx_destroy(&svgascreen->tex_mutex);
 932
 933    svgascreen->sws->destroy(svgascreen->sws);
 934
 935    FREE(svgascreen);
 936 }
 937
 938
 939 /**
 940  * Create a new svga_screen object
 941  */
 942 struct pipe_screen *
 943 svga_screen_create(struct svga_winsys_screen *sws)
 944 {
 945    struct svga_screen *svgascreen;
 946    struct pipe_screen *screen;
 947
 948 #ifdef DEBUG
 949    SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
 950 #endif
 951
 952    svgascreen = CALLOC_STRUCT(svga_screen);
 953    if (!svgascreen)
 954       goto error1;
 955
 956    svgascreen->debug.force_level_surface_view =
 957       debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
 958    svgascreen->debug.force_surface_view =
 959       debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
 960    svgascreen->debug.force_sampler_view =
 961       debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
 962    svgascreen->debug.no_surface_view =
 963       debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
 964    svgascreen->debug.no_sampler_view =
 965       debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
 966    svgascreen->debug.no_cache_index_buffers =
 967       debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
 968
 969    screen = &svgascreen->screen;
 970
 971    screen->destroy = svga_destroy_screen;
 972    screen->get_name = svga_get_name;
 973    screen->get_vendor = svga_get_vendor;
 974    screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
 975    screen->get_param = svga_get_param;
 976    screen->get_shader_param = svga_get_shader_param;
 977    screen->get_paramf = svga_get_paramf;
 978    screen->get_timestamp = NULL;
 979    screen->is_format_supported = svga_is_format_supported;
 980    screen->context_create = svga_context_create;
 981    screen->fence_reference = svga_fence_reference;
 982    screen->fence_finish = svga_fence_finish;
 983    screen->get_driver_query_info = svga_get_driver_query_info;
 984    svgascreen->sws = sws;
 985
 986    svga_init_screen_resource_functions(svgascreen);
 987
 988    if (sws->get_hw_version) {
 989       svgascreen->hw_version = sws->get_hw_version(sws);
 990    } else {
 991       svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
 992    }
 993
 994    if (svgascreen->hw_version < SVGA3D_HWVERSION_WS8_B1) {
 995       /* too old for 3D acceleration */
 996       debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
 997                    svgascreen->hw_version);
 998       goto error2;
 999    }
1000
1001    /*
1002     * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
1003     * when sampled from, where as the DF16, DF24, and D24S8_INT do not.  So
1004     * we prefer the later when available.
1005     *
1006     * This mimics hardware vendors extensions for D3D depth sampling. See also
1007     * http://aras-p.info/texts/D3D9GPUHacks.html
1008     */
1009
1010    {
1011       boolean has_df16, has_df24, has_d24s8_int;
1012       SVGA3dSurfaceFormatCaps caps;
1013       SVGA3dSurfaceFormatCaps mask;
1014       mask.value = 0;
1015       mask.zStencil = 1;
1016       mask.texture = 1;
1017
1018       svgascreen->depth.z16 = SVGA3D_Z_D16;
1019       svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
1020       svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
1021
1022       svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
1023       has_df16 = (caps.value & mask.value) == mask.value;
1024
1025       svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
1026       has_df24 = (caps.value & mask.value) == mask.value;
1027
1028       svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
1029       has_d24s8_int = (caps.value & mask.value) == mask.value;
1030
1031       /* XXX: We might want some other logic here.
1032        * Like if we only have d24s8_int we should
1033        * emulate the other formats with that.
1034        */
1035       if (has_df16) {
1036          svgascreen->depth.z16 = SVGA3D_Z_DF16;
1037       }
1038       if (has_df24) {
1039          svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1040       }
1041       if (has_d24s8_int) {
1042          svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1043       }
1044    }
1045
1046    /* Query device caps
1047     */
1048    if (sws->have_vgpu10) {
1049       svgascreen->haveProvokingVertex
1050          = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1051       svgascreen->haveLineSmooth = TRUE;
1052       svgascreen->maxPointSize = 80.0F;
1053       svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1054
1055       /* Multisample samples per pixel */
1056       if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
1057          svgascreen->ms_samples =
1058             get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
1059       }
1060
1061       /* Maximum number of constant buffers */
1062       svgascreen->max_const_buffers =
1063          get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1064       assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1065    }
1066    else {
1067       /* VGPU9 */
1068       unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1069                                      SVGA3DVSVERSION_NONE);
1070       unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1071                                      SVGA3DPSVERSION_NONE);
1072
1073       /* we require Shader model 3.0 or later */
1074       if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1075          goto error2;
1076       }
1077
1078       svgascreen->haveProvokingVertex = FALSE;
1079
1080       svgascreen->haveLineSmooth =
1081          get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1082
1083       svgascreen->maxPointSize =
1084          get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1085       /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1086       svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1087
1088       /* The SVGA3D device always supports 4 targets at this time, regardless
1089        * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1090        */
1091       svgascreen->max_color_buffers = 4;
1092
1093       /* Only support one constant buffer
1094        */
1095       svgascreen->max_const_buffers = 1;
1096
1097       /* No multisampling */
1098       svgascreen->ms_samples = 0;
1099    }
1100
1101    /* common VGPU9 / VGPU10 caps */
1102    svgascreen->haveLineStipple =
1103       get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1104
1105    svgascreen->maxLineWidth =
1106       get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f);
1107
1108    svgascreen->maxLineWidthAA =
1109       get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f);
1110
1111    if (0) {
1112       debug_printf("svga: haveProvokingVertex %u\n",
1113                    svgascreen->haveProvokingVertex);
1114       debug_printf("svga: haveLineStip %u  "
1115                    "haveLineSmooth %u  maxLineWidth %f\n",
1116                    svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1117                    svgascreen->maxLineWidth);
1118       debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1119       debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1120    }
1121
1122    (void) mtx_init(&svgascreen->tex_mutex, mtx_plain);
1123    (void) mtx_init(&svgascreen->swc_mutex, mtx_plain);
1124
1125    svga_screen_cache_init(svgascreen);
1126
1127    return screen;
1128 error2:
1129    FREE(svgascreen);
1130 error1:
1131    return NULL;
1132 }
1133
1134 struct svga_winsys_screen *
1135 svga_winsys_screen(struct pipe_screen *screen)
1136 {
1137    return svga_screen(screen)->sws;
1138 }
1139
1140 #ifdef DEBUG
1141 struct svga_screen *
1142 svga_screen(struct pipe_screen *screen)
1143 {
1144    assert(screen);
1145    assert(screen->destroy == svga_destroy_screen);
1146    return (struct svga_screen *)screen;
1147 }
1148 #endif