src/gallium/drivers/svga/svga_screen.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "util/u_format.h"
  27 #include "util/u_memory.h"
  28 #include "util/u_inlines.h"
  29 #include "util/u_string.h"
  30 #include "util/u_math.h"
  31
  32 #include "svga_winsys.h"
  33 #include "svga_public.h"
  34 #include "svga_context.h"
  35 #include "svga_format.h"
  36 #include "svga_screen.h"
  37 #include "svga_tgsi.h"
  38 #include "svga_resource_texture.h"
  39 #include "svga_resource.h"
  40 #include "svga_debug.h"
  41
  42 #include "svga3d_shaderdefs.h"
  43 #include "VGPU10ShaderTokens.h"
  44
  45 /* NOTE: this constant may get moved into a svga3d*.h header file */
  46 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
  47
  48 #ifdef DEBUG
  49 int SVGA_DEBUG = 0;
  50
  51 static const struct debug_named_value svga_debug_flags[] = {
  52    { "dma",         DEBUG_DMA, NULL },
  53    { "tgsi",        DEBUG_TGSI, NULL },
  54    { "pipe",        DEBUG_PIPE, NULL },
  55    { "state",       DEBUG_STATE, NULL },
  56    { "screen",      DEBUG_SCREEN, NULL },
  57    { "tex",         DEBUG_TEX, NULL },
  58    { "swtnl",       DEBUG_SWTNL, NULL },
  59    { "const",       DEBUG_CONSTS, NULL },
  60    { "viewport",    DEBUG_VIEWPORT, NULL },
  61    { "views",       DEBUG_VIEWS, NULL },
  62    { "perf",        DEBUG_PERF, NULL },
  63    { "flush",       DEBUG_FLUSH, NULL },
  64    { "sync",        DEBUG_SYNC, NULL },
  65    { "cache",       DEBUG_CACHE, NULL },
  66    { "streamout",   DEBUG_STREAMOUT, NULL },
  67    { "query",       DEBUG_QUERY, NULL },
  68    DEBUG_NAMED_VALUE_END
  69 };
  70 #endif
  71
  72 static const char *
  73 svga_get_vendor( struct pipe_screen *pscreen )
  74 {
  75    return "VMware, Inc.";
  76 }
  77
  78
  79 static const char *
  80 svga_get_name( struct pipe_screen *pscreen )
  81 {
  82    const char *build = "", *llvm = "", *mutex = "";
  83    static char name[100];
  84 #ifdef DEBUG
  85    /* Only return internal details in the DEBUG version:
  86     */
  87    build = "build: DEBUG;";
  88    mutex = "mutex: " PIPE_ATOMIC ";";
  89 #else
  90    build = "build: RELEASE;";
  91 #endif
  92 #ifdef HAVE_LLVM
  93    llvm = "LLVM;";
  94 #endif
  95
  96    util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
  97    return name;
  98 }
  99
 100
 101 /** Helper for querying float-valued device cap */
 102 static float
 103 get_float_cap(struct svga_winsys_screen *sws, unsigned cap, float defaultVal)
 104 {
 105    SVGA3dDevCapResult result;
 106    if (sws->get_cap(sws, cap, &result))
 107       return result.f;
 108    else
 109       return defaultVal;
 110 }
 111
 112
 113 /** Helper for querying uint-valued device cap */
 114 static unsigned
 115 get_uint_cap(struct svga_winsys_screen *sws, unsigned cap, unsigned defaultVal)
 116 {
 117    SVGA3dDevCapResult result;
 118    if (sws->get_cap(sws, cap, &result))
 119       return result.u;
 120    else
 121       return defaultVal;
 122 }
 123
 124
 125 /** Helper for querying boolean-valued device cap */
 126 static boolean
 127 get_bool_cap(struct svga_winsys_screen *sws, unsigned cap, boolean defaultVal)
 128 {
 129    SVGA3dDevCapResult result;
 130    if (sws->get_cap(sws, cap, &result))
 131       return result.b;
 132    else
 133       return defaultVal;
 134 }
 135
 136
 137 static float
 138 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 139 {
 140    struct svga_screen *svgascreen = svga_screen(screen);
 141    struct svga_winsys_screen *sws = svgascreen->sws;
 142
 143    switch (param) {
 144    case PIPE_CAPF_MAX_LINE_WIDTH:
 145       return svgascreen->maxLineWidth;
 146    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 147       return svgascreen->maxLineWidthAA;
 148
 149    case PIPE_CAPF_MAX_POINT_WIDTH:
 150       /* fall-through */
 151    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 152       return svgascreen->maxPointSize;
 153
 154    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 155       return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
 156
 157    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 158       return 15.0;
 159
 160    case PIPE_CAPF_GUARD_BAND_LEFT:
 161    case PIPE_CAPF_GUARD_BAND_TOP:
 162    case PIPE_CAPF_GUARD_BAND_RIGHT:
 163    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 164       return 0.0;
 165    }
 166
 167    debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
 168    return 0;
 169 }
 170
 171
 172 static int
 173 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
 174 {
 175    struct svga_screen *svgascreen = svga_screen(screen);
 176    struct svga_winsys_screen *sws = svgascreen->sws;
 177    SVGA3dDevCapResult result;
 178
 179    switch (param) {
 180    case PIPE_CAP_NPOT_TEXTURES:
 181    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 182       return 1;
 183    case PIPE_CAP_TWO_SIDED_STENCIL:
 184       return 1;
 185    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 186       /*
 187        * "In virtually every OpenGL implementation and hardware,
 188        * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
 189        * http://www.opengl.org/wiki/Blending
 190        */
 191       return sws->have_vgpu10 ? 1 : 0;
 192    case PIPE_CAP_ANISOTROPIC_FILTER:
 193       return 1;
 194    case PIPE_CAP_POINT_SPRITE:
 195       return 1;
 196    case PIPE_CAP_TGSI_TEXCOORD:
 197       return 0;
 198    case PIPE_CAP_MAX_RENDER_TARGETS:
 199       return svgascreen->max_color_buffers;
 200    case PIPE_CAP_OCCLUSION_QUERY:
 201       return 1;
 202    case PIPE_CAP_QUERY_TIME_ELAPSED:
 203       return 0;
 204    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 205       return sws->have_vgpu10;
 206    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 207       return 1;
 208    case PIPE_CAP_TEXTURE_SWIZZLE:
 209       return 1;
 210    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 211       return 0;
 212    case PIPE_CAP_USER_VERTEX_BUFFERS:
 213    case PIPE_CAP_USER_INDEX_BUFFERS:
 214       return 0;
 215    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 216       return 1;
 217    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 218       return 256;
 219
 220    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 221       {
 222          unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
 223          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
 224             levels = MIN2(util_logbase2(result.u) + 1, levels);
 225          else
 226             levels = 12 /* 2048x2048 */;
 227          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
 228             levels = MIN2(util_logbase2(result.u) + 1, levels);
 229          else
 230             levels = 12 /* 2048x2048 */;
 231          return levels;
 232       }
 233
 234    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 235       if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
 236          return 8;  /* max 128x128x128 */
 237       return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
 238
 239    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 240       /*
 241        * No mechanism to query the host, and at least limited to 2048x2048 on
 242        * certain hardware.
 243        */
 244       return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
 245                   12 /* 2048x2048 */);
 246
 247    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 248       return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
 249
 250    case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
 251       return 1;
 252
 253    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 254       return 1;
 255    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 256       return sws->have_vgpu10;
 257    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 258       return 0;
 259    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 260       return !sws->have_vgpu10;
 261
 262    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 263       return 1; /* The color outputs of vertex shaders are not clamped */
 264    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 265       return 0; /* The driver can't clamp vertex colors */
 266    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 267       return 0; /* The driver can't clamp fragment colors */
 268
 269    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 270       return 1; /* expected for GL_ARB_framebuffer_object */
 271
 272    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 273       return sws->have_vgpu10 ? 330 : 120;
 274
 275    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 276       return 0;
 277
 278    case PIPE_CAP_SM3:
 279       return 1;
 280
 281    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 282    case PIPE_CAP_INDEP_BLEND_ENABLE:
 283    case PIPE_CAP_CONDITIONAL_RENDER:
 284    case PIPE_CAP_QUERY_TIMESTAMP:
 285    case PIPE_CAP_TGSI_INSTANCEID:
 286    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 287    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 288    case PIPE_CAP_FAKE_SW_MSAA:
 289       return sws->have_vgpu10;
 290
 291    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 292       return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
 293    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 294       return sws->have_vgpu10 ? 4 : 0;
 295    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 296       return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
 297    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 298       return 0;
 299    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 300       return svgascreen->ms_samples ? 1 : 0;
 301
 302    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 303       return SVGA3D_DX_MAX_RESOURCE_SIZE;
 304
 305    case PIPE_CAP_MIN_TEXEL_OFFSET:
 306       return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
 307    case PIPE_CAP_MAX_TEXEL_OFFSET:
 308       return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
 309
 310    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 311    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 312       return 0;
 313
 314    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 315       return sws->have_vgpu10 ? 256 : 0;
 316    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 317       return sws->have_vgpu10 ? 1024 : 0;
 318
 319    case PIPE_CAP_PRIMITIVE_RESTART:
 320       return 1; /* may be a sw fallback, depending on restart index */
 321
 322    case PIPE_CAP_GENERATE_MIPMAP:
 323       return sws->have_vgpu10;
 324
 325    /* Unsupported features */
 326    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 327    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 328    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 329    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 330    case PIPE_CAP_INDEP_BLEND_FUNC:
 331    case PIPE_CAP_TEXTURE_BARRIER:
 332    case PIPE_CAP_MAX_VERTEX_STREAMS:
 333    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 334    case PIPE_CAP_COMPUTE:
 335    case PIPE_CAP_START_INSTANCE:
 336    case PIPE_CAP_CUBE_MAP_ARRAY:
 337    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 338    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 339    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 340    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 341    case PIPE_CAP_TEXTURE_GATHER_SM5:
 342    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 343    case PIPE_CAP_TEXTURE_QUERY_LOD:
 344    case PIPE_CAP_SAMPLE_SHADING:
 345    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 346    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 347    case PIPE_CAP_DRAW_INDIRECT:
 348    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 349    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 350    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 351    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 352    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 353    case PIPE_CAP_CLIP_HALFZ:
 354    case PIPE_CAP_VERTEXID_NOBASE:
 355    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 356    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 357    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 358    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 359    case PIPE_CAP_INVALIDATE_BUFFER:
 360    case PIPE_CAP_STRING_MARKER:
 361    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 362    case PIPE_CAP_QUERY_MEMORY_INFO:
 363    case PIPE_CAP_PCI_GROUP:
 364    case PIPE_CAP_PCI_BUS:
 365    case PIPE_CAP_PCI_DEVICE:
 366    case PIPE_CAP_PCI_FUNCTION:
 367    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 368       return 0;
 369    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 370       return 64;
 371    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 372    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 373    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 374       return 1;  /* need 4-byte alignment for all offsets and strides */
 375    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 376       return 2048;
 377    case PIPE_CAP_MAX_VIEWPORTS:
 378       return 1;
 379    case PIPE_CAP_ENDIANNESS:
 380       return PIPE_ENDIAN_LITTLE;
 381
 382    case PIPE_CAP_VENDOR_ID:
 383       return 0x15ad; /* VMware Inc. */
 384    case PIPE_CAP_DEVICE_ID:
 385       return 0x0405; /* assume SVGA II */
 386    case PIPE_CAP_ACCELERATED:
 387       return 0; /* XXX: */
 388    case PIPE_CAP_VIDEO_MEMORY:
 389       /* XXX: Query the host ? */
 390       return 1;
 391    case PIPE_CAP_UMA:
 392    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 393    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 394    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 395    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 396    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 397    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 398    case PIPE_CAP_TGSI_TXQS:
 399    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 400    case PIPE_CAP_SHAREABLE_SHADERS:
 401    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 402    case PIPE_CAP_CLEAR_TEXTURE:
 403    case PIPE_CAP_DRAW_PARAMETERS:
 404    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 405    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 406    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 407    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 408    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 409       return 0;
 410    }
 411
 412    debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
 413    return 0;
 414 }
 415
 416
 417 static int
 418 vgpu9_get_shader_param(struct pipe_screen *screen, unsigned shader,
 419                        enum pipe_shader_cap param)
 420 {
 421    struct svga_screen *svgascreen = svga_screen(screen);
 422    struct svga_winsys_screen *sws = svgascreen->sws;
 423    unsigned val;
 424
 425    assert(!sws->have_vgpu10);
 426
 427    switch (shader)
 428    {
 429    case PIPE_SHADER_FRAGMENT:
 430       switch (param)
 431       {
 432       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 433       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 434       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 435       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 436          return 512;
 437       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 438          return SVGA3D_MAX_NESTING_LEVEL;
 439       case PIPE_SHADER_CAP_MAX_INPUTS:
 440          return 10;
 441       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 442          return svgascreen->max_color_buffers;
 443       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 444          return 224 * sizeof(float[4]);
 445       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 446          return 1;
 447       case PIPE_SHADER_CAP_MAX_TEMPS:
 448          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
 449          return MIN2(val, SVGA3D_TEMPREG_MAX);
 450       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 451          /*
 452           * Although PS 3.0 has some addressing abilities it can only represent
 453           * loops that can be statically determined and unrolled. Given we can
 454           * only handle a subset of the cases that the state tracker already
 455           * does it is better to defer loop unrolling to the state tracker.
 456           */
 457          return 0;
 458       case PIPE_SHADER_CAP_MAX_PREDS:
 459          return 1;
 460       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 461          return 0;
 462       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 463          return 0;
 464       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 465       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 466       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 467          return 0;
 468       case PIPE_SHADER_CAP_SUBROUTINES:
 469          return 0;
 470       case PIPE_SHADER_CAP_INTEGERS:
 471          return 0;
 472       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 473       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 474          return 16;
 475       case PIPE_SHADER_CAP_PREFERRED_IR:
 476          return PIPE_SHADER_IR_TGSI;
 477       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 478          return 0;
 479       case PIPE_SHADER_CAP_DOUBLES:
 480       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 481       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 482       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 483       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 484       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 485       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 486          return 0;
 487       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 488          return 32;
 489       }
 490       /* If we get here, we failed to handle a cap above */
 491       debug_printf("Unexpected fragment shader query %u\n", param);
 492       return 0;
 493    case PIPE_SHADER_VERTEX:
 494       switch (param)
 495       {
 496       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 497       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 498          return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
 499                              512);
 500       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 501       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 502          /* XXX: until we have vertex texture support */
 503          return 0;
 504       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 505          return SVGA3D_MAX_NESTING_LEVEL;
 506       case PIPE_SHADER_CAP_MAX_INPUTS:
 507          return 16;
 508       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 509          return 10;
 510       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 511          return 256 * sizeof(float[4]);
 512       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 513          return 1;
 514       case PIPE_SHADER_CAP_MAX_TEMPS:
 515          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
 516          return MIN2(val, SVGA3D_TEMPREG_MAX);
 517       case PIPE_SHADER_CAP_MAX_PREDS:
 518          return 1;
 519       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 520          return 0;
 521       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 522          return 0;
 523       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 524       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 525          return 1;
 526       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 527          return 0;
 528       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 529          return 1;
 530       case PIPE_SHADER_CAP_SUBROUTINES:
 531          return 0;
 532       case PIPE_SHADER_CAP_INTEGERS:
 533          return 0;
 534       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 535       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 536          return 0;
 537       case PIPE_SHADER_CAP_PREFERRED_IR:
 538          return PIPE_SHADER_IR_TGSI;
 539       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 540          return 0;
 541       case PIPE_SHADER_CAP_DOUBLES:
 542       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 543       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 544       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 545       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 546       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 547       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 548          return 0;
 549       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 550          return 32;
 551       }
 552       /* If we get here, we failed to handle a cap above */
 553       debug_printf("Unexpected vertex shader query %u\n", param);
 554       return 0;
 555    case PIPE_SHADER_GEOMETRY:
 556    case PIPE_SHADER_COMPUTE:
 557    case PIPE_SHADER_TESS_CTRL:
 558    case PIPE_SHADER_TESS_EVAL:
 559       /* no support for geometry, tess or compute shaders at this time */
 560       return 0;
 561    default:
 562       debug_printf("Unexpected shader type (%u) query\n", shader);
 563       return 0;
 564    }
 565    return 0;
 566 }
 567
 568
 569 static int
 570 vgpu10_get_shader_param(struct pipe_screen *screen, unsigned shader,
 571                         enum pipe_shader_cap param)
 572 {
 573    struct svga_screen *svgascreen = svga_screen(screen);
 574    struct svga_winsys_screen *sws = svgascreen->sws;
 575
 576    assert(sws->have_vgpu10);
 577    (void) sws;  /* silence unused var warnings in non-debug builds */
 578
 579    /* Only VS, GS, FS supported */
 580    if (shader != PIPE_SHADER_VERTEX &&
 581        shader != PIPE_SHADER_GEOMETRY &&
 582        shader != PIPE_SHADER_FRAGMENT) {
 583       return 0;
 584    }
 585
 586    /* NOTE: we do not query the device for any caps/limits at this time */
 587
 588    /* Generally the same limits for vertex, geometry and fragment shaders */
 589    switch (param) {
 590    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 591    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 592    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 593    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 594       return 64 * 1024;
 595    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 596       return 64;
 597    case PIPE_SHADER_CAP_MAX_INPUTS:
 598       if (shader == PIPE_SHADER_FRAGMENT)
 599          return VGPU10_MAX_FS_INPUTS;
 600       else if (shader == PIPE_SHADER_GEOMETRY)
 601          return VGPU10_MAX_GS_INPUTS;
 602       else
 603          return VGPU10_MAX_VS_INPUTS;
 604    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 605       if (shader == PIPE_SHADER_FRAGMENT)
 606          return VGPU10_MAX_FS_OUTPUTS;
 607       else if (shader == PIPE_SHADER_GEOMETRY)
 608          return VGPU10_MAX_GS_OUTPUTS;
 609       else
 610          return VGPU10_MAX_VS_OUTPUTS;
 611    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 612       return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
 613    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 614       return svgascreen->max_const_buffers;
 615    case PIPE_SHADER_CAP_MAX_TEMPS:
 616       return VGPU10_MAX_TEMPS;
 617    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 618    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 619    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 620    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 621       return TRUE; /* XXX verify */
 622    case PIPE_SHADER_CAP_MAX_PREDS:
 623       return 0;
 624    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 625    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 626    case PIPE_SHADER_CAP_SUBROUTINES:
 627    case PIPE_SHADER_CAP_INTEGERS:
 628       return TRUE;
 629    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 630    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 631       return SVGA3D_DX_MAX_SAMPLERS;
 632    case PIPE_SHADER_CAP_PREFERRED_IR:
 633       return PIPE_SHADER_IR_TGSI;
 634    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 635          return 0;
 636    case PIPE_SHADER_CAP_DOUBLES:
 637    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 638    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 639    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 640    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 641    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 642    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 643       return 0;
 644    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 645       return 32;
 646    default:
 647       debug_printf("Unexpected vgpu10 shader query %u\n", param);
 648       return 0;
 649    }
 650    return 0;
 651 }
 652
 653
 654 static int
 655 svga_get_shader_param(struct pipe_screen *screen, unsigned shader,
 656                       enum pipe_shader_cap param)
 657 {
 658    struct svga_screen *svgascreen = svga_screen(screen);
 659    struct svga_winsys_screen *sws = svgascreen->sws;
 660    if (sws->have_vgpu10) {
 661       return vgpu10_get_shader_param(screen, shader, param);
 662    }
 663    else {
 664       return vgpu9_get_shader_param(screen, shader, param);
 665    }
 666 }
 667
 668
 669 /**
 670  * Implement pipe_screen::is_format_supported().
 671  * \param bindings  bitmask of PIPE_BIND_x flags
 672  */
 673 static boolean
 674 svga_is_format_supported( struct pipe_screen *screen,
 675                           enum pipe_format format,
 676                           enum pipe_texture_target target,
 677                           unsigned sample_count,
 678                           unsigned bindings)
 679 {
 680    struct svga_screen *ss = svga_screen(screen);
 681    SVGA3dSurfaceFormat svga_format;
 682    SVGA3dSurfaceFormatCaps caps;
 683    SVGA3dSurfaceFormatCaps mask;
 684
 685    assert(bindings);
 686
 687    if (sample_count > 1) {
 688       /* In ms_samples, if bit N is set it means that we support
 689        * multisample with N+1 samples per pixel.
 690        */
 691       if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
 692          return FALSE;
 693       }
 694    }
 695
 696    svga_format = svga_translate_format(ss, format, bindings);
 697    if (svga_format == SVGA3D_FORMAT_INVALID) {
 698       return FALSE;
 699    }
 700
 701    /* we don't support sRGB rendering into display targets */
 702    if (util_format_is_srgb(format) && (bindings & PIPE_BIND_DISPLAY_TARGET)) {
 703       return FALSE;
 704    }
 705
 706    /*
 707     * For VGPU10 vertex formats, skip querying host capabilities
 708     */
 709
 710    if (ss->sws->have_vgpu10 && (bindings & PIPE_BIND_VERTEX_BUFFER)) {
 711       SVGA3dSurfaceFormat svga_format;
 712       unsigned flags;
 713       svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
 714       return svga_format != SVGA3D_FORMAT_INVALID;
 715    }
 716
 717    /*
 718     * Override host capabilities, so that we end up with the same
 719     * visuals for all virtual hardware implementations.
 720     */
 721
 722    if (bindings & PIPE_BIND_DISPLAY_TARGET) {
 723       switch (svga_format) {
 724       case SVGA3D_A8R8G8B8:
 725       case SVGA3D_X8R8G8B8:
 726       case SVGA3D_R5G6B5:
 727          break;
 728
 729       /* VGPU10 formats */
 730       case SVGA3D_B8G8R8A8_UNORM:
 731       case SVGA3D_B8G8R8X8_UNORM:
 732       case SVGA3D_B5G6R5_UNORM:
 733          break;
 734
 735       /* Often unsupported/problematic. This means we end up with the same
 736        * visuals for all virtual hardware implementations.
 737        */
 738       case SVGA3D_A4R4G4B4:
 739       case SVGA3D_A1R5G5B5:
 740          return FALSE;
 741
 742       default:
 743          return FALSE;
 744       }
 745    }
 746
 747    /*
 748     * Query the host capabilities.
 749     */
 750
 751    svga_get_format_cap(ss, svga_format, &caps);
 752
 753    if (bindings & PIPE_BIND_RENDER_TARGET) {
 754       /* Check that the color surface is blendable, unless it's an
 755        * integer format.
 756        */
 757       if (!svga_format_is_integer(svga_format) &&
 758           (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
 759          return FALSE;
 760       }
 761    }
 762
 763    mask.value = 0;
 764    if (bindings & PIPE_BIND_RENDER_TARGET) {
 765       mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
 766    }
 767    if (bindings & PIPE_BIND_DEPTH_STENCIL) {
 768       mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
 769    }
 770    if (bindings & PIPE_BIND_SAMPLER_VIEW) {
 771       mask.value |= SVGA3DFORMAT_OP_TEXTURE;
 772    }
 773
 774    if (target == PIPE_TEXTURE_CUBE) {
 775       mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
 776    }
 777    else if (target == PIPE_TEXTURE_3D) {
 778       mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
 779    }
 780
 781    return (caps.value & mask.value) == mask.value;
 782 }
 783
 784
 785 static void
 786 svga_fence_reference(struct pipe_screen *screen,
 787                      struct pipe_fence_handle **ptr,
 788                      struct pipe_fence_handle *fence)
 789 {
 790    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 791    sws->fence_reference(sws, ptr, fence);
 792 }
 793
 794
 795 static boolean
 796 svga_fence_finish(struct pipe_screen *screen,
 797                   struct pipe_fence_handle *fence,
 798                   uint64_t timeout)
 799 {
 800    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 801
 802    if (!timeout)
 803       return sws->fence_signalled(sws, fence, 0) == 0;
 804
 805    SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
 806             __FUNCTION__, fence);
 807
 808    return sws->fence_finish(sws, fence, 0) == 0;
 809 }
 810
 811
 812 static int
 813 svga_get_driver_query_info(struct pipe_screen *screen,
 814                            unsigned index,
 815                            struct pipe_driver_query_info *info)
 816 {
 817 #define QUERY(NAME, ENUM, UNITS) \
 818    {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
 819
 820    static const struct pipe_driver_query_info queries[] = {
 821       /* per-frame counters */
 822       QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
 823             PIPE_DRIVER_QUERY_TYPE_UINT64),
 824       QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
 825             PIPE_DRIVER_QUERY_TYPE_UINT64),
 826       QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
 827             PIPE_DRIVER_QUERY_TYPE_UINT64),
 828       QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
 829             PIPE_DRIVER_QUERY_TYPE_UINT64),
 830       QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
 831             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 832       QUERY("num-resources-mapped", SVGA_QUERY_NUM_RESOURCES_MAPPED,
 833             PIPE_DRIVER_QUERY_TYPE_UINT64),
 834       QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
 835             PIPE_DRIVER_QUERY_TYPE_BYTES),
 836       QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
 837             PIPE_DRIVER_QUERY_TYPE_BYTES),
 838       QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
 839             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 840       QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
 841             PIPE_DRIVER_QUERY_TYPE_UINT64),
 842       QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
 843             PIPE_DRIVER_QUERY_TYPE_UINT64),
 844       QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
 845             PIPE_DRIVER_QUERY_TYPE_UINT64),
 846       QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
 847             PIPE_DRIVER_QUERY_TYPE_UINT64),
 848       QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
 849             PIPE_DRIVER_QUERY_TYPE_UINT64),
 850       QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
 851             PIPE_DRIVER_QUERY_TYPE_UINT64),
 852
 853       /* running total counters */
 854       QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
 855             PIPE_DRIVER_QUERY_TYPE_BYTES),
 856       QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
 857             PIPE_DRIVER_QUERY_TYPE_UINT64),
 858       QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
 859             PIPE_DRIVER_QUERY_TYPE_UINT64),
 860       QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
 861             PIPE_DRIVER_QUERY_TYPE_UINT64),
 862       QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
 863             PIPE_DRIVER_QUERY_TYPE_UINT64),
 864       QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
 865             PIPE_DRIVER_QUERY_TYPE_UINT64),
 866    };
 867 #undef QUERY
 868
 869    if (!info)
 870       return Elements(queries);
 871
 872    if (index >= Elements(queries))
 873       return 0;
 874
 875    *info = queries[index];
 876    return 1;
 877 }
 878
 879
 880 static void
 881 svga_destroy_screen( struct pipe_screen *screen )
 882 {
 883    struct svga_screen *svgascreen = svga_screen(screen);
 884
 885    svga_screen_cache_cleanup(svgascreen);
 886
 887    pipe_mutex_destroy(svgascreen->swc_mutex);
 888    pipe_mutex_destroy(svgascreen->tex_mutex);
 889
 890    svgascreen->sws->destroy(svgascreen->sws);
 891
 892    FREE(svgascreen);
 893 }
 894
 895
 896 /**
 897  * Create a new svga_screen object
 898  */
 899 struct pipe_screen *
 900 svga_screen_create(struct svga_winsys_screen *sws)
 901 {
 902    struct svga_screen *svgascreen;
 903    struct pipe_screen *screen;
 904
 905 #ifdef DEBUG
 906    SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
 907 #endif
 908
 909    svgascreen = CALLOC_STRUCT(svga_screen);
 910    if (!svgascreen)
 911       goto error1;
 912
 913    svgascreen->debug.force_level_surface_view =
 914       debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
 915    svgascreen->debug.force_surface_view =
 916       debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
 917    svgascreen->debug.force_sampler_view =
 918       debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
 919    svgascreen->debug.no_surface_view =
 920       debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
 921    svgascreen->debug.no_sampler_view =
 922       debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
 923
 924    screen = &svgascreen->screen;
 925
 926    screen->destroy = svga_destroy_screen;
 927    screen->get_name = svga_get_name;
 928    screen->get_vendor = svga_get_vendor;
 929    screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
 930    screen->get_param = svga_get_param;
 931    screen->get_shader_param = svga_get_shader_param;
 932    screen->get_paramf = svga_get_paramf;
 933    screen->get_timestamp = NULL;
 934    screen->is_format_supported = svga_is_format_supported;
 935    screen->context_create = svga_context_create;
 936    screen->fence_reference = svga_fence_reference;
 937    screen->fence_finish = svga_fence_finish;
 938    screen->get_driver_query_info = svga_get_driver_query_info;
 939    svgascreen->sws = sws;
 940
 941    svga_init_screen_resource_functions(svgascreen);
 942
 943    if (sws->get_hw_version) {
 944       svgascreen->hw_version = sws->get_hw_version(sws);
 945    } else {
 946       svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
 947    }
 948
 949    /*
 950     * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
 951     * when sampled from, where as the DF16, DF24, and D24S8_INT do not.  So
 952     * we prefer the later when available.
 953     *
 954     * This mimics hardware vendors extensions for D3D depth sampling. See also
 955     * http://aras-p.info/texts/D3D9GPUHacks.html
 956     */
 957
 958    {
 959       boolean has_df16, has_df24, has_d24s8_int;
 960       SVGA3dSurfaceFormatCaps caps;
 961       SVGA3dSurfaceFormatCaps mask;
 962       mask.value = 0;
 963       mask.zStencil = 1;
 964       mask.texture = 1;
 965
 966       svgascreen->depth.z16 = SVGA3D_Z_D16;
 967       svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
 968       svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
 969
 970       svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
 971       has_df16 = (caps.value & mask.value) == mask.value;
 972
 973       svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
 974       has_df24 = (caps.value & mask.value) == mask.value;
 975
 976       svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
 977       has_d24s8_int = (caps.value & mask.value) == mask.value;
 978
 979       /* XXX: We might want some other logic here.
 980        * Like if we only have d24s8_int we should
 981        * emulate the other formats with that.
 982        */
 983       if (has_df16) {
 984          svgascreen->depth.z16 = SVGA3D_Z_DF16;
 985       }
 986       if (has_df24) {
 987          svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
 988       }
 989       if (has_d24s8_int) {
 990          svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
 991       }
 992    }
 993
 994    /* Query device caps
 995     */
 996    if (sws->have_vgpu10) {
 997       svgascreen->haveProvokingVertex
 998          = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
 999       svgascreen->haveLineSmooth = TRUE;
1000       svgascreen->maxPointSize = 80.0F;
1001       svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1002
1003       /* Multisample samples per pixel */
1004       if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
1005          svgascreen->ms_samples =
1006             get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
1007       }
1008
1009       /* Maximum number of constant buffers */
1010       svgascreen->max_const_buffers =
1011          get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1012       assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1013    }
1014    else {
1015       /* VGPU9 */
1016       unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1017                                      SVGA3DVSVERSION_NONE);
1018       unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1019                                      SVGA3DPSVERSION_NONE);
1020
1021       /* we require Shader model 3.0 or later */
1022       if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1023          goto error2;
1024       }
1025
1026       svgascreen->haveProvokingVertex = FALSE;
1027
1028       svgascreen->haveLineSmooth =
1029          get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1030
1031       svgascreen->maxPointSize =
1032          get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1033       /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1034       svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1035
1036       /* The SVGA3D device always supports 4 targets at this time, regardless
1037        * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1038        */
1039       svgascreen->max_color_buffers = 4;
1040
1041       /* Only support one constant buffer
1042        */
1043       svgascreen->max_const_buffers = 1;
1044
1045       /* No multisampling */
1046       svgascreen->ms_samples = 0;
1047    }
1048
1049    /* common VGPU9 / VGPU10 caps */
1050    svgascreen->haveLineStipple =
1051       get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1052
1053    svgascreen->maxLineWidth =
1054       get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f);
1055
1056    svgascreen->maxLineWidthAA =
1057       get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f);
1058
1059    if (0) {
1060       debug_printf("svga: haveProvokingVertex %u\n",
1061                    svgascreen->haveProvokingVertex);
1062       debug_printf("svga: haveLineStip %u  "
1063                    "haveLineSmooth %u  maxLineWidth %f\n",
1064                    svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1065                    svgascreen->maxLineWidth);
1066       debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1067    }
1068
1069    pipe_mutex_init(svgascreen->tex_mutex);
1070    pipe_mutex_init(svgascreen->swc_mutex);
1071
1072    svga_screen_cache_init(svgascreen);
1073
1074    return screen;
1075 error2:
1076    FREE(svgascreen);
1077 error1:
1078    return NULL;
1079 }
1080
1081 struct svga_winsys_screen *
1082 svga_winsys_screen(struct pipe_screen *screen)
1083 {
1084    return svga_screen(screen)->sws;
1085 }
1086
1087 #ifdef DEBUG
1088 struct svga_screen *
1089 svga_screen(struct pipe_screen *screen)
1090 {
1091    assert(screen);
1092    assert(screen->destroy == svga_destroy_screen);
1093    return (struct svga_screen *)screen;
1094 }
1095 #endif