1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
26 #include "util/u_format.h"
27 #include "util/u_memory.h"
28 #include "util/u_inlines.h"
29 #include "util/u_string.h"
30 #include "util/u_math.h"
32 #include "svga_winsys.h"
33 #include "svga_public.h"
34 #include "svga_context.h"
35 #include "svga_format.h"
36 #include "svga_screen.h"
37 #include "svga_tgsi.h"
38 #include "svga_resource_texture.h"
39 #include "svga_resource.h"
40 #include "svga_debug.h"
42 #include "svga3d_shaderdefs.h"
43 #include "VGPU10ShaderTokens.h"
45 /* NOTE: this constant may get moved into a svga3d*.h header file */
46 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
51 static const struct debug_named_value svga_debug_flags
[] = {
52 { "dma", DEBUG_DMA
, NULL
},
53 { "tgsi", DEBUG_TGSI
, NULL
},
54 { "pipe", DEBUG_PIPE
, NULL
},
55 { "state", DEBUG_STATE
, NULL
},
56 { "screen", DEBUG_SCREEN
, NULL
},
57 { "tex", DEBUG_TEX
, NULL
},
58 { "swtnl", DEBUG_SWTNL
, NULL
},
59 { "const", DEBUG_CONSTS
, NULL
},
60 { "viewport", DEBUG_VIEWPORT
, NULL
},
61 { "views", DEBUG_VIEWS
, NULL
},
62 { "perf", DEBUG_PERF
, NULL
},
63 { "flush", DEBUG_FLUSH
, NULL
},
64 { "sync", DEBUG_SYNC
, NULL
},
65 { "cache", DEBUG_CACHE
, NULL
},
66 { "streamout", DEBUG_STREAMOUT
, NULL
},
67 { "query", DEBUG_QUERY
, NULL
},
73 svga_get_vendor( struct pipe_screen
*pscreen
)
75 return "VMware, Inc.";
80 svga_get_name( struct pipe_screen
*pscreen
)
82 const char *build
= "", *llvm
= "", *mutex
= "";
83 static char name
[100];
85 /* Only return internal details in the DEBUG version:
87 build
= "build: DEBUG;";
88 mutex
= "mutex: " PIPE_ATOMIC
";";
90 build
= "build: RELEASE;";
96 util_snprintf(name
, sizeof(name
), "SVGA3D; %s %s %s", build
, mutex
, llvm
);
101 /** Helper for querying float-valued device cap */
103 get_float_cap(struct svga_winsys_screen
*sws
, unsigned cap
, float defaultVal
)
105 SVGA3dDevCapResult result
;
106 if (sws
->get_cap(sws
, cap
, &result
))
113 /** Helper for querying uint-valued device cap */
115 get_uint_cap(struct svga_winsys_screen
*sws
, unsigned cap
, unsigned defaultVal
)
117 SVGA3dDevCapResult result
;
118 if (sws
->get_cap(sws
, cap
, &result
))
125 /** Helper for querying boolean-valued device cap */
127 get_bool_cap(struct svga_winsys_screen
*sws
, unsigned cap
, boolean defaultVal
)
129 SVGA3dDevCapResult result
;
130 if (sws
->get_cap(sws
, cap
, &result
))
138 svga_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
140 struct svga_screen
*svgascreen
= svga_screen(screen
);
141 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
144 case PIPE_CAPF_MAX_LINE_WIDTH
:
145 return svgascreen
->maxLineWidth
;
146 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
147 return svgascreen
->maxLineWidthAA
;
149 case PIPE_CAPF_MAX_POINT_WIDTH
:
151 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
152 return svgascreen
->maxPointSize
;
154 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
155 return (float) get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY
, 4);
157 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
160 case PIPE_CAPF_GUARD_BAND_LEFT
:
161 case PIPE_CAPF_GUARD_BAND_TOP
:
162 case PIPE_CAPF_GUARD_BAND_RIGHT
:
163 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
167 debug_printf("Unexpected PIPE_CAPF_ query %u\n", param
);
173 svga_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
175 struct svga_screen
*svgascreen
= svga_screen(screen
);
176 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
177 SVGA3dDevCapResult result
;
180 case PIPE_CAP_NPOT_TEXTURES
:
181 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
183 case PIPE_CAP_TWO_SIDED_STENCIL
:
185 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
187 * "In virtually every OpenGL implementation and hardware,
188 * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
189 * http://www.opengl.org/wiki/Blending
191 return sws
->have_vgpu10
? 1 : 0;
192 case PIPE_CAP_ANISOTROPIC_FILTER
:
194 case PIPE_CAP_POINT_SPRITE
:
196 case PIPE_CAP_TGSI_TEXCOORD
:
198 case PIPE_CAP_MAX_RENDER_TARGETS
:
199 return svgascreen
->max_color_buffers
;
200 case PIPE_CAP_OCCLUSION_QUERY
:
202 case PIPE_CAP_QUERY_TIME_ELAPSED
:
204 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
205 return sws
->have_vgpu10
;
206 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
208 case PIPE_CAP_TEXTURE_SWIZZLE
:
210 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
212 case PIPE_CAP_USER_VERTEX_BUFFERS
:
213 case PIPE_CAP_USER_INDEX_BUFFERS
:
215 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
217 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
220 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
222 unsigned levels
= SVGA_MAX_TEXTURE_LEVELS
;
223 if (sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH
, &result
))
224 levels
= MIN2(util_logbase2(result
.u
) + 1, levels
);
226 levels
= 12 /* 2048x2048 */;
227 if (sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT
, &result
))
228 levels
= MIN2(util_logbase2(result
.u
) + 1, levels
);
230 levels
= 12 /* 2048x2048 */;
234 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
235 if (!sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT
, &result
))
236 return 8; /* max 128x128x128 */
237 return MIN2(util_logbase2(result
.u
) + 1, SVGA_MAX_TEXTURE_LEVELS
);
239 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
241 * No mechanism to query the host, and at least limited to 2048x2048 on
244 return MIN2(screen
->get_param(screen
, PIPE_CAP_MAX_TEXTURE_2D_LEVELS
),
247 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
248 return sws
->have_vgpu10
? SVGA3D_MAX_SURFACE_ARRAYSIZE
: 0;
250 case PIPE_CAP_BLEND_EQUATION_SEPARATE
: /* req. for GL 1.5 */
253 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
255 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
256 return sws
->have_vgpu10
;
257 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
259 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
260 return !sws
->have_vgpu10
;
262 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
263 return 1; /* The color outputs of vertex shaders are not clamped */
264 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
265 return 0; /* The driver can't clamp vertex colors */
266 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
267 return 0; /* The driver can't clamp fragment colors */
269 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
270 return 1; /* expected for GL_ARB_framebuffer_object */
272 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
273 return sws
->have_vgpu10
? 330 : 120;
275 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
281 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
282 case PIPE_CAP_INDEP_BLEND_ENABLE
:
283 case PIPE_CAP_CONDITIONAL_RENDER
:
284 case PIPE_CAP_QUERY_TIMESTAMP
:
285 case PIPE_CAP_TGSI_INSTANCEID
:
286 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
287 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
288 case PIPE_CAP_FAKE_SW_MSAA
:
289 return sws
->have_vgpu10
;
291 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
292 return sws
->have_vgpu10
? SVGA3D_DX_MAX_SOTARGETS
: 0;
293 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
294 return sws
->have_vgpu10
? 4 : 0;
295 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
296 return sws
->have_vgpu10
? SVGA3D_MAX_STREAMOUT_DECLS
: 0;
297 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
299 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
300 return svgascreen
->ms_samples
? 1 : 0;
302 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
303 return SVGA3D_DX_MAX_RESOURCE_SIZE
;
305 case PIPE_CAP_MIN_TEXEL_OFFSET
:
306 return sws
->have_vgpu10
? VGPU10_MIN_TEXEL_FETCH_OFFSET
: 0;
307 case PIPE_CAP_MAX_TEXEL_OFFSET
:
308 return sws
->have_vgpu10
? VGPU10_MAX_TEXEL_FETCH_OFFSET
: 0;
310 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
311 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
314 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
315 return sws
->have_vgpu10
? 256 : 0;
316 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
317 return sws
->have_vgpu10
? 1024 : 0;
319 case PIPE_CAP_PRIMITIVE_RESTART
:
320 return 1; /* may be a sw fallback, depending on restart index */
322 case PIPE_CAP_GENERATE_MIPMAP
:
323 return sws
->have_vgpu10
;
325 /* Unsupported features */
326 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
327 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
328 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
329 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
330 case PIPE_CAP_INDEP_BLEND_FUNC
:
331 case PIPE_CAP_TEXTURE_BARRIER
:
332 case PIPE_CAP_MAX_VERTEX_STREAMS
:
333 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
334 case PIPE_CAP_COMPUTE
:
335 case PIPE_CAP_START_INSTANCE
:
336 case PIPE_CAP_CUBE_MAP_ARRAY
:
337 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
338 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
339 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
340 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
341 case PIPE_CAP_TEXTURE_GATHER_SM5
:
342 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
343 case PIPE_CAP_TEXTURE_QUERY_LOD
:
344 case PIPE_CAP_SAMPLE_SHADING
:
345 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
346 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
347 case PIPE_CAP_DRAW_INDIRECT
:
348 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
349 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
350 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
351 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
352 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
353 case PIPE_CAP_CLIP_HALFZ
:
354 case PIPE_CAP_VERTEXID_NOBASE
:
355 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
356 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
357 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
358 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
359 case PIPE_CAP_INVALIDATE_BUFFER
:
360 case PIPE_CAP_STRING_MARKER
:
361 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
362 case PIPE_CAP_QUERY_MEMORY_INFO
:
364 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
366 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
367 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
368 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
369 return 1; /* need 4-byte alignment for all offsets and strides */
370 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
372 case PIPE_CAP_MAX_VIEWPORTS
:
374 case PIPE_CAP_ENDIANNESS
:
375 return PIPE_ENDIAN_LITTLE
;
377 case PIPE_CAP_VENDOR_ID
:
378 return 0x15ad; /* VMware Inc. */
379 case PIPE_CAP_DEVICE_ID
:
380 return 0x0405; /* assume SVGA II */
381 case PIPE_CAP_ACCELERATED
:
383 case PIPE_CAP_VIDEO_MEMORY
:
384 /* XXX: Query the host ? */
387 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
388 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
389 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
390 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
391 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
392 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
393 case PIPE_CAP_TGSI_TXQS
:
394 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
395 case PIPE_CAP_SHAREABLE_SHADERS
:
396 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
397 case PIPE_CAP_CLEAR_TEXTURE
:
398 case PIPE_CAP_DRAW_PARAMETERS
:
399 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
400 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
401 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
402 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
406 debug_printf("Unexpected PIPE_CAP_ query %u\n", param
);
412 vgpu9_get_shader_param(struct pipe_screen
*screen
, unsigned shader
,
413 enum pipe_shader_cap param
)
415 struct svga_screen
*svgascreen
= svga_screen(screen
);
416 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
419 assert(!sws
->have_vgpu10
);
423 case PIPE_SHADER_FRAGMENT
:
426 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
427 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
428 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
429 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
431 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
432 return SVGA3D_MAX_NESTING_LEVEL
;
433 case PIPE_SHADER_CAP_MAX_INPUTS
:
435 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
436 return svgascreen
->max_color_buffers
;
437 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
438 return 224 * sizeof(float[4]);
439 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
441 case PIPE_SHADER_CAP_MAX_TEMPS
:
442 val
= get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS
, 32);
443 return MIN2(val
, SVGA3D_TEMPREG_MAX
);
444 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
446 * Although PS 3.0 has some addressing abilities it can only represent
447 * loops that can be statically determined and unrolled. Given we can
448 * only handle a subset of the cases that the state tracker already
449 * does it is better to defer loop unrolling to the state tracker.
452 case PIPE_SHADER_CAP_MAX_PREDS
:
454 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
456 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
458 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
459 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
460 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
462 case PIPE_SHADER_CAP_SUBROUTINES
:
464 case PIPE_SHADER_CAP_INTEGERS
:
466 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
467 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
469 case PIPE_SHADER_CAP_PREFERRED_IR
:
470 return PIPE_SHADER_IR_TGSI
;
471 case PIPE_SHADER_CAP_DOUBLES
:
472 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
473 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
474 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
475 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
476 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
478 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
481 /* If we get here, we failed to handle a cap above */
482 debug_printf("Unexpected fragment shader query %u\n", param
);
484 case PIPE_SHADER_VERTEX
:
487 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
488 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
489 return get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS
,
491 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
492 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
493 /* XXX: until we have vertex texture support */
495 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
496 return SVGA3D_MAX_NESTING_LEVEL
;
497 case PIPE_SHADER_CAP_MAX_INPUTS
:
499 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
501 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
502 return 256 * sizeof(float[4]);
503 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
505 case PIPE_SHADER_CAP_MAX_TEMPS
:
506 val
= get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS
, 32);
507 return MIN2(val
, SVGA3D_TEMPREG_MAX
);
508 case PIPE_SHADER_CAP_MAX_PREDS
:
510 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
512 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
514 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
515 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
517 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
519 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
521 case PIPE_SHADER_CAP_SUBROUTINES
:
523 case PIPE_SHADER_CAP_INTEGERS
:
525 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
526 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
528 case PIPE_SHADER_CAP_PREFERRED_IR
:
529 return PIPE_SHADER_IR_TGSI
;
530 case PIPE_SHADER_CAP_DOUBLES
:
531 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
532 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
533 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
534 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
535 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
537 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
540 /* If we get here, we failed to handle a cap above */
541 debug_printf("Unexpected vertex shader query %u\n", param
);
543 case PIPE_SHADER_GEOMETRY
:
544 case PIPE_SHADER_COMPUTE
:
545 case PIPE_SHADER_TESS_CTRL
:
546 case PIPE_SHADER_TESS_EVAL
:
547 /* no support for geometry, tess or compute shaders at this time */
550 debug_printf("Unexpected shader type (%u) query\n", shader
);
558 vgpu10_get_shader_param(struct pipe_screen
*screen
, unsigned shader
,
559 enum pipe_shader_cap param
)
561 struct svga_screen
*svgascreen
= svga_screen(screen
);
562 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
564 assert(sws
->have_vgpu10
);
565 (void) sws
; /* silence unused var warnings in non-debug builds */
567 /* Only VS, GS, FS supported */
568 if (shader
!= PIPE_SHADER_VERTEX
&&
569 shader
!= PIPE_SHADER_GEOMETRY
&&
570 shader
!= PIPE_SHADER_FRAGMENT
) {
574 /* NOTE: we do not query the device for any caps/limits at this time */
576 /* Generally the same limits for vertex, geometry and fragment shaders */
578 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
579 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
580 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
581 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
583 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
585 case PIPE_SHADER_CAP_MAX_INPUTS
:
586 if (shader
== PIPE_SHADER_FRAGMENT
)
587 return VGPU10_MAX_FS_INPUTS
;
588 else if (shader
== PIPE_SHADER_GEOMETRY
)
589 return VGPU10_MAX_GS_INPUTS
;
591 return VGPU10_MAX_VS_INPUTS
;
592 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
593 if (shader
== PIPE_SHADER_FRAGMENT
)
594 return VGPU10_MAX_FS_OUTPUTS
;
595 else if (shader
== PIPE_SHADER_GEOMETRY
)
596 return VGPU10_MAX_GS_OUTPUTS
;
598 return VGPU10_MAX_VS_OUTPUTS
;
599 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
600 return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT
* sizeof(float[4]);
601 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
602 return svgascreen
->max_const_buffers
;
603 case PIPE_SHADER_CAP_MAX_TEMPS
:
604 return VGPU10_MAX_TEMPS
;
605 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
606 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
607 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
608 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
609 return TRUE
; /* XXX verify */
610 case PIPE_SHADER_CAP_MAX_PREDS
:
612 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
613 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
614 case PIPE_SHADER_CAP_SUBROUTINES
:
615 case PIPE_SHADER_CAP_INTEGERS
:
617 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
618 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
619 return SVGA3D_DX_MAX_SAMPLERS
;
620 case PIPE_SHADER_CAP_PREFERRED_IR
:
621 return PIPE_SHADER_IR_TGSI
;
622 case PIPE_SHADER_CAP_DOUBLES
:
623 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
624 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
625 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
626 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
627 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
629 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
632 debug_printf("Unexpected vgpu10 shader query %u\n", param
);
640 svga_get_shader_param(struct pipe_screen
*screen
, unsigned shader
,
641 enum pipe_shader_cap param
)
643 struct svga_screen
*svgascreen
= svga_screen(screen
);
644 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
645 if (sws
->have_vgpu10
) {
646 return vgpu10_get_shader_param(screen
, shader
, param
);
649 return vgpu9_get_shader_param(screen
, shader
, param
);
655 * Implement pipe_screen::is_format_supported().
656 * \param bindings bitmask of PIPE_BIND_x flags
659 svga_is_format_supported( struct pipe_screen
*screen
,
660 enum pipe_format format
,
661 enum pipe_texture_target target
,
662 unsigned sample_count
,
665 struct svga_screen
*ss
= svga_screen(screen
);
666 SVGA3dSurfaceFormat svga_format
;
667 SVGA3dSurfaceFormatCaps caps
;
668 SVGA3dSurfaceFormatCaps mask
;
672 if (sample_count
> 1) {
673 /* In ms_samples, if bit N is set it means that we support
674 * multisample with N+1 samples per pixel.
676 if ((ss
->ms_samples
& (1 << (sample_count
- 1))) == 0) {
681 svga_format
= svga_translate_format(ss
, format
, bindings
);
682 if (svga_format
== SVGA3D_FORMAT_INVALID
) {
686 /* we don't support sRGB rendering into display targets */
687 if (util_format_is_srgb(format
) && (bindings
& PIPE_BIND_DISPLAY_TARGET
)) {
692 * For VGPU10 vertex formats, skip querying host capabilities
695 if (ss
->sws
->have_vgpu10
&& (bindings
& PIPE_BIND_VERTEX_BUFFER
)) {
696 SVGA3dSurfaceFormat svga_format
;
698 svga_translate_vertex_format_vgpu10(format
, &svga_format
, &flags
);
699 return svga_format
!= SVGA3D_FORMAT_INVALID
;
703 * Override host capabilities, so that we end up with the same
704 * visuals for all virtual hardware implementations.
707 if (bindings
& PIPE_BIND_DISPLAY_TARGET
) {
708 switch (svga_format
) {
709 case SVGA3D_A8R8G8B8
:
710 case SVGA3D_X8R8G8B8
:
715 case SVGA3D_B8G8R8A8_UNORM
:
716 case SVGA3D_B8G8R8X8_UNORM
:
717 case SVGA3D_B5G6R5_UNORM
:
720 /* Often unsupported/problematic. This means we end up with the same
721 * visuals for all virtual hardware implementations.
723 case SVGA3D_A4R4G4B4
:
724 case SVGA3D_A1R5G5B5
:
733 * Query the host capabilities.
736 svga_get_format_cap(ss
, svga_format
, &caps
);
738 if (bindings
& PIPE_BIND_RENDER_TARGET
) {
739 /* Check that the color surface is blendable, unless it's an
742 if (!svga_format_is_integer(svga_format
) &&
743 (caps
.value
& SVGA3DFORMAT_OP_NOALPHABLEND
)) {
749 if (bindings
& PIPE_BIND_RENDER_TARGET
) {
750 mask
.value
|= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
;
752 if (bindings
& PIPE_BIND_DEPTH_STENCIL
) {
753 mask
.value
|= SVGA3DFORMAT_OP_ZSTENCIL
;
755 if (bindings
& PIPE_BIND_SAMPLER_VIEW
) {
756 mask
.value
|= SVGA3DFORMAT_OP_TEXTURE
;
759 if (target
== PIPE_TEXTURE_CUBE
) {
760 mask
.value
|= SVGA3DFORMAT_OP_CUBETEXTURE
;
762 else if (target
== PIPE_TEXTURE_3D
) {
763 mask
.value
|= SVGA3DFORMAT_OP_VOLUMETEXTURE
;
766 return (caps
.value
& mask
.value
) == mask
.value
;
771 svga_fence_reference(struct pipe_screen
*screen
,
772 struct pipe_fence_handle
**ptr
,
773 struct pipe_fence_handle
*fence
)
775 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
776 sws
->fence_reference(sws
, ptr
, fence
);
781 svga_fence_finish(struct pipe_screen
*screen
,
782 struct pipe_fence_handle
*fence
,
785 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
788 return sws
->fence_signalled(sws
, fence
, 0) == 0;
790 SVGA_DBG(DEBUG_DMA
|DEBUG_PERF
, "%s fence_ptr %p\n",
791 __FUNCTION__
, fence
);
793 return sws
->fence_finish(sws
, fence
, 0) == 0;
798 svga_get_driver_query_info(struct pipe_screen
*screen
,
800 struct pipe_driver_query_info
*info
)
802 #define QUERY(NAME, ENUM, UNITS) \
803 {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
805 static const struct pipe_driver_query_info queries
[] = {
806 /* per-frame counters */
807 QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS
,
808 PIPE_DRIVER_QUERY_TYPE_UINT64
),
809 QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS
,
810 PIPE_DRIVER_QUERY_TYPE_UINT64
),
811 QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES
,
812 PIPE_DRIVER_QUERY_TYPE_UINT64
),
813 QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS
,
814 PIPE_DRIVER_QUERY_TYPE_UINT64
),
815 QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME
,
816 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
),
817 QUERY("num-resources-mapped", SVGA_QUERY_NUM_RESOURCES_MAPPED
,
818 PIPE_DRIVER_QUERY_TYPE_UINT64
),
819 QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED
,
820 PIPE_DRIVER_QUERY_TYPE_BYTES
),
822 /* running total counters */
823 QUERY("memory-used", SVGA_QUERY_MEMORY_USED
,
824 PIPE_DRIVER_QUERY_TYPE_BYTES
),
825 QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS
,
826 PIPE_DRIVER_QUERY_TYPE_UINT64
),
827 QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES
,
828 PIPE_DRIVER_QUERY_TYPE_UINT64
),
829 QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS
,
830 PIPE_DRIVER_QUERY_TYPE_UINT64
),
831 QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS
,
832 PIPE_DRIVER_QUERY_TYPE_UINT64
),
833 QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP
,
834 PIPE_DRIVER_QUERY_TYPE_UINT64
),
839 return Elements(queries
);
841 if (index
>= Elements(queries
))
844 *info
= queries
[index
];
850 svga_destroy_screen( struct pipe_screen
*screen
)
852 struct svga_screen
*svgascreen
= svga_screen(screen
);
854 svga_screen_cache_cleanup(svgascreen
);
856 pipe_mutex_destroy(svgascreen
->swc_mutex
);
857 pipe_mutex_destroy(svgascreen
->tex_mutex
);
859 svgascreen
->sws
->destroy(svgascreen
->sws
);
866 * Create a new svga_screen object
869 svga_screen_create(struct svga_winsys_screen
*sws
)
871 struct svga_screen
*svgascreen
;
872 struct pipe_screen
*screen
;
875 SVGA_DEBUG
= debug_get_flags_option("SVGA_DEBUG", svga_debug_flags
, 0 );
878 svgascreen
= CALLOC_STRUCT(svga_screen
);
882 svgascreen
->debug
.force_level_surface_view
=
883 debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE
);
884 svgascreen
->debug
.force_surface_view
=
885 debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE
);
886 svgascreen
->debug
.force_sampler_view
=
887 debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE
);
888 svgascreen
->debug
.no_surface_view
=
889 debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE
);
890 svgascreen
->debug
.no_sampler_view
=
891 debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE
);
893 screen
= &svgascreen
->screen
;
895 screen
->destroy
= svga_destroy_screen
;
896 screen
->get_name
= svga_get_name
;
897 screen
->get_vendor
= svga_get_vendor
;
898 screen
->get_device_vendor
= svga_get_vendor
; // TODO actual device vendor
899 screen
->get_param
= svga_get_param
;
900 screen
->get_shader_param
= svga_get_shader_param
;
901 screen
->get_paramf
= svga_get_paramf
;
902 screen
->get_timestamp
= NULL
;
903 screen
->is_format_supported
= svga_is_format_supported
;
904 screen
->context_create
= svga_context_create
;
905 screen
->fence_reference
= svga_fence_reference
;
906 screen
->fence_finish
= svga_fence_finish
;
907 screen
->get_driver_query_info
= svga_get_driver_query_info
;
908 svgascreen
->sws
= sws
;
910 svga_init_screen_resource_functions(svgascreen
);
912 if (sws
->get_hw_version
) {
913 svgascreen
->hw_version
= sws
->get_hw_version(sws
);
915 svgascreen
->hw_version
= SVGA3D_HWVERSION_WS65_B1
;
919 * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
920 * when sampled from, where as the DF16, DF24, and D24S8_INT do not. So
921 * we prefer the later when available.
923 * This mimics hardware vendors extensions for D3D depth sampling. See also
924 * http://aras-p.info/texts/D3D9GPUHacks.html
928 boolean has_df16
, has_df24
, has_d24s8_int
;
929 SVGA3dSurfaceFormatCaps caps
;
930 SVGA3dSurfaceFormatCaps mask
;
935 svgascreen
->depth
.z16
= SVGA3D_Z_D16
;
936 svgascreen
->depth
.x8z24
= SVGA3D_Z_D24X8
;
937 svgascreen
->depth
.s8z24
= SVGA3D_Z_D24S8
;
939 svga_get_format_cap(svgascreen
, SVGA3D_Z_DF16
, &caps
);
940 has_df16
= (caps
.value
& mask
.value
) == mask
.value
;
942 svga_get_format_cap(svgascreen
, SVGA3D_Z_DF24
, &caps
);
943 has_df24
= (caps
.value
& mask
.value
) == mask
.value
;
945 svga_get_format_cap(svgascreen
, SVGA3D_Z_D24S8_INT
, &caps
);
946 has_d24s8_int
= (caps
.value
& mask
.value
) == mask
.value
;
948 /* XXX: We might want some other logic here.
949 * Like if we only have d24s8_int we should
950 * emulate the other formats with that.
953 svgascreen
->depth
.z16
= SVGA3D_Z_DF16
;
956 svgascreen
->depth
.x8z24
= SVGA3D_Z_DF24
;
959 svgascreen
->depth
.s8z24
= SVGA3D_Z_D24S8_INT
;
965 if (sws
->have_vgpu10
) {
966 svgascreen
->haveProvokingVertex
967 = get_bool_cap(sws
, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX
, FALSE
);
968 svgascreen
->haveLineSmooth
= TRUE
;
969 svgascreen
->maxPointSize
= 80.0F
;
970 svgascreen
->max_color_buffers
= SVGA3D_DX_MAX_RENDER_TARGETS
;
972 /* Multisample samples per pixel */
973 svgascreen
->ms_samples
=
974 get_uint_cap(sws
, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES
, 0);
976 /* Maximum number of constant buffers */
977 svgascreen
->max_const_buffers
=
978 get_uint_cap(sws
, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS
, 1);
979 assert(svgascreen
->max_const_buffers
<= SVGA_MAX_CONST_BUFS
);
983 unsigned vs_ver
= get_uint_cap(sws
, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION
,
984 SVGA3DVSVERSION_NONE
);
985 unsigned fs_ver
= get_uint_cap(sws
, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION
,
986 SVGA3DPSVERSION_NONE
);
988 /* we require Shader model 3.0 or later */
989 if (fs_ver
< SVGA3DPSVERSION_30
|| vs_ver
< SVGA3DVSVERSION_30
) {
993 svgascreen
->haveProvokingVertex
= FALSE
;
995 svgascreen
->haveLineSmooth
=
996 get_bool_cap(sws
, SVGA3D_DEVCAP_LINE_AA
, FALSE
);
998 svgascreen
->maxPointSize
=
999 get_float_cap(sws
, SVGA3D_DEVCAP_MAX_POINT_SIZE
, 1.0f
);
1000 /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1001 svgascreen
->maxPointSize
= MIN2(svgascreen
->maxPointSize
, 80.0f
);
1003 /* The SVGA3D device always supports 4 targets at this time, regardless
1004 * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1006 svgascreen
->max_color_buffers
= 4;
1008 /* Only support one constant buffer
1010 svgascreen
->max_const_buffers
= 1;
1012 /* No multisampling */
1013 svgascreen
->ms_samples
= 0;
1016 /* common VGPU9 / VGPU10 caps */
1017 svgascreen
->haveLineStipple
=
1018 get_bool_cap(sws
, SVGA3D_DEVCAP_LINE_STIPPLE
, FALSE
);
1020 svgascreen
->maxLineWidth
=
1021 get_float_cap(sws
, SVGA3D_DEVCAP_MAX_LINE_WIDTH
, 1.0f
);
1023 svgascreen
->maxLineWidthAA
=
1024 get_float_cap(sws
, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH
, 1.0f
);
1027 debug_printf("svga: haveProvokingVertex %u\n",
1028 svgascreen
->haveProvokingVertex
);
1029 debug_printf("svga: haveLineStip %u "
1030 "haveLineSmooth %u maxLineWidth %f\n",
1031 svgascreen
->haveLineStipple
, svgascreen
->haveLineSmooth
,
1032 svgascreen
->maxLineWidth
);
1033 debug_printf("svga: maxPointSize %g\n", svgascreen
->maxPointSize
);
1036 pipe_mutex_init(svgascreen
->tex_mutex
);
1037 pipe_mutex_init(svgascreen
->swc_mutex
);
1039 svga_screen_cache_init(svgascreen
);
1048 struct svga_winsys_screen
*
1049 svga_winsys_screen(struct pipe_screen
*screen
)
1051 return svga_screen(screen
)->sws
;
1055 struct svga_screen
*
1056 svga_screen(struct pipe_screen
*screen
)
1059 assert(screen
->destroy
== svga_destroy_screen
);
1060 return (struct svga_screen
*)screen
;